1*150812a8SEvalZero; Copyright (c) 2009-2018 ARM Limited. All rights reserved. 2*150812a8SEvalZero; 3*150812a8SEvalZero; SPDX-License-Identifier: Apache-2.0 4*150812a8SEvalZero; 5*150812a8SEvalZero; Licensed under the Apache License, Version 2.0 (the License); you may 6*150812a8SEvalZero; not use this file except in compliance with the License. 7*150812a8SEvalZero; You may obtain a copy of the License at 8*150812a8SEvalZero; 9*150812a8SEvalZero; www.apache.org/licenses/LICENSE-2.0 10*150812a8SEvalZero; 11*150812a8SEvalZero; Unless required by applicable law or agreed to in writing, software 12*150812a8SEvalZero; distributed under the License is distributed on an AS IS BASIS, WITHOUT 13*150812a8SEvalZero; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14*150812a8SEvalZero; See the License for the specific language governing permissions and 15*150812a8SEvalZero; limitations under the License. 16*150812a8SEvalZero; 17*150812a8SEvalZero; NOTICE: This file has been modified by Nordic Semiconductor ASA. 18*150812a8SEvalZero 19*150812a8SEvalZero IF :DEF: __STARTUP_CONFIG 20*150812a8SEvalZero#ifdef __STARTUP_CONFIG 21*150812a8SEvalZero#include "startup_config.h" 22*150812a8SEvalZero#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT 23*150812a8SEvalZero#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3 24*150812a8SEvalZero#endif 25*150812a8SEvalZero#endif 26*150812a8SEvalZero ENDIF 27*150812a8SEvalZero 28*150812a8SEvalZero IF :DEF: __STARTUP_CONFIG 29*150812a8SEvalZeroStack_Size EQU __STARTUP_CONFIG_STACK_SIZE 30*150812a8SEvalZero ELIF :DEF: __STACK_SIZE 31*150812a8SEvalZeroStack_Size EQU __STACK_SIZE 32*150812a8SEvalZero ELSE 33*150812a8SEvalZeroStack_Size EQU 8192 34*150812a8SEvalZero ENDIF 35*150812a8SEvalZero 36*150812a8SEvalZero IF :DEF: __STARTUP_CONFIG 37*150812a8SEvalZeroStack_Align EQU __STARTUP_CONFIG_STACK_ALIGNEMENT 38*150812a8SEvalZero ELSE 39*150812a8SEvalZeroStack_Align EQU 3 40*150812a8SEvalZero ENDIF 41*150812a8SEvalZero 42*150812a8SEvalZero AREA STACK, NOINIT, READWRITE, ALIGN=Stack_Align 43*150812a8SEvalZeroStack_Mem SPACE Stack_Size 44*150812a8SEvalZero__initial_sp 45*150812a8SEvalZero 46*150812a8SEvalZero IF :DEF: __STARTUP_CONFIG 47*150812a8SEvalZeroHeap_Size EQU __STARTUP_CONFIG_HEAP_SIZE 48*150812a8SEvalZero ELIF :DEF: __HEAP_SIZE 49*150812a8SEvalZeroHeap_Size EQU __HEAP_SIZE 50*150812a8SEvalZero ELSE 51*150812a8SEvalZeroHeap_Size EQU 8192 52*150812a8SEvalZero ENDIF 53*150812a8SEvalZero 54*150812a8SEvalZero AREA HEAP, NOINIT, READWRITE, ALIGN=3 55*150812a8SEvalZero__heap_base 56*150812a8SEvalZeroHeap_Mem SPACE Heap_Size 57*150812a8SEvalZero__heap_limit 58*150812a8SEvalZero 59*150812a8SEvalZero PRESERVE8 60*150812a8SEvalZero THUMB 61*150812a8SEvalZero 62*150812a8SEvalZero; Vector Table Mapped to Address 0 at Reset 63*150812a8SEvalZero 64*150812a8SEvalZero AREA RESET, DATA, READONLY 65*150812a8SEvalZero EXPORT __Vectors 66*150812a8SEvalZero EXPORT __Vectors_End 67*150812a8SEvalZero EXPORT __Vectors_Size 68*150812a8SEvalZero 69*150812a8SEvalZero__Vectors DCD __initial_sp ; Top of Stack 70*150812a8SEvalZero DCD Reset_Handler 71*150812a8SEvalZero DCD NMI_Handler 72*150812a8SEvalZero DCD HardFault_Handler 73*150812a8SEvalZero DCD MemoryManagement_Handler 74*150812a8SEvalZero DCD BusFault_Handler 75*150812a8SEvalZero DCD UsageFault_Handler 76*150812a8SEvalZero DCD SecureFault_Handler 77*150812a8SEvalZero DCD 0 ; Reserved 78*150812a8SEvalZero DCD 0 ; Reserved 79*150812a8SEvalZero DCD 0 ; Reserved 80*150812a8SEvalZero DCD SVC_Handler 81*150812a8SEvalZero DCD DebugMon_Handler 82*150812a8SEvalZero DCD 0 ; Reserved 83*150812a8SEvalZero DCD PendSV_Handler 84*150812a8SEvalZero DCD SysTick_Handler 85*150812a8SEvalZero 86*150812a8SEvalZero ; External Interrupts 87*150812a8SEvalZero DCD 0 ; Reserved 88*150812a8SEvalZero DCD 0 ; Reserved 89*150812a8SEvalZero DCD 0 ; Reserved 90*150812a8SEvalZero DCD SPU_IRQHandler 91*150812a8SEvalZero DCD 0 ; Reserved 92*150812a8SEvalZero DCD CLOCK_POWER_IRQHandler 93*150812a8SEvalZero DCD 0 ; Reserved 94*150812a8SEvalZero DCD 0 ; Reserved 95*150812a8SEvalZero DCD UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQHandler 96*150812a8SEvalZero DCD UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQHandler 97*150812a8SEvalZero DCD UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQHandler 98*150812a8SEvalZero DCD UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQHandler 99*150812a8SEvalZero DCD 0 ; Reserved 100*150812a8SEvalZero DCD GPIOTE0_IRQHandler 101*150812a8SEvalZero DCD SAADC_IRQHandler 102*150812a8SEvalZero DCD TIMER0_IRQHandler 103*150812a8SEvalZero DCD TIMER1_IRQHandler 104*150812a8SEvalZero DCD TIMER2_IRQHandler 105*150812a8SEvalZero DCD 0 ; Reserved 106*150812a8SEvalZero DCD 0 ; Reserved 107*150812a8SEvalZero DCD RTC0_IRQHandler 108*150812a8SEvalZero DCD RTC1_IRQHandler 109*150812a8SEvalZero DCD 0 ; Reserved 110*150812a8SEvalZero DCD 0 ; Reserved 111*150812a8SEvalZero DCD WDT_IRQHandler 112*150812a8SEvalZero DCD 0 ; Reserved 113*150812a8SEvalZero DCD 0 ; Reserved 114*150812a8SEvalZero DCD EGU0_IRQHandler 115*150812a8SEvalZero DCD EGU1_IRQHandler 116*150812a8SEvalZero DCD EGU2_IRQHandler 117*150812a8SEvalZero DCD EGU3_IRQHandler 118*150812a8SEvalZero DCD EGU4_IRQHandler 119*150812a8SEvalZero DCD EGU5_IRQHandler 120*150812a8SEvalZero DCD PWM0_IRQHandler 121*150812a8SEvalZero DCD PWM1_IRQHandler 122*150812a8SEvalZero DCD PWM2_IRQHandler 123*150812a8SEvalZero DCD PWM3_IRQHandler 124*150812a8SEvalZero DCD 0 ; Reserved 125*150812a8SEvalZero DCD PDM_IRQHandler 126*150812a8SEvalZero DCD 0 ; Reserved 127*150812a8SEvalZero DCD I2S_IRQHandler 128*150812a8SEvalZero DCD 0 ; Reserved 129*150812a8SEvalZero DCD IPC_IRQHandler 130*150812a8SEvalZero DCD 0 ; Reserved 131*150812a8SEvalZero DCD FPU_IRQHandler 132*150812a8SEvalZero DCD 0 ; Reserved 133*150812a8SEvalZero DCD 0 ; Reserved 134*150812a8SEvalZero DCD 0 ; Reserved 135*150812a8SEvalZero DCD 0 ; Reserved 136*150812a8SEvalZero DCD GPIOTE1_IRQHandler 137*150812a8SEvalZero DCD 0 ; Reserved 138*150812a8SEvalZero DCD 0 ; Reserved 139*150812a8SEvalZero DCD 0 ; Reserved 140*150812a8SEvalZero DCD 0 ; Reserved 141*150812a8SEvalZero DCD 0 ; Reserved 142*150812a8SEvalZero DCD 0 ; Reserved 143*150812a8SEvalZero DCD 0 ; Reserved 144*150812a8SEvalZero DCD KMU_IRQHandler 145*150812a8SEvalZero DCD 0 ; Reserved 146*150812a8SEvalZero DCD 0 ; Reserved 147*150812a8SEvalZero DCD 0 ; Reserved 148*150812a8SEvalZero DCD 0 ; Reserved 149*150812a8SEvalZero DCD 0 ; Reserved 150*150812a8SEvalZero DCD 0 ; Reserved 151*150812a8SEvalZero DCD CRYPTOCELL_IRQHandler 152*150812a8SEvalZero DCD 0 ; Reserved 153*150812a8SEvalZero DCD 0 ; Reserved 154*150812a8SEvalZero DCD 0 ; Reserved 155*150812a8SEvalZero DCD 0 ; Reserved 156*150812a8SEvalZero DCD 0 ; Reserved 157*150812a8SEvalZero DCD 0 ; Reserved 158*150812a8SEvalZero DCD 0 ; Reserved 159*150812a8SEvalZero DCD 0 ; Reserved 160*150812a8SEvalZero DCD 0 ; Reserved 161*150812a8SEvalZero DCD 0 ; Reserved 162*150812a8SEvalZero DCD 0 ; Reserved 163*150812a8SEvalZero DCD 0 ; Reserved 164*150812a8SEvalZero DCD 0 ; Reserved 165*150812a8SEvalZero DCD 0 ; Reserved 166*150812a8SEvalZero DCD 0 ; Reserved 167*150812a8SEvalZero DCD 0 ; Reserved 168*150812a8SEvalZero DCD 0 ; Reserved 169*150812a8SEvalZero DCD 0 ; Reserved 170*150812a8SEvalZero DCD 0 ; Reserved 171*150812a8SEvalZero DCD 0 ; Reserved 172*150812a8SEvalZero DCD 0 ; Reserved 173*150812a8SEvalZero DCD 0 ; Reserved 174*150812a8SEvalZero DCD 0 ; Reserved 175*150812a8SEvalZero DCD 0 ; Reserved 176*150812a8SEvalZero DCD 0 ; Reserved 177*150812a8SEvalZero DCD 0 ; Reserved 178*150812a8SEvalZero DCD 0 ; Reserved 179*150812a8SEvalZero DCD 0 ; Reserved 180*150812a8SEvalZero DCD 0 ; Reserved 181*150812a8SEvalZero DCD 0 ; Reserved 182*150812a8SEvalZero DCD 0 ; Reserved 183*150812a8SEvalZero DCD 0 ; Reserved 184*150812a8SEvalZero DCD 0 ; Reserved 185*150812a8SEvalZero DCD 0 ; Reserved 186*150812a8SEvalZero DCD 0 ; Reserved 187*150812a8SEvalZero DCD 0 ; Reserved 188*150812a8SEvalZero DCD 0 ; Reserved 189*150812a8SEvalZero DCD 0 ; Reserved 190*150812a8SEvalZero DCD 0 ; Reserved 191*150812a8SEvalZero DCD 0 ; Reserved 192*150812a8SEvalZero DCD 0 ; Reserved 193*150812a8SEvalZero DCD 0 ; Reserved 194*150812a8SEvalZero DCD 0 ; Reserved 195*150812a8SEvalZero DCD 0 ; Reserved 196*150812a8SEvalZero DCD 0 ; Reserved 197*150812a8SEvalZero DCD 0 ; Reserved 198*150812a8SEvalZero DCD 0 ; Reserved 199*150812a8SEvalZero DCD 0 ; Reserved 200*150812a8SEvalZero DCD 0 ; Reserved 201*150812a8SEvalZero DCD 0 ; Reserved 202*150812a8SEvalZero DCD 0 ; Reserved 203*150812a8SEvalZero DCD 0 ; Reserved 204*150812a8SEvalZero DCD 0 ; Reserved 205*150812a8SEvalZero DCD 0 ; Reserved 206*150812a8SEvalZero DCD 0 ; Reserved 207*150812a8SEvalZero DCD 0 ; Reserved 208*150812a8SEvalZero DCD 0 ; Reserved 209*150812a8SEvalZero DCD 0 ; Reserved 210*150812a8SEvalZero DCD 0 ; Reserved 211*150812a8SEvalZero DCD 0 ; Reserved 212*150812a8SEvalZero DCD 0 ; Reserved 213*150812a8SEvalZero DCD 0 ; Reserved 214*150812a8SEvalZero DCD 0 ; Reserved 215*150812a8SEvalZero DCD 0 ; Reserved 216*150812a8SEvalZero DCD 0 ; Reserved 217*150812a8SEvalZero DCD 0 ; Reserved 218*150812a8SEvalZero DCD 0 ; Reserved 219*150812a8SEvalZero DCD 0 ; Reserved 220*150812a8SEvalZero DCD 0 ; Reserved 221*150812a8SEvalZero DCD 0 ; Reserved 222*150812a8SEvalZero DCD 0 ; Reserved 223*150812a8SEvalZero DCD 0 ; Reserved 224*150812a8SEvalZero DCD 0 ; Reserved 225*150812a8SEvalZero DCD 0 ; Reserved 226*150812a8SEvalZero DCD 0 ; Reserved 227*150812a8SEvalZero DCD 0 ; Reserved 228*150812a8SEvalZero DCD 0 ; Reserved 229*150812a8SEvalZero DCD 0 ; Reserved 230*150812a8SEvalZero DCD 0 ; Reserved 231*150812a8SEvalZero DCD 0 ; Reserved 232*150812a8SEvalZero DCD 0 ; Reserved 233*150812a8SEvalZero DCD 0 ; Reserved 234*150812a8SEvalZero DCD 0 ; Reserved 235*150812a8SEvalZero DCD 0 ; Reserved 236*150812a8SEvalZero DCD 0 ; Reserved 237*150812a8SEvalZero DCD 0 ; Reserved 238*150812a8SEvalZero DCD 0 ; Reserved 239*150812a8SEvalZero DCD 0 ; Reserved 240*150812a8SEvalZero DCD 0 ; Reserved 241*150812a8SEvalZero DCD 0 ; Reserved 242*150812a8SEvalZero DCD 0 ; Reserved 243*150812a8SEvalZero DCD 0 ; Reserved 244*150812a8SEvalZero DCD 0 ; Reserved 245*150812a8SEvalZero DCD 0 ; Reserved 246*150812a8SEvalZero DCD 0 ; Reserved 247*150812a8SEvalZero DCD 0 ; Reserved 248*150812a8SEvalZero DCD 0 ; Reserved 249*150812a8SEvalZero DCD 0 ; Reserved 250*150812a8SEvalZero DCD 0 ; Reserved 251*150812a8SEvalZero DCD 0 ; Reserved 252*150812a8SEvalZero DCD 0 ; Reserved 253*150812a8SEvalZero DCD 0 ; Reserved 254*150812a8SEvalZero DCD 0 ; Reserved 255*150812a8SEvalZero DCD 0 ; Reserved 256*150812a8SEvalZero DCD 0 ; Reserved 257*150812a8SEvalZero DCD 0 ; Reserved 258*150812a8SEvalZero DCD 0 ; Reserved 259*150812a8SEvalZero DCD 0 ; Reserved 260*150812a8SEvalZero DCD 0 ; Reserved 261*150812a8SEvalZero DCD 0 ; Reserved 262*150812a8SEvalZero DCD 0 ; Reserved 263*150812a8SEvalZero DCD 0 ; Reserved 264*150812a8SEvalZero DCD 0 ; Reserved 265*150812a8SEvalZero DCD 0 ; Reserved 266*150812a8SEvalZero DCD 0 ; Reserved 267*150812a8SEvalZero DCD 0 ; Reserved 268*150812a8SEvalZero DCD 0 ; Reserved 269*150812a8SEvalZero DCD 0 ; Reserved 270*150812a8SEvalZero DCD 0 ; Reserved 271*150812a8SEvalZero DCD 0 ; Reserved 272*150812a8SEvalZero DCD 0 ; Reserved 273*150812a8SEvalZero DCD 0 ; Reserved 274*150812a8SEvalZero DCD 0 ; Reserved 275*150812a8SEvalZero DCD 0 ; Reserved 276*150812a8SEvalZero DCD 0 ; Reserved 277*150812a8SEvalZero DCD 0 ; Reserved 278*150812a8SEvalZero DCD 0 ; Reserved 279*150812a8SEvalZero DCD 0 ; Reserved 280*150812a8SEvalZero DCD 0 ; Reserved 281*150812a8SEvalZero DCD 0 ; Reserved 282*150812a8SEvalZero DCD 0 ; Reserved 283*150812a8SEvalZero DCD 0 ; Reserved 284*150812a8SEvalZero DCD 0 ; Reserved 285*150812a8SEvalZero DCD 0 ; Reserved 286*150812a8SEvalZero DCD 0 ; Reserved 287*150812a8SEvalZero DCD 0 ; Reserved 288*150812a8SEvalZero DCD 0 ; Reserved 289*150812a8SEvalZero DCD 0 ; Reserved 290*150812a8SEvalZero DCD 0 ; Reserved 291*150812a8SEvalZero DCD 0 ; Reserved 292*150812a8SEvalZero DCD 0 ; Reserved 293*150812a8SEvalZero DCD 0 ; Reserved 294*150812a8SEvalZero DCD 0 ; Reserved 295*150812a8SEvalZero DCD 0 ; Reserved 296*150812a8SEvalZero DCD 0 ; Reserved 297*150812a8SEvalZero DCD 0 ; Reserved 298*150812a8SEvalZero DCD 0 ; Reserved 299*150812a8SEvalZero DCD 0 ; Reserved 300*150812a8SEvalZero DCD 0 ; Reserved 301*150812a8SEvalZero DCD 0 ; Reserved 302*150812a8SEvalZero DCD 0 ; Reserved 303*150812a8SEvalZero DCD 0 ; Reserved 304*150812a8SEvalZero DCD 0 ; Reserved 305*150812a8SEvalZero DCD 0 ; Reserved 306*150812a8SEvalZero DCD 0 ; Reserved 307*150812a8SEvalZero DCD 0 ; Reserved 308*150812a8SEvalZero DCD 0 ; Reserved 309*150812a8SEvalZero DCD 0 ; Reserved 310*150812a8SEvalZero DCD 0 ; Reserved 311*150812a8SEvalZero DCD 0 ; Reserved 312*150812a8SEvalZero DCD 0 ; Reserved 313*150812a8SEvalZero DCD 0 ; Reserved 314*150812a8SEvalZero DCD 0 ; Reserved 315*150812a8SEvalZero DCD 0 ; Reserved 316*150812a8SEvalZero DCD 0 ; Reserved 317*150812a8SEvalZero DCD 0 ; Reserved 318*150812a8SEvalZero DCD 0 ; Reserved 319*150812a8SEvalZero DCD 0 ; Reserved 320*150812a8SEvalZero DCD 0 ; Reserved 321*150812a8SEvalZero DCD 0 ; Reserved 322*150812a8SEvalZero DCD 0 ; Reserved 323*150812a8SEvalZero DCD 0 ; Reserved 324*150812a8SEvalZero DCD 0 ; Reserved 325*150812a8SEvalZero DCD 0 ; Reserved 326*150812a8SEvalZero DCD 0 ; Reserved 327*150812a8SEvalZero 328*150812a8SEvalZero__Vectors_End 329*150812a8SEvalZero 330*150812a8SEvalZero__Vectors_Size EQU __Vectors_End - __Vectors 331*150812a8SEvalZero 332*150812a8SEvalZero AREA |.text|, CODE, READONLY 333*150812a8SEvalZero 334*150812a8SEvalZero; Reset Handler 335*150812a8SEvalZero 336*150812a8SEvalZero 337*150812a8SEvalZeroReset_Handler PROC 338*150812a8SEvalZero EXPORT Reset_Handler [WEAK] 339*150812a8SEvalZero IMPORT SystemInit 340*150812a8SEvalZero IMPORT __main 341*150812a8SEvalZero 342*150812a8SEvalZero 343*150812a8SEvalZero LDR R0, =SystemInit 344*150812a8SEvalZero BLX R0 345*150812a8SEvalZero LDR R0, =__main 346*150812a8SEvalZero BX R0 347*150812a8SEvalZero ENDP 348*150812a8SEvalZero 349*150812a8SEvalZero; Dummy Exception Handlers (infinite loops which can be modified) 350*150812a8SEvalZero 351*150812a8SEvalZeroNMI_Handler PROC 352*150812a8SEvalZero EXPORT NMI_Handler [WEAK] 353*150812a8SEvalZero B . 354*150812a8SEvalZero ENDP 355*150812a8SEvalZeroHardFault_Handler\ 356*150812a8SEvalZero PROC 357*150812a8SEvalZero EXPORT HardFault_Handler [WEAK] 358*150812a8SEvalZero B . 359*150812a8SEvalZero ENDP 360*150812a8SEvalZeroMemoryManagement_Handler\ 361*150812a8SEvalZero PROC 362*150812a8SEvalZero EXPORT MemoryManagement_Handler [WEAK] 363*150812a8SEvalZero B . 364*150812a8SEvalZero ENDP 365*150812a8SEvalZeroBusFault_Handler\ 366*150812a8SEvalZero PROC 367*150812a8SEvalZero EXPORT BusFault_Handler [WEAK] 368*150812a8SEvalZero B . 369*150812a8SEvalZero ENDP 370*150812a8SEvalZeroUsageFault_Handler\ 371*150812a8SEvalZero PROC 372*150812a8SEvalZero EXPORT UsageFault_Handler [WEAK] 373*150812a8SEvalZero B . 374*150812a8SEvalZero ENDP 375*150812a8SEvalZeroSecureFault_Handler\ 376*150812a8SEvalZero PROC 377*150812a8SEvalZero EXPORT SecureFault_Handler [WEAK] 378*150812a8SEvalZero B . 379*150812a8SEvalZero ENDP 380*150812a8SEvalZeroSVC_Handler PROC 381*150812a8SEvalZero EXPORT SVC_Handler [WEAK] 382*150812a8SEvalZero B . 383*150812a8SEvalZero ENDP 384*150812a8SEvalZeroDebugMon_Handler\ 385*150812a8SEvalZero PROC 386*150812a8SEvalZero EXPORT DebugMon_Handler [WEAK] 387*150812a8SEvalZero B . 388*150812a8SEvalZero ENDP 389*150812a8SEvalZeroPendSV_Handler PROC 390*150812a8SEvalZero EXPORT PendSV_Handler [WEAK] 391*150812a8SEvalZero B . 392*150812a8SEvalZero ENDP 393*150812a8SEvalZeroSysTick_Handler PROC 394*150812a8SEvalZero EXPORT SysTick_Handler [WEAK] 395*150812a8SEvalZero B . 396*150812a8SEvalZero ENDP 397*150812a8SEvalZero 398*150812a8SEvalZeroDefault_Handler PROC 399*150812a8SEvalZero 400*150812a8SEvalZero EXPORT SPU_IRQHandler [WEAK] 401*150812a8SEvalZero EXPORT CLOCK_POWER_IRQHandler [WEAK] 402*150812a8SEvalZero EXPORT UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQHandler [WEAK] 403*150812a8SEvalZero EXPORT UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQHandler [WEAK] 404*150812a8SEvalZero EXPORT UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQHandler [WEAK] 405*150812a8SEvalZero EXPORT UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQHandler [WEAK] 406*150812a8SEvalZero EXPORT GPIOTE0_IRQHandler [WEAK] 407*150812a8SEvalZero EXPORT SAADC_IRQHandler [WEAK] 408*150812a8SEvalZero EXPORT TIMER0_IRQHandler [WEAK] 409*150812a8SEvalZero EXPORT TIMER1_IRQHandler [WEAK] 410*150812a8SEvalZero EXPORT TIMER2_IRQHandler [WEAK] 411*150812a8SEvalZero EXPORT RTC0_IRQHandler [WEAK] 412*150812a8SEvalZero EXPORT RTC1_IRQHandler [WEAK] 413*150812a8SEvalZero EXPORT WDT_IRQHandler [WEAK] 414*150812a8SEvalZero EXPORT EGU0_IRQHandler [WEAK] 415*150812a8SEvalZero EXPORT EGU1_IRQHandler [WEAK] 416*150812a8SEvalZero EXPORT EGU2_IRQHandler [WEAK] 417*150812a8SEvalZero EXPORT EGU3_IRQHandler [WEAK] 418*150812a8SEvalZero EXPORT EGU4_IRQHandler [WEAK] 419*150812a8SEvalZero EXPORT EGU5_IRQHandler [WEAK] 420*150812a8SEvalZero EXPORT PWM0_IRQHandler [WEAK] 421*150812a8SEvalZero EXPORT PWM1_IRQHandler [WEAK] 422*150812a8SEvalZero EXPORT PWM2_IRQHandler [WEAK] 423*150812a8SEvalZero EXPORT PWM3_IRQHandler [WEAK] 424*150812a8SEvalZero EXPORT PDM_IRQHandler [WEAK] 425*150812a8SEvalZero EXPORT I2S_IRQHandler [WEAK] 426*150812a8SEvalZero EXPORT IPC_IRQHandler [WEAK] 427*150812a8SEvalZero EXPORT FPU_IRQHandler [WEAK] 428*150812a8SEvalZero EXPORT GPIOTE1_IRQHandler [WEAK] 429*150812a8SEvalZero EXPORT KMU_IRQHandler [WEAK] 430*150812a8SEvalZero EXPORT CRYPTOCELL_IRQHandler [WEAK] 431*150812a8SEvalZeroSPU_IRQHandler 432*150812a8SEvalZeroCLOCK_POWER_IRQHandler 433*150812a8SEvalZeroUARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQHandler 434*150812a8SEvalZeroUARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQHandler 435*150812a8SEvalZeroUARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQHandler 436*150812a8SEvalZeroUARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQHandler 437*150812a8SEvalZeroGPIOTE0_IRQHandler 438*150812a8SEvalZeroSAADC_IRQHandler 439*150812a8SEvalZeroTIMER0_IRQHandler 440*150812a8SEvalZeroTIMER1_IRQHandler 441*150812a8SEvalZeroTIMER2_IRQHandler 442*150812a8SEvalZeroRTC0_IRQHandler 443*150812a8SEvalZeroRTC1_IRQHandler 444*150812a8SEvalZeroWDT_IRQHandler 445*150812a8SEvalZeroEGU0_IRQHandler 446*150812a8SEvalZeroEGU1_IRQHandler 447*150812a8SEvalZeroEGU2_IRQHandler 448*150812a8SEvalZeroEGU3_IRQHandler 449*150812a8SEvalZeroEGU4_IRQHandler 450*150812a8SEvalZeroEGU5_IRQHandler 451*150812a8SEvalZeroPWM0_IRQHandler 452*150812a8SEvalZeroPWM1_IRQHandler 453*150812a8SEvalZeroPWM2_IRQHandler 454*150812a8SEvalZeroPWM3_IRQHandler 455*150812a8SEvalZeroPDM_IRQHandler 456*150812a8SEvalZeroI2S_IRQHandler 457*150812a8SEvalZeroIPC_IRQHandler 458*150812a8SEvalZeroFPU_IRQHandler 459*150812a8SEvalZeroGPIOTE1_IRQHandler 460*150812a8SEvalZeroKMU_IRQHandler 461*150812a8SEvalZeroCRYPTOCELL_IRQHandler 462*150812a8SEvalZero B . 463*150812a8SEvalZero ENDP 464*150812a8SEvalZero ALIGN 465*150812a8SEvalZero 466*150812a8SEvalZero; User Initial Stack & Heap 467*150812a8SEvalZero 468*150812a8SEvalZero IF :DEF:__MICROLIB 469*150812a8SEvalZero 470*150812a8SEvalZero EXPORT __initial_sp 471*150812a8SEvalZero EXPORT __heap_base 472*150812a8SEvalZero EXPORT __heap_limit 473*150812a8SEvalZero 474*150812a8SEvalZero ELSE 475*150812a8SEvalZero 476*150812a8SEvalZero IMPORT __use_two_region_memory 477*150812a8SEvalZero EXPORT __user_initial_stackheap 478*150812a8SEvalZero 479*150812a8SEvalZero__user_initial_stackheap PROC 480*150812a8SEvalZero 481*150812a8SEvalZero LDR R0, = Heap_Mem 482*150812a8SEvalZero LDR R1, = (Stack_Mem + Stack_Size) 483*150812a8SEvalZero LDR R2, = (Heap_Mem + Heap_Size) 484*150812a8SEvalZero LDR R3, = Stack_Mem 485*150812a8SEvalZero BX LR 486*150812a8SEvalZero ENDP 487*150812a8SEvalZero 488*150812a8SEvalZero ALIGN 489*150812a8SEvalZero 490*150812a8SEvalZero ENDIF 491*150812a8SEvalZero 492*150812a8SEvalZero END 493