1*150812a8SEvalZero; Copyright (c) 2009-2018 ARM Limited. All rights reserved. 2*150812a8SEvalZero; 3*150812a8SEvalZero; SPDX-License-Identifier: Apache-2.0 4*150812a8SEvalZero; 5*150812a8SEvalZero; Licensed under the Apache License, Version 2.0 (the License); you may 6*150812a8SEvalZero; not use this file except in compliance with the License. 7*150812a8SEvalZero; You may obtain a copy of the License at 8*150812a8SEvalZero; 9*150812a8SEvalZero; www.apache.org/licenses/LICENSE-2.0 10*150812a8SEvalZero; 11*150812a8SEvalZero; Unless required by applicable law or agreed to in writing, software 12*150812a8SEvalZero; distributed under the License is distributed on an AS IS BASIS, WITHOUT 13*150812a8SEvalZero; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14*150812a8SEvalZero; See the License for the specific language governing permissions and 15*150812a8SEvalZero; limitations under the License. 16*150812a8SEvalZero; 17*150812a8SEvalZero; NOTICE: This file has been modified by Nordic Semiconductor ASA. 18*150812a8SEvalZero 19*150812a8SEvalZero IF :DEF: __STARTUP_CONFIG 20*150812a8SEvalZero#ifdef __STARTUP_CONFIG 21*150812a8SEvalZero#include "startup_config.h" 22*150812a8SEvalZero#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT 23*150812a8SEvalZero#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3 24*150812a8SEvalZero#endif 25*150812a8SEvalZero#endif 26*150812a8SEvalZero ENDIF 27*150812a8SEvalZero 28*150812a8SEvalZero IF :DEF: __STARTUP_CONFIG 29*150812a8SEvalZeroStack_Size EQU __STARTUP_CONFIG_STACK_SIZE 30*150812a8SEvalZero ELIF :DEF: __STACK_SIZE 31*150812a8SEvalZeroStack_Size EQU __STACK_SIZE 32*150812a8SEvalZero ELSE 33*150812a8SEvalZeroStack_Size EQU 8192 34*150812a8SEvalZero ENDIF 35*150812a8SEvalZero 36*150812a8SEvalZero IF :DEF: __STARTUP_CONFIG 37*150812a8SEvalZeroStack_Align EQU __STARTUP_CONFIG_STACK_ALIGNEMENT 38*150812a8SEvalZero ELSE 39*150812a8SEvalZeroStack_Align EQU 3 40*150812a8SEvalZero ENDIF 41*150812a8SEvalZero 42*150812a8SEvalZero AREA STACK, NOINIT, READWRITE, ALIGN=Stack_Align 43*150812a8SEvalZeroStack_Mem SPACE Stack_Size 44*150812a8SEvalZero__initial_sp 45*150812a8SEvalZero 46*150812a8SEvalZero IF :DEF: __STARTUP_CONFIG 47*150812a8SEvalZeroHeap_Size EQU __STARTUP_CONFIG_HEAP_SIZE 48*150812a8SEvalZero ELIF :DEF: __HEAP_SIZE 49*150812a8SEvalZeroHeap_Size EQU __HEAP_SIZE 50*150812a8SEvalZero ELSE 51*150812a8SEvalZeroHeap_Size EQU 8192 52*150812a8SEvalZero ENDIF 53*150812a8SEvalZero 54*150812a8SEvalZero AREA HEAP, NOINIT, READWRITE, ALIGN=3 55*150812a8SEvalZero__heap_base 56*150812a8SEvalZeroHeap_Mem SPACE Heap_Size 57*150812a8SEvalZero__heap_limit 58*150812a8SEvalZero 59*150812a8SEvalZero PRESERVE8 60*150812a8SEvalZero THUMB 61*150812a8SEvalZero 62*150812a8SEvalZero; Vector Table Mapped to Address 0 at Reset 63*150812a8SEvalZero 64*150812a8SEvalZero AREA RESET, DATA, READONLY 65*150812a8SEvalZero EXPORT __Vectors 66*150812a8SEvalZero EXPORT __Vectors_End 67*150812a8SEvalZero EXPORT __Vectors_Size 68*150812a8SEvalZero 69*150812a8SEvalZero__Vectors DCD __initial_sp ; Top of Stack 70*150812a8SEvalZero DCD Reset_Handler 71*150812a8SEvalZero DCD NMI_Handler 72*150812a8SEvalZero DCD HardFault_Handler 73*150812a8SEvalZero DCD MemoryManagement_Handler 74*150812a8SEvalZero DCD BusFault_Handler 75*150812a8SEvalZero DCD UsageFault_Handler 76*150812a8SEvalZero DCD 0 ; Reserved 77*150812a8SEvalZero DCD 0 ; Reserved 78*150812a8SEvalZero DCD 0 ; Reserved 79*150812a8SEvalZero DCD 0 ; Reserved 80*150812a8SEvalZero DCD SVC_Handler 81*150812a8SEvalZero DCD DebugMon_Handler 82*150812a8SEvalZero DCD 0 ; Reserved 83*150812a8SEvalZero DCD PendSV_Handler 84*150812a8SEvalZero DCD SysTick_Handler 85*150812a8SEvalZero 86*150812a8SEvalZero ; External Interrupts 87*150812a8SEvalZero DCD POWER_CLOCK_IRQHandler 88*150812a8SEvalZero DCD RADIO_IRQHandler 89*150812a8SEvalZero DCD UARTE0_UART0_IRQHandler 90*150812a8SEvalZero DCD SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler 91*150812a8SEvalZero DCD SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler 92*150812a8SEvalZero DCD NFCT_IRQHandler 93*150812a8SEvalZero DCD GPIOTE_IRQHandler 94*150812a8SEvalZero DCD SAADC_IRQHandler 95*150812a8SEvalZero DCD TIMER0_IRQHandler 96*150812a8SEvalZero DCD TIMER1_IRQHandler 97*150812a8SEvalZero DCD TIMER2_IRQHandler 98*150812a8SEvalZero DCD RTC0_IRQHandler 99*150812a8SEvalZero DCD TEMP_IRQHandler 100*150812a8SEvalZero DCD RNG_IRQHandler 101*150812a8SEvalZero DCD ECB_IRQHandler 102*150812a8SEvalZero DCD CCM_AAR_IRQHandler 103*150812a8SEvalZero DCD WDT_IRQHandler 104*150812a8SEvalZero DCD RTC1_IRQHandler 105*150812a8SEvalZero DCD QDEC_IRQHandler 106*150812a8SEvalZero DCD COMP_LPCOMP_IRQHandler 107*150812a8SEvalZero DCD SWI0_EGU0_IRQHandler 108*150812a8SEvalZero DCD SWI1_EGU1_IRQHandler 109*150812a8SEvalZero DCD SWI2_EGU2_IRQHandler 110*150812a8SEvalZero DCD SWI3_EGU3_IRQHandler 111*150812a8SEvalZero DCD SWI4_EGU4_IRQHandler 112*150812a8SEvalZero DCD SWI5_EGU5_IRQHandler 113*150812a8SEvalZero DCD TIMER3_IRQHandler 114*150812a8SEvalZero DCD TIMER4_IRQHandler 115*150812a8SEvalZero DCD PWM0_IRQHandler 116*150812a8SEvalZero DCD PDM_IRQHandler 117*150812a8SEvalZero DCD 0 ; Reserved 118*150812a8SEvalZero DCD 0 ; Reserved 119*150812a8SEvalZero DCD MWU_IRQHandler 120*150812a8SEvalZero DCD PWM1_IRQHandler 121*150812a8SEvalZero DCD PWM2_IRQHandler 122*150812a8SEvalZero DCD SPIM2_SPIS2_SPI2_IRQHandler 123*150812a8SEvalZero DCD RTC2_IRQHandler 124*150812a8SEvalZero DCD I2S_IRQHandler 125*150812a8SEvalZero DCD FPU_IRQHandler 126*150812a8SEvalZero DCD 0 ; Reserved 127*150812a8SEvalZero DCD 0 ; Reserved 128*150812a8SEvalZero DCD 0 ; Reserved 129*150812a8SEvalZero DCD 0 ; Reserved 130*150812a8SEvalZero DCD 0 ; Reserved 131*150812a8SEvalZero DCD 0 ; Reserved 132*150812a8SEvalZero DCD 0 ; Reserved 133*150812a8SEvalZero DCD 0 ; Reserved 134*150812a8SEvalZero DCD 0 ; Reserved 135*150812a8SEvalZero DCD 0 ; Reserved 136*150812a8SEvalZero DCD 0 ; Reserved 137*150812a8SEvalZero DCD 0 ; Reserved 138*150812a8SEvalZero DCD 0 ; Reserved 139*150812a8SEvalZero DCD 0 ; Reserved 140*150812a8SEvalZero DCD 0 ; Reserved 141*150812a8SEvalZero DCD 0 ; Reserved 142*150812a8SEvalZero DCD 0 ; Reserved 143*150812a8SEvalZero DCD 0 ; Reserved 144*150812a8SEvalZero DCD 0 ; Reserved 145*150812a8SEvalZero DCD 0 ; Reserved 146*150812a8SEvalZero DCD 0 ; Reserved 147*150812a8SEvalZero DCD 0 ; Reserved 148*150812a8SEvalZero DCD 0 ; Reserved 149*150812a8SEvalZero DCD 0 ; Reserved 150*150812a8SEvalZero DCD 0 ; Reserved 151*150812a8SEvalZero DCD 0 ; Reserved 152*150812a8SEvalZero DCD 0 ; Reserved 153*150812a8SEvalZero DCD 0 ; Reserved 154*150812a8SEvalZero DCD 0 ; Reserved 155*150812a8SEvalZero DCD 0 ; Reserved 156*150812a8SEvalZero DCD 0 ; Reserved 157*150812a8SEvalZero DCD 0 ; Reserved 158*150812a8SEvalZero DCD 0 ; Reserved 159*150812a8SEvalZero DCD 0 ; Reserved 160*150812a8SEvalZero DCD 0 ; Reserved 161*150812a8SEvalZero DCD 0 ; Reserved 162*150812a8SEvalZero DCD 0 ; Reserved 163*150812a8SEvalZero DCD 0 ; Reserved 164*150812a8SEvalZero DCD 0 ; Reserved 165*150812a8SEvalZero DCD 0 ; Reserved 166*150812a8SEvalZero DCD 0 ; Reserved 167*150812a8SEvalZero DCD 0 ; Reserved 168*150812a8SEvalZero DCD 0 ; Reserved 169*150812a8SEvalZero DCD 0 ; Reserved 170*150812a8SEvalZero DCD 0 ; Reserved 171*150812a8SEvalZero DCD 0 ; Reserved 172*150812a8SEvalZero DCD 0 ; Reserved 173*150812a8SEvalZero DCD 0 ; Reserved 174*150812a8SEvalZero DCD 0 ; Reserved 175*150812a8SEvalZero DCD 0 ; Reserved 176*150812a8SEvalZero DCD 0 ; Reserved 177*150812a8SEvalZero DCD 0 ; Reserved 178*150812a8SEvalZero DCD 0 ; Reserved 179*150812a8SEvalZero DCD 0 ; Reserved 180*150812a8SEvalZero DCD 0 ; Reserved 181*150812a8SEvalZero DCD 0 ; Reserved 182*150812a8SEvalZero DCD 0 ; Reserved 183*150812a8SEvalZero DCD 0 ; Reserved 184*150812a8SEvalZero DCD 0 ; Reserved 185*150812a8SEvalZero DCD 0 ; Reserved 186*150812a8SEvalZero DCD 0 ; Reserved 187*150812a8SEvalZero DCD 0 ; Reserved 188*150812a8SEvalZero DCD 0 ; Reserved 189*150812a8SEvalZero DCD 0 ; Reserved 190*150812a8SEvalZero DCD 0 ; Reserved 191*150812a8SEvalZero DCD 0 ; Reserved 192*150812a8SEvalZero DCD 0 ; Reserved 193*150812a8SEvalZero DCD 0 ; Reserved 194*150812a8SEvalZero DCD 0 ; Reserved 195*150812a8SEvalZero DCD 0 ; Reserved 196*150812a8SEvalZero DCD 0 ; Reserved 197*150812a8SEvalZero DCD 0 ; Reserved 198*150812a8SEvalZero DCD 0 ; Reserved 199*150812a8SEvalZero 200*150812a8SEvalZero__Vectors_End 201*150812a8SEvalZero 202*150812a8SEvalZero__Vectors_Size EQU __Vectors_End - __Vectors 203*150812a8SEvalZero 204*150812a8SEvalZero AREA |.text|, CODE, READONLY 205*150812a8SEvalZero 206*150812a8SEvalZero; Reset Handler 207*150812a8SEvalZero 208*150812a8SEvalZero 209*150812a8SEvalZeroReset_Handler PROC 210*150812a8SEvalZero EXPORT Reset_Handler [WEAK] 211*150812a8SEvalZero IMPORT SystemInit 212*150812a8SEvalZero IMPORT __main 213*150812a8SEvalZero 214*150812a8SEvalZero 215*150812a8SEvalZero LDR R0, =SystemInit 216*150812a8SEvalZero BLX R0 217*150812a8SEvalZero LDR R0, =__main 218*150812a8SEvalZero BX R0 219*150812a8SEvalZero ENDP 220*150812a8SEvalZero 221*150812a8SEvalZero; Dummy Exception Handlers (infinite loops which can be modified) 222*150812a8SEvalZero 223*150812a8SEvalZeroNMI_Handler PROC 224*150812a8SEvalZero EXPORT NMI_Handler [WEAK] 225*150812a8SEvalZero B . 226*150812a8SEvalZero ENDP 227*150812a8SEvalZeroHardFault_Handler\ 228*150812a8SEvalZero PROC 229*150812a8SEvalZero EXPORT HardFault_Handler [WEAK] 230*150812a8SEvalZero B . 231*150812a8SEvalZero ENDP 232*150812a8SEvalZeroMemoryManagement_Handler\ 233*150812a8SEvalZero PROC 234*150812a8SEvalZero EXPORT MemoryManagement_Handler [WEAK] 235*150812a8SEvalZero B . 236*150812a8SEvalZero ENDP 237*150812a8SEvalZeroBusFault_Handler\ 238*150812a8SEvalZero PROC 239*150812a8SEvalZero EXPORT BusFault_Handler [WEAK] 240*150812a8SEvalZero B . 241*150812a8SEvalZero ENDP 242*150812a8SEvalZeroUsageFault_Handler\ 243*150812a8SEvalZero PROC 244*150812a8SEvalZero EXPORT UsageFault_Handler [WEAK] 245*150812a8SEvalZero B . 246*150812a8SEvalZero ENDP 247*150812a8SEvalZeroSVC_Handler PROC 248*150812a8SEvalZero EXPORT SVC_Handler [WEAK] 249*150812a8SEvalZero B . 250*150812a8SEvalZero ENDP 251*150812a8SEvalZeroDebugMon_Handler\ 252*150812a8SEvalZero PROC 253*150812a8SEvalZero EXPORT DebugMon_Handler [WEAK] 254*150812a8SEvalZero B . 255*150812a8SEvalZero ENDP 256*150812a8SEvalZeroPendSV_Handler PROC 257*150812a8SEvalZero EXPORT PendSV_Handler [WEAK] 258*150812a8SEvalZero B . 259*150812a8SEvalZero ENDP 260*150812a8SEvalZeroSysTick_Handler PROC 261*150812a8SEvalZero EXPORT SysTick_Handler [WEAK] 262*150812a8SEvalZero B . 263*150812a8SEvalZero ENDP 264*150812a8SEvalZero 265*150812a8SEvalZeroDefault_Handler PROC 266*150812a8SEvalZero 267*150812a8SEvalZero EXPORT POWER_CLOCK_IRQHandler [WEAK] 268*150812a8SEvalZero EXPORT RADIO_IRQHandler [WEAK] 269*150812a8SEvalZero EXPORT UARTE0_UART0_IRQHandler [WEAK] 270*150812a8SEvalZero EXPORT SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler [WEAK] 271*150812a8SEvalZero EXPORT SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler [WEAK] 272*150812a8SEvalZero EXPORT NFCT_IRQHandler [WEAK] 273*150812a8SEvalZero EXPORT GPIOTE_IRQHandler [WEAK] 274*150812a8SEvalZero EXPORT SAADC_IRQHandler [WEAK] 275*150812a8SEvalZero EXPORT TIMER0_IRQHandler [WEAK] 276*150812a8SEvalZero EXPORT TIMER1_IRQHandler [WEAK] 277*150812a8SEvalZero EXPORT TIMER2_IRQHandler [WEAK] 278*150812a8SEvalZero EXPORT RTC0_IRQHandler [WEAK] 279*150812a8SEvalZero EXPORT TEMP_IRQHandler [WEAK] 280*150812a8SEvalZero EXPORT RNG_IRQHandler [WEAK] 281*150812a8SEvalZero EXPORT ECB_IRQHandler [WEAK] 282*150812a8SEvalZero EXPORT CCM_AAR_IRQHandler [WEAK] 283*150812a8SEvalZero EXPORT WDT_IRQHandler [WEAK] 284*150812a8SEvalZero EXPORT RTC1_IRQHandler [WEAK] 285*150812a8SEvalZero EXPORT QDEC_IRQHandler [WEAK] 286*150812a8SEvalZero EXPORT COMP_LPCOMP_IRQHandler [WEAK] 287*150812a8SEvalZero EXPORT SWI0_EGU0_IRQHandler [WEAK] 288*150812a8SEvalZero EXPORT SWI1_EGU1_IRQHandler [WEAK] 289*150812a8SEvalZero EXPORT SWI2_EGU2_IRQHandler [WEAK] 290*150812a8SEvalZero EXPORT SWI3_EGU3_IRQHandler [WEAK] 291*150812a8SEvalZero EXPORT SWI4_EGU4_IRQHandler [WEAK] 292*150812a8SEvalZero EXPORT SWI5_EGU5_IRQHandler [WEAK] 293*150812a8SEvalZero EXPORT TIMER3_IRQHandler [WEAK] 294*150812a8SEvalZero EXPORT TIMER4_IRQHandler [WEAK] 295*150812a8SEvalZero EXPORT PWM0_IRQHandler [WEAK] 296*150812a8SEvalZero EXPORT PDM_IRQHandler [WEAK] 297*150812a8SEvalZero EXPORT MWU_IRQHandler [WEAK] 298*150812a8SEvalZero EXPORT PWM1_IRQHandler [WEAK] 299*150812a8SEvalZero EXPORT PWM2_IRQHandler [WEAK] 300*150812a8SEvalZero EXPORT SPIM2_SPIS2_SPI2_IRQHandler [WEAK] 301*150812a8SEvalZero EXPORT RTC2_IRQHandler [WEAK] 302*150812a8SEvalZero EXPORT I2S_IRQHandler [WEAK] 303*150812a8SEvalZero EXPORT FPU_IRQHandler [WEAK] 304*150812a8SEvalZeroPOWER_CLOCK_IRQHandler 305*150812a8SEvalZeroRADIO_IRQHandler 306*150812a8SEvalZeroUARTE0_UART0_IRQHandler 307*150812a8SEvalZeroSPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler 308*150812a8SEvalZeroSPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler 309*150812a8SEvalZeroNFCT_IRQHandler 310*150812a8SEvalZeroGPIOTE_IRQHandler 311*150812a8SEvalZeroSAADC_IRQHandler 312*150812a8SEvalZeroTIMER0_IRQHandler 313*150812a8SEvalZeroTIMER1_IRQHandler 314*150812a8SEvalZeroTIMER2_IRQHandler 315*150812a8SEvalZeroRTC0_IRQHandler 316*150812a8SEvalZeroTEMP_IRQHandler 317*150812a8SEvalZeroRNG_IRQHandler 318*150812a8SEvalZeroECB_IRQHandler 319*150812a8SEvalZeroCCM_AAR_IRQHandler 320*150812a8SEvalZeroWDT_IRQHandler 321*150812a8SEvalZeroRTC1_IRQHandler 322*150812a8SEvalZeroQDEC_IRQHandler 323*150812a8SEvalZeroCOMP_LPCOMP_IRQHandler 324*150812a8SEvalZeroSWI0_EGU0_IRQHandler 325*150812a8SEvalZeroSWI1_EGU1_IRQHandler 326*150812a8SEvalZeroSWI2_EGU2_IRQHandler 327*150812a8SEvalZeroSWI3_EGU3_IRQHandler 328*150812a8SEvalZeroSWI4_EGU4_IRQHandler 329*150812a8SEvalZeroSWI5_EGU5_IRQHandler 330*150812a8SEvalZeroTIMER3_IRQHandler 331*150812a8SEvalZeroTIMER4_IRQHandler 332*150812a8SEvalZeroPWM0_IRQHandler 333*150812a8SEvalZeroPDM_IRQHandler 334*150812a8SEvalZeroMWU_IRQHandler 335*150812a8SEvalZeroPWM1_IRQHandler 336*150812a8SEvalZeroPWM2_IRQHandler 337*150812a8SEvalZeroSPIM2_SPIS2_SPI2_IRQHandler 338*150812a8SEvalZeroRTC2_IRQHandler 339*150812a8SEvalZeroI2S_IRQHandler 340*150812a8SEvalZeroFPU_IRQHandler 341*150812a8SEvalZero B . 342*150812a8SEvalZero ENDP 343*150812a8SEvalZero ALIGN 344*150812a8SEvalZero 345*150812a8SEvalZero; User Initial Stack & Heap 346*150812a8SEvalZero 347*150812a8SEvalZero IF :DEF:__MICROLIB 348*150812a8SEvalZero 349*150812a8SEvalZero EXPORT __initial_sp 350*150812a8SEvalZero EXPORT __heap_base 351*150812a8SEvalZero EXPORT __heap_limit 352*150812a8SEvalZero 353*150812a8SEvalZero ELSE 354*150812a8SEvalZero 355*150812a8SEvalZero IMPORT __use_two_region_memory 356*150812a8SEvalZero EXPORT __user_initial_stackheap 357*150812a8SEvalZero 358*150812a8SEvalZero__user_initial_stackheap PROC 359*150812a8SEvalZero 360*150812a8SEvalZero LDR R0, = Heap_Mem 361*150812a8SEvalZero LDR R1, = (Stack_Mem + Stack_Size) 362*150812a8SEvalZero LDR R2, = (Heap_Mem + Heap_Size) 363*150812a8SEvalZero LDR R3, = Stack_Mem 364*150812a8SEvalZero BX LR 365*150812a8SEvalZero ENDP 366*150812a8SEvalZero 367*150812a8SEvalZero ALIGN 368*150812a8SEvalZero 369*150812a8SEvalZero ENDIF 370*150812a8SEvalZero 371*150812a8SEvalZero END 372