1; Copyright (c) 2009-2018 ARM Limited. All rights reserved. 2; 3; SPDX-License-Identifier: Apache-2.0 4; 5; Licensed under the Apache License, Version 2.0 (the License); you may 6; not use this file except in compliance with the License. 7; You may obtain a copy of the License at 8; 9; www.apache.org/licenses/LICENSE-2.0 10; 11; Unless required by applicable law or agreed to in writing, software 12; distributed under the License is distributed on an AS IS BASIS, WITHOUT 13; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14; See the License for the specific language governing permissions and 15; limitations under the License. 16; 17; NOTICE: This file has been modified by Nordic Semiconductor ASA. 18 19 IF :DEF: __STARTUP_CONFIG 20#ifdef __STARTUP_CONFIG 21#include "startup_config.h" 22#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT 23#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3 24#endif 25#endif 26 ENDIF 27 28 IF :DEF: __STARTUP_CONFIG 29Stack_Size EQU __STARTUP_CONFIG_STACK_SIZE 30 ELIF :DEF: __STACK_SIZE 31Stack_Size EQU __STACK_SIZE 32 ELSE 33Stack_Size EQU 2048 34 ENDIF 35 36 IF :DEF: __STARTUP_CONFIG 37Stack_Align EQU __STARTUP_CONFIG_STACK_ALIGNEMENT 38 ELSE 39Stack_Align EQU 3 40 ENDIF 41 42 AREA STACK, NOINIT, READWRITE, ALIGN=Stack_Align 43Stack_Mem SPACE Stack_Size 44__initial_sp 45 46 IF :DEF: __STARTUP_CONFIG 47Heap_Size EQU __STARTUP_CONFIG_HEAP_SIZE 48 ELIF :DEF: __HEAP_SIZE 49Heap_Size EQU __HEAP_SIZE 50 ELSE 51Heap_Size EQU 2048 52 ENDIF 53 54 AREA HEAP, NOINIT, READWRITE, ALIGN=3 55__heap_base 56Heap_Mem SPACE Heap_Size 57__heap_limit 58 59 PRESERVE8 60 THUMB 61 62; Vector Table Mapped to Address 0 at Reset 63 64 AREA RESET, DATA, READONLY 65 EXPORT __Vectors 66 EXPORT __Vectors_End 67 EXPORT __Vectors_Size 68 69__Vectors DCD __initial_sp ; Top of Stack 70 DCD Reset_Handler 71 DCD NMI_Handler 72 DCD HardFault_Handler 73 DCD 0 ; Reserved 74 DCD 0 ; Reserved 75 DCD 0 ; Reserved 76 DCD 0 ; Reserved 77 DCD 0 ; Reserved 78 DCD 0 ; Reserved 79 DCD 0 ; Reserved 80 DCD SVC_Handler 81 DCD 0 ; Reserved 82 DCD 0 ; Reserved 83 DCD PendSV_Handler 84 DCD SysTick_Handler 85 86 ; External Interrupts 87 DCD POWER_CLOCK_IRQHandler 88 DCD RADIO_IRQHandler 89 DCD UART0_IRQHandler 90 DCD SPI0_TWI0_IRQHandler 91 DCD SPI1_TWI1_IRQHandler 92 DCD 0 ; Reserved 93 DCD GPIOTE_IRQHandler 94 DCD ADC_IRQHandler 95 DCD TIMER0_IRQHandler 96 DCD TIMER1_IRQHandler 97 DCD TIMER2_IRQHandler 98 DCD RTC0_IRQHandler 99 DCD TEMP_IRQHandler 100 DCD RNG_IRQHandler 101 DCD ECB_IRQHandler 102 DCD CCM_AAR_IRQHandler 103 DCD WDT_IRQHandler 104 DCD RTC1_IRQHandler 105 DCD QDEC_IRQHandler 106 DCD LPCOMP_IRQHandler 107 DCD SWI0_IRQHandler 108 DCD SWI1_IRQHandler 109 DCD SWI2_IRQHandler 110 DCD SWI3_IRQHandler 111 DCD SWI4_IRQHandler 112 DCD SWI5_IRQHandler 113 DCD 0 ; Reserved 114 DCD 0 ; Reserved 115 DCD 0 ; Reserved 116 DCD 0 ; Reserved 117 DCD 0 ; Reserved 118 DCD 0 ; Reserved 119 120__Vectors_End 121 122__Vectors_Size EQU __Vectors_End - __Vectors 123 124 AREA |.text|, CODE, READONLY 125 126; Reset Handler 127 128NRF_POWER_RAMON_ADDRESS EQU 0x40000524 ; NRF_POWER->RAMON address 129NRF_POWER_RAMONB_ADDRESS EQU 0x40000554 ; NRF_POWER->RAMONB address 130NRF_POWER_RAMONx_RAMxON_ONMODE_Msk EQU 0x3 ; All RAM blocks on in onmode bit mask 131 132Reset_Handler PROC 133 EXPORT Reset_Handler [WEAK] 134 IMPORT SystemInit 135 IMPORT __main 136 137 MOVS R1, #NRF_POWER_RAMONx_RAMxON_ONMODE_Msk 138 139 LDR R0, =NRF_POWER_RAMON_ADDRESS 140 LDR R2, [R0] 141 ORRS R2, R2, R1 142 STR R2, [R0] 143 144 LDR R0, =NRF_POWER_RAMONB_ADDRESS 145 LDR R2, [R0] 146 ORRS R2, R2, R1 147 STR R2, [R0] 148 149 LDR R0, =SystemInit 150 BLX R0 151 LDR R0, =__main 152 BX R0 153 ENDP 154 155; Dummy Exception Handlers (infinite loops which can be modified) 156 157NMI_Handler PROC 158 EXPORT NMI_Handler [WEAK] 159 B . 160 ENDP 161HardFault_Handler\ 162 PROC 163 EXPORT HardFault_Handler [WEAK] 164 B . 165 ENDP 166SVC_Handler PROC 167 EXPORT SVC_Handler [WEAK] 168 B . 169 ENDP 170PendSV_Handler PROC 171 EXPORT PendSV_Handler [WEAK] 172 B . 173 ENDP 174SysTick_Handler PROC 175 EXPORT SysTick_Handler [WEAK] 176 B . 177 ENDP 178 179Default_Handler PROC 180 181 EXPORT POWER_CLOCK_IRQHandler [WEAK] 182 EXPORT RADIO_IRQHandler [WEAK] 183 EXPORT UART0_IRQHandler [WEAK] 184 EXPORT SPI0_TWI0_IRQHandler [WEAK] 185 EXPORT SPI1_TWI1_IRQHandler [WEAK] 186 EXPORT GPIOTE_IRQHandler [WEAK] 187 EXPORT ADC_IRQHandler [WEAK] 188 EXPORT TIMER0_IRQHandler [WEAK] 189 EXPORT TIMER1_IRQHandler [WEAK] 190 EXPORT TIMER2_IRQHandler [WEAK] 191 EXPORT RTC0_IRQHandler [WEAK] 192 EXPORT TEMP_IRQHandler [WEAK] 193 EXPORT RNG_IRQHandler [WEAK] 194 EXPORT ECB_IRQHandler [WEAK] 195 EXPORT CCM_AAR_IRQHandler [WEAK] 196 EXPORT WDT_IRQHandler [WEAK] 197 EXPORT RTC1_IRQHandler [WEAK] 198 EXPORT QDEC_IRQHandler [WEAK] 199 EXPORT LPCOMP_IRQHandler [WEAK] 200 EXPORT SWI0_IRQHandler [WEAK] 201 EXPORT SWI1_IRQHandler [WEAK] 202 EXPORT SWI2_IRQHandler [WEAK] 203 EXPORT SWI3_IRQHandler [WEAK] 204 EXPORT SWI4_IRQHandler [WEAK] 205 EXPORT SWI5_IRQHandler [WEAK] 206POWER_CLOCK_IRQHandler 207RADIO_IRQHandler 208UART0_IRQHandler 209SPI0_TWI0_IRQHandler 210SPI1_TWI1_IRQHandler 211GPIOTE_IRQHandler 212ADC_IRQHandler 213TIMER0_IRQHandler 214TIMER1_IRQHandler 215TIMER2_IRQHandler 216RTC0_IRQHandler 217TEMP_IRQHandler 218RNG_IRQHandler 219ECB_IRQHandler 220CCM_AAR_IRQHandler 221WDT_IRQHandler 222RTC1_IRQHandler 223QDEC_IRQHandler 224LPCOMP_IRQHandler 225SWI0_IRQHandler 226SWI1_IRQHandler 227SWI2_IRQHandler 228SWI3_IRQHandler 229SWI4_IRQHandler 230SWI5_IRQHandler 231 B . 232 ENDP 233 ALIGN 234 235; User Initial Stack & Heap 236 237 IF :DEF:__MICROLIB 238 239 EXPORT __initial_sp 240 EXPORT __heap_base 241 EXPORT __heap_limit 242 243 ELSE 244 245 IMPORT __use_two_region_memory 246 EXPORT __user_initial_stackheap 247 248__user_initial_stackheap PROC 249 250 LDR R0, = Heap_Mem 251 LDR R1, = (Stack_Mem + Stack_Size) 252 LDR R2, = (Heap_Mem + Heap_Size) 253 LDR R3, = Stack_Mem 254 BX LR 255 ENDP 256 257 ALIGN 258 259 ENDIF 260 261 END 262