1*150812a8SEvalZero; Copyright (c) 2009-2018 ARM Limited. All rights reserved. 2*150812a8SEvalZero; 3*150812a8SEvalZero; SPDX-License-Identifier: Apache-2.0 4*150812a8SEvalZero; 5*150812a8SEvalZero; Licensed under the Apache License, Version 2.0 (the License); you may 6*150812a8SEvalZero; not use this file except in compliance with the License. 7*150812a8SEvalZero; You may obtain a copy of the License at 8*150812a8SEvalZero; 9*150812a8SEvalZero; www.apache.org/licenses/LICENSE-2.0 10*150812a8SEvalZero; 11*150812a8SEvalZero; Unless required by applicable law or agreed to in writing, software 12*150812a8SEvalZero; distributed under the License is distributed on an AS IS BASIS, WITHOUT 13*150812a8SEvalZero; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14*150812a8SEvalZero; See the License for the specific language governing permissions and 15*150812a8SEvalZero; limitations under the License. 16*150812a8SEvalZero; 17*150812a8SEvalZero; NOTICE: This file has been modified by Nordic Semiconductor ASA. 18*150812a8SEvalZero 19*150812a8SEvalZero IF :DEF: __STARTUP_CONFIG 20*150812a8SEvalZero#ifdef __STARTUP_CONFIG 21*150812a8SEvalZero#include "startup_config.h" 22*150812a8SEvalZero#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT 23*150812a8SEvalZero#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3 24*150812a8SEvalZero#endif 25*150812a8SEvalZero#endif 26*150812a8SEvalZero ENDIF 27*150812a8SEvalZero 28*150812a8SEvalZero IF :DEF: __STARTUP_CONFIG 29*150812a8SEvalZeroStack_Size EQU __STARTUP_CONFIG_STACK_SIZE 30*150812a8SEvalZero ELIF :DEF: __STACK_SIZE 31*150812a8SEvalZeroStack_Size EQU __STACK_SIZE 32*150812a8SEvalZero ELSE 33*150812a8SEvalZeroStack_Size EQU 2048 34*150812a8SEvalZero ENDIF 35*150812a8SEvalZero 36*150812a8SEvalZero IF :DEF: __STARTUP_CONFIG 37*150812a8SEvalZeroStack_Align EQU __STARTUP_CONFIG_STACK_ALIGNEMENT 38*150812a8SEvalZero ELSE 39*150812a8SEvalZeroStack_Align EQU 3 40*150812a8SEvalZero ENDIF 41*150812a8SEvalZero 42*150812a8SEvalZero AREA STACK, NOINIT, READWRITE, ALIGN=Stack_Align 43*150812a8SEvalZeroStack_Mem SPACE Stack_Size 44*150812a8SEvalZero__initial_sp 45*150812a8SEvalZero 46*150812a8SEvalZero IF :DEF: __STARTUP_CONFIG 47*150812a8SEvalZeroHeap_Size EQU __STARTUP_CONFIG_HEAP_SIZE 48*150812a8SEvalZero ELIF :DEF: __HEAP_SIZE 49*150812a8SEvalZeroHeap_Size EQU __HEAP_SIZE 50*150812a8SEvalZero ELSE 51*150812a8SEvalZeroHeap_Size EQU 2048 52*150812a8SEvalZero ENDIF 53*150812a8SEvalZero 54*150812a8SEvalZero AREA HEAP, NOINIT, READWRITE, ALIGN=3 55*150812a8SEvalZero__heap_base 56*150812a8SEvalZeroHeap_Mem SPACE Heap_Size 57*150812a8SEvalZero__heap_limit 58*150812a8SEvalZero 59*150812a8SEvalZero PRESERVE8 60*150812a8SEvalZero THUMB 61*150812a8SEvalZero 62*150812a8SEvalZero; Vector Table Mapped to Address 0 at Reset 63*150812a8SEvalZero 64*150812a8SEvalZero AREA RESET, DATA, READONLY 65*150812a8SEvalZero EXPORT __Vectors 66*150812a8SEvalZero EXPORT __Vectors_End 67*150812a8SEvalZero EXPORT __Vectors_Size 68*150812a8SEvalZero 69*150812a8SEvalZero__Vectors DCD __initial_sp ; Top of Stack 70*150812a8SEvalZero DCD Reset_Handler 71*150812a8SEvalZero DCD NMI_Handler 72*150812a8SEvalZero DCD HardFault_Handler 73*150812a8SEvalZero DCD 0 ; Reserved 74*150812a8SEvalZero DCD 0 ; Reserved 75*150812a8SEvalZero DCD 0 ; Reserved 76*150812a8SEvalZero DCD 0 ; Reserved 77*150812a8SEvalZero DCD 0 ; Reserved 78*150812a8SEvalZero DCD 0 ; Reserved 79*150812a8SEvalZero DCD 0 ; Reserved 80*150812a8SEvalZero DCD SVC_Handler 81*150812a8SEvalZero DCD 0 ; Reserved 82*150812a8SEvalZero DCD 0 ; Reserved 83*150812a8SEvalZero DCD PendSV_Handler 84*150812a8SEvalZero DCD SysTick_Handler 85*150812a8SEvalZero 86*150812a8SEvalZero ; External Interrupts 87*150812a8SEvalZero DCD POWER_CLOCK_IRQHandler 88*150812a8SEvalZero DCD RADIO_IRQHandler 89*150812a8SEvalZero DCD UART0_IRQHandler 90*150812a8SEvalZero DCD SPI0_TWI0_IRQHandler 91*150812a8SEvalZero DCD SPI1_TWI1_IRQHandler 92*150812a8SEvalZero DCD 0 ; Reserved 93*150812a8SEvalZero DCD GPIOTE_IRQHandler 94*150812a8SEvalZero DCD ADC_IRQHandler 95*150812a8SEvalZero DCD TIMER0_IRQHandler 96*150812a8SEvalZero DCD TIMER1_IRQHandler 97*150812a8SEvalZero DCD TIMER2_IRQHandler 98*150812a8SEvalZero DCD RTC0_IRQHandler 99*150812a8SEvalZero DCD TEMP_IRQHandler 100*150812a8SEvalZero DCD RNG_IRQHandler 101*150812a8SEvalZero DCD ECB_IRQHandler 102*150812a8SEvalZero DCD CCM_AAR_IRQHandler 103*150812a8SEvalZero DCD WDT_IRQHandler 104*150812a8SEvalZero DCD RTC1_IRQHandler 105*150812a8SEvalZero DCD QDEC_IRQHandler 106*150812a8SEvalZero DCD LPCOMP_IRQHandler 107*150812a8SEvalZero DCD SWI0_IRQHandler 108*150812a8SEvalZero DCD SWI1_IRQHandler 109*150812a8SEvalZero DCD SWI2_IRQHandler 110*150812a8SEvalZero DCD SWI3_IRQHandler 111*150812a8SEvalZero DCD SWI4_IRQHandler 112*150812a8SEvalZero DCD SWI5_IRQHandler 113*150812a8SEvalZero DCD 0 ; Reserved 114*150812a8SEvalZero DCD 0 ; Reserved 115*150812a8SEvalZero DCD 0 ; Reserved 116*150812a8SEvalZero DCD 0 ; Reserved 117*150812a8SEvalZero DCD 0 ; Reserved 118*150812a8SEvalZero DCD 0 ; Reserved 119*150812a8SEvalZero 120*150812a8SEvalZero__Vectors_End 121*150812a8SEvalZero 122*150812a8SEvalZero__Vectors_Size EQU __Vectors_End - __Vectors 123*150812a8SEvalZero 124*150812a8SEvalZero AREA |.text|, CODE, READONLY 125*150812a8SEvalZero 126*150812a8SEvalZero; Reset Handler 127*150812a8SEvalZero 128*150812a8SEvalZeroNRF_POWER_RAMON_ADDRESS EQU 0x40000524 ; NRF_POWER->RAMON address 129*150812a8SEvalZeroNRF_POWER_RAMONB_ADDRESS EQU 0x40000554 ; NRF_POWER->RAMONB address 130*150812a8SEvalZeroNRF_POWER_RAMONx_RAMxON_ONMODE_Msk EQU 0x3 ; All RAM blocks on in onmode bit mask 131*150812a8SEvalZero 132*150812a8SEvalZeroReset_Handler PROC 133*150812a8SEvalZero EXPORT Reset_Handler [WEAK] 134*150812a8SEvalZero IMPORT SystemInit 135*150812a8SEvalZero IMPORT __main 136*150812a8SEvalZero 137*150812a8SEvalZero MOVS R1, #NRF_POWER_RAMONx_RAMxON_ONMODE_Msk 138*150812a8SEvalZero 139*150812a8SEvalZero LDR R0, =NRF_POWER_RAMON_ADDRESS 140*150812a8SEvalZero LDR R2, [R0] 141*150812a8SEvalZero ORRS R2, R2, R1 142*150812a8SEvalZero STR R2, [R0] 143*150812a8SEvalZero 144*150812a8SEvalZero LDR R0, =NRF_POWER_RAMONB_ADDRESS 145*150812a8SEvalZero LDR R2, [R0] 146*150812a8SEvalZero ORRS R2, R2, R1 147*150812a8SEvalZero STR R2, [R0] 148*150812a8SEvalZero 149*150812a8SEvalZero LDR R0, =SystemInit 150*150812a8SEvalZero BLX R0 151*150812a8SEvalZero LDR R0, =__main 152*150812a8SEvalZero BX R0 153*150812a8SEvalZero ENDP 154*150812a8SEvalZero 155*150812a8SEvalZero; Dummy Exception Handlers (infinite loops which can be modified) 156*150812a8SEvalZero 157*150812a8SEvalZeroNMI_Handler PROC 158*150812a8SEvalZero EXPORT NMI_Handler [WEAK] 159*150812a8SEvalZero B . 160*150812a8SEvalZero ENDP 161*150812a8SEvalZeroHardFault_Handler\ 162*150812a8SEvalZero PROC 163*150812a8SEvalZero EXPORT HardFault_Handler [WEAK] 164*150812a8SEvalZero B . 165*150812a8SEvalZero ENDP 166*150812a8SEvalZeroSVC_Handler PROC 167*150812a8SEvalZero EXPORT SVC_Handler [WEAK] 168*150812a8SEvalZero B . 169*150812a8SEvalZero ENDP 170*150812a8SEvalZeroPendSV_Handler PROC 171*150812a8SEvalZero EXPORT PendSV_Handler [WEAK] 172*150812a8SEvalZero B . 173*150812a8SEvalZero ENDP 174*150812a8SEvalZeroSysTick_Handler PROC 175*150812a8SEvalZero EXPORT SysTick_Handler [WEAK] 176*150812a8SEvalZero B . 177*150812a8SEvalZero ENDP 178*150812a8SEvalZero 179*150812a8SEvalZeroDefault_Handler PROC 180*150812a8SEvalZero 181*150812a8SEvalZero EXPORT POWER_CLOCK_IRQHandler [WEAK] 182*150812a8SEvalZero EXPORT RADIO_IRQHandler [WEAK] 183*150812a8SEvalZero EXPORT UART0_IRQHandler [WEAK] 184*150812a8SEvalZero EXPORT SPI0_TWI0_IRQHandler [WEAK] 185*150812a8SEvalZero EXPORT SPI1_TWI1_IRQHandler [WEAK] 186*150812a8SEvalZero EXPORT GPIOTE_IRQHandler [WEAK] 187*150812a8SEvalZero EXPORT ADC_IRQHandler [WEAK] 188*150812a8SEvalZero EXPORT TIMER0_IRQHandler [WEAK] 189*150812a8SEvalZero EXPORT TIMER1_IRQHandler [WEAK] 190*150812a8SEvalZero EXPORT TIMER2_IRQHandler [WEAK] 191*150812a8SEvalZero EXPORT RTC0_IRQHandler [WEAK] 192*150812a8SEvalZero EXPORT TEMP_IRQHandler [WEAK] 193*150812a8SEvalZero EXPORT RNG_IRQHandler [WEAK] 194*150812a8SEvalZero EXPORT ECB_IRQHandler [WEAK] 195*150812a8SEvalZero EXPORT CCM_AAR_IRQHandler [WEAK] 196*150812a8SEvalZero EXPORT WDT_IRQHandler [WEAK] 197*150812a8SEvalZero EXPORT RTC1_IRQHandler [WEAK] 198*150812a8SEvalZero EXPORT QDEC_IRQHandler [WEAK] 199*150812a8SEvalZero EXPORT LPCOMP_IRQHandler [WEAK] 200*150812a8SEvalZero EXPORT SWI0_IRQHandler [WEAK] 201*150812a8SEvalZero EXPORT SWI1_IRQHandler [WEAK] 202*150812a8SEvalZero EXPORT SWI2_IRQHandler [WEAK] 203*150812a8SEvalZero EXPORT SWI3_IRQHandler [WEAK] 204*150812a8SEvalZero EXPORT SWI4_IRQHandler [WEAK] 205*150812a8SEvalZero EXPORT SWI5_IRQHandler [WEAK] 206*150812a8SEvalZeroPOWER_CLOCK_IRQHandler 207*150812a8SEvalZeroRADIO_IRQHandler 208*150812a8SEvalZeroUART0_IRQHandler 209*150812a8SEvalZeroSPI0_TWI0_IRQHandler 210*150812a8SEvalZeroSPI1_TWI1_IRQHandler 211*150812a8SEvalZeroGPIOTE_IRQHandler 212*150812a8SEvalZeroADC_IRQHandler 213*150812a8SEvalZeroTIMER0_IRQHandler 214*150812a8SEvalZeroTIMER1_IRQHandler 215*150812a8SEvalZeroTIMER2_IRQHandler 216*150812a8SEvalZeroRTC0_IRQHandler 217*150812a8SEvalZeroTEMP_IRQHandler 218*150812a8SEvalZeroRNG_IRQHandler 219*150812a8SEvalZeroECB_IRQHandler 220*150812a8SEvalZeroCCM_AAR_IRQHandler 221*150812a8SEvalZeroWDT_IRQHandler 222*150812a8SEvalZeroRTC1_IRQHandler 223*150812a8SEvalZeroQDEC_IRQHandler 224*150812a8SEvalZeroLPCOMP_IRQHandler 225*150812a8SEvalZeroSWI0_IRQHandler 226*150812a8SEvalZeroSWI1_IRQHandler 227*150812a8SEvalZeroSWI2_IRQHandler 228*150812a8SEvalZeroSWI3_IRQHandler 229*150812a8SEvalZeroSWI4_IRQHandler 230*150812a8SEvalZeroSWI5_IRQHandler 231*150812a8SEvalZero B . 232*150812a8SEvalZero ENDP 233*150812a8SEvalZero ALIGN 234*150812a8SEvalZero 235*150812a8SEvalZero; User Initial Stack & Heap 236*150812a8SEvalZero 237*150812a8SEvalZero IF :DEF:__MICROLIB 238*150812a8SEvalZero 239*150812a8SEvalZero EXPORT __initial_sp 240*150812a8SEvalZero EXPORT __heap_base 241*150812a8SEvalZero EXPORT __heap_limit 242*150812a8SEvalZero 243*150812a8SEvalZero ELSE 244*150812a8SEvalZero 245*150812a8SEvalZero IMPORT __use_two_region_memory 246*150812a8SEvalZero EXPORT __user_initial_stackheap 247*150812a8SEvalZero 248*150812a8SEvalZero__user_initial_stackheap PROC 249*150812a8SEvalZero 250*150812a8SEvalZero LDR R0, = Heap_Mem 251*150812a8SEvalZero LDR R1, = (Stack_Mem + Stack_Size) 252*150812a8SEvalZero LDR R2, = (Heap_Mem + Heap_Size) 253*150812a8SEvalZero LDR R3, = Stack_Mem 254*150812a8SEvalZero BX LR 255*150812a8SEvalZero ENDP 256*150812a8SEvalZero 257*150812a8SEvalZero ALIGN 258*150812a8SEvalZero 259*150812a8SEvalZero ENDIF 260*150812a8SEvalZero 261*150812a8SEvalZero END 262