1*150812a8SEvalZero /*
2*150812a8SEvalZero * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
3*150812a8SEvalZero * All rights reserved.
4*150812a8SEvalZero *
5*150812a8SEvalZero * Redistribution and use in source and binary forms, with or without
6*150812a8SEvalZero * modification, are permitted provided that the following conditions are met:
7*150812a8SEvalZero *
8*150812a8SEvalZero * 1. Redistributions of source code must retain the above copyright notice, this
9*150812a8SEvalZero * list of conditions and the following disclaimer.
10*150812a8SEvalZero *
11*150812a8SEvalZero * 2. Redistributions in binary form must reproduce the above copyright
12*150812a8SEvalZero * notice, this list of conditions and the following disclaimer in the
13*150812a8SEvalZero * documentation and/or other materials provided with the distribution.
14*150812a8SEvalZero *
15*150812a8SEvalZero * 3. Neither the name of the copyright holder nor the names of its
16*150812a8SEvalZero * contributors may be used to endorse or promote products derived from this
17*150812a8SEvalZero * software without specific prior written permission.
18*150812a8SEvalZero *
19*150812a8SEvalZero * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20*150812a8SEvalZero * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21*150812a8SEvalZero * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22*150812a8SEvalZero * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23*150812a8SEvalZero * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24*150812a8SEvalZero * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25*150812a8SEvalZero * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26*150812a8SEvalZero * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27*150812a8SEvalZero * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28*150812a8SEvalZero * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29*150812a8SEvalZero * POSSIBILITY OF SUCH DAMAGE.
30*150812a8SEvalZero */
31*150812a8SEvalZero
32*150812a8SEvalZero #ifndef NRF_WDT_H__
33*150812a8SEvalZero #define NRF_WDT_H__
34*150812a8SEvalZero
35*150812a8SEvalZero #include <nrfx.h>
36*150812a8SEvalZero
37*150812a8SEvalZero #ifdef __cplusplus
38*150812a8SEvalZero extern "C" {
39*150812a8SEvalZero #endif
40*150812a8SEvalZero
41*150812a8SEvalZero /**
42*150812a8SEvalZero * @defgroup nrf_wdt_hal WDT HAL
43*150812a8SEvalZero * @{
44*150812a8SEvalZero * @ingroup nrf_wdt
45*150812a8SEvalZero * @brief Hardware access layer for managing the Watchdog Timer (WDT) peripheral.
46*150812a8SEvalZero */
47*150812a8SEvalZero
48*150812a8SEvalZero #define NRF_WDT_CHANNEL_NUMBER 0x8UL
49*150812a8SEvalZero #define NRF_WDT_RR_VALUE 0x6E524635UL /* Fixed value, shouldn't be modified.*/
50*150812a8SEvalZero
51*150812a8SEvalZero #define NRF_WDT_TASK_SET 1UL
52*150812a8SEvalZero #define NRF_WDT_EVENT_CLEAR 0UL
53*150812a8SEvalZero
54*150812a8SEvalZero /**
55*150812a8SEvalZero * @enum nrf_wdt_task_t
56*150812a8SEvalZero * @brief WDT tasks.
57*150812a8SEvalZero */
58*150812a8SEvalZero typedef enum
59*150812a8SEvalZero {
60*150812a8SEvalZero /*lint -save -e30 -esym(628,__INTADDR__)*/
61*150812a8SEvalZero NRF_WDT_TASK_START = offsetof(NRF_WDT_Type, TASKS_START), /**< Task for starting WDT. */
62*150812a8SEvalZero /*lint -restore*/
63*150812a8SEvalZero } nrf_wdt_task_t;
64*150812a8SEvalZero
65*150812a8SEvalZero /**
66*150812a8SEvalZero * @enum nrf_wdt_event_t
67*150812a8SEvalZero * @brief WDT events.
68*150812a8SEvalZero */
69*150812a8SEvalZero typedef enum
70*150812a8SEvalZero {
71*150812a8SEvalZero /*lint -save -e30*/
72*150812a8SEvalZero NRF_WDT_EVENT_TIMEOUT = offsetof(NRF_WDT_Type, EVENTS_TIMEOUT), /**< Event from WDT time-out. */
73*150812a8SEvalZero /*lint -restore*/
74*150812a8SEvalZero } nrf_wdt_event_t;
75*150812a8SEvalZero
76*150812a8SEvalZero /**
77*150812a8SEvalZero * @enum nrf_wdt_behaviour_t
78*150812a8SEvalZero * @brief WDT behavior in CPU SLEEP or HALT mode.
79*150812a8SEvalZero */
80*150812a8SEvalZero typedef enum
81*150812a8SEvalZero {
82*150812a8SEvalZero NRF_WDT_BEHAVIOUR_RUN_SLEEP = WDT_CONFIG_SLEEP_Msk, /**< WDT will run when CPU is in SLEEP mode. */
83*150812a8SEvalZero NRF_WDT_BEHAVIOUR_RUN_HALT = WDT_CONFIG_HALT_Msk, /**< WDT will run when CPU is in HALT mode. */
84*150812a8SEvalZero NRF_WDT_BEHAVIOUR_RUN_SLEEP_HALT = WDT_CONFIG_SLEEP_Msk | WDT_CONFIG_HALT_Msk, /**< WDT will run when CPU is in SLEEP or HALT mode. */
85*150812a8SEvalZero NRF_WDT_BEHAVIOUR_PAUSE_SLEEP_HALT = 0, /**< WDT will be paused when CPU is in SLEEP or HALT mode. */
86*150812a8SEvalZero } nrf_wdt_behaviour_t;
87*150812a8SEvalZero
88*150812a8SEvalZero /**
89*150812a8SEvalZero * @enum nrf_wdt_rr_register_t
90*150812a8SEvalZero * @brief WDT reload request registers.
91*150812a8SEvalZero */
92*150812a8SEvalZero typedef enum
93*150812a8SEvalZero {
94*150812a8SEvalZero NRF_WDT_RR0 = 0, /**< Reload request register 0. */
95*150812a8SEvalZero NRF_WDT_RR1, /**< Reload request register 1. */
96*150812a8SEvalZero NRF_WDT_RR2, /**< Reload request register 2. */
97*150812a8SEvalZero NRF_WDT_RR3, /**< Reload request register 3. */
98*150812a8SEvalZero NRF_WDT_RR4, /**< Reload request register 4. */
99*150812a8SEvalZero NRF_WDT_RR5, /**< Reload request register 5. */
100*150812a8SEvalZero NRF_WDT_RR6, /**< Reload request register 6. */
101*150812a8SEvalZero NRF_WDT_RR7 /**< Reload request register 7. */
102*150812a8SEvalZero } nrf_wdt_rr_register_t;
103*150812a8SEvalZero
104*150812a8SEvalZero /**
105*150812a8SEvalZero * @enum nrf_wdt_int_mask_t
106*150812a8SEvalZero * @brief WDT interrupts.
107*150812a8SEvalZero */
108*150812a8SEvalZero typedef enum
109*150812a8SEvalZero {
110*150812a8SEvalZero NRF_WDT_INT_TIMEOUT_MASK = WDT_INTENSET_TIMEOUT_Msk, /**< WDT interrupt from time-out event. */
111*150812a8SEvalZero } nrf_wdt_int_mask_t;
112*150812a8SEvalZero
113*150812a8SEvalZero /**
114*150812a8SEvalZero * @brief Function for configuring the watchdog behavior when the CPU is sleeping or halted.
115*150812a8SEvalZero *
116*150812a8SEvalZero * @param behaviour Watchdog behavior when CPU is in SLEEP or HALT mode.
117*150812a8SEvalZero */
118*150812a8SEvalZero __STATIC_INLINE void nrf_wdt_behaviour_set(nrf_wdt_behaviour_t behaviour);
119*150812a8SEvalZero
120*150812a8SEvalZero /**
121*150812a8SEvalZero * @brief Function for starting the WDT task.
122*150812a8SEvalZero *
123*150812a8SEvalZero * @param[in] task Task.
124*150812a8SEvalZero */
125*150812a8SEvalZero __STATIC_INLINE void nrf_wdt_task_trigger(nrf_wdt_task_t task);
126*150812a8SEvalZero
127*150812a8SEvalZero /**
128*150812a8SEvalZero * @brief Function for clearing the WDT event.
129*150812a8SEvalZero *
130*150812a8SEvalZero * @param[in] event Event.
131*150812a8SEvalZero */
132*150812a8SEvalZero __STATIC_INLINE void nrf_wdt_event_clear(nrf_wdt_event_t event);
133*150812a8SEvalZero
134*150812a8SEvalZero /**
135*150812a8SEvalZero * @brief Function for retrieving the state of the WDT event.
136*150812a8SEvalZero *
137*150812a8SEvalZero * @param[in] event Event.
138*150812a8SEvalZero *
139*150812a8SEvalZero * @retval true If the event is set.
140*150812a8SEvalZero * @retval false If the event is not set.
141*150812a8SEvalZero */
142*150812a8SEvalZero __STATIC_INLINE bool nrf_wdt_event_check(nrf_wdt_event_t event);
143*150812a8SEvalZero
144*150812a8SEvalZero /**
145*150812a8SEvalZero * @brief Function for enabling a specific interrupt.
146*150812a8SEvalZero *
147*150812a8SEvalZero * @param[in] int_mask Interrupt.
148*150812a8SEvalZero */
149*150812a8SEvalZero __STATIC_INLINE void nrf_wdt_int_enable(uint32_t int_mask);
150*150812a8SEvalZero
151*150812a8SEvalZero /**
152*150812a8SEvalZero * @brief Function for retrieving the state of given interrupt.
153*150812a8SEvalZero *
154*150812a8SEvalZero * @param[in] int_mask Interrupt.
155*150812a8SEvalZero *
156*150812a8SEvalZero * @retval true Interrupt is enabled.
157*150812a8SEvalZero * @retval false Interrupt is not enabled.
158*150812a8SEvalZero */
159*150812a8SEvalZero __STATIC_INLINE bool nrf_wdt_int_enable_check(uint32_t int_mask);
160*150812a8SEvalZero
161*150812a8SEvalZero /**
162*150812a8SEvalZero * @brief Function for disabling a specific interrupt.
163*150812a8SEvalZero *
164*150812a8SEvalZero * @param[in] int_mask Interrupt.
165*150812a8SEvalZero */
166*150812a8SEvalZero __STATIC_INLINE void nrf_wdt_int_disable(uint32_t int_mask);
167*150812a8SEvalZero
168*150812a8SEvalZero #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
169*150812a8SEvalZero /**
170*150812a8SEvalZero * @brief Function for setting the subscribe configuration for a given
171*150812a8SEvalZero * WDT task.
172*150812a8SEvalZero *
173*150812a8SEvalZero * @param[in] task Task for which to set the configuration.
174*150812a8SEvalZero * @param[in] channel Channel through which to subscribe events.
175*150812a8SEvalZero */
176*150812a8SEvalZero __STATIC_INLINE void nrf_wdt_subscribe_set(nrf_wdt_task_t task,
177*150812a8SEvalZero uint8_t channel);
178*150812a8SEvalZero
179*150812a8SEvalZero /**
180*150812a8SEvalZero * @brief Function for clearing the subscribe configuration for a given
181*150812a8SEvalZero * WDT task.
182*150812a8SEvalZero *
183*150812a8SEvalZero * @param[in] task Task for which to clear the configuration.
184*150812a8SEvalZero */
185*150812a8SEvalZero __STATIC_INLINE void nrf_wdt_subscribe_clear(nrf_wdt_task_t task);
186*150812a8SEvalZero
187*150812a8SEvalZero /**
188*150812a8SEvalZero * @brief Function for setting the publish configuration for a given
189*150812a8SEvalZero * WDT event.
190*150812a8SEvalZero *
191*150812a8SEvalZero * @param[in] event Event for which to set the configuration.
192*150812a8SEvalZero * @param[in] channel Channel through which to publish the event.
193*150812a8SEvalZero */
194*150812a8SEvalZero __STATIC_INLINE void nrf_wdt_publish_set(nrf_wdt_event_t event,
195*150812a8SEvalZero uint8_t channel);
196*150812a8SEvalZero
197*150812a8SEvalZero /**
198*150812a8SEvalZero * @brief Function for clearing the publish configuration for a given
199*150812a8SEvalZero * WDT event.
200*150812a8SEvalZero *
201*150812a8SEvalZero * @param[in] event Event for which to clear the configuration.
202*150812a8SEvalZero */
203*150812a8SEvalZero __STATIC_INLINE void nrf_wdt_publish_clear(nrf_wdt_event_t event);
204*150812a8SEvalZero #endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
205*150812a8SEvalZero
206*150812a8SEvalZero /**
207*150812a8SEvalZero * @brief Function for returning the address of a specific WDT task register.
208*150812a8SEvalZero *
209*150812a8SEvalZero * @param[in] task Task.
210*150812a8SEvalZero */
211*150812a8SEvalZero __STATIC_INLINE uint32_t nrf_wdt_task_address_get(nrf_wdt_task_t task);
212*150812a8SEvalZero
213*150812a8SEvalZero /**
214*150812a8SEvalZero * @brief Function for returning the address of a specific WDT event register.
215*150812a8SEvalZero *
216*150812a8SEvalZero * @param[in] event Event.
217*150812a8SEvalZero *
218*150812a8SEvalZero * @retval address of requested event register
219*150812a8SEvalZero */
220*150812a8SEvalZero __STATIC_INLINE uint32_t nrf_wdt_event_address_get(nrf_wdt_event_t event);
221*150812a8SEvalZero
222*150812a8SEvalZero /**
223*150812a8SEvalZero * @brief Function for retrieving the watchdog status.
224*150812a8SEvalZero *
225*150812a8SEvalZero * @retval true If the watchdog is started.
226*150812a8SEvalZero * @retval false If the watchdog is not started.
227*150812a8SEvalZero */
228*150812a8SEvalZero __STATIC_INLINE bool nrf_wdt_started(void);
229*150812a8SEvalZero
230*150812a8SEvalZero /**
231*150812a8SEvalZero * @brief Function for retrieving the watchdog reload request status.
232*150812a8SEvalZero *
233*150812a8SEvalZero * @param[in] rr_register Reload request register to check.
234*150812a8SEvalZero *
235*150812a8SEvalZero * @retval true If a reload request is running.
236*150812a8SEvalZero * @retval false If no reload request is running.
237*150812a8SEvalZero */
238*150812a8SEvalZero __STATIC_INLINE bool nrf_wdt_request_status(nrf_wdt_rr_register_t rr_register);
239*150812a8SEvalZero
240*150812a8SEvalZero /**
241*150812a8SEvalZero * @brief Function for setting the watchdog reload value.
242*150812a8SEvalZero *
243*150812a8SEvalZero * @param[in] reload_value Watchdog counter initial value.
244*150812a8SEvalZero */
245*150812a8SEvalZero __STATIC_INLINE void nrf_wdt_reload_value_set(uint32_t reload_value);
246*150812a8SEvalZero
247*150812a8SEvalZero /**
248*150812a8SEvalZero * @brief Function for retrieving the watchdog reload value.
249*150812a8SEvalZero *
250*150812a8SEvalZero * @retval Reload value.
251*150812a8SEvalZero */
252*150812a8SEvalZero __STATIC_INLINE uint32_t nrf_wdt_reload_value_get(void);
253*150812a8SEvalZero
254*150812a8SEvalZero /**
255*150812a8SEvalZero * @brief Function for enabling a specific reload request register.
256*150812a8SEvalZero *
257*150812a8SEvalZero * @param[in] rr_register Reload request register to enable.
258*150812a8SEvalZero */
259*150812a8SEvalZero __STATIC_INLINE void nrf_wdt_reload_request_enable(nrf_wdt_rr_register_t rr_register);
260*150812a8SEvalZero
261*150812a8SEvalZero /**
262*150812a8SEvalZero * @brief Function for disabling a specific reload request register.
263*150812a8SEvalZero *
264*150812a8SEvalZero * @param[in] rr_register Reload request register to disable.
265*150812a8SEvalZero */
266*150812a8SEvalZero __STATIC_INLINE void nrf_wdt_reload_request_disable(nrf_wdt_rr_register_t rr_register);
267*150812a8SEvalZero
268*150812a8SEvalZero /**
269*150812a8SEvalZero * @brief Function for retrieving the status of a specific reload request register.
270*150812a8SEvalZero *
271*150812a8SEvalZero * @param[in] rr_register Reload request register to check.
272*150812a8SEvalZero *
273*150812a8SEvalZero * @retval true If the reload request register is enabled.
274*150812a8SEvalZero * @retval false If the reload request register is not enabled.
275*150812a8SEvalZero */
276*150812a8SEvalZero __STATIC_INLINE bool nrf_wdt_reload_request_is_enabled(nrf_wdt_rr_register_t rr_register);
277*150812a8SEvalZero
278*150812a8SEvalZero /**
279*150812a8SEvalZero * @brief Function for setting a specific reload request register.
280*150812a8SEvalZero *
281*150812a8SEvalZero * @param[in] rr_register Reload request register to set.
282*150812a8SEvalZero */
283*150812a8SEvalZero __STATIC_INLINE void nrf_wdt_reload_request_set(nrf_wdt_rr_register_t rr_register);
284*150812a8SEvalZero
285*150812a8SEvalZero #ifndef SUPPRESS_INLINE_IMPLEMENTATION
286*150812a8SEvalZero
nrf_wdt_behaviour_set(nrf_wdt_behaviour_t behaviour)287*150812a8SEvalZero __STATIC_INLINE void nrf_wdt_behaviour_set(nrf_wdt_behaviour_t behaviour)
288*150812a8SEvalZero {
289*150812a8SEvalZero NRF_WDT->CONFIG = behaviour;
290*150812a8SEvalZero }
291*150812a8SEvalZero
nrf_wdt_task_trigger(nrf_wdt_task_t task)292*150812a8SEvalZero __STATIC_INLINE void nrf_wdt_task_trigger(nrf_wdt_task_t task)
293*150812a8SEvalZero {
294*150812a8SEvalZero *((volatile uint32_t *)((uint8_t *)NRF_WDT + task)) = NRF_WDT_TASK_SET;
295*150812a8SEvalZero }
296*150812a8SEvalZero
nrf_wdt_event_clear(nrf_wdt_event_t event)297*150812a8SEvalZero __STATIC_INLINE void nrf_wdt_event_clear(nrf_wdt_event_t event)
298*150812a8SEvalZero {
299*150812a8SEvalZero *((volatile uint32_t *)((uint8_t *)NRF_WDT + (uint32_t)event)) = NRF_WDT_EVENT_CLEAR;
300*150812a8SEvalZero #if __CORTEX_M == 0x04
301*150812a8SEvalZero volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_WDT + (uint32_t)event));
302*150812a8SEvalZero (void)dummy;
303*150812a8SEvalZero #endif
304*150812a8SEvalZero }
305*150812a8SEvalZero
nrf_wdt_event_check(nrf_wdt_event_t event)306*150812a8SEvalZero __STATIC_INLINE bool nrf_wdt_event_check(nrf_wdt_event_t event)
307*150812a8SEvalZero {
308*150812a8SEvalZero return (bool)*((volatile uint32_t *)((uint8_t *)NRF_WDT + event));
309*150812a8SEvalZero }
310*150812a8SEvalZero
nrf_wdt_int_enable(uint32_t int_mask)311*150812a8SEvalZero __STATIC_INLINE void nrf_wdt_int_enable(uint32_t int_mask)
312*150812a8SEvalZero {
313*150812a8SEvalZero NRF_WDT->INTENSET = int_mask;
314*150812a8SEvalZero }
315*150812a8SEvalZero
nrf_wdt_int_enable_check(uint32_t int_mask)316*150812a8SEvalZero __STATIC_INLINE bool nrf_wdt_int_enable_check(uint32_t int_mask)
317*150812a8SEvalZero {
318*150812a8SEvalZero return (bool)(NRF_WDT->INTENSET & int_mask);
319*150812a8SEvalZero }
320*150812a8SEvalZero
nrf_wdt_int_disable(uint32_t int_mask)321*150812a8SEvalZero __STATIC_INLINE void nrf_wdt_int_disable(uint32_t int_mask)
322*150812a8SEvalZero {
323*150812a8SEvalZero NRF_WDT->INTENCLR = int_mask;
324*150812a8SEvalZero }
325*150812a8SEvalZero
326*150812a8SEvalZero #if defined(DPPI_PRESENT)
nrf_wdt_subscribe_set(nrf_wdt_task_t task,uint8_t channel)327*150812a8SEvalZero __STATIC_INLINE void nrf_wdt_subscribe_set(nrf_wdt_task_t task,
328*150812a8SEvalZero uint8_t channel)
329*150812a8SEvalZero {
330*150812a8SEvalZero *((volatile uint32_t *) ((uint8_t *) NRF_WDT + (uint32_t) task + 0x80uL)) =
331*150812a8SEvalZero ((uint32_t)channel | WDT_SUBSCRIBE_START_EN_Msk);
332*150812a8SEvalZero }
333*150812a8SEvalZero
nrf_wdt_subscribe_clear(nrf_wdt_task_t task)334*150812a8SEvalZero __STATIC_INLINE void nrf_wdt_subscribe_clear(nrf_wdt_task_t task)
335*150812a8SEvalZero {
336*150812a8SEvalZero *((volatile uint32_t *) ((uint8_t *) NRF_WDT + (uint32_t) task + 0x80uL)) = 0;
337*150812a8SEvalZero }
338*150812a8SEvalZero
nrf_wdt_publish_set(nrf_wdt_event_t event,uint8_t channel)339*150812a8SEvalZero __STATIC_INLINE void nrf_wdt_publish_set(nrf_wdt_event_t event,
340*150812a8SEvalZero uint8_t channel)
341*150812a8SEvalZero {
342*150812a8SEvalZero *((volatile uint32_t *) ((uint8_t *) NRF_WDT + (uint32_t) event + 0x80uL)) =
343*150812a8SEvalZero ((uint32_t)channel | WDT_PUBLISH_TIMEOUT_EN_Msk);
344*150812a8SEvalZero }
345*150812a8SEvalZero
nrf_wdt_publish_clear(nrf_wdt_event_t event)346*150812a8SEvalZero __STATIC_INLINE void nrf_wdt_publish_clear(nrf_wdt_event_t event)
347*150812a8SEvalZero {
348*150812a8SEvalZero *((volatile uint32_t *) ((uint8_t *) NRF_WDT + (uint32_t) event + 0x80uL)) = 0;
349*150812a8SEvalZero }
350*150812a8SEvalZero #endif // defined(DPPI_PRESENT)
351*150812a8SEvalZero
nrf_wdt_task_address_get(nrf_wdt_task_t task)352*150812a8SEvalZero __STATIC_INLINE uint32_t nrf_wdt_task_address_get(nrf_wdt_task_t task)
353*150812a8SEvalZero {
354*150812a8SEvalZero return ((uint32_t)NRF_WDT + task);
355*150812a8SEvalZero }
356*150812a8SEvalZero
nrf_wdt_event_address_get(nrf_wdt_event_t event)357*150812a8SEvalZero __STATIC_INLINE uint32_t nrf_wdt_event_address_get(nrf_wdt_event_t event)
358*150812a8SEvalZero {
359*150812a8SEvalZero return ((uint32_t)NRF_WDT + event);
360*150812a8SEvalZero }
361*150812a8SEvalZero
nrf_wdt_started(void)362*150812a8SEvalZero __STATIC_INLINE bool nrf_wdt_started(void)
363*150812a8SEvalZero {
364*150812a8SEvalZero return (bool)(NRF_WDT->RUNSTATUS);
365*150812a8SEvalZero }
366*150812a8SEvalZero
nrf_wdt_request_status(nrf_wdt_rr_register_t rr_register)367*150812a8SEvalZero __STATIC_INLINE bool nrf_wdt_request_status(nrf_wdt_rr_register_t rr_register)
368*150812a8SEvalZero {
369*150812a8SEvalZero return (bool)(((NRF_WDT->REQSTATUS) >> rr_register) & 0x1UL);
370*150812a8SEvalZero }
371*150812a8SEvalZero
nrf_wdt_reload_value_set(uint32_t reload_value)372*150812a8SEvalZero __STATIC_INLINE void nrf_wdt_reload_value_set(uint32_t reload_value)
373*150812a8SEvalZero {
374*150812a8SEvalZero NRF_WDT->CRV = reload_value;
375*150812a8SEvalZero }
376*150812a8SEvalZero
nrf_wdt_reload_value_get(void)377*150812a8SEvalZero __STATIC_INLINE uint32_t nrf_wdt_reload_value_get(void)
378*150812a8SEvalZero {
379*150812a8SEvalZero return (uint32_t)NRF_WDT->CRV;
380*150812a8SEvalZero }
381*150812a8SEvalZero
nrf_wdt_reload_request_enable(nrf_wdt_rr_register_t rr_register)382*150812a8SEvalZero __STATIC_INLINE void nrf_wdt_reload_request_enable(nrf_wdt_rr_register_t rr_register)
383*150812a8SEvalZero {
384*150812a8SEvalZero NRF_WDT->RREN |= 0x1UL << rr_register;
385*150812a8SEvalZero }
386*150812a8SEvalZero
nrf_wdt_reload_request_disable(nrf_wdt_rr_register_t rr_register)387*150812a8SEvalZero __STATIC_INLINE void nrf_wdt_reload_request_disable(nrf_wdt_rr_register_t rr_register)
388*150812a8SEvalZero {
389*150812a8SEvalZero NRF_WDT->RREN &= ~(0x1UL << rr_register);
390*150812a8SEvalZero }
391*150812a8SEvalZero
nrf_wdt_reload_request_is_enabled(nrf_wdt_rr_register_t rr_register)392*150812a8SEvalZero __STATIC_INLINE bool nrf_wdt_reload_request_is_enabled(nrf_wdt_rr_register_t rr_register)
393*150812a8SEvalZero {
394*150812a8SEvalZero return (bool)(NRF_WDT->RREN & (0x1UL << rr_register));
395*150812a8SEvalZero }
396*150812a8SEvalZero
nrf_wdt_reload_request_set(nrf_wdt_rr_register_t rr_register)397*150812a8SEvalZero __STATIC_INLINE void nrf_wdt_reload_request_set(nrf_wdt_rr_register_t rr_register)
398*150812a8SEvalZero {
399*150812a8SEvalZero NRF_WDT->RR[rr_register] = NRF_WDT_RR_VALUE;
400*150812a8SEvalZero }
401*150812a8SEvalZero
402*150812a8SEvalZero #endif // SUPPRESS_INLINE_IMPLEMENTATION
403*150812a8SEvalZero
404*150812a8SEvalZero /** @} */
405*150812a8SEvalZero
406*150812a8SEvalZero #ifdef __cplusplus
407*150812a8SEvalZero }
408*150812a8SEvalZero #endif
409*150812a8SEvalZero
410*150812a8SEvalZero #endif // NRF_WDT_H__
411