1*150812a8SEvalZero /*
2*150812a8SEvalZero * Copyright (c) 2018, Nordic Semiconductor ASA
3*150812a8SEvalZero * All rights reserved.
4*150812a8SEvalZero *
5*150812a8SEvalZero * Redistribution and use in source and binary forms, with or without
6*150812a8SEvalZero * modification, are permitted provided that the following conditions are met:
7*150812a8SEvalZero *
8*150812a8SEvalZero * 1. Redistributions of source code must retain the above copyright notice, this
9*150812a8SEvalZero * list of conditions and the following disclaimer.
10*150812a8SEvalZero *
11*150812a8SEvalZero * 2. Redistributions in binary form must reproduce the above copyright
12*150812a8SEvalZero * notice, this list of conditions and the following disclaimer in the
13*150812a8SEvalZero * documentation and/or other materials provided with the distribution.
14*150812a8SEvalZero *
15*150812a8SEvalZero * 3. Neither the name of the copyright holder nor the names of its
16*150812a8SEvalZero * contributors may be used to endorse or promote products derived from this
17*150812a8SEvalZero * software without specific prior written permission.
18*150812a8SEvalZero *
19*150812a8SEvalZero * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20*150812a8SEvalZero * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21*150812a8SEvalZero * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22*150812a8SEvalZero * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23*150812a8SEvalZero * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24*150812a8SEvalZero * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25*150812a8SEvalZero * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26*150812a8SEvalZero * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27*150812a8SEvalZero * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28*150812a8SEvalZero * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29*150812a8SEvalZero * POSSIBILITY OF SUCH DAMAGE.
30*150812a8SEvalZero */
31*150812a8SEvalZero
32*150812a8SEvalZero #ifndef NRF_VMC_H__
33*150812a8SEvalZero #define NRF_VMC_H__
34*150812a8SEvalZero
35*150812a8SEvalZero #include <nrfx.h>
36*150812a8SEvalZero
37*150812a8SEvalZero #ifdef __cplusplus
38*150812a8SEvalZero extern "C" {
39*150812a8SEvalZero #endif
40*150812a8SEvalZero
41*150812a8SEvalZero /**
42*150812a8SEvalZero * @defgroup nrf_vmc_hal VMC HAL
43*150812a8SEvalZero * @{
44*150812a8SEvalZero * @ingroup nrf_vmc
45*150812a8SEvalZero * @brief Hardware access layer for managing the Volatile Memory Controller (VMC) peripheral.
46*150812a8SEvalZero */
47*150812a8SEvalZero
48*150812a8SEvalZero /** @brief Power configuration bits for each section in particular RAM block. */
49*150812a8SEvalZero typedef enum
50*150812a8SEvalZero {
51*150812a8SEvalZero NRF_VMC_POWER_S0 = VMC_RAM_POWER_S0POWER_Msk, ///< Keep retention on RAM section S0 of the particular RAM block when RAM section is switched off.
52*150812a8SEvalZero NRF_VMC_POWER_S1 = VMC_RAM_POWER_S1POWER_Msk, ///< Keep retention on RAM section S1 of the particular RAM block when RAM section is switched off.
53*150812a8SEvalZero NRF_VMC_POWER_S2 = VMC_RAM_POWER_S2POWER_Msk, ///< Keep retention on RAM section S2 of the particular RAM block when RAM section is switched off.
54*150812a8SEvalZero NRF_VMC_POWER_S3 = VMC_RAM_POWER_S3POWER_Msk, ///< Keep retention on RAM section S3 of the particular RAM block when RAM section is switched off.
55*150812a8SEvalZero } nrf_vmc_power_t;
56*150812a8SEvalZero
57*150812a8SEvalZero /** @brief Retention configuration bits for each section in particular RAM block. */
58*150812a8SEvalZero typedef enum
59*150812a8SEvalZero {
60*150812a8SEvalZero NRF_VMC_RETENTION_S0 = VMC_RAM_POWER_S0RETENTION_Msk, ///< Keep RAM section S0 of the particular RAM block on or off in System ON mode.
61*150812a8SEvalZero NRF_VMC_RETENTION_S1 = VMC_RAM_POWER_S1RETENTION_Msk, ///< Keep RAM section S1 of the particular RAM block on or off in System ON mode.
62*150812a8SEvalZero NRF_VMC_RETENTION_S2 = VMC_RAM_POWER_S2RETENTION_Msk, ///< Keep RAM section S2 of the particular RAM block on or off in System ON mode.
63*150812a8SEvalZero NRF_VMC_RETENTION_S3 = VMC_RAM_POWER_S3RETENTION_Msk, ///< Keep RAM section S3 of the particular RAM block on or off in System ON mode.
64*150812a8SEvalZero } nrf_vmc_retention_t;
65*150812a8SEvalZero
66*150812a8SEvalZero /**
67*150812a8SEvalZero * @brief Function for setting power configuration for the particular RAM block.
68*150812a8SEvalZero *
69*150812a8SEvalZero * @note Overrides current configuration.
70*150812a8SEvalZero *
71*150812a8SEvalZero * @param[in] p_reg Pointer to the peripheral registers structure.
72*150812a8SEvalZero * @param[in] ram_block_num RAM block number.
73*150812a8SEvalZero * @param[in] power_mask Bitmask with sections configuration of particular RAM block.
74*150812a8SEvalZero * @ref nrf_vmc_power_t should be use to prepare this bitmask.
75*150812a8SEvalZero * @param[in] retention_mask Bitmask with sections configuration of particular RAM block.
76*150812a8SEvalZero * @ref nrf_vmc_retention_t should be use to prepare this bitmask.
77*150812a8SEvalZero */
78*150812a8SEvalZero __STATIC_INLINE void nrf_vmc_ram_block_config(NRF_VMC_Type * p_reg,
79*150812a8SEvalZero uint8_t ram_block_num,
80*150812a8SEvalZero uint32_t power_mask,
81*150812a8SEvalZero uint32_t retention_mask);
82*150812a8SEvalZero
83*150812a8SEvalZero /**
84*150812a8SEvalZero * @brief Function for clearing power configuration for the particular RAM block.
85*150812a8SEvalZero *
86*150812a8SEvalZero * @param[in] p_reg Pointer to the peripheral registers structure.
87*150812a8SEvalZero * @param[in] ram_block_num RAM block number.
88*150812a8SEvalZero */
89*150812a8SEvalZero __STATIC_INLINE void nrf_vmc_ram_block_clear(NRF_VMC_Type * p_reg, uint8_t ram_block_num);
90*150812a8SEvalZero
91*150812a8SEvalZero /**
92*150812a8SEvalZero * @brief Function for setting power configuration for the particular RAM block.
93*150812a8SEvalZero *
94*150812a8SEvalZero * @param[in] p_reg Pointer to the peripheral registers structure.
95*150812a8SEvalZero * @param[in] ram_block_num RAM block number.
96*150812a8SEvalZero * @param[in] sect_power Paricular section of the RAM block.
97*150812a8SEvalZero */
98*150812a8SEvalZero __STATIC_INLINE void nrf_vmc_ram_block_power_set(NRF_VMC_Type * p_reg,
99*150812a8SEvalZero uint8_t ram_block_num,
100*150812a8SEvalZero nrf_vmc_power_t sect_power);
101*150812a8SEvalZero
102*150812a8SEvalZero /**
103*150812a8SEvalZero * @brief Function for clearing power configuration for the particular RAM block.
104*150812a8SEvalZero *
105*150812a8SEvalZero * @param[in] p_reg Pointer to the peripheral registers structure.
106*150812a8SEvalZero * @param[in] ram_block_num RAM block number.
107*150812a8SEvalZero * @param[in] sect_power Paricular section of the RAM block.
108*150812a8SEvalZero */
109*150812a8SEvalZero __STATIC_INLINE void nrf_vmc_ram_block_power_clear(NRF_VMC_Type * p_reg,
110*150812a8SEvalZero uint8_t ram_block_num,
111*150812a8SEvalZero nrf_vmc_power_t sect_power);
112*150812a8SEvalZero
113*150812a8SEvalZero /**
114*150812a8SEvalZero * @brief Function for getting power configuration of the particular RAM block.
115*150812a8SEvalZero *
116*150812a8SEvalZero * @param[in] p_reg Pointer to the peripheral registers structure.
117*150812a8SEvalZero * @param[in] ram_block_num RAM block number.
118*150812a8SEvalZero *
119*150812a8SEvalZero * @return Bitmask with power configuration of sections of particular RAM block.
120*150812a8SEvalZero */
121*150812a8SEvalZero __STATIC_INLINE uint32_t nrf_vmc_ram_block_power_mask_get(NRF_VMC_Type const * p_reg,
122*150812a8SEvalZero uint8_t ram_block_num);
123*150812a8SEvalZero
124*150812a8SEvalZero /**
125*150812a8SEvalZero * @brief Function for setting retention configuration for the particular RAM block.
126*150812a8SEvalZero *
127*150812a8SEvalZero * @param[in] p_reg Pointer to the peripheral registers structure.
128*150812a8SEvalZero * @param[in] ram_block_num RAM block number.
129*150812a8SEvalZero * @param[in] sect_retention Paricular section of the RAM block.
130*150812a8SEvalZero */
131*150812a8SEvalZero __STATIC_INLINE void nrf_vmc_ram_block_retention_set(NRF_VMC_Type * p_reg,
132*150812a8SEvalZero uint8_t ram_block_num,
133*150812a8SEvalZero nrf_vmc_retention_t sect_retention);
134*150812a8SEvalZero
135*150812a8SEvalZero /**
136*150812a8SEvalZero * @brief Function for clearing retention configuration for the particular RAM block.
137*150812a8SEvalZero *
138*150812a8SEvalZero * @param[in] p_reg Pointer to the peripheral registers structure.
139*150812a8SEvalZero * @param[in] ram_block_num RAM block number.
140*150812a8SEvalZero * @param[in] sect_retention Paricular section of the RAM block.
141*150812a8SEvalZero */
142*150812a8SEvalZero __STATIC_INLINE void nrf_vmc_ram_block_retention_clear(NRF_VMC_Type * p_reg,
143*150812a8SEvalZero uint8_t ram_block_num,
144*150812a8SEvalZero nrf_vmc_retention_t sect_retention);
145*150812a8SEvalZero
146*150812a8SEvalZero /**
147*150812a8SEvalZero * @brief Function for getting retention configuration of the particular RAM block.
148*150812a8SEvalZero *
149*150812a8SEvalZero * @param[in] p_reg Pointer to the peripheral registers structure.
150*150812a8SEvalZero * @param[in] ram_block_num RAM block number.
151*150812a8SEvalZero *
152*150812a8SEvalZero * @return Bitmask with retention configuration of sections of particular RAM block
153*150812a8SEvalZero */
154*150812a8SEvalZero __STATIC_INLINE uint32_t nrf_vmc_ram_block_retention_mask_get(NRF_VMC_Type const * p_reg,
155*150812a8SEvalZero uint8_t ram_block_num);
156*150812a8SEvalZero
157*150812a8SEvalZero #ifndef SUPPRESS_INLINE_IMPLEMENTATION
158*150812a8SEvalZero
nrf_vmc_ram_block_config(NRF_VMC_Type * p_reg,uint8_t ram_block_num,uint32_t power_mask,uint32_t retention_mask)159*150812a8SEvalZero __STATIC_INLINE void nrf_vmc_ram_block_config(NRF_VMC_Type * p_reg,
160*150812a8SEvalZero uint8_t ram_block_num,
161*150812a8SEvalZero uint32_t power_mask,
162*150812a8SEvalZero uint32_t retention_mask)
163*150812a8SEvalZero {
164*150812a8SEvalZero p_reg->RAM[ram_block_num].POWER =
165*150812a8SEvalZero (power_mask & (
166*150812a8SEvalZero VMC_RAM_POWER_S0POWER_Msk |
167*150812a8SEvalZero VMC_RAM_POWER_S1POWER_Msk |
168*150812a8SEvalZero VMC_RAM_POWER_S2POWER_Msk |
169*150812a8SEvalZero VMC_RAM_POWER_S3POWER_Msk)) |
170*150812a8SEvalZero (retention_mask & (
171*150812a8SEvalZero VMC_RAM_POWER_S0RETENTION_Msk |
172*150812a8SEvalZero VMC_RAM_POWER_S1RETENTION_Msk |
173*150812a8SEvalZero VMC_RAM_POWER_S2RETENTION_Msk |
174*150812a8SEvalZero VMC_RAM_POWER_S3RETENTION_Msk));
175*150812a8SEvalZero // Perform dummy read of the POWER register to ensure that configuration of sections was
176*150812a8SEvalZero // written to the VMC peripheral.
177*150812a8SEvalZero volatile uint32_t dummy = p_reg->RAM[ram_block_num].POWER;
178*150812a8SEvalZero (void)dummy;
179*150812a8SEvalZero }
180*150812a8SEvalZero
nrf_vmc_ram_block_clear(NRF_VMC_Type * p_reg,uint8_t ram_block_num)181*150812a8SEvalZero __STATIC_INLINE void nrf_vmc_ram_block_clear(NRF_VMC_Type * p_reg, uint8_t ram_block_num)
182*150812a8SEvalZero {
183*150812a8SEvalZero p_reg->RAM[ram_block_num].POWER = 0;
184*150812a8SEvalZero }
185*150812a8SEvalZero
nrf_vmc_ram_block_power_set(NRF_VMC_Type * p_reg,uint8_t ram_block_num,nrf_vmc_power_t sect_power)186*150812a8SEvalZero __STATIC_INLINE void nrf_vmc_ram_block_power_set(NRF_VMC_Type * p_reg,
187*150812a8SEvalZero uint8_t ram_block_num,
188*150812a8SEvalZero nrf_vmc_power_t sect_power)
189*150812a8SEvalZero {
190*150812a8SEvalZero p_reg->RAM[ram_block_num].POWERSET = (uint32_t)sect_power;
191*150812a8SEvalZero // Perform dummy read of the POWERSET register to ensure that configuration of sections was
192*150812a8SEvalZero // written to the VMC peripheral.
193*150812a8SEvalZero volatile uint32_t dummy = p_reg->RAM[ram_block_num].POWERSET;
194*150812a8SEvalZero (void)dummy;
195*150812a8SEvalZero }
196*150812a8SEvalZero
nrf_vmc_ram_block_power_clear(NRF_VMC_Type * p_reg,uint8_t ram_block_num,nrf_vmc_power_t sect_power)197*150812a8SEvalZero __STATIC_INLINE void nrf_vmc_ram_block_power_clear(NRF_VMC_Type * p_reg,
198*150812a8SEvalZero uint8_t ram_block_num,
199*150812a8SEvalZero nrf_vmc_power_t sect_power)
200*150812a8SEvalZero {
201*150812a8SEvalZero p_reg->RAM[ram_block_num].POWERCLR = (uint32_t)sect_power;
202*150812a8SEvalZero }
203*150812a8SEvalZero
nrf_vmc_ram_block_power_mask_get(NRF_VMC_Type const * p_reg,uint8_t ram_block_num)204*150812a8SEvalZero __STATIC_INLINE uint32_t nrf_vmc_ram_block_power_mask_get(NRF_VMC_Type const * p_reg,
205*150812a8SEvalZero uint8_t ram_block_num)
206*150812a8SEvalZero {
207*150812a8SEvalZero return p_reg->RAM[ram_block_num].POWER & (
208*150812a8SEvalZero VMC_RAM_POWER_S0POWER_Msk |
209*150812a8SEvalZero VMC_RAM_POWER_S1POWER_Msk |
210*150812a8SEvalZero VMC_RAM_POWER_S2POWER_Msk |
211*150812a8SEvalZero VMC_RAM_POWER_S3POWER_Msk);
212*150812a8SEvalZero }
213*150812a8SEvalZero
nrf_vmc_ram_block_retention_set(NRF_VMC_Type * p_reg,uint8_t ram_block_num,nrf_vmc_retention_t sect_retention)214*150812a8SEvalZero __STATIC_INLINE void nrf_vmc_ram_block_retention_set(NRF_VMC_Type * p_reg,
215*150812a8SEvalZero uint8_t ram_block_num,
216*150812a8SEvalZero nrf_vmc_retention_t sect_retention)
217*150812a8SEvalZero {
218*150812a8SEvalZero p_reg->RAM[ram_block_num].POWERSET = (uint32_t)sect_retention;
219*150812a8SEvalZero // Perform dummy read of the POWERSET register to ensure that configuration of sections was
220*150812a8SEvalZero // written to the VMC peripheral.
221*150812a8SEvalZero volatile uint32_t dummy = p_reg->RAM[ram_block_num].POWERSET;
222*150812a8SEvalZero (void)dummy;
223*150812a8SEvalZero }
224*150812a8SEvalZero
nrf_vmc_ram_block_retention_clear(NRF_VMC_Type * p_reg,uint8_t ram_block_num,nrf_vmc_retention_t sect_retention)225*150812a8SEvalZero __STATIC_INLINE void nrf_vmc_ram_block_retention_clear(NRF_VMC_Type * p_reg,
226*150812a8SEvalZero uint8_t ram_block_num,
227*150812a8SEvalZero nrf_vmc_retention_t sect_retention)
228*150812a8SEvalZero {
229*150812a8SEvalZero p_reg->RAM[ram_block_num].POWERCLR = (uint32_t)sect_retention;
230*150812a8SEvalZero }
231*150812a8SEvalZero
nrf_vmc_ram_block_retention_mask_get(NRF_VMC_Type const * p_reg,uint8_t ram_block_num)232*150812a8SEvalZero __STATIC_INLINE uint32_t nrf_vmc_ram_block_retention_mask_get(NRF_VMC_Type const * p_reg,
233*150812a8SEvalZero uint8_t ram_block_num)
234*150812a8SEvalZero {
235*150812a8SEvalZero return p_reg->RAM[ram_block_num].POWER & (
236*150812a8SEvalZero VMC_RAM_POWER_S0RETENTION_Msk |
237*150812a8SEvalZero VMC_RAM_POWER_S1RETENTION_Msk |
238*150812a8SEvalZero VMC_RAM_POWER_S2RETENTION_Msk |
239*150812a8SEvalZero VMC_RAM_POWER_S3RETENTION_Msk);
240*150812a8SEvalZero }
241*150812a8SEvalZero
242*150812a8SEvalZero #endif // SUPPRESS_INLINE_IMPLEMENTATION
243*150812a8SEvalZero
244*150812a8SEvalZero /** @} */
245*150812a8SEvalZero
246*150812a8SEvalZero #ifdef __cplusplus
247*150812a8SEvalZero }
248*150812a8SEvalZero #endif
249*150812a8SEvalZero
250*150812a8SEvalZero #endif // NRF_VMC_H__
251