1 /*
2 * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice, this
9 * list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the copyright holder nor the names of its
16 * contributors may be used to endorse or promote products derived from this
17 * software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #ifndef NRF_UARTE_H__
33 #define NRF_UARTE_H__
34
35 #include <nrfx.h>
36
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40
41 #define NRF_UARTE_PSEL_DISCONNECTED 0xFFFFFFFF
42
43 /**
44 * @defgroup nrf_uarte_hal UARTE HAL
45 * @{
46 * @ingroup nrf_uarte
47 * @brief Hardware access layer for managing the UARTE peripheral.
48 */
49
50 /**
51 * @enum nrf_uarte_task_t
52 * @brief UARTE tasks.
53 */
54 typedef enum
55 {
56 /*lint -save -e30*/
57 NRF_UARTE_TASK_STARTRX = offsetof(NRF_UARTE_Type, TASKS_STARTRX), ///< Start UART receiver.
58 NRF_UARTE_TASK_STOPRX = offsetof(NRF_UARTE_Type, TASKS_STOPRX), ///< Stop UART receiver.
59 NRF_UARTE_TASK_STARTTX = offsetof(NRF_UARTE_Type, TASKS_STARTTX), ///< Start UART transmitter.
60 NRF_UARTE_TASK_STOPTX = offsetof(NRF_UARTE_Type, TASKS_STOPTX), ///< Stop UART transmitter.
61 NRF_UARTE_TASK_FLUSHRX = offsetof(NRF_UARTE_Type, TASKS_FLUSHRX) ///< Flush RX FIFO in RX buffer.
62 /*lint -restore*/
63 } nrf_uarte_task_t;
64
65 /**
66 * @enum nrf_uarte_event_t
67 * @brief UARTE events.
68 */
69 typedef enum
70 {
71 /*lint -save -e30*/
72 NRF_UARTE_EVENT_CTS = offsetof(NRF_UARTE_Type, EVENTS_CTS), ///< CTS is activated.
73 NRF_UARTE_EVENT_NCTS = offsetof(NRF_UARTE_Type, EVENTS_NCTS), ///< CTS is deactivated.
74 NRF_UARTE_EVENT_RXDRDY = offsetof(NRF_UARTE_Type, EVENTS_RXDRDY), ///< Data received in RXD (but potentially not yet transferred to Data RAM).
75 NRF_UARTE_EVENT_ENDRX = offsetof(NRF_UARTE_Type, EVENTS_ENDRX), ///< Receive buffer is filled up.
76 NRF_UARTE_EVENT_TXDRDY = offsetof(NRF_UARTE_Type, EVENTS_TXDRDY), ///< Data sent from TXD.
77 NRF_UARTE_EVENT_ENDTX = offsetof(NRF_UARTE_Type, EVENTS_ENDTX), ///< Last TX byte transmitted.
78 NRF_UARTE_EVENT_ERROR = offsetof(NRF_UARTE_Type, EVENTS_ERROR), ///< Error detected.
79 NRF_UARTE_EVENT_RXTO = offsetof(NRF_UARTE_Type, EVENTS_RXTO), ///< Receiver timeout.
80 NRF_UARTE_EVENT_RXSTARTED = offsetof(NRF_UARTE_Type, EVENTS_RXSTARTED), ///< Receiver has started.
81 NRF_UARTE_EVENT_TXSTARTED = offsetof(NRF_UARTE_Type, EVENTS_TXSTARTED), ///< Transmitter has started.
82 NRF_UARTE_EVENT_TXSTOPPED = offsetof(NRF_UARTE_Type, EVENTS_TXSTOPPED) ///< Transmitted stopped.
83 /*lint -restore*/
84 } nrf_uarte_event_t;
85
86 /**
87 * @brief Types of UARTE shortcuts.
88 */
89 typedef enum
90 {
91 NRF_UARTE_SHORT_ENDRX_STARTRX = UARTE_SHORTS_ENDRX_STARTRX_Msk, ///< Shortcut between ENDRX event and STARTRX task.
92 NRF_UARTE_SHORT_ENDRX_STOPRX = UARTE_SHORTS_ENDRX_STOPRX_Msk ///< Shortcut between ENDRX event and STOPRX task.
93 } nrf_uarte_short_t;
94
95
96 /**
97 * @enum nrf_uarte_int_mask_t
98 * @brief UARTE interrupts.
99 */
100 typedef enum
101 {
102 NRF_UARTE_INT_CTS_MASK = UARTE_INTENSET_CTS_Msk, ///< Interrupt on CTS event.
103 NRF_UARTE_INT_NCTS_MASK = UARTE_INTENSET_NCTS_Msk, ///< Interrupt on NCTS event.
104 NRF_UARTE_INT_RXDRDY_MASK = UARTE_INTENSET_RXDRDY_Msk, ///< Interrupt on RXDRDY event.
105 NRF_UARTE_INT_ENDRX_MASK = UARTE_INTENSET_ENDRX_Msk, ///< Interrupt on ENDRX event.
106 NRF_UARTE_INT_TXDRDY_MASK = UARTE_INTENSET_TXDRDY_Msk, ///< Interrupt on TXDRDY event.
107 NRF_UARTE_INT_ENDTX_MASK = UARTE_INTENSET_ENDTX_Msk, ///< Interrupt on ENDTX event.
108 NRF_UARTE_INT_ERROR_MASK = UARTE_INTENSET_ERROR_Msk, ///< Interrupt on ERROR event.
109 NRF_UARTE_INT_RXTO_MASK = UARTE_INTENSET_RXTO_Msk, ///< Interrupt on RXTO event.
110 NRF_UARTE_INT_RXSTARTED_MASK = UARTE_INTENSET_RXSTARTED_Msk, ///< Interrupt on RXSTARTED event.
111 NRF_UARTE_INT_TXSTARTED_MASK = UARTE_INTENSET_TXSTARTED_Msk, ///< Interrupt on TXSTARTED event.
112 NRF_UARTE_INT_TXSTOPPED_MASK = UARTE_INTENSET_TXSTOPPED_Msk ///< Interrupt on TXSTOPPED event.
113 } nrf_uarte_int_mask_t;
114
115 /**
116 * @enum nrf_uarte_baudrate_t
117 * @brief Baudrates supported by UARTE.
118 */
119 typedef enum
120 {
121 NRF_UARTE_BAUDRATE_1200 = UARTE_BAUDRATE_BAUDRATE_Baud1200, ///< 1200 baud.
122 NRF_UARTE_BAUDRATE_2400 = UARTE_BAUDRATE_BAUDRATE_Baud2400, ///< 2400 baud.
123 NRF_UARTE_BAUDRATE_4800 = UARTE_BAUDRATE_BAUDRATE_Baud4800, ///< 4800 baud.
124 NRF_UARTE_BAUDRATE_9600 = UARTE_BAUDRATE_BAUDRATE_Baud9600, ///< 9600 baud.
125 NRF_UARTE_BAUDRATE_14400 = UARTE_BAUDRATE_BAUDRATE_Baud14400, ///< 14400 baud.
126 NRF_UARTE_BAUDRATE_19200 = UARTE_BAUDRATE_BAUDRATE_Baud19200, ///< 19200 baud.
127 NRF_UARTE_BAUDRATE_28800 = UARTE_BAUDRATE_BAUDRATE_Baud28800, ///< 28800 baud.
128 NRF_UARTE_BAUDRATE_31250 = UARTE_BAUDRATE_BAUDRATE_Baud31250, ///< 31250 baud.
129 NRF_UARTE_BAUDRATE_38400 = UARTE_BAUDRATE_BAUDRATE_Baud38400, ///< 38400 baud.
130 NRF_UARTE_BAUDRATE_56000 = UARTE_BAUDRATE_BAUDRATE_Baud56000, ///< 56000 baud.
131 NRF_UARTE_BAUDRATE_57600 = UARTE_BAUDRATE_BAUDRATE_Baud57600, ///< 57600 baud.
132 NRF_UARTE_BAUDRATE_76800 = UARTE_BAUDRATE_BAUDRATE_Baud76800, ///< 76800 baud.
133 NRF_UARTE_BAUDRATE_115200 = UARTE_BAUDRATE_BAUDRATE_Baud115200, ///< 115200 baud.
134 NRF_UARTE_BAUDRATE_230400 = UARTE_BAUDRATE_BAUDRATE_Baud230400, ///< 230400 baud.
135 NRF_UARTE_BAUDRATE_250000 = UARTE_BAUDRATE_BAUDRATE_Baud250000, ///< 250000 baud.
136 NRF_UARTE_BAUDRATE_460800 = UARTE_BAUDRATE_BAUDRATE_Baud460800, ///< 460800 baud.
137 NRF_UARTE_BAUDRATE_921600 = UARTE_BAUDRATE_BAUDRATE_Baud921600, ///< 921600 baud.
138 NRF_UARTE_BAUDRATE_1000000 = UARTE_BAUDRATE_BAUDRATE_Baud1M ///< 1000000 baud.
139 } nrf_uarte_baudrate_t;
140
141 /**
142 * @enum nrf_uarte_error_mask_t
143 * @brief Types of UARTE error masks.
144 */
145 typedef enum
146 {
147 NRF_UARTE_ERROR_OVERRUN_MASK = UARTE_ERRORSRC_OVERRUN_Msk, ///< Overrun error.
148 NRF_UARTE_ERROR_PARITY_MASK = UARTE_ERRORSRC_PARITY_Msk, ///< Parity error.
149 NRF_UARTE_ERROR_FRAMING_MASK = UARTE_ERRORSRC_FRAMING_Msk, ///< Framing error.
150 NRF_UARTE_ERROR_BREAK_MASK = UARTE_ERRORSRC_BREAK_Msk ///< Break error.
151 } nrf_uarte_error_mask_t;
152
153 /**
154 * @enum nrf_uarte_parity_t
155 * @brief Types of UARTE parity modes.
156 */
157 typedef enum
158 {
159 NRF_UARTE_PARITY_EXCLUDED = UARTE_CONFIG_PARITY_Excluded << UARTE_CONFIG_PARITY_Pos, ///< Parity excluded.
160 NRF_UARTE_PARITY_INCLUDED = UARTE_CONFIG_PARITY_Included << UARTE_CONFIG_PARITY_Pos ///< Parity included.
161 } nrf_uarte_parity_t;
162
163 /**
164 * @enum nrf_uarte_hwfc_t
165 * @brief Types of UARTE flow control modes.
166 */
167 typedef enum
168 {
169 NRF_UARTE_HWFC_DISABLED = UARTE_CONFIG_HWFC_Disabled << UARTE_CONFIG_HWFC_Pos, ///< HW flow control disabled.
170 NRF_UARTE_HWFC_ENABLED = UARTE_CONFIG_HWFC_Enabled << UARTE_CONFIG_HWFC_Pos ///< HW flow control enabled.
171 } nrf_uarte_hwfc_t;
172
173
174 /**
175 * @brief Function for clearing a specific UARTE event.
176 *
177 * @param[in] p_reg Pointer to the peripheral registers structure.
178 * @param[in] event Event to clear.
179 */
180 __STATIC_INLINE void nrf_uarte_event_clear(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event);
181
182 /**
183 * @brief Function for checking the state of a specific UARTE event.
184 *
185 * @param[in] p_reg Pointer to the peripheral registers structure.
186 * @param[in] event Event to check.
187 *
188 * @retval True if event is set, False otherwise.
189 */
190 __STATIC_INLINE bool nrf_uarte_event_check(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event);
191
192 /**
193 * @brief Function for returning the address of a specific UARTE event register.
194 *
195 * @param[in] p_reg Pointer to the peripheral registers structure.
196 * @param[in] event Desired event.
197 *
198 * @retval Address of specified event register.
199 */
200 __STATIC_INLINE uint32_t nrf_uarte_event_address_get(NRF_UARTE_Type * p_reg,
201 nrf_uarte_event_t event);
202
203 /**
204 * @brief Function for enabling UARTE shortcuts.
205 *
206 * @param p_reg Pointer to the peripheral registers structure.
207 * @param shorts_mask Shortcuts to enable.
208 */
209 __STATIC_INLINE void nrf_uarte_shorts_enable(NRF_UARTE_Type * p_reg, uint32_t shorts_mask);
210
211 /**
212 * @brief Function for disabling UARTE shortcuts.
213 *
214 * @param p_reg Pointer to the peripheral registers structure.
215 * @param shorts_mask Shortcuts to disable.
216 */
217 __STATIC_INLINE void nrf_uarte_shorts_disable(NRF_UARTE_Type * p_reg, uint32_t shorts_mask);
218
219 /**
220 * @brief Function for enabling UARTE interrupts.
221 *
222 * @param p_reg Pointer to the peripheral registers structure.
223 * @param int_mask Interrupts to enable.
224 */
225 __STATIC_INLINE void nrf_uarte_int_enable(NRF_UARTE_Type * p_reg, uint32_t int_mask);
226
227 /**
228 * @brief Function for retrieving the state of a given interrupt.
229 *
230 * @param p_reg Pointer to the peripheral registers structure.
231 * @param int_mask Mask of interrupt to check.
232 *
233 * @retval true If the interrupt is enabled.
234 * @retval false If the interrupt is not enabled.
235 */
236 __STATIC_INLINE bool nrf_uarte_int_enable_check(NRF_UARTE_Type * p_reg, nrf_uarte_int_mask_t int_mask);
237
238 /**
239 * @brief Function for disabling specific interrupts.
240 *
241 * @param p_reg Instance.
242 * @param int_mask Interrupts to disable.
243 */
244 __STATIC_INLINE void nrf_uarte_int_disable(NRF_UARTE_Type * p_reg, uint32_t int_mask);
245
246 #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
247 /**
248 * @brief Function for setting the subscribe configuration for a given
249 * UARTE task.
250 *
251 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
252 * @param[in] task Task for which to set the configuration.
253 * @param[in] channel Channel through which to subscribe events.
254 */
255 __STATIC_INLINE void nrf_uarte_subscribe_set(NRF_UARTE_Type * p_reg,
256 nrf_uarte_task_t task,
257 uint8_t channel);
258
259 /**
260 * @brief Function for clearing the subscribe configuration for a given
261 * UARTE task.
262 *
263 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
264 * @param[in] task Task for which to clear the configuration.
265 */
266 __STATIC_INLINE void nrf_uarte_subscribe_clear(NRF_UARTE_Type * p_reg,
267 nrf_uarte_task_t task);
268
269 /**
270 * @brief Function for setting the publish configuration for a given
271 * UARTE event.
272 *
273 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
274 * @param[in] event Event for which to set the configuration.
275 * @param[in] channel Channel through which to publish the event.
276 */
277 __STATIC_INLINE void nrf_uarte_publish_set(NRF_UARTE_Type * p_reg,
278 nrf_uarte_event_t event,
279 uint8_t channel);
280
281 /**
282 * @brief Function for clearing the publish configuration for a given
283 * UARTE event.
284 *
285 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
286 * @param[in] event Event for which to clear the configuration.
287 */
288 __STATIC_INLINE void nrf_uarte_publish_clear(NRF_UARTE_Type * p_reg,
289 nrf_uarte_event_t event);
290 #endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
291
292 /**
293 * @brief Function for getting error source mask. Function is clearing error source flags after reading.
294 *
295 * @param p_reg Pointer to the peripheral registers structure.
296 * @return Mask with error source flags.
297 */
298 __STATIC_INLINE uint32_t nrf_uarte_errorsrc_get_and_clear(NRF_UARTE_Type * p_reg);
299
300 /**
301 * @brief Function for enabling UARTE.
302 *
303 * @param p_reg Pointer to the peripheral registers structure.
304 */
305 __STATIC_INLINE void nrf_uarte_enable(NRF_UARTE_Type * p_reg);
306
307 /**
308 * @brief Function for disabling UARTE.
309 *
310 * @param p_reg Pointer to the peripheral registers structure.
311 */
312 __STATIC_INLINE void nrf_uarte_disable(NRF_UARTE_Type * p_reg);
313
314 /**
315 * @brief Function for configuring TX/RX pins.
316 *
317 * @param p_reg Pointer to the peripheral registers structure.
318 * @param pseltxd TXD pin number.
319 * @param pselrxd RXD pin number.
320 */
321 __STATIC_INLINE void nrf_uarte_txrx_pins_set(NRF_UARTE_Type * p_reg, uint32_t pseltxd, uint32_t pselrxd);
322
323 /**
324 * @brief Function for disconnecting TX/RX pins.
325 *
326 * @param p_reg Pointer to the peripheral registers structure.
327 */
328 __STATIC_INLINE void nrf_uarte_txrx_pins_disconnect(NRF_UARTE_Type * p_reg);
329
330 /**
331 * @brief Function for getting TX pin.
332 *
333 * @param p_reg Pointer to the peripheral registers structure.
334 */
335 __STATIC_INLINE uint32_t nrf_uarte_tx_pin_get(NRF_UARTE_Type * p_reg);
336
337 /**
338 * @brief Function for getting RX pin.
339 *
340 * @param p_reg Pointer to the peripheral registers structure.
341 */
342 __STATIC_INLINE uint32_t nrf_uarte_rx_pin_get(NRF_UARTE_Type * p_reg);
343
344 /**
345 * @brief Function for getting RTS pin.
346 *
347 * @param p_reg Pointer to the peripheral registers structure.
348 */
349 __STATIC_INLINE uint32_t nrf_uarte_rts_pin_get(NRF_UARTE_Type * p_reg);
350
351 /**
352 * @brief Function for getting CTS pin.
353 *
354 * @param p_reg Pointer to the peripheral registers structure.
355 */
356 __STATIC_INLINE uint32_t nrf_uarte_cts_pin_get(NRF_UARTE_Type * p_reg);
357
358
359 /**
360 * @brief Function for configuring flow control pins.
361 *
362 * @param p_reg Pointer to the peripheral registers structure.
363 * @param pselrts RTS pin number.
364 * @param pselcts CTS pin number.
365 */
366 __STATIC_INLINE void nrf_uarte_hwfc_pins_set(NRF_UARTE_Type * p_reg,
367 uint32_t pselrts,
368 uint32_t pselcts);
369
370 /**
371 * @brief Function for disconnecting flow control pins.
372 *
373 * @param p_reg Pointer to the peripheral registers structure.
374 */
375 __STATIC_INLINE void nrf_uarte_hwfc_pins_disconnect(NRF_UARTE_Type * p_reg);
376
377 /**
378 * @brief Function for starting an UARTE task.
379 *
380 * @param p_reg Pointer to the peripheral registers structure.
381 * @param task Task.
382 */
383 __STATIC_INLINE void nrf_uarte_task_trigger(NRF_UARTE_Type * p_reg, nrf_uarte_task_t task);
384
385 /**
386 * @brief Function for returning the address of a specific task register.
387 *
388 * @param p_reg Pointer to the peripheral registers structure.
389 * @param task Task.
390 *
391 * @return Task address.
392 */
393 __STATIC_INLINE uint32_t nrf_uarte_task_address_get(NRF_UARTE_Type * p_reg, nrf_uarte_task_t task);
394
395 /**
396 * @brief Function for configuring UARTE.
397 *
398 * @param p_reg Pointer to the peripheral registers structure.
399 * @param hwfc Hardware flow control. Enabled if true.
400 * @param parity Parity. Included if true.
401 */
402 __STATIC_INLINE void nrf_uarte_configure(NRF_UARTE_Type * p_reg,
403 nrf_uarte_parity_t parity,
404 nrf_uarte_hwfc_t hwfc);
405
406
407 /**
408 * @brief Function for setting UARTE baudrate.
409 *
410 * @param p_reg Instance.
411 * @param baudrate Baudrate.
412 */
413 __STATIC_INLINE void nrf_uarte_baudrate_set(NRF_UARTE_Type * p_reg, nrf_uarte_baudrate_t baudrate);
414
415 /**
416 * @brief Function for setting the transmit buffer.
417 *
418 * @param[in] p_reg Instance.
419 * @param[in] p_buffer Pointer to the buffer with data to send.
420 * @param[in] length Maximum number of data bytes to transmit.
421 */
422 __STATIC_INLINE void nrf_uarte_tx_buffer_set(NRF_UARTE_Type * p_reg,
423 uint8_t const * p_buffer,
424 size_t length);
425
426 /**
427 * @brief Function for getting number of bytes transmitted in the last transaction.
428 *
429 * @param[in] p_reg Instance.
430 *
431 * @retval Amount of bytes transmitted.
432 */
433 __STATIC_INLINE uint32_t nrf_uarte_tx_amount_get(NRF_UARTE_Type * p_reg);
434
435 /**
436 * @brief Function for setting the receive buffer.
437 *
438 * @param[in] p_reg Pointer to the peripheral registers structure.
439 * @param[in] p_buffer Pointer to the buffer for received data.
440 * @param[in] length Maximum number of data bytes to receive.
441 */
442 __STATIC_INLINE void nrf_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg,
443 uint8_t * p_buffer,
444 size_t length);
445
446 /**
447 * @brief Function for getting number of bytes received in the last transaction.
448 *
449 * @param[in] p_reg Pointer to the peripheral registers structure.
450 *
451 * @retval Amount of bytes received.
452 */
453 __STATIC_INLINE uint32_t nrf_uarte_rx_amount_get(NRF_UARTE_Type * p_reg);
454
455 #ifndef SUPPRESS_INLINE_IMPLEMENTATION
nrf_uarte_event_clear(NRF_UARTE_Type * p_reg,nrf_uarte_event_t event)456 __STATIC_INLINE void nrf_uarte_event_clear(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event)
457 {
458 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
459 #if __CORTEX_M == 0x04
460 volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
461 (void)dummy;
462 #endif
463
464 }
465
nrf_uarte_event_check(NRF_UARTE_Type * p_reg,nrf_uarte_event_t event)466 __STATIC_INLINE bool nrf_uarte_event_check(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event)
467 {
468 return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
469 }
470
nrf_uarte_event_address_get(NRF_UARTE_Type * p_reg,nrf_uarte_event_t event)471 __STATIC_INLINE uint32_t nrf_uarte_event_address_get(NRF_UARTE_Type * p_reg,
472 nrf_uarte_event_t event)
473 {
474 return (uint32_t)((uint8_t *)p_reg + (uint32_t)event);
475 }
476
nrf_uarte_shorts_enable(NRF_UARTE_Type * p_reg,uint32_t shorts_mask)477 __STATIC_INLINE void nrf_uarte_shorts_enable(NRF_UARTE_Type * p_reg, uint32_t shorts_mask)
478 {
479 p_reg->SHORTS |= shorts_mask;
480 }
481
nrf_uarte_shorts_disable(NRF_UARTE_Type * p_reg,uint32_t shorts_mask)482 __STATIC_INLINE void nrf_uarte_shorts_disable(NRF_UARTE_Type * p_reg, uint32_t shorts_mask)
483 {
484 p_reg->SHORTS &= ~(shorts_mask);
485 }
486
nrf_uarte_int_enable(NRF_UARTE_Type * p_reg,uint32_t int_mask)487 __STATIC_INLINE void nrf_uarte_int_enable(NRF_UARTE_Type * p_reg, uint32_t int_mask)
488 {
489 p_reg->INTENSET = int_mask;
490 }
491
nrf_uarte_int_enable_check(NRF_UARTE_Type * p_reg,nrf_uarte_int_mask_t int_mask)492 __STATIC_INLINE bool nrf_uarte_int_enable_check(NRF_UARTE_Type * p_reg, nrf_uarte_int_mask_t int_mask)
493 {
494 return (bool)(p_reg->INTENSET & int_mask);
495 }
496
nrf_uarte_int_disable(NRF_UARTE_Type * p_reg,uint32_t int_mask)497 __STATIC_INLINE void nrf_uarte_int_disable(NRF_UARTE_Type * p_reg, uint32_t int_mask)
498 {
499 p_reg->INTENCLR = int_mask;
500 }
501
502 #if defined(DPPI_PRESENT)
nrf_uarte_subscribe_set(NRF_UARTE_Type * p_reg,nrf_uarte_task_t task,uint8_t channel)503 __STATIC_INLINE void nrf_uarte_subscribe_set(NRF_UARTE_Type * p_reg,
504 nrf_uarte_task_t task,
505 uint8_t channel)
506 {
507 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
508 ((uint32_t)channel | UARTE_SUBSCRIBE_STARTRX_EN_Msk);
509 }
510
nrf_uarte_subscribe_clear(NRF_UARTE_Type * p_reg,nrf_uarte_task_t task)511 __STATIC_INLINE void nrf_uarte_subscribe_clear(NRF_UARTE_Type * p_reg,
512 nrf_uarte_task_t task)
513 {
514 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
515 }
516
nrf_uarte_publish_set(NRF_UARTE_Type * p_reg,nrf_uarte_event_t event,uint8_t channel)517 __STATIC_INLINE void nrf_uarte_publish_set(NRF_UARTE_Type * p_reg,
518 nrf_uarte_event_t event,
519 uint8_t channel)
520 {
521 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
522 ((uint32_t)channel | UARTE_PUBLISH_CTS_EN_Msk);
523 }
524
nrf_uarte_publish_clear(NRF_UARTE_Type * p_reg,nrf_uarte_event_t event)525 __STATIC_INLINE void nrf_uarte_publish_clear(NRF_UARTE_Type * p_reg,
526 nrf_uarte_event_t event)
527 {
528 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0;
529 }
530 #endif // defined(DPPI_PRESENT)
531
nrf_uarte_errorsrc_get_and_clear(NRF_UARTE_Type * p_reg)532 __STATIC_INLINE uint32_t nrf_uarte_errorsrc_get_and_clear(NRF_UARTE_Type * p_reg)
533 {
534 uint32_t errsrc_mask = p_reg->ERRORSRC;
535 p_reg->ERRORSRC = errsrc_mask;
536 return errsrc_mask;
537 }
538
nrf_uarte_enable(NRF_UARTE_Type * p_reg)539 __STATIC_INLINE void nrf_uarte_enable(NRF_UARTE_Type * p_reg)
540 {
541 p_reg->ENABLE = UARTE_ENABLE_ENABLE_Enabled;
542 }
543
nrf_uarte_disable(NRF_UARTE_Type * p_reg)544 __STATIC_INLINE void nrf_uarte_disable(NRF_UARTE_Type * p_reg)
545 {
546 p_reg->ENABLE = UARTE_ENABLE_ENABLE_Disabled;
547 }
548
nrf_uarte_txrx_pins_set(NRF_UARTE_Type * p_reg,uint32_t pseltxd,uint32_t pselrxd)549 __STATIC_INLINE void nrf_uarte_txrx_pins_set(NRF_UARTE_Type * p_reg, uint32_t pseltxd, uint32_t pselrxd)
550 {
551 p_reg->PSEL.TXD = pseltxd;
552 p_reg->PSEL.RXD = pselrxd;
553 }
554
nrf_uarte_txrx_pins_disconnect(NRF_UARTE_Type * p_reg)555 __STATIC_INLINE void nrf_uarte_txrx_pins_disconnect(NRF_UARTE_Type * p_reg)
556 {
557 nrf_uarte_txrx_pins_set(p_reg, NRF_UARTE_PSEL_DISCONNECTED, NRF_UARTE_PSEL_DISCONNECTED);
558 }
559
nrf_uarte_tx_pin_get(NRF_UARTE_Type * p_reg)560 __STATIC_INLINE uint32_t nrf_uarte_tx_pin_get(NRF_UARTE_Type * p_reg)
561 {
562 return p_reg->PSEL.TXD;
563 }
564
nrf_uarte_rx_pin_get(NRF_UARTE_Type * p_reg)565 __STATIC_INLINE uint32_t nrf_uarte_rx_pin_get(NRF_UARTE_Type * p_reg)
566 {
567 return p_reg->PSEL.RXD;
568 }
569
nrf_uarte_rts_pin_get(NRF_UARTE_Type * p_reg)570 __STATIC_INLINE uint32_t nrf_uarte_rts_pin_get(NRF_UARTE_Type * p_reg)
571 {
572 return p_reg->PSEL.RTS;
573 }
574
nrf_uarte_cts_pin_get(NRF_UARTE_Type * p_reg)575 __STATIC_INLINE uint32_t nrf_uarte_cts_pin_get(NRF_UARTE_Type * p_reg)
576 {
577 return p_reg->PSEL.CTS;
578 }
579
nrf_uarte_hwfc_pins_set(NRF_UARTE_Type * p_reg,uint32_t pselrts,uint32_t pselcts)580 __STATIC_INLINE void nrf_uarte_hwfc_pins_set(NRF_UARTE_Type * p_reg, uint32_t pselrts, uint32_t pselcts)
581 {
582 p_reg->PSEL.RTS = pselrts;
583 p_reg->PSEL.CTS = pselcts;
584 }
585
nrf_uarte_hwfc_pins_disconnect(NRF_UARTE_Type * p_reg)586 __STATIC_INLINE void nrf_uarte_hwfc_pins_disconnect(NRF_UARTE_Type * p_reg)
587 {
588 nrf_uarte_hwfc_pins_set(p_reg, NRF_UARTE_PSEL_DISCONNECTED, NRF_UARTE_PSEL_DISCONNECTED);
589 }
590
nrf_uarte_task_trigger(NRF_UARTE_Type * p_reg,nrf_uarte_task_t task)591 __STATIC_INLINE void nrf_uarte_task_trigger(NRF_UARTE_Type * p_reg, nrf_uarte_task_t task)
592 {
593 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
594 }
595
nrf_uarte_task_address_get(NRF_UARTE_Type * p_reg,nrf_uarte_task_t task)596 __STATIC_INLINE uint32_t nrf_uarte_task_address_get(NRF_UARTE_Type * p_reg, nrf_uarte_task_t task)
597 {
598 return (uint32_t)p_reg + (uint32_t)task;
599 }
600
nrf_uarte_configure(NRF_UARTE_Type * p_reg,nrf_uarte_parity_t parity,nrf_uarte_hwfc_t hwfc)601 __STATIC_INLINE void nrf_uarte_configure(NRF_UARTE_Type * p_reg,
602 nrf_uarte_parity_t parity,
603 nrf_uarte_hwfc_t hwfc)
604 {
605 p_reg->CONFIG = (uint32_t)parity | (uint32_t)hwfc;
606 }
607
nrf_uarte_baudrate_set(NRF_UARTE_Type * p_reg,nrf_uarte_baudrate_t baudrate)608 __STATIC_INLINE void nrf_uarte_baudrate_set(NRF_UARTE_Type * p_reg, nrf_uarte_baudrate_t baudrate)
609 {
610 p_reg->BAUDRATE = baudrate;
611 }
612
nrf_uarte_tx_buffer_set(NRF_UARTE_Type * p_reg,uint8_t const * p_buffer,size_t length)613 __STATIC_INLINE void nrf_uarte_tx_buffer_set(NRF_UARTE_Type * p_reg,
614 uint8_t const * p_buffer,
615 size_t length)
616 {
617 p_reg->TXD.PTR = (uint32_t)p_buffer;
618 p_reg->TXD.MAXCNT = length;
619 }
620
nrf_uarte_tx_amount_get(NRF_UARTE_Type * p_reg)621 __STATIC_INLINE uint32_t nrf_uarte_tx_amount_get(NRF_UARTE_Type * p_reg)
622 {
623 return p_reg->TXD.AMOUNT;
624 }
625
nrf_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg,uint8_t * p_buffer,size_t length)626 __STATIC_INLINE void nrf_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg,
627 uint8_t * p_buffer,
628 size_t length)
629 {
630 p_reg->RXD.PTR = (uint32_t)p_buffer;
631 p_reg->RXD.MAXCNT = length;
632 }
633
nrf_uarte_rx_amount_get(NRF_UARTE_Type * p_reg)634 __STATIC_INLINE uint32_t nrf_uarte_rx_amount_get(NRF_UARTE_Type * p_reg)
635 {
636 return p_reg->RXD.AMOUNT;
637 }
638 #endif //SUPPRESS_INLINE_IMPLEMENTATION
639
640 /** @} */
641
642 #ifdef __cplusplus
643 }
644 #endif
645
646 #endif //NRF_UARTE_H__
647