xref: /nrf52832-nimble/nordic/nrfx/hal/nrf_twis.h (revision 150812a83cab50279bd772ef6db1bfaf255f2c5b)
1*150812a8SEvalZero /*
2*150812a8SEvalZero  * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
3*150812a8SEvalZero  * All rights reserved.
4*150812a8SEvalZero  *
5*150812a8SEvalZero  * Redistribution and use in source and binary forms, with or without
6*150812a8SEvalZero  * modification, are permitted provided that the following conditions are met:
7*150812a8SEvalZero  *
8*150812a8SEvalZero  * 1. Redistributions of source code must retain the above copyright notice, this
9*150812a8SEvalZero  *    list of conditions and the following disclaimer.
10*150812a8SEvalZero  *
11*150812a8SEvalZero  * 2. Redistributions in binary form must reproduce the above copyright
12*150812a8SEvalZero  *    notice, this list of conditions and the following disclaimer in the
13*150812a8SEvalZero  *    documentation and/or other materials provided with the distribution.
14*150812a8SEvalZero  *
15*150812a8SEvalZero  * 3. Neither the name of the copyright holder nor the names of its
16*150812a8SEvalZero  *    contributors may be used to endorse or promote products derived from this
17*150812a8SEvalZero  *    software without specific prior written permission.
18*150812a8SEvalZero  *
19*150812a8SEvalZero  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20*150812a8SEvalZero  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21*150812a8SEvalZero  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22*150812a8SEvalZero  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23*150812a8SEvalZero  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24*150812a8SEvalZero  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25*150812a8SEvalZero  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26*150812a8SEvalZero  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27*150812a8SEvalZero  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28*150812a8SEvalZero  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29*150812a8SEvalZero  * POSSIBILITY OF SUCH DAMAGE.
30*150812a8SEvalZero  */
31*150812a8SEvalZero 
32*150812a8SEvalZero #ifndef NRF_TWIS_H__
33*150812a8SEvalZero #define NRF_TWIS_H__
34*150812a8SEvalZero 
35*150812a8SEvalZero #include <nrfx.h>
36*150812a8SEvalZero 
37*150812a8SEvalZero #ifdef __cplusplus
38*150812a8SEvalZero extern "C" {
39*150812a8SEvalZero #endif
40*150812a8SEvalZero 
41*150812a8SEvalZero /**
42*150812a8SEvalZero  * @defgroup nrf_twis_hal TWIS HAL
43*150812a8SEvalZero  * @{
44*150812a8SEvalZero  * @ingroup nrf_twis
45*150812a8SEvalZero  * @brief   Hardware access layer for managing the Two Wire Interface Slave with EasyDMA
46*150812a8SEvalZero  *          (TWIS) peripheral.
47*150812a8SEvalZero  */
48*150812a8SEvalZero 
49*150812a8SEvalZero /**
50*150812a8SEvalZero  * @brief TWIS tasks
51*150812a8SEvalZero  */
52*150812a8SEvalZero typedef enum
53*150812a8SEvalZero {
54*150812a8SEvalZero     /*lint -save -e30*/
55*150812a8SEvalZero     NRF_TWIS_TASK_STOP      = offsetof(NRF_TWIS_Type, TASKS_STOP),      /**< Stop TWIS transaction */
56*150812a8SEvalZero     NRF_TWIS_TASK_SUSPEND   = offsetof(NRF_TWIS_Type, TASKS_SUSPEND),   /**< Suspend TWIS transaction */
57*150812a8SEvalZero     NRF_TWIS_TASK_RESUME    = offsetof(NRF_TWIS_Type, TASKS_RESUME),    /**< Resume TWIS transaction */
58*150812a8SEvalZero     NRF_TWIS_TASK_PREPARERX = offsetof(NRF_TWIS_Type, TASKS_PREPARERX), /**< Prepare the TWIS slave to respond to a write command */
59*150812a8SEvalZero     NRF_TWIS_TASK_PREPARETX = offsetof(NRF_TWIS_Type, TASKS_PREPARETX)  /**< Prepare the TWIS slave to respond to a read command */
60*150812a8SEvalZero     /*lint -restore*/
61*150812a8SEvalZero } nrf_twis_task_t;
62*150812a8SEvalZero 
63*150812a8SEvalZero /**
64*150812a8SEvalZero  * @brief TWIS events
65*150812a8SEvalZero  */
66*150812a8SEvalZero typedef enum
67*150812a8SEvalZero {
68*150812a8SEvalZero     /*lint -save -e30*/
69*150812a8SEvalZero     NRF_TWIS_EVENT_STOPPED   = offsetof(NRF_TWIS_Type, EVENTS_STOPPED),   /**< TWIS stopped */
70*150812a8SEvalZero     NRF_TWIS_EVENT_ERROR     = offsetof(NRF_TWIS_Type, EVENTS_ERROR),     /**< TWIS error */
71*150812a8SEvalZero     NRF_TWIS_EVENT_RXSTARTED = offsetof(NRF_TWIS_Type, EVENTS_RXSTARTED), /**< Receive sequence started */
72*150812a8SEvalZero     NRF_TWIS_EVENT_TXSTARTED = offsetof(NRF_TWIS_Type, EVENTS_TXSTARTED), /**< Transmit sequence started */
73*150812a8SEvalZero     NRF_TWIS_EVENT_WRITE     = offsetof(NRF_TWIS_Type, EVENTS_WRITE),     /**< Write command received */
74*150812a8SEvalZero     NRF_TWIS_EVENT_READ      = offsetof(NRF_TWIS_Type, EVENTS_READ)       /**< Read command received */
75*150812a8SEvalZero     /*lint -restore*/
76*150812a8SEvalZero } nrf_twis_event_t;
77*150812a8SEvalZero 
78*150812a8SEvalZero /**
79*150812a8SEvalZero  * @brief TWIS shortcuts
80*150812a8SEvalZero  */
81*150812a8SEvalZero typedef enum
82*150812a8SEvalZero {
83*150812a8SEvalZero     NRF_TWIS_SHORT_WRITE_SUSPEND_MASK   = TWIS_SHORTS_WRITE_SUSPEND_Msk,   /**< Shortcut between WRITE event and SUSPEND task */
84*150812a8SEvalZero     NRF_TWIS_SHORT_READ_SUSPEND_MASK    = TWIS_SHORTS_READ_SUSPEND_Msk,    /**< Shortcut between READ event and SUSPEND task */
85*150812a8SEvalZero } nrf_twis_short_mask_t;
86*150812a8SEvalZero 
87*150812a8SEvalZero /**
88*150812a8SEvalZero  * @brief TWIS interrupts
89*150812a8SEvalZero  */
90*150812a8SEvalZero typedef enum
91*150812a8SEvalZero {
92*150812a8SEvalZero     NRF_TWIS_INT_STOPPED_MASK   = TWIS_INTEN_STOPPED_Msk,   /**< Interrupt on STOPPED event */
93*150812a8SEvalZero     NRF_TWIS_INT_ERROR_MASK     = TWIS_INTEN_ERROR_Msk,     /**< Interrupt on ERROR event */
94*150812a8SEvalZero     NRF_TWIS_INT_RXSTARTED_MASK = TWIS_INTEN_RXSTARTED_Msk, /**< Interrupt on RXSTARTED event */
95*150812a8SEvalZero     NRF_TWIS_INT_TXSTARTED_MASK = TWIS_INTEN_TXSTARTED_Msk, /**< Interrupt on TXSTARTED event */
96*150812a8SEvalZero     NRF_TWIS_INT_WRITE_MASK     = TWIS_INTEN_WRITE_Msk,     /**< Interrupt on WRITE event */
97*150812a8SEvalZero     NRF_TWIS_INT_READ_MASK      = TWIS_INTEN_READ_Msk,      /**< Interrupt on READ event */
98*150812a8SEvalZero } nrf_twis_int_mask_t;
99*150812a8SEvalZero 
100*150812a8SEvalZero /**
101*150812a8SEvalZero  * @brief TWIS error source
102*150812a8SEvalZero  */
103*150812a8SEvalZero typedef enum
104*150812a8SEvalZero {
105*150812a8SEvalZero     NRF_TWIS_ERROR_OVERFLOW  = TWIS_ERRORSRC_OVERFLOW_Msk, /**< RX buffer overflow detected, and prevented */
106*150812a8SEvalZero     NRF_TWIS_ERROR_DATA_NACK = TWIS_ERRORSRC_DNACK_Msk,    /**< NACK sent after receiving a data byte */
107*150812a8SEvalZero     NRF_TWIS_ERROR_OVERREAD  = TWIS_ERRORSRC_OVERREAD_Msk  /**< TX buffer over-read detected, and prevented */
108*150812a8SEvalZero } nrf_twis_error_t;
109*150812a8SEvalZero 
110*150812a8SEvalZero /**
111*150812a8SEvalZero  * @brief TWIS address matching configuration
112*150812a8SEvalZero  */
113*150812a8SEvalZero typedef enum
114*150812a8SEvalZero {
115*150812a8SEvalZero     NRF_TWIS_CONFIG_ADDRESS0_MASK  = TWIS_CONFIG_ADDRESS0_Msk, /**< Enable or disable address matching on ADDRESS[0] */
116*150812a8SEvalZero     NRF_TWIS_CONFIG_ADDRESS1_MASK  = TWIS_CONFIG_ADDRESS1_Msk, /**< Enable or disable address matching on ADDRESS[1] */
117*150812a8SEvalZero     NRF_TWIS_CONFIG_ADDRESS01_MASK = TWIS_CONFIG_ADDRESS0_Msk | TWIS_CONFIG_ADDRESS1_Msk /**< Enable both address matching */
118*150812a8SEvalZero } nrf_twis_config_addr_mask_t;
119*150812a8SEvalZero 
120*150812a8SEvalZero /**
121*150812a8SEvalZero  * @brief Variable type to hold amount of data for EasyDMA
122*150812a8SEvalZero  *
123*150812a8SEvalZero  * Variable of the minimum size that can hold the amount of data to transfer.
124*150812a8SEvalZero  *
125*150812a8SEvalZero  * @note
126*150812a8SEvalZero  * Defined to make it simple to change if EasyDMA would be updated to support more data in
127*150812a8SEvalZero  * the future devices to.
128*150812a8SEvalZero  */
129*150812a8SEvalZero typedef uint8_t nrf_twis_amount_t;
130*150812a8SEvalZero 
131*150812a8SEvalZero /**
132*150812a8SEvalZero  * @brief Smallest variable type to hold TWI address
133*150812a8SEvalZero  *
134*150812a8SEvalZero  * Variable of the minimum size that can hold single TWI address.
135*150812a8SEvalZero  *
136*150812a8SEvalZero  * @note
137*150812a8SEvalZero  * Defined to make it simple to change if new TWI would support for example
138*150812a8SEvalZero  * 10 bit addressing mode.
139*150812a8SEvalZero  */
140*150812a8SEvalZero typedef uint8_t nrf_twis_address_t;
141*150812a8SEvalZero 
142*150812a8SEvalZero 
143*150812a8SEvalZero /**
144*150812a8SEvalZero  * @brief Function for activating a specific TWIS task.
145*150812a8SEvalZero  *
146*150812a8SEvalZero  * @param[in] p_reg Pointer to the peripheral registers structure.
147*150812a8SEvalZero  * @param     task   Task.
148*150812a8SEvalZero  */
149*150812a8SEvalZero __STATIC_INLINE void nrf_twis_task_trigger(NRF_TWIS_Type * const p_reg, nrf_twis_task_t task);
150*150812a8SEvalZero 
151*150812a8SEvalZero /**
152*150812a8SEvalZero  * @brief Function for returning the address of a specific TWIS task register.
153*150812a8SEvalZero  *
154*150812a8SEvalZero  * @param[in]  p_reg Pointer to the peripheral registers structure.
155*150812a8SEvalZero  * @param      task   Task.
156*150812a8SEvalZero  *
157*150812a8SEvalZero  * @return Task address.
158*150812a8SEvalZero  */
159*150812a8SEvalZero __STATIC_INLINE uint32_t nrf_twis_task_address_get(
160*150812a8SEvalZero         NRF_TWIS_Type const * const p_reg,
161*150812a8SEvalZero         nrf_twis_task_t      task);
162*150812a8SEvalZero 
163*150812a8SEvalZero /**
164*150812a8SEvalZero  * @brief Function for clearing a specific event.
165*150812a8SEvalZero  *
166*150812a8SEvalZero  * @param[in] p_reg Pointer to the peripheral registers structure.
167*150812a8SEvalZero  * @param     event  Event.
168*150812a8SEvalZero  */
169*150812a8SEvalZero __STATIC_INLINE void nrf_twis_event_clear(
170*150812a8SEvalZero         NRF_TWIS_Type     * const p_reg,
171*150812a8SEvalZero         nrf_twis_event_t   event);
172*150812a8SEvalZero /**
173*150812a8SEvalZero  * @brief Function for returning the state of a specific event.
174*150812a8SEvalZero  *
175*150812a8SEvalZero  * @param[in] p_reg Pointer to the peripheral registers structure.
176*150812a8SEvalZero  * @param     event  Event.
177*150812a8SEvalZero  *
178*150812a8SEvalZero  * @retval true If the event is set.
179*150812a8SEvalZero  * @retval false If the event is not set.
180*150812a8SEvalZero  */
181*150812a8SEvalZero __STATIC_INLINE bool nrf_twis_event_check(
182*150812a8SEvalZero         NRF_TWIS_Type const * const p_reg,
183*150812a8SEvalZero         nrf_twis_event_t     event);
184*150812a8SEvalZero 
185*150812a8SEvalZero 
186*150812a8SEvalZero /**
187*150812a8SEvalZero  * @brief Function for getting and clearing the state of specific event
188*150812a8SEvalZero  *
189*150812a8SEvalZero  * This function checks the state of the event and clears it.
190*150812a8SEvalZero  * @param[in,out] p_reg Pointer to the peripheral registers structure.
191*150812a8SEvalZero  * @param         event Event.
192*150812a8SEvalZero  *
193*150812a8SEvalZero  * @retval true If the event was set.
194*150812a8SEvalZero  * @retval false If the event was not set.
195*150812a8SEvalZero  */
196*150812a8SEvalZero __STATIC_INLINE bool nrf_twis_event_get_and_clear(
197*150812a8SEvalZero         NRF_TWIS_Type    * const p_reg,
198*150812a8SEvalZero         nrf_twis_event_t   event);
199*150812a8SEvalZero 
200*150812a8SEvalZero 
201*150812a8SEvalZero /**
202*150812a8SEvalZero  * @brief Function for returning the address of a specific TWIS event register.
203*150812a8SEvalZero  *
204*150812a8SEvalZero  * @param[in] p_reg Pointer to the peripheral registers structure.
205*150812a8SEvalZero  * @param     event  Event.
206*150812a8SEvalZero  *
207*150812a8SEvalZero  * @return Address.
208*150812a8SEvalZero  */
209*150812a8SEvalZero __STATIC_INLINE uint32_t nrf_twis_event_address_get(
210*150812a8SEvalZero         NRF_TWIS_Type const * const p_reg,
211*150812a8SEvalZero         nrf_twis_event_t     event);
212*150812a8SEvalZero 
213*150812a8SEvalZero /**
214*150812a8SEvalZero  * @brief Function for setting a shortcut.
215*150812a8SEvalZero  *
216*150812a8SEvalZero  * @param[in] p_reg     Pointer to the peripheral registers structure.
217*150812a8SEvalZero  * @param     short_mask Shortcuts mask.
218*150812a8SEvalZero  */
219*150812a8SEvalZero __STATIC_INLINE void nrf_twis_shorts_enable(NRF_TWIS_Type * const p_reg, uint32_t short_mask);
220*150812a8SEvalZero 
221*150812a8SEvalZero /**
222*150812a8SEvalZero  * @brief Function for clearing shortcuts.
223*150812a8SEvalZero  *
224*150812a8SEvalZero  * @param[in] p_reg     Pointer to the peripheral registers structure.
225*150812a8SEvalZero  * @param     short_mask Shortcuts mask.
226*150812a8SEvalZero  */
227*150812a8SEvalZero __STATIC_INLINE void nrf_twis_shorts_disable(NRF_TWIS_Type * const p_reg, uint32_t short_mask);
228*150812a8SEvalZero 
229*150812a8SEvalZero /**
230*150812a8SEvalZero  * @brief Get the shorts mask
231*150812a8SEvalZero  *
232*150812a8SEvalZero  * Function returns shorts register.
233*150812a8SEvalZero  * @param[in] p_reg     Pointer to the peripheral registers structure.
234*150812a8SEvalZero  * @return Flags of currently enabled shortcuts
235*150812a8SEvalZero  */
236*150812a8SEvalZero __STATIC_INLINE uint32_t nrf_twis_shorts_get(NRF_TWIS_Type * const p_reg);
237*150812a8SEvalZero 
238*150812a8SEvalZero /**
239*150812a8SEvalZero  * @brief Function for enabling selected interrupts.
240*150812a8SEvalZero  *
241*150812a8SEvalZero  * @param[in] p_reg   Pointer to the peripheral registers structure.
242*150812a8SEvalZero  * @param     int_mask Interrupts mask.
243*150812a8SEvalZero  */
244*150812a8SEvalZero __STATIC_INLINE void nrf_twis_int_enable(NRF_TWIS_Type * const p_reg, uint32_t int_mask);
245*150812a8SEvalZero 
246*150812a8SEvalZero /**
247*150812a8SEvalZero  * @brief Function for retrieving the state of selected interrupts.
248*150812a8SEvalZero  *
249*150812a8SEvalZero  * @param[in] p_reg   Pointer to the peripheral registers structure.
250*150812a8SEvalZero  * @param     int_mask Interrupts mask.
251*150812a8SEvalZero  *
252*150812a8SEvalZero  * @retval true If any of selected interrupts is enabled.
253*150812a8SEvalZero  * @retval false If none of selected interrupts is enabled.
254*150812a8SEvalZero  */
255*150812a8SEvalZero __STATIC_INLINE bool nrf_twis_int_enable_check(NRF_TWIS_Type const * const p_reg, uint32_t int_mask);
256*150812a8SEvalZero 
257*150812a8SEvalZero /**
258*150812a8SEvalZero  * @brief Function for disabling selected interrupts.
259*150812a8SEvalZero  *
260*150812a8SEvalZero  * @param[in] p_reg   Pointer to the peripheral registers structure.
261*150812a8SEvalZero  * @param     int_mask Interrupts mask.
262*150812a8SEvalZero  */
263*150812a8SEvalZero __STATIC_INLINE void nrf_twis_int_disable(NRF_TWIS_Type * const p_reg, uint32_t int_mask);
264*150812a8SEvalZero 
265*150812a8SEvalZero #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
266*150812a8SEvalZero /**
267*150812a8SEvalZero  * @brief Function for setting the subscribe configuration for a given
268*150812a8SEvalZero  *        TWIS task.
269*150812a8SEvalZero  *
270*150812a8SEvalZero  * @param[in] p_reg   Pointer to the structure of registers of the peripheral.
271*150812a8SEvalZero  * @param[in] task    Task for which to set the configuration.
272*150812a8SEvalZero  * @param[in] channel Channel through which to subscribe events.
273*150812a8SEvalZero  */
274*150812a8SEvalZero __STATIC_INLINE void nrf_twis_subscribe_set(NRF_TWIS_Type * p_reg,
275*150812a8SEvalZero                                             nrf_twis_task_t task,
276*150812a8SEvalZero                                             uint8_t         channel);
277*150812a8SEvalZero 
278*150812a8SEvalZero /**
279*150812a8SEvalZero  * @brief Function for clearing the subscribe configuration for a given
280*150812a8SEvalZero  *        TWIS task.
281*150812a8SEvalZero  *
282*150812a8SEvalZero  * @param[in] p_reg Pointer to the structure of registers of the peripheral.
283*150812a8SEvalZero  * @param[in] task  Task for which to clear the configuration.
284*150812a8SEvalZero  */
285*150812a8SEvalZero __STATIC_INLINE void nrf_twis_subscribe_clear(NRF_TWIS_Type * p_reg,
286*150812a8SEvalZero                                               nrf_twis_task_t task);
287*150812a8SEvalZero 
288*150812a8SEvalZero /**
289*150812a8SEvalZero  * @brief Function for setting the publish configuration for a given
290*150812a8SEvalZero  *        TWIS event.
291*150812a8SEvalZero  *
292*150812a8SEvalZero  * @param[in] p_reg   Pointer to the structure of registers of the peripheral.
293*150812a8SEvalZero  * @param[in] event   Event for which to set the configuration.
294*150812a8SEvalZero  * @param[in] channel Channel through which to publish the event.
295*150812a8SEvalZero  */
296*150812a8SEvalZero __STATIC_INLINE void nrf_twis_publish_set(NRF_TWIS_Type *  p_reg,
297*150812a8SEvalZero                                           nrf_twis_event_t event,
298*150812a8SEvalZero                                           uint8_t         channel);
299*150812a8SEvalZero 
300*150812a8SEvalZero /**
301*150812a8SEvalZero  * @brief Function for clearing the publish configuration for a given
302*150812a8SEvalZero  *        TWIS event.
303*150812a8SEvalZero  *
304*150812a8SEvalZero  * @param[in] p_reg Pointer to the structure of registers of the peripheral.
305*150812a8SEvalZero  * @param[in] event Event for which to clear the configuration.
306*150812a8SEvalZero  */
307*150812a8SEvalZero __STATIC_INLINE void nrf_twis_publish_clear(NRF_TWIS_Type *  p_reg,
308*150812a8SEvalZero                                             nrf_twis_event_t event);
309*150812a8SEvalZero #endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
310*150812a8SEvalZero 
311*150812a8SEvalZero /**
312*150812a8SEvalZero  * @brief Function for retrieving and clearing the TWIS error source.
313*150812a8SEvalZero  *
314*150812a8SEvalZero  * @attention Error sources are cleared after read.
315*150812a8SEvalZero  * @param[in] p_reg Pointer to the peripheral registers structure.
316*150812a8SEvalZero  * @return Error source mask with values from @ref nrf_twis_error_t.
317*150812a8SEvalZero  */
318*150812a8SEvalZero __STATIC_INLINE uint32_t nrf_twis_error_source_get_and_clear(NRF_TWIS_Type * const p_reg);
319*150812a8SEvalZero 
320*150812a8SEvalZero /**
321*150812a8SEvalZero  * @brief Get information which of addresses matched
322*150812a8SEvalZero  *
323*150812a8SEvalZero  * Function returns index in the address table
324*150812a8SEvalZero  * that points to the address that already matched.
325*150812a8SEvalZero  * @param[in] p_reg Pointer to the peripheral registers structure.
326*150812a8SEvalZero  * @return Index of matched address
327*150812a8SEvalZero  */
328*150812a8SEvalZero __STATIC_INLINE uint_fast8_t nrf_twis_match_get(NRF_TWIS_Type const * p_reg);
329*150812a8SEvalZero 
330*150812a8SEvalZero /**
331*150812a8SEvalZero  * @brief Function for enabling TWIS.
332*150812a8SEvalZero  *
333*150812a8SEvalZero  * @param[in] p_reg Pointer to the peripheral registers structure.
334*150812a8SEvalZero  */
335*150812a8SEvalZero __STATIC_INLINE void nrf_twis_enable(NRF_TWIS_Type * const p_reg);
336*150812a8SEvalZero 
337*150812a8SEvalZero /**
338*150812a8SEvalZero  * @brief Function for disabling TWIS.
339*150812a8SEvalZero  *
340*150812a8SEvalZero  * @param[in] p_reg Pointer to the peripheral registers structure.
341*150812a8SEvalZero  */
342*150812a8SEvalZero __STATIC_INLINE void nrf_twis_disable(NRF_TWIS_Type * const p_reg);
343*150812a8SEvalZero 
344*150812a8SEvalZero /**
345*150812a8SEvalZero  * @brief Function for configuring TWIS pins.
346*150812a8SEvalZero  *
347*150812a8SEvalZero  * @param[in] p_reg Pointer to the peripheral registers structure.
348*150812a8SEvalZero  * @param scl SCL pin number.
349*150812a8SEvalZero  * @param sda SDA pin number.
350*150812a8SEvalZero  */
351*150812a8SEvalZero __STATIC_INLINE void nrf_twis_pins_set(NRF_TWIS_Type * const p_reg, uint32_t scl, uint32_t sda);
352*150812a8SEvalZero 
353*150812a8SEvalZero /**
354*150812a8SEvalZero  * @brief Function for setting the receive buffer.
355*150812a8SEvalZero  *
356*150812a8SEvalZero  * @param[in] p_reg Pointer to the peripheral registers structure.
357*150812a8SEvalZero  * @param     p_buf  Pointer to the buffer for received data.
358*150812a8SEvalZero  * @param     length Maximum number of data bytes to receive.
359*150812a8SEvalZero  */
360*150812a8SEvalZero __STATIC_INLINE void nrf_twis_rx_buffer_set(
361*150812a8SEvalZero         NRF_TWIS_Type     * const p_reg,
362*150812a8SEvalZero         uint8_t           * p_buf,
363*150812a8SEvalZero         nrf_twis_amount_t   length);
364*150812a8SEvalZero 
365*150812a8SEvalZero /**
366*150812a8SEvalZero  * @brief Function that prepares TWIS for receiving
367*150812a8SEvalZero  *
368*150812a8SEvalZero  * This function sets receive buffer and then sets NRF_TWIS_TASK_PREPARERX task.
369*150812a8SEvalZero  * @param[in] p_reg Pointer to the peripheral registers structure.
370*150812a8SEvalZero  * @param     p_buf  Pointer to the buffer for received data.
371*150812a8SEvalZero  * @param     length Maximum number of data bytes to receive.
372*150812a8SEvalZero  */
373*150812a8SEvalZero __STATIC_INLINE void nrf_twis_rx_prepare(
374*150812a8SEvalZero         NRF_TWIS_Type     * const p_reg,
375*150812a8SEvalZero         uint8_t           * p_buf,
376*150812a8SEvalZero         nrf_twis_amount_t   length);
377*150812a8SEvalZero 
378*150812a8SEvalZero /**
379*150812a8SEvalZero  * @brief Function for getting number of bytes received in the last transaction.
380*150812a8SEvalZero  *
381*150812a8SEvalZero  * @param[in] p_reg TWIS instance.
382*150812a8SEvalZero  * @return Amount of bytes received.
383*150812a8SEvalZero  * */
384*150812a8SEvalZero __STATIC_INLINE nrf_twis_amount_t nrf_twis_rx_amount_get(NRF_TWIS_Type const * const p_reg);
385*150812a8SEvalZero 
386*150812a8SEvalZero /**
387*150812a8SEvalZero  * @brief Function for setting the transmit buffer.
388*150812a8SEvalZero  *
389*150812a8SEvalZero  * @param[in] p_reg Pointer to the peripheral registers structure.
390*150812a8SEvalZero  * @param     p_buf  Pointer to the buffer with data to send.
391*150812a8SEvalZero  * @param     length Maximum number of data bytes to transmit.
392*150812a8SEvalZero  */
393*150812a8SEvalZero __STATIC_INLINE void nrf_twis_tx_buffer_set(
394*150812a8SEvalZero         NRF_TWIS_Type     * const p_reg,
395*150812a8SEvalZero         uint8_t const     * p_buf,
396*150812a8SEvalZero         nrf_twis_amount_t   length);
397*150812a8SEvalZero 
398*150812a8SEvalZero /**
399*150812a8SEvalZero  * @brief Function that prepares TWIS for transmitting
400*150812a8SEvalZero  *
401*150812a8SEvalZero  * This function sets transmit buffer and then sets NRF_TWIS_TASK_PREPARETX task.
402*150812a8SEvalZero  * @param[in] p_reg Pointer to the peripheral registers structure.
403*150812a8SEvalZero  * @param     p_buf  Pointer to the buffer with data to send.
404*150812a8SEvalZero  * @param     length Maximum number of data bytes to transmit.
405*150812a8SEvalZero  */
406*150812a8SEvalZero __STATIC_INLINE void nrf_twis_tx_prepare(
407*150812a8SEvalZero         NRF_TWIS_Type     * const p_reg,
408*150812a8SEvalZero         uint8_t const     * p_buf,
409*150812a8SEvalZero         nrf_twis_amount_t   length);
410*150812a8SEvalZero 
411*150812a8SEvalZero /**
412*150812a8SEvalZero  * @brief Function for getting number of bytes transmitted in the last transaction.
413*150812a8SEvalZero  *
414*150812a8SEvalZero  * @param[in] p_reg Pointer to the peripheral registers structure.
415*150812a8SEvalZero  * @return Amount of bytes transmitted.
416*150812a8SEvalZero  */
417*150812a8SEvalZero __STATIC_INLINE nrf_twis_amount_t nrf_twis_tx_amount_get(NRF_TWIS_Type const * const p_reg);
418*150812a8SEvalZero 
419*150812a8SEvalZero /**
420*150812a8SEvalZero  * @brief Function for setting slave address
421*150812a8SEvalZero  *
422*150812a8SEvalZero  * Function sets the selected address for this TWI interface.
423*150812a8SEvalZero  * @param[in] p_reg Pointer to the peripheral registers structure.
424*150812a8SEvalZero  * @param     n Index of address to set
425*150812a8SEvalZero  * @param     addr Addres to set
426*150812a8SEvalZero  * @sa nrf_twis_config_address_set
427*150812a8SEvalZero  * @sa nrf_twis_config_address_get
428*150812a8SEvalZero  */
429*150812a8SEvalZero __STATIC_INLINE void nrf_twis_address_set(
430*150812a8SEvalZero         NRF_TWIS_Type      * const p_reg,
431*150812a8SEvalZero         uint_fast8_t         n,
432*150812a8SEvalZero         nrf_twis_address_t   addr);
433*150812a8SEvalZero 
434*150812a8SEvalZero /**
435*150812a8SEvalZero  * @brief Function for retrieving configured slave address
436*150812a8SEvalZero  *
437*150812a8SEvalZero  * Function gets the selected address for this TWI interface.
438*150812a8SEvalZero  * @param[in] p_reg Pointer to the peripheral registers structure.
439*150812a8SEvalZero  * @param n   Index of address to get
440*150812a8SEvalZero  */
441*150812a8SEvalZero __STATIC_INLINE nrf_twis_address_t nrf_twis_address_get(
442*150812a8SEvalZero         NRF_TWIS_Type const * const p_reg,
443*150812a8SEvalZero         uint_fast8_t          n);
444*150812a8SEvalZero 
445*150812a8SEvalZero /**
446*150812a8SEvalZero  * @brief Function for setting the device address configuration.
447*150812a8SEvalZero  *
448*150812a8SEvalZero  * @param[in] p_reg    Pointer to the peripheral registers structure.
449*150812a8SEvalZero  * @param     addr_mask Mask of address indexes of what device should answer to.
450*150812a8SEvalZero  *
451*150812a8SEvalZero  * @sa nrf_twis_address_set
452*150812a8SEvalZero  */
453*150812a8SEvalZero __STATIC_INLINE void nrf_twis_config_address_set(
454*150812a8SEvalZero         NRF_TWIS_Type              * const p_reg,
455*150812a8SEvalZero         nrf_twis_config_addr_mask_t        addr_mask);
456*150812a8SEvalZero 
457*150812a8SEvalZero /**
458*150812a8SEvalZero  * @brief Function for retrieving the device address configuration.
459*150812a8SEvalZero  *
460*150812a8SEvalZero  * @param[in] p_reg Pointer to the peripheral registers structure.
461*150812a8SEvalZero  *
462*150812a8SEvalZero  * @return Mask of address indexes of what device should answer to.
463*150812a8SEvalZero  */
464*150812a8SEvalZero __STATIC_INLINE nrf_twis_config_addr_mask_t nrf_twis_config_address_get(
465*150812a8SEvalZero         NRF_TWIS_Type const * const p_reg);
466*150812a8SEvalZero 
467*150812a8SEvalZero /**
468*150812a8SEvalZero  * @brief Function for setting the over-read character.
469*150812a8SEvalZero  *
470*150812a8SEvalZero  * @param[in] p_reg    Pointer to the peripheral registers structure.
471*150812a8SEvalZero  * @param[in] orc       Over-read character. Character clocked out in case of
472*150812a8SEvalZero  *                      over-read of the TXD buffer.
473*150812a8SEvalZero  */
474*150812a8SEvalZero __STATIC_INLINE void nrf_twis_orc_set(
475*150812a8SEvalZero         NRF_TWIS_Type * const p_reg,
476*150812a8SEvalZero         uint8_t         orc);
477*150812a8SEvalZero 
478*150812a8SEvalZero /**
479*150812a8SEvalZero  * @brief Function for setting the over-read character.
480*150812a8SEvalZero  *
481*150812a8SEvalZero  * @param[in] p_reg Pointer to the peripheral registers structure.
482*150812a8SEvalZero  *
483*150812a8SEvalZero  * @return Over-read character configured for selected instance.
484*150812a8SEvalZero  */
485*150812a8SEvalZero __STATIC_INLINE uint8_t nrf_twis_orc_get(NRF_TWIS_Type const * const p_reg);
486*150812a8SEvalZero 
487*150812a8SEvalZero 
488*150812a8SEvalZero /** @} */ /*  End of nrf_twis_hal */
489*150812a8SEvalZero 
490*150812a8SEvalZero #ifndef SUPPRESS_INLINE_IMPLEMENTATION
491*150812a8SEvalZero 
492*150812a8SEvalZero /* ------------------------------------------------------------------------------------------------
493*150812a8SEvalZero  *  Internal functions
494*150812a8SEvalZero  */
495*150812a8SEvalZero 
496*150812a8SEvalZero /**
497*150812a8SEvalZero  * @internal
498*150812a8SEvalZero  * @brief Internal function for getting task/event register address
499*150812a8SEvalZero  *
500*150812a8SEvalZero  * @param[in] p_reg Pointer to the peripheral registers structure.
501*150812a8SEvalZero  * @oaram     offset Offset of the register from the instance beginning
502*150812a8SEvalZero  *
503*150812a8SEvalZero  * @attention offset has to be modulo 4 value. In other case we can get hardware fault.
504*150812a8SEvalZero  * @return Pointer to the register
505*150812a8SEvalZero  */
nrf_twis_getRegPtr(NRF_TWIS_Type * const p_reg,uint32_t offset)506*150812a8SEvalZero __STATIC_INLINE volatile uint32_t* nrf_twis_getRegPtr(NRF_TWIS_Type * const p_reg, uint32_t offset)
507*150812a8SEvalZero {
508*150812a8SEvalZero     return (volatile uint32_t*)((uint8_t *)p_reg + (uint32_t)offset);
509*150812a8SEvalZero }
510*150812a8SEvalZero 
511*150812a8SEvalZero /**
512*150812a8SEvalZero  * @internal
513*150812a8SEvalZero  * @brief Internal function for getting task/event register address - constant version
514*150812a8SEvalZero  *
515*150812a8SEvalZero  * @param[in] p_reg Pointer to the peripheral registers structure.
516*150812a8SEvalZero  * @oaram     offset Offset of the register from the instance beginning
517*150812a8SEvalZero  *
518*150812a8SEvalZero  * @attention offset has to be modulo 4 value. In other case we can get hardware fault.
519*150812a8SEvalZero  * @return Pointer to the register
520*150812a8SEvalZero  */
nrf_twis_getRegPtr_c(NRF_TWIS_Type const * const p_reg,uint32_t offset)521*150812a8SEvalZero __STATIC_INLINE volatile const uint32_t* nrf_twis_getRegPtr_c(NRF_TWIS_Type const * const p_reg, uint32_t offset)
522*150812a8SEvalZero {
523*150812a8SEvalZero     return (volatile const uint32_t*)((uint8_t *)p_reg + (uint32_t)offset);
524*150812a8SEvalZero }
525*150812a8SEvalZero 
526*150812a8SEvalZero 
527*150812a8SEvalZero /* ------------------------------------------------------------------------------------------------
528*150812a8SEvalZero  *  Interface functions definitions
529*150812a8SEvalZero  */
530*150812a8SEvalZero 
531*150812a8SEvalZero 
nrf_twis_task_trigger(NRF_TWIS_Type * const p_reg,nrf_twis_task_t task)532*150812a8SEvalZero void nrf_twis_task_trigger(NRF_TWIS_Type * const p_reg, nrf_twis_task_t task)
533*150812a8SEvalZero {
534*150812a8SEvalZero     *(nrf_twis_getRegPtr(p_reg, (uint32_t)task)) = 1UL;
535*150812a8SEvalZero }
536*150812a8SEvalZero 
nrf_twis_task_address_get(NRF_TWIS_Type const * const p_reg,nrf_twis_task_t task)537*150812a8SEvalZero uint32_t nrf_twis_task_address_get(
538*150812a8SEvalZero         NRF_TWIS_Type const * const p_reg,
539*150812a8SEvalZero         nrf_twis_task_t       task)
540*150812a8SEvalZero {
541*150812a8SEvalZero     return (uint32_t)nrf_twis_getRegPtr_c(p_reg, (uint32_t)task);
542*150812a8SEvalZero }
543*150812a8SEvalZero 
nrf_twis_event_clear(NRF_TWIS_Type * const p_reg,nrf_twis_event_t event)544*150812a8SEvalZero void nrf_twis_event_clear(
545*150812a8SEvalZero         NRF_TWIS_Type     * const p_reg,
546*150812a8SEvalZero         nrf_twis_event_t    event)
547*150812a8SEvalZero {
548*150812a8SEvalZero     *(nrf_twis_getRegPtr(p_reg, (uint32_t)event)) = 0UL;
549*150812a8SEvalZero #if __CORTEX_M == 0x04
550*150812a8SEvalZero     volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
551*150812a8SEvalZero     (void)dummy;
552*150812a8SEvalZero #endif
553*150812a8SEvalZero }
554*150812a8SEvalZero 
nrf_twis_event_check(NRF_TWIS_Type const * const p_reg,nrf_twis_event_t event)555*150812a8SEvalZero bool nrf_twis_event_check(
556*150812a8SEvalZero         NRF_TWIS_Type const * const p_reg,
557*150812a8SEvalZero         nrf_twis_event_t      event)
558*150812a8SEvalZero {
559*150812a8SEvalZero     return (bool)*nrf_twis_getRegPtr_c(p_reg, (uint32_t)event);
560*150812a8SEvalZero }
561*150812a8SEvalZero 
nrf_twis_event_get_and_clear(NRF_TWIS_Type * const p_reg,nrf_twis_event_t event)562*150812a8SEvalZero bool nrf_twis_event_get_and_clear(
563*150812a8SEvalZero         NRF_TWIS_Type    * const p_reg,
564*150812a8SEvalZero         nrf_twis_event_t   event)
565*150812a8SEvalZero {
566*150812a8SEvalZero     bool ret = nrf_twis_event_check(p_reg, event);
567*150812a8SEvalZero     if (ret)
568*150812a8SEvalZero     {
569*150812a8SEvalZero         nrf_twis_event_clear(p_reg, event);
570*150812a8SEvalZero     }
571*150812a8SEvalZero     return ret;
572*150812a8SEvalZero }
573*150812a8SEvalZero 
nrf_twis_event_address_get(NRF_TWIS_Type const * const p_reg,nrf_twis_event_t event)574*150812a8SEvalZero uint32_t nrf_twis_event_address_get(
575*150812a8SEvalZero         NRF_TWIS_Type const * const p_reg,
576*150812a8SEvalZero         nrf_twis_event_t      event)
577*150812a8SEvalZero {
578*150812a8SEvalZero     return (uint32_t)nrf_twis_getRegPtr_c(p_reg, (uint32_t)event);
579*150812a8SEvalZero }
580*150812a8SEvalZero 
nrf_twis_shorts_enable(NRF_TWIS_Type * const p_reg,uint32_t short_mask)581*150812a8SEvalZero void nrf_twis_shorts_enable(NRF_TWIS_Type * const p_reg, uint32_t short_mask)
582*150812a8SEvalZero {
583*150812a8SEvalZero     p_reg->SHORTS |= short_mask;
584*150812a8SEvalZero }
585*150812a8SEvalZero 
nrf_twis_shorts_disable(NRF_TWIS_Type * const p_reg,uint32_t short_mask)586*150812a8SEvalZero void nrf_twis_shorts_disable(NRF_TWIS_Type * const p_reg, uint32_t short_mask)
587*150812a8SEvalZero {
588*150812a8SEvalZero     if (~0U == short_mask)
589*150812a8SEvalZero     {
590*150812a8SEvalZero         /* Optimized version for "disable all" */
591*150812a8SEvalZero         p_reg->SHORTS = 0;
592*150812a8SEvalZero     }
593*150812a8SEvalZero     else
594*150812a8SEvalZero     {
595*150812a8SEvalZero         p_reg->SHORTS &= ~short_mask;
596*150812a8SEvalZero     }
597*150812a8SEvalZero }
598*150812a8SEvalZero 
nrf_twis_shorts_get(NRF_TWIS_Type * const p_reg)599*150812a8SEvalZero uint32_t nrf_twis_shorts_get(NRF_TWIS_Type * const p_reg)
600*150812a8SEvalZero {
601*150812a8SEvalZero     return p_reg->SHORTS;
602*150812a8SEvalZero }
603*150812a8SEvalZero 
nrf_twis_int_enable(NRF_TWIS_Type * const p_reg,uint32_t int_mask)604*150812a8SEvalZero void nrf_twis_int_enable(NRF_TWIS_Type * const p_reg, uint32_t int_mask)
605*150812a8SEvalZero {
606*150812a8SEvalZero     p_reg->INTENSET = int_mask;
607*150812a8SEvalZero }
608*150812a8SEvalZero 
nrf_twis_int_enable_check(NRF_TWIS_Type const * const p_reg,uint32_t int_mask)609*150812a8SEvalZero bool nrf_twis_int_enable_check(NRF_TWIS_Type const * const p_reg, uint32_t int_mask)
610*150812a8SEvalZero {
611*150812a8SEvalZero     return (bool)(p_reg->INTENSET & int_mask);
612*150812a8SEvalZero }
613*150812a8SEvalZero 
nrf_twis_int_disable(NRF_TWIS_Type * const p_reg,uint32_t int_mask)614*150812a8SEvalZero void nrf_twis_int_disable(NRF_TWIS_Type * const p_reg, uint32_t int_mask)
615*150812a8SEvalZero {
616*150812a8SEvalZero     p_reg->INTENCLR = int_mask;
617*150812a8SEvalZero }
618*150812a8SEvalZero 
619*150812a8SEvalZero #if defined(DPPI_PRESENT)
nrf_twis_subscribe_set(NRF_TWIS_Type * p_reg,nrf_twis_task_t task,uint8_t channel)620*150812a8SEvalZero __STATIC_INLINE void nrf_twis_subscribe_set(NRF_TWIS_Type * p_reg,
621*150812a8SEvalZero                                             nrf_twis_task_t task,
622*150812a8SEvalZero                                             uint8_t        channel)
623*150812a8SEvalZero {
624*150812a8SEvalZero     *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
625*150812a8SEvalZero             ((uint32_t)channel | TWIS_SUBSCRIBE_STOP_EN_Msk);
626*150812a8SEvalZero }
627*150812a8SEvalZero 
nrf_twis_subscribe_clear(NRF_TWIS_Type * p_reg,nrf_twis_task_t task)628*150812a8SEvalZero __STATIC_INLINE void nrf_twis_subscribe_clear(NRF_TWIS_Type * p_reg,
629*150812a8SEvalZero                                               nrf_twis_task_t task)
630*150812a8SEvalZero {
631*150812a8SEvalZero     *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
632*150812a8SEvalZero }
633*150812a8SEvalZero 
nrf_twis_publish_set(NRF_TWIS_Type * p_reg,nrf_twis_event_t event,uint8_t channel)634*150812a8SEvalZero __STATIC_INLINE void nrf_twis_publish_set(NRF_TWIS_Type *  p_reg,
635*150812a8SEvalZero                                           nrf_twis_event_t event,
636*150812a8SEvalZero                                           uint8_t         channel)
637*150812a8SEvalZero {
638*150812a8SEvalZero     *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
639*150812a8SEvalZero             ((uint32_t)channel | TWIS_PUBLISH_STOPPED_EN_Msk);
640*150812a8SEvalZero }
641*150812a8SEvalZero 
nrf_twis_publish_clear(NRF_TWIS_Type * p_reg,nrf_twis_event_t event)642*150812a8SEvalZero __STATIC_INLINE void nrf_twis_publish_clear(NRF_TWIS_Type *  p_reg,
643*150812a8SEvalZero                                             nrf_twis_event_t event)
644*150812a8SEvalZero {
645*150812a8SEvalZero     *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0;
646*150812a8SEvalZero }
647*150812a8SEvalZero #endif // defined(DPPI_PRESENT)
648*150812a8SEvalZero 
nrf_twis_error_source_get_and_clear(NRF_TWIS_Type * const p_reg)649*150812a8SEvalZero uint32_t nrf_twis_error_source_get_and_clear(NRF_TWIS_Type * const p_reg)
650*150812a8SEvalZero {
651*150812a8SEvalZero     uint32_t ret = p_reg->ERRORSRC;
652*150812a8SEvalZero     p_reg->ERRORSRC = ret;
653*150812a8SEvalZero     return ret;
654*150812a8SEvalZero }
655*150812a8SEvalZero 
nrf_twis_match_get(NRF_TWIS_Type const * p_reg)656*150812a8SEvalZero uint_fast8_t nrf_twis_match_get(NRF_TWIS_Type const * p_reg)
657*150812a8SEvalZero {
658*150812a8SEvalZero     return (uint_fast8_t)p_reg->MATCH;
659*150812a8SEvalZero }
660*150812a8SEvalZero 
nrf_twis_enable(NRF_TWIS_Type * const p_reg)661*150812a8SEvalZero void nrf_twis_enable(NRF_TWIS_Type * const p_reg)
662*150812a8SEvalZero {
663*150812a8SEvalZero     p_reg->ENABLE = (TWIS_ENABLE_ENABLE_Enabled << TWIS_ENABLE_ENABLE_Pos);
664*150812a8SEvalZero }
665*150812a8SEvalZero 
nrf_twis_disable(NRF_TWIS_Type * const p_reg)666*150812a8SEvalZero void nrf_twis_disable(NRF_TWIS_Type * const p_reg)
667*150812a8SEvalZero {
668*150812a8SEvalZero     p_reg->ENABLE = (TWIS_ENABLE_ENABLE_Disabled << TWIS_ENABLE_ENABLE_Pos);
669*150812a8SEvalZero }
670*150812a8SEvalZero 
nrf_twis_pins_set(NRF_TWIS_Type * const p_reg,uint32_t scl,uint32_t sda)671*150812a8SEvalZero void nrf_twis_pins_set(NRF_TWIS_Type * const p_reg, uint32_t scl, uint32_t sda)
672*150812a8SEvalZero {
673*150812a8SEvalZero     p_reg->PSEL.SCL = scl;
674*150812a8SEvalZero     p_reg->PSEL.SDA = sda;
675*150812a8SEvalZero }
676*150812a8SEvalZero 
nrf_twis_rx_buffer_set(NRF_TWIS_Type * const p_reg,uint8_t * p_buf,nrf_twis_amount_t length)677*150812a8SEvalZero void nrf_twis_rx_buffer_set(
678*150812a8SEvalZero         NRF_TWIS_Type     * const p_reg,
679*150812a8SEvalZero         uint8_t           * p_buf,
680*150812a8SEvalZero         nrf_twis_amount_t   length)
681*150812a8SEvalZero {
682*150812a8SEvalZero     p_reg->RXD.PTR    = (uint32_t)p_buf;
683*150812a8SEvalZero     p_reg->RXD.MAXCNT = length;
684*150812a8SEvalZero }
685*150812a8SEvalZero 
nrf_twis_rx_prepare(NRF_TWIS_Type * const p_reg,uint8_t * p_buf,nrf_twis_amount_t length)686*150812a8SEvalZero __STATIC_INLINE void nrf_twis_rx_prepare(
687*150812a8SEvalZero         NRF_TWIS_Type     * const p_reg,
688*150812a8SEvalZero         uint8_t           * p_buf,
689*150812a8SEvalZero         nrf_twis_amount_t   length)
690*150812a8SEvalZero {
691*150812a8SEvalZero     nrf_twis_rx_buffer_set(p_reg, p_buf, length);
692*150812a8SEvalZero     nrf_twis_task_trigger(p_reg, NRF_TWIS_TASK_PREPARERX);
693*150812a8SEvalZero }
694*150812a8SEvalZero 
nrf_twis_rx_amount_get(NRF_TWIS_Type const * const p_reg)695*150812a8SEvalZero nrf_twis_amount_t nrf_twis_rx_amount_get(NRF_TWIS_Type const * const p_reg)
696*150812a8SEvalZero {
697*150812a8SEvalZero     return (nrf_twis_amount_t)p_reg->RXD.AMOUNT;
698*150812a8SEvalZero }
699*150812a8SEvalZero 
nrf_twis_tx_buffer_set(NRF_TWIS_Type * const p_reg,uint8_t const * p_buf,nrf_twis_amount_t length)700*150812a8SEvalZero void nrf_twis_tx_buffer_set(
701*150812a8SEvalZero         NRF_TWIS_Type     * const p_reg,
702*150812a8SEvalZero         uint8_t const     * p_buf,
703*150812a8SEvalZero         nrf_twis_amount_t   length)
704*150812a8SEvalZero {
705*150812a8SEvalZero     p_reg->TXD.PTR    = (uint32_t)p_buf;
706*150812a8SEvalZero     p_reg->TXD.MAXCNT = length;
707*150812a8SEvalZero }
708*150812a8SEvalZero 
nrf_twis_tx_prepare(NRF_TWIS_Type * const p_reg,uint8_t const * p_buf,nrf_twis_amount_t length)709*150812a8SEvalZero __STATIC_INLINE void nrf_twis_tx_prepare(
710*150812a8SEvalZero         NRF_TWIS_Type     * const p_reg,
711*150812a8SEvalZero         uint8_t const     * p_buf,
712*150812a8SEvalZero         nrf_twis_amount_t   length)
713*150812a8SEvalZero {
714*150812a8SEvalZero     nrf_twis_tx_buffer_set(p_reg, p_buf, length);
715*150812a8SEvalZero     nrf_twis_task_trigger(p_reg, NRF_TWIS_TASK_PREPARETX);
716*150812a8SEvalZero }
717*150812a8SEvalZero 
nrf_twis_tx_amount_get(NRF_TWIS_Type const * const p_reg)718*150812a8SEvalZero nrf_twis_amount_t nrf_twis_tx_amount_get(NRF_TWIS_Type const * const p_reg)
719*150812a8SEvalZero {
720*150812a8SEvalZero     return (nrf_twis_amount_t)p_reg->TXD.AMOUNT;
721*150812a8SEvalZero }
722*150812a8SEvalZero 
nrf_twis_address_set(NRF_TWIS_Type * const p_reg,uint_fast8_t n,nrf_twis_address_t addr)723*150812a8SEvalZero void nrf_twis_address_set(
724*150812a8SEvalZero         NRF_TWIS_Type      * const p_reg,
725*150812a8SEvalZero         uint_fast8_t         n,
726*150812a8SEvalZero         nrf_twis_address_t   addr)
727*150812a8SEvalZero {
728*150812a8SEvalZero     p_reg->ADDRESS[n] = addr;
729*150812a8SEvalZero }
730*150812a8SEvalZero 
nrf_twis_address_get(NRF_TWIS_Type const * const p_reg,uint_fast8_t n)731*150812a8SEvalZero nrf_twis_address_t nrf_twis_address_get(
732*150812a8SEvalZero         NRF_TWIS_Type const * const p_reg,
733*150812a8SEvalZero         uint_fast8_t          n)
734*150812a8SEvalZero {
735*150812a8SEvalZero     return (nrf_twis_address_t)p_reg->ADDRESS[n];
736*150812a8SEvalZero }
nrf_twis_config_address_set(NRF_TWIS_Type * const p_reg,nrf_twis_config_addr_mask_t addr_mask)737*150812a8SEvalZero void nrf_twis_config_address_set(
738*150812a8SEvalZero         NRF_TWIS_Type              * const p_reg,
739*150812a8SEvalZero         nrf_twis_config_addr_mask_t        addr_mask)
740*150812a8SEvalZero {
741*150812a8SEvalZero     /* This is the only configuration in TWIS - just write it without masking */
742*150812a8SEvalZero     p_reg->CONFIG = addr_mask;
743*150812a8SEvalZero }
744*150812a8SEvalZero 
nrf_twis_config_address_get(NRF_TWIS_Type const * const p_reg)745*150812a8SEvalZero nrf_twis_config_addr_mask_t nrf_twis_config_address_get(NRF_TWIS_Type const * const p_reg)
746*150812a8SEvalZero {
747*150812a8SEvalZero     return (nrf_twis_config_addr_mask_t)(p_reg->CONFIG & TWIS_ADDRESS_ADDRESS_Msk);
748*150812a8SEvalZero }
749*150812a8SEvalZero 
nrf_twis_orc_set(NRF_TWIS_Type * const p_reg,uint8_t orc)750*150812a8SEvalZero void nrf_twis_orc_set(
751*150812a8SEvalZero         NRF_TWIS_Type * const p_reg,
752*150812a8SEvalZero         uint8_t         orc)
753*150812a8SEvalZero {
754*150812a8SEvalZero     p_reg->ORC = orc;
755*150812a8SEvalZero }
756*150812a8SEvalZero 
nrf_twis_orc_get(NRF_TWIS_Type const * const p_reg)757*150812a8SEvalZero uint8_t nrf_twis_orc_get(NRF_TWIS_Type const * const p_reg)
758*150812a8SEvalZero {
759*150812a8SEvalZero     return (uint8_t)p_reg->ORC;
760*150812a8SEvalZero }
761*150812a8SEvalZero 
762*150812a8SEvalZero #endif /* SUPPRESS_INLINE_IMPLEMENTATION */
763*150812a8SEvalZero 
764*150812a8SEvalZero 
765*150812a8SEvalZero #ifdef __cplusplus
766*150812a8SEvalZero }
767*150812a8SEvalZero #endif
768*150812a8SEvalZero 
769*150812a8SEvalZero #endif /* NRF_TWIS_H__ */
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