1*150812a8SEvalZero /*
2*150812a8SEvalZero * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
3*150812a8SEvalZero * All rights reserved.
4*150812a8SEvalZero *
5*150812a8SEvalZero * Redistribution and use in source and binary forms, with or without
6*150812a8SEvalZero * modification, are permitted provided that the following conditions are met:
7*150812a8SEvalZero *
8*150812a8SEvalZero * 1. Redistributions of source code must retain the above copyright notice, this
9*150812a8SEvalZero * list of conditions and the following disclaimer.
10*150812a8SEvalZero *
11*150812a8SEvalZero * 2. Redistributions in binary form must reproduce the above copyright
12*150812a8SEvalZero * notice, this list of conditions and the following disclaimer in the
13*150812a8SEvalZero * documentation and/or other materials provided with the distribution.
14*150812a8SEvalZero *
15*150812a8SEvalZero * 3. Neither the name of the copyright holder nor the names of its
16*150812a8SEvalZero * contributors may be used to endorse or promote products derived from this
17*150812a8SEvalZero * software without specific prior written permission.
18*150812a8SEvalZero *
19*150812a8SEvalZero * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20*150812a8SEvalZero * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21*150812a8SEvalZero * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22*150812a8SEvalZero * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23*150812a8SEvalZero * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24*150812a8SEvalZero * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25*150812a8SEvalZero * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26*150812a8SEvalZero * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27*150812a8SEvalZero * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28*150812a8SEvalZero * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29*150812a8SEvalZero * POSSIBILITY OF SUCH DAMAGE.
30*150812a8SEvalZero */
31*150812a8SEvalZero
32*150812a8SEvalZero #ifndef NRF_TWIM_H__
33*150812a8SEvalZero #define NRF_TWIM_H__
34*150812a8SEvalZero
35*150812a8SEvalZero #include <nrfx.h>
36*150812a8SEvalZero
37*150812a8SEvalZero #ifdef __cplusplus
38*150812a8SEvalZero extern "C" {
39*150812a8SEvalZero #endif
40*150812a8SEvalZero
41*150812a8SEvalZero /**
42*150812a8SEvalZero * @defgroup nrf_twim_hal TWIM HAL
43*150812a8SEvalZero * @{
44*150812a8SEvalZero * @ingroup nrf_twim
45*150812a8SEvalZero * @brief Hardware access layer for managing the TWIM peripheral.
46*150812a8SEvalZero */
47*150812a8SEvalZero
48*150812a8SEvalZero /**
49*150812a8SEvalZero * @brief TWIM tasks.
50*150812a8SEvalZero */
51*150812a8SEvalZero typedef enum
52*150812a8SEvalZero {
53*150812a8SEvalZero /*lint -save -e30*/
54*150812a8SEvalZero NRF_TWIM_TASK_STARTRX = offsetof(NRF_TWIM_Type, TASKS_STARTRX), ///< Start TWI receive sequence.
55*150812a8SEvalZero NRF_TWIM_TASK_STARTTX = offsetof(NRF_TWIM_Type, TASKS_STARTTX), ///< Start TWI transmit sequence.
56*150812a8SEvalZero NRF_TWIM_TASK_STOP = offsetof(NRF_TWIM_Type, TASKS_STOP), ///< Stop TWI transaction.
57*150812a8SEvalZero NRF_TWIM_TASK_SUSPEND = offsetof(NRF_TWIM_Type, TASKS_SUSPEND), ///< Suspend TWI transaction.
58*150812a8SEvalZero NRF_TWIM_TASK_RESUME = offsetof(NRF_TWIM_Type, TASKS_RESUME) ///< Resume TWI transaction.
59*150812a8SEvalZero /*lint -restore*/
60*150812a8SEvalZero } nrf_twim_task_t;
61*150812a8SEvalZero
62*150812a8SEvalZero /**
63*150812a8SEvalZero * @brief TWIM events.
64*150812a8SEvalZero */
65*150812a8SEvalZero typedef enum
66*150812a8SEvalZero {
67*150812a8SEvalZero /*lint -save -e30*/
68*150812a8SEvalZero NRF_TWIM_EVENT_STOPPED = offsetof(NRF_TWIM_Type, EVENTS_STOPPED), ///< TWI stopped.
69*150812a8SEvalZero NRF_TWIM_EVENT_ERROR = offsetof(NRF_TWIM_Type, EVENTS_ERROR), ///< TWI error.
70*150812a8SEvalZero NRF_TWIM_EVENT_SUSPENDED = 0x148, ///< TWI suspended.
71*150812a8SEvalZero NRF_TWIM_EVENT_RXSTARTED = offsetof(NRF_TWIM_Type, EVENTS_RXSTARTED), ///< Receive sequence started.
72*150812a8SEvalZero NRF_TWIM_EVENT_TXSTARTED = offsetof(NRF_TWIM_Type, EVENTS_TXSTARTED), ///< Transmit sequence started.
73*150812a8SEvalZero NRF_TWIM_EVENT_LASTRX = offsetof(NRF_TWIM_Type, EVENTS_LASTRX), ///< Byte boundary, starting to receive the last byte.
74*150812a8SEvalZero NRF_TWIM_EVENT_LASTTX = offsetof(NRF_TWIM_Type, EVENTS_LASTTX) ///< Byte boundary, starting to transmit the last byte.
75*150812a8SEvalZero /*lint -restore*/
76*150812a8SEvalZero } nrf_twim_event_t;
77*150812a8SEvalZero
78*150812a8SEvalZero /**
79*150812a8SEvalZero * @brief TWIM shortcuts.
80*150812a8SEvalZero */
81*150812a8SEvalZero typedef enum
82*150812a8SEvalZero {
83*150812a8SEvalZero NRF_TWIM_SHORT_LASTTX_STARTRX_MASK = TWIM_SHORTS_LASTTX_STARTRX_Msk, ///< Shortcut between LASTTX event and STARTRX task.
84*150812a8SEvalZero NRF_TWIM_SHORT_LASTTX_SUSPEND_MASK = TWIM_SHORTS_LASTTX_SUSPEND_Msk, ///< Shortcut between LASTTX event and SUSPEND task.
85*150812a8SEvalZero NRF_TWIM_SHORT_LASTTX_STOP_MASK = TWIM_SHORTS_LASTTX_STOP_Msk, ///< Shortcut between LASTTX event and STOP task.
86*150812a8SEvalZero NRF_TWIM_SHORT_LASTRX_STARTTX_MASK = TWIM_SHORTS_LASTRX_STARTTX_Msk, ///< Shortcut between LASTRX event and STARTTX task.
87*150812a8SEvalZero NRF_TWIM_SHORT_LASTRX_STOP_MASK = TWIM_SHORTS_LASTRX_STOP_Msk, ///< Shortcut between LASTRX event and STOP task.
88*150812a8SEvalZero NRF_TWIM_ALL_SHORTS_MASK = TWIM_SHORTS_LASTTX_STARTRX_Msk |
89*150812a8SEvalZero TWIM_SHORTS_LASTTX_SUSPEND_Msk |
90*150812a8SEvalZero TWIM_SHORTS_LASTTX_STOP_Msk |
91*150812a8SEvalZero TWIM_SHORTS_LASTRX_STARTTX_Msk |
92*150812a8SEvalZero TWIM_SHORTS_LASTRX_STOP_Msk ///< All TWIM shortcuts.
93*150812a8SEvalZero } nrf_twim_short_mask_t;
94*150812a8SEvalZero
95*150812a8SEvalZero /**
96*150812a8SEvalZero * @brief TWIM interrupts.
97*150812a8SEvalZero */
98*150812a8SEvalZero typedef enum
99*150812a8SEvalZero {
100*150812a8SEvalZero NRF_TWIM_INT_STOPPED_MASK = TWIM_INTENSET_STOPPED_Msk, ///< Interrupt on STOPPED event.
101*150812a8SEvalZero NRF_TWIM_INT_ERROR_MASK = TWIM_INTENSET_ERROR_Msk, ///< Interrupt on ERROR event.
102*150812a8SEvalZero NRF_TWIM_INT_SUSPENDED_MASK = TWIM_INTENSET_SUSPENDED_Msk, ///< Interrupt on SUSPENDED event.
103*150812a8SEvalZero NRF_TWIM_INT_RXSTARTED_MASK = TWIM_INTENSET_RXSTARTED_Msk, ///< Interrupt on RXSTARTED event.
104*150812a8SEvalZero NRF_TWIM_INT_TXSTARTED_MASK = TWIM_INTENSET_TXSTARTED_Msk, ///< Interrupt on TXSTARTED event.
105*150812a8SEvalZero NRF_TWIM_INT_LASTRX_MASK = TWIM_INTENSET_LASTRX_Msk, ///< Interrupt on LASTRX event.
106*150812a8SEvalZero NRF_TWIM_INT_LASTTX_MASK = TWIM_INTENSET_LASTTX_Msk, ///< Interrupt on LASTTX event.
107*150812a8SEvalZero NRF_TWIM_ALL_INTS_MASK = TWIM_INTENSET_STOPPED_Msk |
108*150812a8SEvalZero TWIM_INTENSET_ERROR_Msk |
109*150812a8SEvalZero TWIM_INTENSET_SUSPENDED_Msk |
110*150812a8SEvalZero TWIM_INTENSET_RXSTARTED_Msk |
111*150812a8SEvalZero TWIM_INTENSET_TXSTARTED_Msk |
112*150812a8SEvalZero TWIM_INTENSET_LASTRX_Msk |
113*150812a8SEvalZero TWIM_INTENSET_LASTTX_Msk ///< Interrupt on LASTTX event.
114*150812a8SEvalZero } nrf_twim_int_mask_t;
115*150812a8SEvalZero
116*150812a8SEvalZero /**
117*150812a8SEvalZero * @brief TWIM master clock frequency.
118*150812a8SEvalZero */
119*150812a8SEvalZero typedef enum
120*150812a8SEvalZero {
121*150812a8SEvalZero NRF_TWIM_FREQ_100K = TWIM_FREQUENCY_FREQUENCY_K100, ///< 100 kbps.
122*150812a8SEvalZero NRF_TWIM_FREQ_250K = TWIM_FREQUENCY_FREQUENCY_K250, ///< 250 kbps.
123*150812a8SEvalZero NRF_TWIM_FREQ_400K = TWIM_FREQUENCY_FREQUENCY_K400 ///< 400 kbps.
124*150812a8SEvalZero } nrf_twim_frequency_t;
125*150812a8SEvalZero
126*150812a8SEvalZero /**
127*150812a8SEvalZero * @brief TWIM error source.
128*150812a8SEvalZero */
129*150812a8SEvalZero typedef enum
130*150812a8SEvalZero {
131*150812a8SEvalZero NRF_TWIM_ERROR_ADDRESS_NACK = TWIM_ERRORSRC_ANACK_Msk, ///< NACK received after sending the address.
132*150812a8SEvalZero NRF_TWIM_ERROR_DATA_NACK = TWIM_ERRORSRC_DNACK_Msk ///< NACK received after sending a data byte.
133*150812a8SEvalZero } nrf_twim_error_t;
134*150812a8SEvalZero
135*150812a8SEvalZero
136*150812a8SEvalZero /**
137*150812a8SEvalZero * @brief Function for activating a specific TWIM task.
138*150812a8SEvalZero *
139*150812a8SEvalZero * @param[in] p_reg Pointer to the peripheral registers structure.
140*150812a8SEvalZero * @param[in] task Task to activate.
141*150812a8SEvalZero */
142*150812a8SEvalZero __STATIC_INLINE void nrf_twim_task_trigger(NRF_TWIM_Type * p_reg,
143*150812a8SEvalZero nrf_twim_task_t task);
144*150812a8SEvalZero
145*150812a8SEvalZero /**
146*150812a8SEvalZero * @brief Function for getting the address of a specific TWIM task register.
147*150812a8SEvalZero *
148*150812a8SEvalZero * @param[in] p_reg Pointer to the peripheral registers structure.
149*150812a8SEvalZero * @param[in] task Requested task.
150*150812a8SEvalZero *
151*150812a8SEvalZero * @return Address of the specified task register.
152*150812a8SEvalZero */
153*150812a8SEvalZero __STATIC_INLINE uint32_t * nrf_twim_task_address_get(NRF_TWIM_Type * p_reg,
154*150812a8SEvalZero nrf_twim_task_t task);
155*150812a8SEvalZero
156*150812a8SEvalZero /**
157*150812a8SEvalZero * @brief Function for clearing a specific TWIM event.
158*150812a8SEvalZero *
159*150812a8SEvalZero * @param[in] p_reg Pointer to the peripheral registers structure.
160*150812a8SEvalZero * @param[in] event Event to clear.
161*150812a8SEvalZero */
162*150812a8SEvalZero __STATIC_INLINE void nrf_twim_event_clear(NRF_TWIM_Type * p_reg,
163*150812a8SEvalZero nrf_twim_event_t event);
164*150812a8SEvalZero
165*150812a8SEvalZero /**
166*150812a8SEvalZero * @brief Function for checking the state of a specific TWIM event.
167*150812a8SEvalZero *
168*150812a8SEvalZero * @param[in] p_reg Pointer to the peripheral registers structure.
169*150812a8SEvalZero * @param[in] event Event to check.
170*150812a8SEvalZero *
171*150812a8SEvalZero * @retval true If the event is set.
172*150812a8SEvalZero * @retval false If the event is not set.
173*150812a8SEvalZero */
174*150812a8SEvalZero __STATIC_INLINE bool nrf_twim_event_check(NRF_TWIM_Type * p_reg,
175*150812a8SEvalZero nrf_twim_event_t event);
176*150812a8SEvalZero
177*150812a8SEvalZero /**
178*150812a8SEvalZero * @brief Function for getting the address of a specific TWIM event register.
179*150812a8SEvalZero *
180*150812a8SEvalZero * @param[in] p_reg Pointer to the peripheral registers structure.
181*150812a8SEvalZero * @param[in] event Requested event.
182*150812a8SEvalZero *
183*150812a8SEvalZero * @return Address of the specified event register.
184*150812a8SEvalZero */
185*150812a8SEvalZero __STATIC_INLINE uint32_t * nrf_twim_event_address_get(NRF_TWIM_Type * p_reg,
186*150812a8SEvalZero nrf_twim_event_t event);
187*150812a8SEvalZero
188*150812a8SEvalZero /**
189*150812a8SEvalZero * @brief Function for enabling specified shortcuts.
190*150812a8SEvalZero *
191*150812a8SEvalZero * @param[in] p_reg Pointer to the peripheral registers structure.
192*150812a8SEvalZero * @param[in] shorts_mask Shortcuts to enable.
193*150812a8SEvalZero */
194*150812a8SEvalZero __STATIC_INLINE void nrf_twim_shorts_enable(NRF_TWIM_Type * p_reg,
195*150812a8SEvalZero uint32_t shorts_mask);
196*150812a8SEvalZero
197*150812a8SEvalZero /**
198*150812a8SEvalZero * @brief Function for disabling specified shortcuts.
199*150812a8SEvalZero *
200*150812a8SEvalZero * @param[in] p_reg Pointer to the peripheral registers structure.
201*150812a8SEvalZero * @param[in] shorts_mask Shortcuts to disable.
202*150812a8SEvalZero */
203*150812a8SEvalZero __STATIC_INLINE void nrf_twim_shorts_disable(NRF_TWIM_Type * p_reg,
204*150812a8SEvalZero uint32_t shorts_mask);
205*150812a8SEvalZero
206*150812a8SEvalZero /**
207*150812a8SEvalZero * @brief Function for enabling specified interrupts.
208*150812a8SEvalZero *
209*150812a8SEvalZero * @param[in] p_reg Pointer to the peripheral registers structure.
210*150812a8SEvalZero * @param[in] int_mask Interrupts to enable.
211*150812a8SEvalZero */
212*150812a8SEvalZero __STATIC_INLINE void nrf_twim_int_enable(NRF_TWIM_Type * p_reg,
213*150812a8SEvalZero uint32_t int_mask);
214*150812a8SEvalZero
215*150812a8SEvalZero /**
216*150812a8SEvalZero * @brief Function for disabling specified interrupts.
217*150812a8SEvalZero *
218*150812a8SEvalZero * @param[in] p_reg Pointer to the peripheral registers structure.
219*150812a8SEvalZero * @param[in] int_mask Interrupts to disable.
220*150812a8SEvalZero */
221*150812a8SEvalZero __STATIC_INLINE void nrf_twim_int_disable(NRF_TWIM_Type * p_reg,
222*150812a8SEvalZero uint32_t int_mask);
223*150812a8SEvalZero
224*150812a8SEvalZero /**
225*150812a8SEvalZero * @brief Function for checking the state of a given interrupt.
226*150812a8SEvalZero *
227*150812a8SEvalZero * @param[in] p_reg Pointer to the peripheral registers structure.
228*150812a8SEvalZero * @param[in] int_mask Interrupt to check.
229*150812a8SEvalZero *
230*150812a8SEvalZero * @retval true If the interrupt is enabled.
231*150812a8SEvalZero * @retval false If the interrupt is not enabled.
232*150812a8SEvalZero */
233*150812a8SEvalZero __STATIC_INLINE bool nrf_twim_int_enable_check(NRF_TWIM_Type * p_reg,
234*150812a8SEvalZero nrf_twim_int_mask_t int_mask);
235*150812a8SEvalZero
236*150812a8SEvalZero #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
237*150812a8SEvalZero /**
238*150812a8SEvalZero * @brief Function for setting the subscribe configuration for a given
239*150812a8SEvalZero * TWIM task.
240*150812a8SEvalZero *
241*150812a8SEvalZero * @param[in] p_reg Pointer to the structure of registers of the peripheral.
242*150812a8SEvalZero * @param[in] task Task for which to set the configuration.
243*150812a8SEvalZero * @param[in] channel Channel through which to subscribe events.
244*150812a8SEvalZero */
245*150812a8SEvalZero __STATIC_INLINE void nrf_twim_subscribe_set(NRF_TWIM_Type * p_reg,
246*150812a8SEvalZero nrf_twim_task_t task,
247*150812a8SEvalZero uint8_t channel);
248*150812a8SEvalZero
249*150812a8SEvalZero /**
250*150812a8SEvalZero * @brief Function for clearing the subscribe configuration for a given
251*150812a8SEvalZero * TWIM task.
252*150812a8SEvalZero *
253*150812a8SEvalZero * @param[in] p_reg Pointer to the structure of registers of the peripheral.
254*150812a8SEvalZero * @param[in] task Task for which to clear the configuration.
255*150812a8SEvalZero */
256*150812a8SEvalZero __STATIC_INLINE void nrf_twim_subscribe_clear(NRF_TWIM_Type * p_reg,
257*150812a8SEvalZero nrf_twim_task_t task);
258*150812a8SEvalZero
259*150812a8SEvalZero /**
260*150812a8SEvalZero * @brief Function for setting the publish configuration for a given
261*150812a8SEvalZero * TWIM event.
262*150812a8SEvalZero *
263*150812a8SEvalZero * @param[in] p_reg Pointer to the structure of registers of the peripheral.
264*150812a8SEvalZero * @param[in] event Event for which to set the configuration.
265*150812a8SEvalZero * @param[in] channel Channel through which to publish the event.
266*150812a8SEvalZero */
267*150812a8SEvalZero __STATIC_INLINE void nrf_twim_publish_set(NRF_TWIM_Type * p_reg,
268*150812a8SEvalZero nrf_twim_event_t event,
269*150812a8SEvalZero uint8_t channel);
270*150812a8SEvalZero
271*150812a8SEvalZero /**
272*150812a8SEvalZero * @brief Function for clearing the publish configuration for a given
273*150812a8SEvalZero * TWIM event.
274*150812a8SEvalZero *
275*150812a8SEvalZero * @param[in] p_reg Pointer to the structure of registers of the peripheral.
276*150812a8SEvalZero * @param[in] event Event for which to clear the configuration.
277*150812a8SEvalZero */
278*150812a8SEvalZero __STATIC_INLINE void nrf_twim_publish_clear(NRF_TWIM_Type * p_reg,
279*150812a8SEvalZero nrf_twim_event_t event);
280*150812a8SEvalZero #endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
281*150812a8SEvalZero
282*150812a8SEvalZero /**
283*150812a8SEvalZero * @brief Function for enabling the TWIM peripheral.
284*150812a8SEvalZero *
285*150812a8SEvalZero * @param[in] p_reg Pointer to the peripheral registers structure.
286*150812a8SEvalZero */
287*150812a8SEvalZero __STATIC_INLINE void nrf_twim_enable(NRF_TWIM_Type * p_reg);
288*150812a8SEvalZero
289*150812a8SEvalZero /**
290*150812a8SEvalZero * @brief Function for disabling the TWIM peripheral.
291*150812a8SEvalZero *
292*150812a8SEvalZero * @param[in] p_reg Pointer to the peripheral registers structure.
293*150812a8SEvalZero */
294*150812a8SEvalZero __STATIC_INLINE void nrf_twim_disable(NRF_TWIM_Type * p_reg);
295*150812a8SEvalZero
296*150812a8SEvalZero /**
297*150812a8SEvalZero * @brief Function for configuring TWI pins.
298*150812a8SEvalZero *
299*150812a8SEvalZero *
300*150812a8SEvalZero * @param[in] p_reg Pointer to the peripheral registers structure.
301*150812a8SEvalZero * @param[in] scl_pin SCL pin number.
302*150812a8SEvalZero * @param[in] sda_pin SDA pin number.
303*150812a8SEvalZero */
304*150812a8SEvalZero __STATIC_INLINE void nrf_twim_pins_set(NRF_TWIM_Type * p_reg,
305*150812a8SEvalZero uint32_t scl_pin,
306*150812a8SEvalZero uint32_t sda_pin);
307*150812a8SEvalZero
308*150812a8SEvalZero /**
309*150812a8SEvalZero * @brief Function for setting the TWI master clock frequency.
310*150812a8SEvalZero *
311*150812a8SEvalZero * @param[in] p_reg Pointer to the peripheral registers structure.
312*150812a8SEvalZero * @param[in] frequency TWI frequency.
313*150812a8SEvalZero */
314*150812a8SEvalZero __STATIC_INLINE void nrf_twim_frequency_set(NRF_TWIM_Type * p_reg,
315*150812a8SEvalZero nrf_twim_frequency_t frequency);
316*150812a8SEvalZero
317*150812a8SEvalZero /**
318*150812a8SEvalZero * @brief Function for checking the TWI error source.
319*150812a8SEvalZero *
320*150812a8SEvalZero * The error flags are cleared after reading.
321*150812a8SEvalZero *
322*150812a8SEvalZero * @param[in] p_reg Pointer to the peripheral registers structure.
323*150812a8SEvalZero *
324*150812a8SEvalZero * @return Mask with error source flags.
325*150812a8SEvalZero */
326*150812a8SEvalZero __STATIC_INLINE uint32_t nrf_twim_errorsrc_get_and_clear(NRF_TWIM_Type * p_reg);
327*150812a8SEvalZero
328*150812a8SEvalZero /**
329*150812a8SEvalZero * @brief Function for setting the address to be used in TWI transfers.
330*150812a8SEvalZero *
331*150812a8SEvalZero * @param[in] p_reg Pointer to the peripheral registers structure.
332*150812a8SEvalZero * @param[in] address Address to be used in transfers.
333*150812a8SEvalZero */
334*150812a8SEvalZero __STATIC_INLINE void nrf_twim_address_set(NRF_TWIM_Type * p_reg,
335*150812a8SEvalZero uint8_t address);
336*150812a8SEvalZero
337*150812a8SEvalZero /**
338*150812a8SEvalZero * @brief Function for setting the transmit buffer.
339*150812a8SEvalZero *
340*150812a8SEvalZero * @param[in] p_reg Pointer to the peripheral registers structure.
341*150812a8SEvalZero * @param[in] p_buffer Pointer to the buffer with data to send.
342*150812a8SEvalZero * @param[in] length Maximum number of data bytes to transmit.
343*150812a8SEvalZero */
344*150812a8SEvalZero __STATIC_INLINE void nrf_twim_tx_buffer_set(NRF_TWIM_Type * p_reg,
345*150812a8SEvalZero uint8_t const * p_buffer,
346*150812a8SEvalZero size_t length);
347*150812a8SEvalZero
348*150812a8SEvalZero /**
349*150812a8SEvalZero * @brief Function for setting the receive buffer.
350*150812a8SEvalZero *
351*150812a8SEvalZero * @param[in] p_reg Pointer to the peripheral registers structure.
352*150812a8SEvalZero * @param[in] p_buffer Pointer to the buffer for received data.
353*150812a8SEvalZero * @param[in] length Maximum number of data bytes to receive.
354*150812a8SEvalZero */
355*150812a8SEvalZero __STATIC_INLINE void nrf_twim_rx_buffer_set(NRF_TWIM_Type * p_reg,
356*150812a8SEvalZero uint8_t * p_buffer,
357*150812a8SEvalZero size_t length);
358*150812a8SEvalZero
359*150812a8SEvalZero __STATIC_INLINE void nrf_twim_shorts_set(NRF_TWIM_Type * p_reg,
360*150812a8SEvalZero uint32_t shorts_mask);
361*150812a8SEvalZero
362*150812a8SEvalZero __STATIC_INLINE size_t nrf_twim_txd_amount_get(NRF_TWIM_Type * p_reg);
363*150812a8SEvalZero
364*150812a8SEvalZero __STATIC_INLINE size_t nrf_twim_rxd_amount_get(NRF_TWIM_Type * p_reg);
365*150812a8SEvalZero
366*150812a8SEvalZero /**
367*150812a8SEvalZero * @brief Function for enabling the TX list feature.
368*150812a8SEvalZero *
369*150812a8SEvalZero * @param[in] p_reg Pointer to the peripheral registers structure.
370*150812a8SEvalZero */
371*150812a8SEvalZero __STATIC_INLINE void nrf_twim_tx_list_enable(NRF_TWIM_Type * p_reg);
372*150812a8SEvalZero
373*150812a8SEvalZero /**
374*150812a8SEvalZero * @brief Function for disabling the TX list feature.
375*150812a8SEvalZero *
376*150812a8SEvalZero * @param[in] p_reg Pointer to the peripheral registers structure.
377*150812a8SEvalZero */
378*150812a8SEvalZero __STATIC_INLINE void nrf_twim_tx_list_disable(NRF_TWIM_Type * p_reg);
379*150812a8SEvalZero
380*150812a8SEvalZero /**
381*150812a8SEvalZero * @brief Function for enabling the RX list feature.
382*150812a8SEvalZero *
383*150812a8SEvalZero * @param[in] p_reg Pointer to the peripheral registers structure.
384*150812a8SEvalZero */
385*150812a8SEvalZero __STATIC_INLINE void nrf_twim_rx_list_enable(NRF_TWIM_Type * p_reg);
386*150812a8SEvalZero
387*150812a8SEvalZero /**
388*150812a8SEvalZero * @brief Function for disabling the RX list feature.
389*150812a8SEvalZero *
390*150812a8SEvalZero * @param[in] p_reg Pointer to the peripheral registers structure.
391*150812a8SEvalZero */
392*150812a8SEvalZero __STATIC_INLINE void nrf_twim_rx_list_disable(NRF_TWIM_Type * p_reg);
393*150812a8SEvalZero
394*150812a8SEvalZero #ifndef SUPPRESS_INLINE_IMPLEMENTATION
395*150812a8SEvalZero
nrf_twim_task_trigger(NRF_TWIM_Type * p_reg,nrf_twim_task_t task)396*150812a8SEvalZero __STATIC_INLINE void nrf_twim_task_trigger(NRF_TWIM_Type * p_reg,
397*150812a8SEvalZero nrf_twim_task_t task)
398*150812a8SEvalZero {
399*150812a8SEvalZero *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
400*150812a8SEvalZero }
401*150812a8SEvalZero
nrf_twim_task_address_get(NRF_TWIM_Type * p_reg,nrf_twim_task_t task)402*150812a8SEvalZero __STATIC_INLINE uint32_t * nrf_twim_task_address_get(NRF_TWIM_Type * p_reg,
403*150812a8SEvalZero nrf_twim_task_t task)
404*150812a8SEvalZero {
405*150812a8SEvalZero return (uint32_t *)((uint8_t *)p_reg + (uint32_t)task);
406*150812a8SEvalZero }
407*150812a8SEvalZero
nrf_twim_event_clear(NRF_TWIM_Type * p_reg,nrf_twim_event_t event)408*150812a8SEvalZero __STATIC_INLINE void nrf_twim_event_clear(NRF_TWIM_Type * p_reg,
409*150812a8SEvalZero nrf_twim_event_t event)
410*150812a8SEvalZero {
411*150812a8SEvalZero *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
412*150812a8SEvalZero #if __CORTEX_M == 0x04
413*150812a8SEvalZero volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
414*150812a8SEvalZero (void)dummy;
415*150812a8SEvalZero #endif
416*150812a8SEvalZero }
417*150812a8SEvalZero
nrf_twim_event_check(NRF_TWIM_Type * p_reg,nrf_twim_event_t event)418*150812a8SEvalZero __STATIC_INLINE bool nrf_twim_event_check(NRF_TWIM_Type * p_reg,
419*150812a8SEvalZero nrf_twim_event_t event)
420*150812a8SEvalZero {
421*150812a8SEvalZero return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
422*150812a8SEvalZero }
423*150812a8SEvalZero
nrf_twim_event_address_get(NRF_TWIM_Type * p_reg,nrf_twim_event_t event)424*150812a8SEvalZero __STATIC_INLINE uint32_t * nrf_twim_event_address_get(NRF_TWIM_Type * p_reg,
425*150812a8SEvalZero nrf_twim_event_t event)
426*150812a8SEvalZero {
427*150812a8SEvalZero return (uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
428*150812a8SEvalZero }
429*150812a8SEvalZero
nrf_twim_shorts_enable(NRF_TWIM_Type * p_reg,uint32_t shorts_mask)430*150812a8SEvalZero __STATIC_INLINE void nrf_twim_shorts_enable(NRF_TWIM_Type * p_reg,
431*150812a8SEvalZero uint32_t shorts_mask)
432*150812a8SEvalZero {
433*150812a8SEvalZero p_reg->SHORTS |= shorts_mask;
434*150812a8SEvalZero }
435*150812a8SEvalZero
nrf_twim_shorts_disable(NRF_TWIM_Type * p_reg,uint32_t shorts_mask)436*150812a8SEvalZero __STATIC_INLINE void nrf_twim_shorts_disable(NRF_TWIM_Type * p_reg,
437*150812a8SEvalZero uint32_t shorts_mask)
438*150812a8SEvalZero {
439*150812a8SEvalZero p_reg->SHORTS &= ~(shorts_mask);
440*150812a8SEvalZero }
441*150812a8SEvalZero
nrf_twim_int_enable(NRF_TWIM_Type * p_reg,uint32_t int_mask)442*150812a8SEvalZero __STATIC_INLINE void nrf_twim_int_enable(NRF_TWIM_Type * p_reg,
443*150812a8SEvalZero uint32_t int_mask)
444*150812a8SEvalZero {
445*150812a8SEvalZero p_reg->INTENSET = int_mask;
446*150812a8SEvalZero }
447*150812a8SEvalZero
nrf_twim_int_disable(NRF_TWIM_Type * p_reg,uint32_t int_mask)448*150812a8SEvalZero __STATIC_INLINE void nrf_twim_int_disable(NRF_TWIM_Type * p_reg,
449*150812a8SEvalZero uint32_t int_mask)
450*150812a8SEvalZero {
451*150812a8SEvalZero p_reg->INTENCLR = int_mask;
452*150812a8SEvalZero }
453*150812a8SEvalZero
nrf_twim_int_enable_check(NRF_TWIM_Type * p_reg,nrf_twim_int_mask_t int_mask)454*150812a8SEvalZero __STATIC_INLINE bool nrf_twim_int_enable_check(NRF_TWIM_Type * p_reg,
455*150812a8SEvalZero nrf_twim_int_mask_t int_mask)
456*150812a8SEvalZero {
457*150812a8SEvalZero return (bool)(p_reg->INTENSET & int_mask);
458*150812a8SEvalZero }
459*150812a8SEvalZero
460*150812a8SEvalZero #if defined(DPPI_PRESENT)
nrf_twim_subscribe_set(NRF_TWIM_Type * p_reg,nrf_twim_task_t task,uint8_t channel)461*150812a8SEvalZero __STATIC_INLINE void nrf_twim_subscribe_set(NRF_TWIM_Type * p_reg,
462*150812a8SEvalZero nrf_twim_task_t task,
463*150812a8SEvalZero uint8_t channel)
464*150812a8SEvalZero {
465*150812a8SEvalZero *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
466*150812a8SEvalZero ((uint32_t)channel | TWIM_SUBSCRIBE_STARTRX_EN_Msk);
467*150812a8SEvalZero }
468*150812a8SEvalZero
nrf_twim_subscribe_clear(NRF_TWIM_Type * p_reg,nrf_twim_task_t task)469*150812a8SEvalZero __STATIC_INLINE void nrf_twim_subscribe_clear(NRF_TWIM_Type * p_reg,
470*150812a8SEvalZero nrf_twim_task_t task)
471*150812a8SEvalZero {
472*150812a8SEvalZero *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
473*150812a8SEvalZero }
474*150812a8SEvalZero
nrf_twim_publish_set(NRF_TWIM_Type * p_reg,nrf_twim_event_t event,uint8_t channel)475*150812a8SEvalZero __STATIC_INLINE void nrf_twim_publish_set(NRF_TWIM_Type * p_reg,
476*150812a8SEvalZero nrf_twim_event_t event,
477*150812a8SEvalZero uint8_t channel)
478*150812a8SEvalZero {
479*150812a8SEvalZero *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
480*150812a8SEvalZero ((uint32_t)channel | TWIM_PUBLISH_STOPPED_EN_Msk);
481*150812a8SEvalZero }
482*150812a8SEvalZero
nrf_twim_publish_clear(NRF_TWIM_Type * p_reg,nrf_twim_event_t event)483*150812a8SEvalZero __STATIC_INLINE void nrf_twim_publish_clear(NRF_TWIM_Type * p_reg,
484*150812a8SEvalZero nrf_twim_event_t event)
485*150812a8SEvalZero {
486*150812a8SEvalZero *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0;
487*150812a8SEvalZero }
488*150812a8SEvalZero #endif // defined(DPPI_PRESENT)
489*150812a8SEvalZero
nrf_twim_enable(NRF_TWIM_Type * p_reg)490*150812a8SEvalZero __STATIC_INLINE void nrf_twim_enable(NRF_TWIM_Type * p_reg)
491*150812a8SEvalZero {
492*150812a8SEvalZero p_reg->ENABLE = (TWIM_ENABLE_ENABLE_Enabled << TWIM_ENABLE_ENABLE_Pos);
493*150812a8SEvalZero }
494*150812a8SEvalZero
nrf_twim_disable(NRF_TWIM_Type * p_reg)495*150812a8SEvalZero __STATIC_INLINE void nrf_twim_disable(NRF_TWIM_Type * p_reg)
496*150812a8SEvalZero {
497*150812a8SEvalZero p_reg->ENABLE = (TWIM_ENABLE_ENABLE_Disabled << TWIM_ENABLE_ENABLE_Pos);
498*150812a8SEvalZero }
499*150812a8SEvalZero
nrf_twim_pins_set(NRF_TWIM_Type * p_reg,uint32_t scl_pin,uint32_t sda_pin)500*150812a8SEvalZero __STATIC_INLINE void nrf_twim_pins_set(NRF_TWIM_Type * p_reg,
501*150812a8SEvalZero uint32_t scl_pin,
502*150812a8SEvalZero uint32_t sda_pin)
503*150812a8SEvalZero {
504*150812a8SEvalZero p_reg->PSEL.SCL = scl_pin;
505*150812a8SEvalZero p_reg->PSEL.SDA = sda_pin;
506*150812a8SEvalZero }
507*150812a8SEvalZero
nrf_twim_frequency_set(NRF_TWIM_Type * p_reg,nrf_twim_frequency_t frequency)508*150812a8SEvalZero __STATIC_INLINE void nrf_twim_frequency_set(NRF_TWIM_Type * p_reg,
509*150812a8SEvalZero nrf_twim_frequency_t frequency)
510*150812a8SEvalZero {
511*150812a8SEvalZero p_reg->FREQUENCY = frequency;
512*150812a8SEvalZero }
513*150812a8SEvalZero
nrf_twim_errorsrc_get_and_clear(NRF_TWIM_Type * p_reg)514*150812a8SEvalZero __STATIC_INLINE uint32_t nrf_twim_errorsrc_get_and_clear(NRF_TWIM_Type * p_reg)
515*150812a8SEvalZero {
516*150812a8SEvalZero uint32_t error_source = p_reg->ERRORSRC;
517*150812a8SEvalZero
518*150812a8SEvalZero // [error flags are cleared by writing '1' on their position]
519*150812a8SEvalZero p_reg->ERRORSRC = error_source;
520*150812a8SEvalZero
521*150812a8SEvalZero return error_source;
522*150812a8SEvalZero }
523*150812a8SEvalZero
nrf_twim_address_set(NRF_TWIM_Type * p_reg,uint8_t address)524*150812a8SEvalZero __STATIC_INLINE void nrf_twim_address_set(NRF_TWIM_Type * p_reg,
525*150812a8SEvalZero uint8_t address)
526*150812a8SEvalZero {
527*150812a8SEvalZero p_reg->ADDRESS = address;
528*150812a8SEvalZero }
529*150812a8SEvalZero
nrf_twim_tx_buffer_set(NRF_TWIM_Type * p_reg,uint8_t const * p_buffer,size_t length)530*150812a8SEvalZero __STATIC_INLINE void nrf_twim_tx_buffer_set(NRF_TWIM_Type * p_reg,
531*150812a8SEvalZero uint8_t const * p_buffer,
532*150812a8SEvalZero size_t length)
533*150812a8SEvalZero {
534*150812a8SEvalZero p_reg->TXD.PTR = (uint32_t)p_buffer;
535*150812a8SEvalZero p_reg->TXD.MAXCNT = length;
536*150812a8SEvalZero }
537*150812a8SEvalZero
nrf_twim_rx_buffer_set(NRF_TWIM_Type * p_reg,uint8_t * p_buffer,size_t length)538*150812a8SEvalZero __STATIC_INLINE void nrf_twim_rx_buffer_set(NRF_TWIM_Type * p_reg,
539*150812a8SEvalZero uint8_t * p_buffer,
540*150812a8SEvalZero size_t length)
541*150812a8SEvalZero {
542*150812a8SEvalZero p_reg->RXD.PTR = (uint32_t)p_buffer;
543*150812a8SEvalZero p_reg->RXD.MAXCNT = length;
544*150812a8SEvalZero }
545*150812a8SEvalZero
nrf_twim_shorts_set(NRF_TWIM_Type * p_reg,uint32_t shorts_mask)546*150812a8SEvalZero __STATIC_INLINE void nrf_twim_shorts_set(NRF_TWIM_Type * p_reg,
547*150812a8SEvalZero uint32_t shorts_mask)
548*150812a8SEvalZero {
549*150812a8SEvalZero p_reg->SHORTS = shorts_mask;
550*150812a8SEvalZero }
551*150812a8SEvalZero
nrf_twim_txd_amount_get(NRF_TWIM_Type * p_reg)552*150812a8SEvalZero __STATIC_INLINE size_t nrf_twim_txd_amount_get(NRF_TWIM_Type * p_reg)
553*150812a8SEvalZero {
554*150812a8SEvalZero return p_reg->TXD.AMOUNT;
555*150812a8SEvalZero }
556*150812a8SEvalZero
nrf_twim_rxd_amount_get(NRF_TWIM_Type * p_reg)557*150812a8SEvalZero __STATIC_INLINE size_t nrf_twim_rxd_amount_get(NRF_TWIM_Type * p_reg)
558*150812a8SEvalZero {
559*150812a8SEvalZero return p_reg->RXD.AMOUNT;
560*150812a8SEvalZero }
561*150812a8SEvalZero
nrf_twim_tx_list_enable(NRF_TWIM_Type * p_reg)562*150812a8SEvalZero __STATIC_INLINE void nrf_twim_tx_list_enable(NRF_TWIM_Type * p_reg)
563*150812a8SEvalZero {
564*150812a8SEvalZero p_reg->TXD.LIST = 1;
565*150812a8SEvalZero }
566*150812a8SEvalZero
nrf_twim_tx_list_disable(NRF_TWIM_Type * p_reg)567*150812a8SEvalZero __STATIC_INLINE void nrf_twim_tx_list_disable(NRF_TWIM_Type * p_reg)
568*150812a8SEvalZero {
569*150812a8SEvalZero p_reg->TXD.LIST = 0;
570*150812a8SEvalZero }
571*150812a8SEvalZero
nrf_twim_rx_list_enable(NRF_TWIM_Type * p_reg)572*150812a8SEvalZero __STATIC_INLINE void nrf_twim_rx_list_enable(NRF_TWIM_Type * p_reg)
573*150812a8SEvalZero {
574*150812a8SEvalZero p_reg->RXD.LIST = 1;
575*150812a8SEvalZero }
576*150812a8SEvalZero
nrf_twim_rx_list_disable(NRF_TWIM_Type * p_reg)577*150812a8SEvalZero __STATIC_INLINE void nrf_twim_rx_list_disable(NRF_TWIM_Type * p_reg)
578*150812a8SEvalZero {
579*150812a8SEvalZero p_reg->RXD.LIST = 0;
580*150812a8SEvalZero }
581*150812a8SEvalZero #endif // SUPPRESS_INLINE_IMPLEMENTATION
582*150812a8SEvalZero
583*150812a8SEvalZero /** @} */
584*150812a8SEvalZero
585*150812a8SEvalZero #ifdef __cplusplus
586*150812a8SEvalZero }
587*150812a8SEvalZero #endif
588*150812a8SEvalZero
589*150812a8SEvalZero #endif // NRF_TWIM_H__
590