xref: /nrf52832-nimble/nordic/nrfx/hal/nrf_twi.h (revision 150812a83cab50279bd772ef6db1bfaf255f2c5b)
1*150812a8SEvalZero /*
2*150812a8SEvalZero  * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
3*150812a8SEvalZero  * All rights reserved.
4*150812a8SEvalZero  *
5*150812a8SEvalZero  * Redistribution and use in source and binary forms, with or without
6*150812a8SEvalZero  * modification, are permitted provided that the following conditions are met:
7*150812a8SEvalZero  *
8*150812a8SEvalZero  * 1. Redistributions of source code must retain the above copyright notice, this
9*150812a8SEvalZero  *    list of conditions and the following disclaimer.
10*150812a8SEvalZero  *
11*150812a8SEvalZero  * 2. Redistributions in binary form must reproduce the above copyright
12*150812a8SEvalZero  *    notice, this list of conditions and the following disclaimer in the
13*150812a8SEvalZero  *    documentation and/or other materials provided with the distribution.
14*150812a8SEvalZero  *
15*150812a8SEvalZero  * 3. Neither the name of the copyright holder nor the names of its
16*150812a8SEvalZero  *    contributors may be used to endorse or promote products derived from this
17*150812a8SEvalZero  *    software without specific prior written permission.
18*150812a8SEvalZero  *
19*150812a8SEvalZero  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20*150812a8SEvalZero  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21*150812a8SEvalZero  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22*150812a8SEvalZero  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23*150812a8SEvalZero  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24*150812a8SEvalZero  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25*150812a8SEvalZero  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26*150812a8SEvalZero  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27*150812a8SEvalZero  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28*150812a8SEvalZero  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29*150812a8SEvalZero  * POSSIBILITY OF SUCH DAMAGE.
30*150812a8SEvalZero  */
31*150812a8SEvalZero 
32*150812a8SEvalZero #ifndef NRF_TWI_H__
33*150812a8SEvalZero #define NRF_TWI_H__
34*150812a8SEvalZero 
35*150812a8SEvalZero #include <nrfx.h>
36*150812a8SEvalZero 
37*150812a8SEvalZero #ifdef __cplusplus
38*150812a8SEvalZero extern "C" {
39*150812a8SEvalZero #endif
40*150812a8SEvalZero 
41*150812a8SEvalZero /**
42*150812a8SEvalZero  * @defgroup nrf_twi_hal TWI HAL
43*150812a8SEvalZero  * @{
44*150812a8SEvalZero  * @ingroup nrf_twi
45*150812a8SEvalZero  * @brief   Hardware access layer for managing the TWI peripheral.
46*150812a8SEvalZero  */
47*150812a8SEvalZero 
48*150812a8SEvalZero /**
49*150812a8SEvalZero  * @brief TWI tasks.
50*150812a8SEvalZero  */
51*150812a8SEvalZero typedef enum
52*150812a8SEvalZero {
53*150812a8SEvalZero     /*lint -save -e30*/
54*150812a8SEvalZero     NRF_TWI_TASK_STARTRX = offsetof(NRF_TWI_Type, TASKS_STARTRX), ///< Start TWI receive sequence.
55*150812a8SEvalZero     NRF_TWI_TASK_STARTTX = offsetof(NRF_TWI_Type, TASKS_STARTTX), ///< Start TWI transmit sequence.
56*150812a8SEvalZero     NRF_TWI_TASK_STOP    = offsetof(NRF_TWI_Type, TASKS_STOP),    ///< Stop TWI transaction.
57*150812a8SEvalZero     NRF_TWI_TASK_SUSPEND = offsetof(NRF_TWI_Type, TASKS_SUSPEND), ///< Suspend TWI transaction.
58*150812a8SEvalZero     NRF_TWI_TASK_RESUME  = offsetof(NRF_TWI_Type, TASKS_RESUME)   ///< Resume TWI transaction.
59*150812a8SEvalZero     /*lint -restore*/
60*150812a8SEvalZero } nrf_twi_task_t;
61*150812a8SEvalZero 
62*150812a8SEvalZero /**
63*150812a8SEvalZero  * @brief TWI events.
64*150812a8SEvalZero  */
65*150812a8SEvalZero typedef enum
66*150812a8SEvalZero {
67*150812a8SEvalZero     /*lint -save -e30*/
68*150812a8SEvalZero     NRF_TWI_EVENT_STOPPED   = offsetof(NRF_TWI_Type, EVENTS_STOPPED),  ///< TWI stopped.
69*150812a8SEvalZero     NRF_TWI_EVENT_RXDREADY  = offsetof(NRF_TWI_Type, EVENTS_RXDREADY), ///< TWI RXD byte received.
70*150812a8SEvalZero     NRF_TWI_EVENT_TXDSENT   = offsetof(NRF_TWI_Type, EVENTS_TXDSENT),  ///< TWI TXD byte sent.
71*150812a8SEvalZero     NRF_TWI_EVENT_ERROR     = offsetof(NRF_TWI_Type, EVENTS_ERROR),    ///< TWI error.
72*150812a8SEvalZero     NRF_TWI_EVENT_BB        = offsetof(NRF_TWI_Type, EVENTS_BB),       ///< TWI byte boundary, generated before each byte that is sent or received.
73*150812a8SEvalZero     NRF_TWI_EVENT_SUSPENDED = offsetof(NRF_TWI_Type, EVENTS_SUSPENDED) ///< TWI entered the suspended state.
74*150812a8SEvalZero     /*lint -restore*/
75*150812a8SEvalZero } nrf_twi_event_t;
76*150812a8SEvalZero 
77*150812a8SEvalZero /**
78*150812a8SEvalZero  * @brief TWI shortcuts.
79*150812a8SEvalZero  */
80*150812a8SEvalZero typedef enum
81*150812a8SEvalZero {
82*150812a8SEvalZero     NRF_TWI_SHORT_BB_SUSPEND_MASK = TWI_SHORTS_BB_SUSPEND_Msk,  ///< Shortcut between BB event and SUSPEND task.
83*150812a8SEvalZero     NRF_TWI_SHORT_BB_STOP_MASK    = TWI_SHORTS_BB_STOP_Msk,     ///< Shortcut between BB event and STOP task.
84*150812a8SEvalZero     NRF_TWI_ALL_SHORTS_MASK       = TWI_SHORTS_BB_SUSPEND_Msk |
85*150812a8SEvalZero                                     TWI_SHORTS_BB_STOP_Msk      ///< All TWI shortcuts.
86*150812a8SEvalZero } nrf_twi_short_mask_t;
87*150812a8SEvalZero 
88*150812a8SEvalZero /**
89*150812a8SEvalZero  * @brief TWI interrupts.
90*150812a8SEvalZero  */
91*150812a8SEvalZero typedef enum
92*150812a8SEvalZero {
93*150812a8SEvalZero     NRF_TWI_INT_STOPPED_MASK    = TWI_INTENSET_STOPPED_Msk,    ///< Interrupt on STOPPED event.
94*150812a8SEvalZero     NRF_TWI_INT_RXDREADY_MASK   = TWI_INTENSET_RXDREADY_Msk,   ///< Interrupt on RXDREADY event.
95*150812a8SEvalZero     NRF_TWI_INT_TXDSENT_MASK    = TWI_INTENSET_TXDSENT_Msk,    ///< Interrupt on TXDSENT event.
96*150812a8SEvalZero     NRF_TWI_INT_ERROR_MASK      = TWI_INTENSET_ERROR_Msk,      ///< Interrupt on ERROR event.
97*150812a8SEvalZero     NRF_TWI_INT_BB_MASK         = TWI_INTENSET_BB_Msk,         ///< Interrupt on BB event.
98*150812a8SEvalZero     NRF_TWI_INT_SUSPENDED_MASK  = TWI_INTENSET_SUSPENDED_Msk,  ///< Interrupt on SUSPENDED event.
99*150812a8SEvalZero     NRF_TWI_ALL_INTS_MASK       = TWI_INTENSET_STOPPED_Msk   |
100*150812a8SEvalZero                                   TWI_INTENSET_RXDREADY_Msk  |
101*150812a8SEvalZero                                   TWI_INTENSET_TXDSENT_Msk   |
102*150812a8SEvalZero                                   TWI_INTENSET_ERROR_Msk     |
103*150812a8SEvalZero                                   TWI_INTENSET_BB_Msk        |
104*150812a8SEvalZero                                   TWI_INTENSET_SUSPENDED_Msk   ///< All TWI interrupts.
105*150812a8SEvalZero } nrf_twi_int_mask_t;
106*150812a8SEvalZero 
107*150812a8SEvalZero /**
108*150812a8SEvalZero  * @brief TWI error source.
109*150812a8SEvalZero  */
110*150812a8SEvalZero typedef enum
111*150812a8SEvalZero {
112*150812a8SEvalZero     NRF_TWI_ERROR_ADDRESS_NACK = TWI_ERRORSRC_ANACK_Msk,  ///< NACK received after sending the address.
113*150812a8SEvalZero     NRF_TWI_ERROR_DATA_NACK    = TWI_ERRORSRC_DNACK_Msk,  ///< NACK received after sending a data byte.
114*150812a8SEvalZero     NRF_TWI_ERROR_OVERRUN      = TWI_ERRORSRC_OVERRUN_Msk ///< Overrun error.
115*150812a8SEvalZero                                                           /**< A new byte was received before the previous byte was read
116*150812a8SEvalZero                                                            *   from the RXD register (previous data is lost). */
117*150812a8SEvalZero } nrf_twi_error_t;
118*150812a8SEvalZero 
119*150812a8SEvalZero /**
120*150812a8SEvalZero  * @brief TWI master clock frequency.
121*150812a8SEvalZero  */
122*150812a8SEvalZero typedef enum
123*150812a8SEvalZero {
124*150812a8SEvalZero     NRF_TWI_FREQ_100K = TWI_FREQUENCY_FREQUENCY_K100, ///< 100 kbps.
125*150812a8SEvalZero     NRF_TWI_FREQ_250K = TWI_FREQUENCY_FREQUENCY_K250, ///< 250 kbps.
126*150812a8SEvalZero     NRF_TWI_FREQ_400K = TWI_FREQUENCY_FREQUENCY_K400  ///< 400 kbps.
127*150812a8SEvalZero } nrf_twi_frequency_t;
128*150812a8SEvalZero 
129*150812a8SEvalZero 
130*150812a8SEvalZero /**
131*150812a8SEvalZero  * @brief Function for activating a specific TWI task.
132*150812a8SEvalZero  *
133*150812a8SEvalZero  * @param[in] p_reg Pointer to the peripheral registers structure.
134*150812a8SEvalZero  * @param[in] task  Task to activate.
135*150812a8SEvalZero  */
136*150812a8SEvalZero __STATIC_INLINE void nrf_twi_task_trigger(NRF_TWI_Type * p_reg,
137*150812a8SEvalZero                                           nrf_twi_task_t task);
138*150812a8SEvalZero 
139*150812a8SEvalZero /**
140*150812a8SEvalZero  * @brief Function for getting the address of a specific TWI task register.
141*150812a8SEvalZero  *
142*150812a8SEvalZero  * @param[in] p_reg Pointer to the peripheral registers structure.
143*150812a8SEvalZero  * @param[in] task  Requested task.
144*150812a8SEvalZero  *
145*150812a8SEvalZero  * @return Address of the specified task register.
146*150812a8SEvalZero  */
147*150812a8SEvalZero __STATIC_INLINE uint32_t * nrf_twi_task_address_get(NRF_TWI_Type * p_reg,
148*150812a8SEvalZero                                                     nrf_twi_task_t task);
149*150812a8SEvalZero 
150*150812a8SEvalZero /**
151*150812a8SEvalZero  * @brief Function for clearing a specific TWI event.
152*150812a8SEvalZero  *
153*150812a8SEvalZero  * @param[in] p_reg Pointer to the peripheral registers structure.
154*150812a8SEvalZero  * @param[in] event Event to clear.
155*150812a8SEvalZero  */
156*150812a8SEvalZero __STATIC_INLINE void nrf_twi_event_clear(NRF_TWI_Type * p_reg,
157*150812a8SEvalZero                                          nrf_twi_event_t event);
158*150812a8SEvalZero 
159*150812a8SEvalZero /**
160*150812a8SEvalZero  * @brief Function for checking the state of a specific event.
161*150812a8SEvalZero  *
162*150812a8SEvalZero  * @param[in] p_reg Pointer to the peripheral registers structure.
163*150812a8SEvalZero  * @param[in] event Event to check.
164*150812a8SEvalZero  *
165*150812a8SEvalZero  * @retval true If the event is set.
166*150812a8SEvalZero  * @retval false If the event is not set.
167*150812a8SEvalZero  */
168*150812a8SEvalZero __STATIC_INLINE bool nrf_twi_event_check(NRF_TWI_Type  * p_reg,
169*150812a8SEvalZero                                          nrf_twi_event_t event);
170*150812a8SEvalZero 
171*150812a8SEvalZero /**
172*150812a8SEvalZero  * @brief Function for getting the address of a specific TWI event register.
173*150812a8SEvalZero  *
174*150812a8SEvalZero  * @param[in] p_reg Pointer to the peripheral registers structure.
175*150812a8SEvalZero  * @param[in] event Requested event.
176*150812a8SEvalZero  *
177*150812a8SEvalZero  * @return Address of the specified event register.
178*150812a8SEvalZero  */
179*150812a8SEvalZero __STATIC_INLINE uint32_t * nrf_twi_event_address_get(NRF_TWI_Type  * p_reg,
180*150812a8SEvalZero                                                      nrf_twi_event_t event);
181*150812a8SEvalZero 
182*150812a8SEvalZero /**
183*150812a8SEvalZero  * @brief Function for enabling specified shortcuts.
184*150812a8SEvalZero  *
185*150812a8SEvalZero  * @param[in] p_reg       Pointer to the peripheral registers structure.
186*150812a8SEvalZero  * @param[in] shorts_mask Shortcuts to enable.
187*150812a8SEvalZero  */
188*150812a8SEvalZero __STATIC_INLINE void nrf_twi_shorts_enable(NRF_TWI_Type * p_reg,
189*150812a8SEvalZero                                            uint32_t shorts_mask);
190*150812a8SEvalZero 
191*150812a8SEvalZero /**
192*150812a8SEvalZero  * @brief Function for disabling specified shortcuts.
193*150812a8SEvalZero  *
194*150812a8SEvalZero  * @param[in] p_reg       Pointer to the peripheral registers structure.
195*150812a8SEvalZero  * @param[in] shorts_mask Shortcuts to disable.
196*150812a8SEvalZero  */
197*150812a8SEvalZero __STATIC_INLINE void nrf_twi_shorts_disable(NRF_TWI_Type * p_reg,
198*150812a8SEvalZero                                             uint32_t shorts_mask);
199*150812a8SEvalZero 
200*150812a8SEvalZero /**
201*150812a8SEvalZero  * @brief Function for enabling specified interrupts.
202*150812a8SEvalZero  *
203*150812a8SEvalZero  * @param[in] p_reg    Pointer to the peripheral registers structure.
204*150812a8SEvalZero  * @param[in] int_mask Interrupts to enable.
205*150812a8SEvalZero  */
206*150812a8SEvalZero __STATIC_INLINE void nrf_twi_int_enable(NRF_TWI_Type * p_reg,
207*150812a8SEvalZero                                         uint32_t int_mask);
208*150812a8SEvalZero 
209*150812a8SEvalZero /**
210*150812a8SEvalZero  * @brief Function for disabling specified interrupts.
211*150812a8SEvalZero  *
212*150812a8SEvalZero  * @param[in] p_reg    Pointer to the peripheral registers structure.
213*150812a8SEvalZero  * @param[in] int_mask Interrupts to disable.
214*150812a8SEvalZero  */
215*150812a8SEvalZero __STATIC_INLINE void nrf_twi_int_disable(NRF_TWI_Type * p_reg,
216*150812a8SEvalZero                                          uint32_t int_mask);
217*150812a8SEvalZero 
218*150812a8SEvalZero /**
219*150812a8SEvalZero  * @brief Function for retrieving the state of a given interrupt.
220*150812a8SEvalZero  *
221*150812a8SEvalZero  * @param[in] p_reg    Pointer to the peripheral registers structure.
222*150812a8SEvalZero  * @param[in] int_mask Interrupt to check.
223*150812a8SEvalZero  *
224*150812a8SEvalZero  * @retval true  If the interrupt is enabled.
225*150812a8SEvalZero  * @retval false If the interrupt is not enabled.
226*150812a8SEvalZero  */
227*150812a8SEvalZero __STATIC_INLINE bool nrf_twi_int_enable_check(NRF_TWI_Type * p_reg,
228*150812a8SEvalZero                                               nrf_twi_int_mask_t int_mask);
229*150812a8SEvalZero 
230*150812a8SEvalZero /**
231*150812a8SEvalZero  * @brief Function for enabling the TWI peripheral.
232*150812a8SEvalZero  *
233*150812a8SEvalZero  * @param[in] p_reg Pointer to the peripheral registers structure.
234*150812a8SEvalZero  */
235*150812a8SEvalZero __STATIC_INLINE void nrf_twi_enable(NRF_TWI_Type * p_reg);
236*150812a8SEvalZero 
237*150812a8SEvalZero /**
238*150812a8SEvalZero  * @brief Function for disabling the TWI peripheral.
239*150812a8SEvalZero  *
240*150812a8SEvalZero  * @param[in] p_reg Pointer to the peripheral registers structure.
241*150812a8SEvalZero  */
242*150812a8SEvalZero __STATIC_INLINE void nrf_twi_disable(NRF_TWI_Type * p_reg);
243*150812a8SEvalZero 
244*150812a8SEvalZero /**
245*150812a8SEvalZero  * @brief Function for configuring TWI pins.
246*150812a8SEvalZero  *
247*150812a8SEvalZero  *
248*150812a8SEvalZero  * @param[in] p_reg   Pointer to the peripheral registers structure.
249*150812a8SEvalZero  * @param[in] scl_pin SCL pin number.
250*150812a8SEvalZero  * @param[in] sda_pin SDA pin number.
251*150812a8SEvalZero  */
252*150812a8SEvalZero __STATIC_INLINE void nrf_twi_pins_set(NRF_TWI_Type * p_reg,
253*150812a8SEvalZero                                       uint32_t scl_pin,
254*150812a8SEvalZero                                       uint32_t sda_pin);
255*150812a8SEvalZero 
256*150812a8SEvalZero /**
257*150812a8SEvalZero  * @brief Function for setting the TWI master clock frequency.
258*150812a8SEvalZero  *
259*150812a8SEvalZero  * @param[in] p_reg     Pointer to the peripheral registers structure.
260*150812a8SEvalZero  * @param[in] frequency TWI frequency.
261*150812a8SEvalZero  */
262*150812a8SEvalZero __STATIC_INLINE void nrf_twi_frequency_set(NRF_TWI_Type * p_reg,
263*150812a8SEvalZero                                            nrf_twi_frequency_t frequency);
264*150812a8SEvalZero 
265*150812a8SEvalZero /**
266*150812a8SEvalZero  * @brief Function for checking the TWI error source.
267*150812a8SEvalZero  *
268*150812a8SEvalZero  * The error flags are cleared after reading.
269*150812a8SEvalZero  *
270*150812a8SEvalZero  * @param[in] p_reg Pointer to the peripheral registers structure.
271*150812a8SEvalZero  *
272*150812a8SEvalZero  * @return Mask with error source flags.
273*150812a8SEvalZero  */
274*150812a8SEvalZero __STATIC_INLINE uint32_t nrf_twi_errorsrc_get_and_clear(NRF_TWI_Type * p_reg);
275*150812a8SEvalZero 
276*150812a8SEvalZero /**
277*150812a8SEvalZero  * @brief Function for setting the address to be used in TWI transfers.
278*150812a8SEvalZero  *
279*150812a8SEvalZero  * @param[in] p_reg   Pointer to the peripheral registers structure.
280*150812a8SEvalZero  * @param[in] address Address to be used in transfers.
281*150812a8SEvalZero  */
282*150812a8SEvalZero __STATIC_INLINE void nrf_twi_address_set(NRF_TWI_Type * p_reg, uint8_t address);
283*150812a8SEvalZero 
284*150812a8SEvalZero /**
285*150812a8SEvalZero  * @brief Function for reading data received by TWI.
286*150812a8SEvalZero  *
287*150812a8SEvalZero  * @param[in] p_reg Pointer to the peripheral registers structure.
288*150812a8SEvalZero  *
289*150812a8SEvalZero  * @return Received data.
290*150812a8SEvalZero  */
291*150812a8SEvalZero __STATIC_INLINE uint8_t nrf_twi_rxd_get(NRF_TWI_Type * p_reg);
292*150812a8SEvalZero 
293*150812a8SEvalZero /**
294*150812a8SEvalZero  * @brief Function for writing data to be transmitted by TWI.
295*150812a8SEvalZero  *
296*150812a8SEvalZero  * @param[in] p_reg Pointer to the peripheral registers structure.
297*150812a8SEvalZero  * @param[in] data  Data to be transmitted.
298*150812a8SEvalZero  */
299*150812a8SEvalZero __STATIC_INLINE void nrf_twi_txd_set(NRF_TWI_Type * p_reg, uint8_t data);
300*150812a8SEvalZero 
301*150812a8SEvalZero __STATIC_INLINE void nrf_twi_shorts_set(NRF_TWI_Type * p_reg,
302*150812a8SEvalZero                                         uint32_t shorts_mask);
303*150812a8SEvalZero 
304*150812a8SEvalZero #ifndef SUPPRESS_INLINE_IMPLEMENTATION
305*150812a8SEvalZero 
nrf_twi_task_trigger(NRF_TWI_Type * p_reg,nrf_twi_task_t task)306*150812a8SEvalZero __STATIC_INLINE void nrf_twi_task_trigger(NRF_TWI_Type * p_reg,
307*150812a8SEvalZero                                           nrf_twi_task_t task)
308*150812a8SEvalZero {
309*150812a8SEvalZero     *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
310*150812a8SEvalZero }
311*150812a8SEvalZero 
nrf_twi_task_address_get(NRF_TWI_Type * p_reg,nrf_twi_task_t task)312*150812a8SEvalZero __STATIC_INLINE uint32_t * nrf_twi_task_address_get(NRF_TWI_Type * p_reg,
313*150812a8SEvalZero                                                     nrf_twi_task_t task)
314*150812a8SEvalZero {
315*150812a8SEvalZero     return (uint32_t *)((uint8_t *)p_reg + (uint32_t)task);
316*150812a8SEvalZero }
317*150812a8SEvalZero 
nrf_twi_event_clear(NRF_TWI_Type * p_reg,nrf_twi_event_t event)318*150812a8SEvalZero __STATIC_INLINE void nrf_twi_event_clear(NRF_TWI_Type  * p_reg,
319*150812a8SEvalZero                                          nrf_twi_event_t event)
320*150812a8SEvalZero {
321*150812a8SEvalZero     *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
322*150812a8SEvalZero #if __CORTEX_M == 0x04
323*150812a8SEvalZero     volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
324*150812a8SEvalZero     (void)dummy;
325*150812a8SEvalZero #endif
326*150812a8SEvalZero }
327*150812a8SEvalZero 
nrf_twi_event_check(NRF_TWI_Type * p_reg,nrf_twi_event_t event)328*150812a8SEvalZero __STATIC_INLINE bool nrf_twi_event_check(NRF_TWI_Type  * p_reg,
329*150812a8SEvalZero                                          nrf_twi_event_t event)
330*150812a8SEvalZero {
331*150812a8SEvalZero     return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
332*150812a8SEvalZero }
333*150812a8SEvalZero 
nrf_twi_event_address_get(NRF_TWI_Type * p_reg,nrf_twi_event_t event)334*150812a8SEvalZero __STATIC_INLINE uint32_t * nrf_twi_event_address_get(NRF_TWI_Type  * p_reg,
335*150812a8SEvalZero                                                      nrf_twi_event_t event)
336*150812a8SEvalZero {
337*150812a8SEvalZero     return (uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
338*150812a8SEvalZero }
339*150812a8SEvalZero 
nrf_twi_shorts_enable(NRF_TWI_Type * p_reg,uint32_t shorts_mask)340*150812a8SEvalZero __STATIC_INLINE void nrf_twi_shorts_enable(NRF_TWI_Type * p_reg,
341*150812a8SEvalZero                                            uint32_t shorts_mask)
342*150812a8SEvalZero {
343*150812a8SEvalZero     p_reg->SHORTS |= shorts_mask;
344*150812a8SEvalZero }
345*150812a8SEvalZero 
nrf_twi_shorts_disable(NRF_TWI_Type * p_reg,uint32_t shorts_mask)346*150812a8SEvalZero __STATIC_INLINE void nrf_twi_shorts_disable(NRF_TWI_Type * p_reg,
347*150812a8SEvalZero                                             uint32_t shorts_mask)
348*150812a8SEvalZero {
349*150812a8SEvalZero     p_reg->SHORTS &= ~(shorts_mask);
350*150812a8SEvalZero }
351*150812a8SEvalZero 
nrf_twi_int_enable(NRF_TWI_Type * p_reg,uint32_t int_mask)352*150812a8SEvalZero __STATIC_INLINE void nrf_twi_int_enable(NRF_TWI_Type * p_reg,
353*150812a8SEvalZero                                         uint32_t int_mask)
354*150812a8SEvalZero {
355*150812a8SEvalZero     p_reg->INTENSET = int_mask;
356*150812a8SEvalZero }
357*150812a8SEvalZero 
nrf_twi_int_disable(NRF_TWI_Type * p_reg,uint32_t int_mask)358*150812a8SEvalZero __STATIC_INLINE void nrf_twi_int_disable(NRF_TWI_Type * p_reg,
359*150812a8SEvalZero                                          uint32_t int_mask)
360*150812a8SEvalZero {
361*150812a8SEvalZero     p_reg->INTENCLR = int_mask;
362*150812a8SEvalZero }
363*150812a8SEvalZero 
nrf_twi_int_enable_check(NRF_TWI_Type * p_reg,nrf_twi_int_mask_t int_mask)364*150812a8SEvalZero __STATIC_INLINE bool nrf_twi_int_enable_check(NRF_TWI_Type * p_reg,
365*150812a8SEvalZero                                               nrf_twi_int_mask_t int_mask)
366*150812a8SEvalZero {
367*150812a8SEvalZero     return (bool)(p_reg->INTENSET & int_mask);
368*150812a8SEvalZero }
369*150812a8SEvalZero 
nrf_twi_enable(NRF_TWI_Type * p_reg)370*150812a8SEvalZero __STATIC_INLINE void nrf_twi_enable(NRF_TWI_Type * p_reg)
371*150812a8SEvalZero {
372*150812a8SEvalZero     p_reg->ENABLE = (TWI_ENABLE_ENABLE_Enabled << TWI_ENABLE_ENABLE_Pos);
373*150812a8SEvalZero }
374*150812a8SEvalZero 
nrf_twi_disable(NRF_TWI_Type * p_reg)375*150812a8SEvalZero __STATIC_INLINE void nrf_twi_disable(NRF_TWI_Type * p_reg)
376*150812a8SEvalZero {
377*150812a8SEvalZero     p_reg->ENABLE = (TWI_ENABLE_ENABLE_Disabled << TWI_ENABLE_ENABLE_Pos);
378*150812a8SEvalZero }
379*150812a8SEvalZero 
nrf_twi_pins_set(NRF_TWI_Type * p_reg,uint32_t scl_pin,uint32_t sda_pin)380*150812a8SEvalZero __STATIC_INLINE void nrf_twi_pins_set(NRF_TWI_Type * p_reg,
381*150812a8SEvalZero                                       uint32_t scl_pin,
382*150812a8SEvalZero                                       uint32_t sda_pin)
383*150812a8SEvalZero {
384*150812a8SEvalZero #if defined(TWI_PSEL_SCL_CONNECT_Pos)
385*150812a8SEvalZero     p_reg->PSEL.SCL = scl_pin;
386*150812a8SEvalZero #else
387*150812a8SEvalZero     p_reg->PSELSCL = scl_pin;
388*150812a8SEvalZero #endif
389*150812a8SEvalZero 
390*150812a8SEvalZero #if defined(TWI_PSEL_SDA_CONNECT_Pos)
391*150812a8SEvalZero     p_reg->PSEL.SDA = sda_pin;
392*150812a8SEvalZero #else
393*150812a8SEvalZero     p_reg->PSELSDA = sda_pin;
394*150812a8SEvalZero #endif
395*150812a8SEvalZero }
396*150812a8SEvalZero 
nrf_twi_frequency_set(NRF_TWI_Type * p_reg,nrf_twi_frequency_t frequency)397*150812a8SEvalZero __STATIC_INLINE void nrf_twi_frequency_set(NRF_TWI_Type * p_reg,
398*150812a8SEvalZero                                            nrf_twi_frequency_t frequency)
399*150812a8SEvalZero {
400*150812a8SEvalZero     p_reg->FREQUENCY = frequency;
401*150812a8SEvalZero }
402*150812a8SEvalZero 
nrf_twi_errorsrc_get_and_clear(NRF_TWI_Type * p_reg)403*150812a8SEvalZero __STATIC_INLINE uint32_t nrf_twi_errorsrc_get_and_clear(NRF_TWI_Type * p_reg)
404*150812a8SEvalZero {
405*150812a8SEvalZero     uint32_t error_source = p_reg->ERRORSRC;
406*150812a8SEvalZero 
407*150812a8SEvalZero     // [error flags are cleared by writing '1' on their position]
408*150812a8SEvalZero     p_reg->ERRORSRC = error_source;
409*150812a8SEvalZero 
410*150812a8SEvalZero     return error_source;
411*150812a8SEvalZero }
412*150812a8SEvalZero 
nrf_twi_address_set(NRF_TWI_Type * p_reg,uint8_t address)413*150812a8SEvalZero __STATIC_INLINE void nrf_twi_address_set(NRF_TWI_Type * p_reg, uint8_t address)
414*150812a8SEvalZero {
415*150812a8SEvalZero     p_reg->ADDRESS = address;
416*150812a8SEvalZero }
417*150812a8SEvalZero 
nrf_twi_rxd_get(NRF_TWI_Type * p_reg)418*150812a8SEvalZero __STATIC_INLINE uint8_t nrf_twi_rxd_get(NRF_TWI_Type * p_reg)
419*150812a8SEvalZero {
420*150812a8SEvalZero     return (uint8_t)p_reg->RXD;
421*150812a8SEvalZero }
422*150812a8SEvalZero 
nrf_twi_txd_set(NRF_TWI_Type * p_reg,uint8_t data)423*150812a8SEvalZero __STATIC_INLINE void nrf_twi_txd_set(NRF_TWI_Type * p_reg, uint8_t data)
424*150812a8SEvalZero {
425*150812a8SEvalZero     p_reg->TXD = data;
426*150812a8SEvalZero }
427*150812a8SEvalZero 
nrf_twi_shorts_set(NRF_TWI_Type * p_reg,uint32_t shorts_mask)428*150812a8SEvalZero __STATIC_INLINE void nrf_twi_shorts_set(NRF_TWI_Type * p_reg,
429*150812a8SEvalZero                                         uint32_t shorts_mask)
430*150812a8SEvalZero {
431*150812a8SEvalZero     p_reg->SHORTS = shorts_mask;
432*150812a8SEvalZero }
433*150812a8SEvalZero 
434*150812a8SEvalZero #endif // SUPPRESS_INLINE_IMPLEMENTATION
435*150812a8SEvalZero 
436*150812a8SEvalZero /** @} */
437*150812a8SEvalZero 
438*150812a8SEvalZero #ifdef __cplusplus
439*150812a8SEvalZero }
440*150812a8SEvalZero #endif
441*150812a8SEvalZero 
442*150812a8SEvalZero #endif // NRF_TWI_H__
443