1*150812a8SEvalZero /*
2*150812a8SEvalZero * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
3*150812a8SEvalZero * All rights reserved.
4*150812a8SEvalZero *
5*150812a8SEvalZero * Redistribution and use in source and binary forms, with or without
6*150812a8SEvalZero * modification, are permitted provided that the following conditions are met:
7*150812a8SEvalZero *
8*150812a8SEvalZero * 1. Redistributions of source code must retain the above copyright notice, this
9*150812a8SEvalZero * list of conditions and the following disclaimer.
10*150812a8SEvalZero *
11*150812a8SEvalZero * 2. Redistributions in binary form must reproduce the above copyright
12*150812a8SEvalZero * notice, this list of conditions and the following disclaimer in the
13*150812a8SEvalZero * documentation and/or other materials provided with the distribution.
14*150812a8SEvalZero *
15*150812a8SEvalZero * 3. Neither the name of the copyright holder nor the names of its
16*150812a8SEvalZero * contributors may be used to endorse or promote products derived from this
17*150812a8SEvalZero * software without specific prior written permission.
18*150812a8SEvalZero *
19*150812a8SEvalZero * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20*150812a8SEvalZero * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21*150812a8SEvalZero * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22*150812a8SEvalZero * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23*150812a8SEvalZero * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24*150812a8SEvalZero * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25*150812a8SEvalZero * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26*150812a8SEvalZero * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27*150812a8SEvalZero * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28*150812a8SEvalZero * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29*150812a8SEvalZero * POSSIBILITY OF SUCH DAMAGE.
30*150812a8SEvalZero */
31*150812a8SEvalZero
32*150812a8SEvalZero #ifndef NRF_SAADC_H_
33*150812a8SEvalZero #define NRF_SAADC_H_
34*150812a8SEvalZero
35*150812a8SEvalZero #include <nrfx.h>
36*150812a8SEvalZero
37*150812a8SEvalZero #ifdef __cplusplus
38*150812a8SEvalZero extern "C" {
39*150812a8SEvalZero #endif
40*150812a8SEvalZero
41*150812a8SEvalZero /**
42*150812a8SEvalZero * @defgroup nrf_saadc_hal SAADC HAL
43*150812a8SEvalZero * @{
44*150812a8SEvalZero * @ingroup nrf_saadc
45*150812a8SEvalZero * @brief Hardware access layer for managing the SAADC peripheral.
46*150812a8SEvalZero */
47*150812a8SEvalZero
48*150812a8SEvalZero #define NRF_SAADC_CHANNEL_COUNT 8
49*150812a8SEvalZero
50*150812a8SEvalZero /**
51*150812a8SEvalZero * @brief Resolution of the analog-to-digital converter.
52*150812a8SEvalZero */
53*150812a8SEvalZero typedef enum
54*150812a8SEvalZero {
55*150812a8SEvalZero NRF_SAADC_RESOLUTION_8BIT = SAADC_RESOLUTION_VAL_8bit, ///< 8 bit resolution.
56*150812a8SEvalZero NRF_SAADC_RESOLUTION_10BIT = SAADC_RESOLUTION_VAL_10bit, ///< 10 bit resolution.
57*150812a8SEvalZero NRF_SAADC_RESOLUTION_12BIT = SAADC_RESOLUTION_VAL_12bit, ///< 12 bit resolution.
58*150812a8SEvalZero NRF_SAADC_RESOLUTION_14BIT = SAADC_RESOLUTION_VAL_14bit ///< 14 bit resolution.
59*150812a8SEvalZero } nrf_saadc_resolution_t;
60*150812a8SEvalZero
61*150812a8SEvalZero
62*150812a8SEvalZero /**
63*150812a8SEvalZero * @brief Input selection for the analog-to-digital converter.
64*150812a8SEvalZero */
65*150812a8SEvalZero typedef enum
66*150812a8SEvalZero {
67*150812a8SEvalZero NRF_SAADC_INPUT_DISABLED = SAADC_CH_PSELP_PSELP_NC, ///< Not connected.
68*150812a8SEvalZero NRF_SAADC_INPUT_AIN0 = SAADC_CH_PSELP_PSELP_AnalogInput0, ///< Analog input 0 (AIN0).
69*150812a8SEvalZero NRF_SAADC_INPUT_AIN1 = SAADC_CH_PSELP_PSELP_AnalogInput1, ///< Analog input 1 (AIN1).
70*150812a8SEvalZero NRF_SAADC_INPUT_AIN2 = SAADC_CH_PSELP_PSELP_AnalogInput2, ///< Analog input 2 (AIN2).
71*150812a8SEvalZero NRF_SAADC_INPUT_AIN3 = SAADC_CH_PSELP_PSELP_AnalogInput3, ///< Analog input 3 (AIN3).
72*150812a8SEvalZero NRF_SAADC_INPUT_AIN4 = SAADC_CH_PSELP_PSELP_AnalogInput4, ///< Analog input 4 (AIN4).
73*150812a8SEvalZero NRF_SAADC_INPUT_AIN5 = SAADC_CH_PSELP_PSELP_AnalogInput5, ///< Analog input 5 (AIN5).
74*150812a8SEvalZero NRF_SAADC_INPUT_AIN6 = SAADC_CH_PSELP_PSELP_AnalogInput6, ///< Analog input 6 (AIN6).
75*150812a8SEvalZero NRF_SAADC_INPUT_AIN7 = SAADC_CH_PSELP_PSELP_AnalogInput7, ///< Analog input 7 (AIN7).
76*150812a8SEvalZero NRF_SAADC_INPUT_VDD = SAADC_CH_PSELP_PSELP_VDD ///< VDD as input.
77*150812a8SEvalZero } nrf_saadc_input_t;
78*150812a8SEvalZero
79*150812a8SEvalZero
80*150812a8SEvalZero /**
81*150812a8SEvalZero * @brief Analog-to-digital converter oversampling mode.
82*150812a8SEvalZero */
83*150812a8SEvalZero typedef enum
84*150812a8SEvalZero {
85*150812a8SEvalZero NRF_SAADC_OVERSAMPLE_DISABLED = SAADC_OVERSAMPLE_OVERSAMPLE_Bypass, ///< No oversampling.
86*150812a8SEvalZero NRF_SAADC_OVERSAMPLE_2X = SAADC_OVERSAMPLE_OVERSAMPLE_Over2x, ///< Oversample 2x.
87*150812a8SEvalZero NRF_SAADC_OVERSAMPLE_4X = SAADC_OVERSAMPLE_OVERSAMPLE_Over4x, ///< Oversample 4x.
88*150812a8SEvalZero NRF_SAADC_OVERSAMPLE_8X = SAADC_OVERSAMPLE_OVERSAMPLE_Over8x, ///< Oversample 8x.
89*150812a8SEvalZero NRF_SAADC_OVERSAMPLE_16X = SAADC_OVERSAMPLE_OVERSAMPLE_Over16x, ///< Oversample 16x.
90*150812a8SEvalZero NRF_SAADC_OVERSAMPLE_32X = SAADC_OVERSAMPLE_OVERSAMPLE_Over32x, ///< Oversample 32x.
91*150812a8SEvalZero NRF_SAADC_OVERSAMPLE_64X = SAADC_OVERSAMPLE_OVERSAMPLE_Over64x, ///< Oversample 64x.
92*150812a8SEvalZero NRF_SAADC_OVERSAMPLE_128X = SAADC_OVERSAMPLE_OVERSAMPLE_Over128x, ///< Oversample 128x.
93*150812a8SEvalZero NRF_SAADC_OVERSAMPLE_256X = SAADC_OVERSAMPLE_OVERSAMPLE_Over256x ///< Oversample 256x.
94*150812a8SEvalZero } nrf_saadc_oversample_t;
95*150812a8SEvalZero
96*150812a8SEvalZero
97*150812a8SEvalZero /**
98*150812a8SEvalZero * @brief Analog-to-digital converter channel resistor control.
99*150812a8SEvalZero */
100*150812a8SEvalZero typedef enum
101*150812a8SEvalZero {
102*150812a8SEvalZero NRF_SAADC_RESISTOR_DISABLED = SAADC_CH_CONFIG_RESP_Bypass, ///< Bypass resistor ladder.
103*150812a8SEvalZero NRF_SAADC_RESISTOR_PULLDOWN = SAADC_CH_CONFIG_RESP_Pulldown, ///< Pull-down to GND.
104*150812a8SEvalZero NRF_SAADC_RESISTOR_PULLUP = SAADC_CH_CONFIG_RESP_Pullup, ///< Pull-up to VDD.
105*150812a8SEvalZero NRF_SAADC_RESISTOR_VDD1_2 = SAADC_CH_CONFIG_RESP_VDD1_2 ///< Set input at VDD/2.
106*150812a8SEvalZero } nrf_saadc_resistor_t;
107*150812a8SEvalZero
108*150812a8SEvalZero
109*150812a8SEvalZero /**
110*150812a8SEvalZero * @brief Gain factor of the analog-to-digital converter input.
111*150812a8SEvalZero */
112*150812a8SEvalZero typedef enum
113*150812a8SEvalZero {
114*150812a8SEvalZero NRF_SAADC_GAIN1_6 = SAADC_CH_CONFIG_GAIN_Gain1_6, ///< Gain factor 1/6.
115*150812a8SEvalZero NRF_SAADC_GAIN1_5 = SAADC_CH_CONFIG_GAIN_Gain1_5, ///< Gain factor 1/5.
116*150812a8SEvalZero NRF_SAADC_GAIN1_4 = SAADC_CH_CONFIG_GAIN_Gain1_4, ///< Gain factor 1/4.
117*150812a8SEvalZero NRF_SAADC_GAIN1_3 = SAADC_CH_CONFIG_GAIN_Gain1_3, ///< Gain factor 1/3.
118*150812a8SEvalZero NRF_SAADC_GAIN1_2 = SAADC_CH_CONFIG_GAIN_Gain1_2, ///< Gain factor 1/2.
119*150812a8SEvalZero NRF_SAADC_GAIN1 = SAADC_CH_CONFIG_GAIN_Gain1, ///< Gain factor 1.
120*150812a8SEvalZero NRF_SAADC_GAIN2 = SAADC_CH_CONFIG_GAIN_Gain2, ///< Gain factor 2.
121*150812a8SEvalZero NRF_SAADC_GAIN4 = SAADC_CH_CONFIG_GAIN_Gain4, ///< Gain factor 4.
122*150812a8SEvalZero } nrf_saadc_gain_t;
123*150812a8SEvalZero
124*150812a8SEvalZero
125*150812a8SEvalZero /**
126*150812a8SEvalZero * @brief Reference selection for the analog-to-digital converter.
127*150812a8SEvalZero */
128*150812a8SEvalZero typedef enum
129*150812a8SEvalZero {
130*150812a8SEvalZero NRF_SAADC_REFERENCE_INTERNAL = SAADC_CH_CONFIG_REFSEL_Internal, ///< Internal reference (0.6 V).
131*150812a8SEvalZero NRF_SAADC_REFERENCE_VDD4 = SAADC_CH_CONFIG_REFSEL_VDD1_4 ///< VDD/4 as reference.
132*150812a8SEvalZero } nrf_saadc_reference_t;
133*150812a8SEvalZero
134*150812a8SEvalZero
135*150812a8SEvalZero /**
136*150812a8SEvalZero * @brief Analog-to-digital converter acquisition time.
137*150812a8SEvalZero */
138*150812a8SEvalZero typedef enum
139*150812a8SEvalZero {
140*150812a8SEvalZero NRF_SAADC_ACQTIME_3US = SAADC_CH_CONFIG_TACQ_3us, ///< 3 us.
141*150812a8SEvalZero NRF_SAADC_ACQTIME_5US = SAADC_CH_CONFIG_TACQ_5us, ///< 5 us.
142*150812a8SEvalZero NRF_SAADC_ACQTIME_10US = SAADC_CH_CONFIG_TACQ_10us, ///< 10 us.
143*150812a8SEvalZero NRF_SAADC_ACQTIME_15US = SAADC_CH_CONFIG_TACQ_15us, ///< 15 us.
144*150812a8SEvalZero NRF_SAADC_ACQTIME_20US = SAADC_CH_CONFIG_TACQ_20us, ///< 20 us.
145*150812a8SEvalZero NRF_SAADC_ACQTIME_40US = SAADC_CH_CONFIG_TACQ_40us ///< 40 us.
146*150812a8SEvalZero } nrf_saadc_acqtime_t;
147*150812a8SEvalZero
148*150812a8SEvalZero
149*150812a8SEvalZero /**
150*150812a8SEvalZero * @brief Analog-to-digital converter channel mode.
151*150812a8SEvalZero */
152*150812a8SEvalZero typedef enum
153*150812a8SEvalZero {
154*150812a8SEvalZero NRF_SAADC_MODE_SINGLE_ENDED = SAADC_CH_CONFIG_MODE_SE, ///< Single ended, PSELN will be ignored, negative input to ADC shorted to GND.
155*150812a8SEvalZero NRF_SAADC_MODE_DIFFERENTIAL = SAADC_CH_CONFIG_MODE_Diff ///< Differential mode.
156*150812a8SEvalZero } nrf_saadc_mode_t;
157*150812a8SEvalZero
158*150812a8SEvalZero
159*150812a8SEvalZero /**
160*150812a8SEvalZero * @brief Analog-to-digital converter channel burst mode.
161*150812a8SEvalZero */
162*150812a8SEvalZero typedef enum
163*150812a8SEvalZero {
164*150812a8SEvalZero NRF_SAADC_BURST_DISABLED = SAADC_CH_CONFIG_BURST_Disabled, ///< Burst mode is disabled (normal operation).
165*150812a8SEvalZero NRF_SAADC_BURST_ENABLED = SAADC_CH_CONFIG_BURST_Enabled ///< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM.
166*150812a8SEvalZero } nrf_saadc_burst_t;
167*150812a8SEvalZero
168*150812a8SEvalZero
169*150812a8SEvalZero /**
170*150812a8SEvalZero * @brief Analog-to-digital converter tasks.
171*150812a8SEvalZero */
172*150812a8SEvalZero typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
173*150812a8SEvalZero {
174*150812a8SEvalZero NRF_SAADC_TASK_START = offsetof(NRF_SAADC_Type, TASKS_START), ///< Start the ADC and prepare the result buffer in RAM.
175*150812a8SEvalZero NRF_SAADC_TASK_SAMPLE = offsetof(NRF_SAADC_Type, TASKS_SAMPLE), ///< Take one ADC sample. If scan is enabled, all channels are sampled.
176*150812a8SEvalZero NRF_SAADC_TASK_STOP = offsetof(NRF_SAADC_Type, TASKS_STOP), ///< Stop the ADC and terminate any on-going conversion.
177*150812a8SEvalZero NRF_SAADC_TASK_CALIBRATEOFFSET = offsetof(NRF_SAADC_Type, TASKS_CALIBRATEOFFSET), ///< Starts offset auto-calibration.
178*150812a8SEvalZero } nrf_saadc_task_t;
179*150812a8SEvalZero
180*150812a8SEvalZero
181*150812a8SEvalZero /**
182*150812a8SEvalZero * @brief Analog-to-digital converter events.
183*150812a8SEvalZero */
184*150812a8SEvalZero typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
185*150812a8SEvalZero {
186*150812a8SEvalZero NRF_SAADC_EVENT_STARTED = offsetof(NRF_SAADC_Type, EVENTS_STARTED), ///< The ADC has started.
187*150812a8SEvalZero NRF_SAADC_EVENT_END = offsetof(NRF_SAADC_Type, EVENTS_END), ///< The ADC has filled up the result buffer.
188*150812a8SEvalZero NRF_SAADC_EVENT_DONE = offsetof(NRF_SAADC_Type, EVENTS_DONE), ///< A conversion task has been completed.
189*150812a8SEvalZero NRF_SAADC_EVENT_RESULTDONE = offsetof(NRF_SAADC_Type, EVENTS_RESULTDONE), ///< A result is ready to get transferred to RAM.
190*150812a8SEvalZero NRF_SAADC_EVENT_CALIBRATEDONE = offsetof(NRF_SAADC_Type, EVENTS_CALIBRATEDONE), ///< Calibration is complete.
191*150812a8SEvalZero NRF_SAADC_EVENT_STOPPED = offsetof(NRF_SAADC_Type, EVENTS_STOPPED), ///< The ADC has stopped.
192*150812a8SEvalZero NRF_SAADC_EVENT_CH0_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[0].LIMITH), ///< Last result is equal or above CH[0].LIMIT.HIGH.
193*150812a8SEvalZero NRF_SAADC_EVENT_CH0_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[0].LIMITL), ///< Last result is equal or below CH[0].LIMIT.LOW.
194*150812a8SEvalZero NRF_SAADC_EVENT_CH1_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[1].LIMITH), ///< Last result is equal or above CH[1].LIMIT.HIGH.
195*150812a8SEvalZero NRF_SAADC_EVENT_CH1_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[1].LIMITL), ///< Last result is equal or below CH[1].LIMIT.LOW.
196*150812a8SEvalZero NRF_SAADC_EVENT_CH2_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[2].LIMITH), ///< Last result is equal or above CH[2].LIMIT.HIGH.
197*150812a8SEvalZero NRF_SAADC_EVENT_CH2_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[2].LIMITL), ///< Last result is equal or below CH[2].LIMIT.LOW.
198*150812a8SEvalZero NRF_SAADC_EVENT_CH3_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[3].LIMITH), ///< Last result is equal or above CH[3].LIMIT.HIGH.
199*150812a8SEvalZero NRF_SAADC_EVENT_CH3_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[3].LIMITL), ///< Last result is equal or below CH[3].LIMIT.LOW.
200*150812a8SEvalZero NRF_SAADC_EVENT_CH4_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[4].LIMITH), ///< Last result is equal or above CH[4].LIMIT.HIGH.
201*150812a8SEvalZero NRF_SAADC_EVENT_CH4_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[4].LIMITL), ///< Last result is equal or below CH[4].LIMIT.LOW.
202*150812a8SEvalZero NRF_SAADC_EVENT_CH5_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[5].LIMITH), ///< Last result is equal or above CH[5].LIMIT.HIGH.
203*150812a8SEvalZero NRF_SAADC_EVENT_CH5_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[5].LIMITL), ///< Last result is equal or below CH[5].LIMIT.LOW.
204*150812a8SEvalZero NRF_SAADC_EVENT_CH6_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[6].LIMITH), ///< Last result is equal or above CH[6].LIMIT.HIGH.
205*150812a8SEvalZero NRF_SAADC_EVENT_CH6_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[6].LIMITL), ///< Last result is equal or below CH[6].LIMIT.LOW.
206*150812a8SEvalZero NRF_SAADC_EVENT_CH7_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[7].LIMITH), ///< Last result is equal or above CH[7].LIMIT.HIGH.
207*150812a8SEvalZero NRF_SAADC_EVENT_CH7_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[7].LIMITL) ///< Last result is equal or below CH[7].LIMIT.LOW.
208*150812a8SEvalZero } nrf_saadc_event_t;
209*150812a8SEvalZero
210*150812a8SEvalZero
211*150812a8SEvalZero /**
212*150812a8SEvalZero * @brief Analog-to-digital converter interrupt masks.
213*150812a8SEvalZero */
214*150812a8SEvalZero typedef enum
215*150812a8SEvalZero {
216*150812a8SEvalZero NRF_SAADC_INT_STARTED = SAADC_INTENSET_STARTED_Msk, ///< Interrupt on EVENTS_STARTED event.
217*150812a8SEvalZero NRF_SAADC_INT_END = SAADC_INTENSET_END_Msk, ///< Interrupt on EVENTS_END event.
218*150812a8SEvalZero NRF_SAADC_INT_DONE = SAADC_INTENSET_DONE_Msk, ///< Interrupt on EVENTS_DONE event.
219*150812a8SEvalZero NRF_SAADC_INT_RESULTDONE = SAADC_INTENSET_RESULTDONE_Msk, ///< Interrupt on EVENTS_RESULTDONE event.
220*150812a8SEvalZero NRF_SAADC_INT_CALIBRATEDONE = SAADC_INTENSET_CALIBRATEDONE_Msk, ///< Interrupt on EVENTS_CALIBRATEDONE event.
221*150812a8SEvalZero NRF_SAADC_INT_STOPPED = SAADC_INTENSET_STOPPED_Msk, ///< Interrupt on EVENTS_STOPPED event.
222*150812a8SEvalZero NRF_SAADC_INT_CH0LIMITH = SAADC_INTENSET_CH0LIMITH_Msk, ///< Interrupt on EVENTS_CH[0].LIMITH event.
223*150812a8SEvalZero NRF_SAADC_INT_CH0LIMITL = SAADC_INTENSET_CH0LIMITL_Msk, ///< Interrupt on EVENTS_CH[0].LIMITL event.
224*150812a8SEvalZero NRF_SAADC_INT_CH1LIMITH = SAADC_INTENSET_CH1LIMITH_Msk, ///< Interrupt on EVENTS_CH[1].LIMITH event.
225*150812a8SEvalZero NRF_SAADC_INT_CH1LIMITL = SAADC_INTENSET_CH1LIMITL_Msk, ///< Interrupt on EVENTS_CH[1].LIMITL event.
226*150812a8SEvalZero NRF_SAADC_INT_CH2LIMITH = SAADC_INTENSET_CH2LIMITH_Msk, ///< Interrupt on EVENTS_CH[2].LIMITH event.
227*150812a8SEvalZero NRF_SAADC_INT_CH2LIMITL = SAADC_INTENSET_CH2LIMITL_Msk, ///< Interrupt on EVENTS_CH[2].LIMITL event.
228*150812a8SEvalZero NRF_SAADC_INT_CH3LIMITH = SAADC_INTENSET_CH3LIMITH_Msk, ///< Interrupt on EVENTS_CH[3].LIMITH event.
229*150812a8SEvalZero NRF_SAADC_INT_CH3LIMITL = SAADC_INTENSET_CH3LIMITL_Msk, ///< Interrupt on EVENTS_CH[3].LIMITL event.
230*150812a8SEvalZero NRF_SAADC_INT_CH4LIMITH = SAADC_INTENSET_CH4LIMITH_Msk, ///< Interrupt on EVENTS_CH[4].LIMITH event.
231*150812a8SEvalZero NRF_SAADC_INT_CH4LIMITL = SAADC_INTENSET_CH4LIMITL_Msk, ///< Interrupt on EVENTS_CH[4].LIMITL event.
232*150812a8SEvalZero NRF_SAADC_INT_CH5LIMITH = SAADC_INTENSET_CH5LIMITH_Msk, ///< Interrupt on EVENTS_CH[5].LIMITH event.
233*150812a8SEvalZero NRF_SAADC_INT_CH5LIMITL = SAADC_INTENSET_CH5LIMITL_Msk, ///< Interrupt on EVENTS_CH[5].LIMITL event.
234*150812a8SEvalZero NRF_SAADC_INT_CH6LIMITH = SAADC_INTENSET_CH6LIMITH_Msk, ///< Interrupt on EVENTS_CH[6].LIMITH event.
235*150812a8SEvalZero NRF_SAADC_INT_CH6LIMITL = SAADC_INTENSET_CH6LIMITL_Msk, ///< Interrupt on EVENTS_CH[6].LIMITL event.
236*150812a8SEvalZero NRF_SAADC_INT_CH7LIMITH = SAADC_INTENSET_CH7LIMITH_Msk, ///< Interrupt on EVENTS_CH[7].LIMITH event.
237*150812a8SEvalZero NRF_SAADC_INT_CH7LIMITL = SAADC_INTENSET_CH7LIMITL_Msk, ///< Interrupt on EVENTS_CH[7].LIMITL event.
238*150812a8SEvalZero NRF_SAADC_INT_ALL = 0x7FFFFFFFUL ///< Mask of all interrupts.
239*150812a8SEvalZero } nrf_saadc_int_mask_t;
240*150812a8SEvalZero
241*150812a8SEvalZero
242*150812a8SEvalZero /**
243*150812a8SEvalZero * @brief Analog-to-digital converter value limit type.
244*150812a8SEvalZero */
245*150812a8SEvalZero typedef enum
246*150812a8SEvalZero {
247*150812a8SEvalZero NRF_SAADC_LIMIT_LOW = 0,
248*150812a8SEvalZero NRF_SAADC_LIMIT_HIGH = 1
249*150812a8SEvalZero } nrf_saadc_limit_t;
250*150812a8SEvalZero
251*150812a8SEvalZero
252*150812a8SEvalZero typedef int16_t nrf_saadc_value_t; ///< Type of a single ADC conversion result.
253*150812a8SEvalZero
254*150812a8SEvalZero
255*150812a8SEvalZero /**
256*150812a8SEvalZero * @brief Analog-to-digital converter configuration structure.
257*150812a8SEvalZero */
258*150812a8SEvalZero typedef struct
259*150812a8SEvalZero {
260*150812a8SEvalZero nrf_saadc_resolution_t resolution;
261*150812a8SEvalZero nrf_saadc_oversample_t oversample;
262*150812a8SEvalZero nrf_saadc_value_t * buffer;
263*150812a8SEvalZero uint32_t buffer_size;
264*150812a8SEvalZero } nrf_saadc_config_t;
265*150812a8SEvalZero
266*150812a8SEvalZero
267*150812a8SEvalZero /**
268*150812a8SEvalZero * @brief Analog-to-digital converter channel configuration structure.
269*150812a8SEvalZero */
270*150812a8SEvalZero typedef struct
271*150812a8SEvalZero {
272*150812a8SEvalZero nrf_saadc_resistor_t resistor_p;
273*150812a8SEvalZero nrf_saadc_resistor_t resistor_n;
274*150812a8SEvalZero nrf_saadc_gain_t gain;
275*150812a8SEvalZero nrf_saadc_reference_t reference;
276*150812a8SEvalZero nrf_saadc_acqtime_t acq_time;
277*150812a8SEvalZero nrf_saadc_mode_t mode;
278*150812a8SEvalZero nrf_saadc_burst_t burst;
279*150812a8SEvalZero nrf_saadc_input_t pin_p;
280*150812a8SEvalZero nrf_saadc_input_t pin_n;
281*150812a8SEvalZero } nrf_saadc_channel_config_t;
282*150812a8SEvalZero
283*150812a8SEvalZero /**
284*150812a8SEvalZero * @brief Function for triggering a specific SAADC task.
285*150812a8SEvalZero *
286*150812a8SEvalZero * @param[in] saadc_task SAADC task.
287*150812a8SEvalZero */
288*150812a8SEvalZero __STATIC_INLINE void nrf_saadc_task_trigger(nrf_saadc_task_t saadc_task);
289*150812a8SEvalZero
290*150812a8SEvalZero /**
291*150812a8SEvalZero * @brief Function for getting the address of a specific SAADC task register.
292*150812a8SEvalZero *
293*150812a8SEvalZero * @param[in] saadc_task SAADC task.
294*150812a8SEvalZero *
295*150812a8SEvalZero * @return Address of the specified SAADC task.
296*150812a8SEvalZero */
297*150812a8SEvalZero __STATIC_INLINE uint32_t nrf_saadc_task_address_get(nrf_saadc_task_t saadc_task);
298*150812a8SEvalZero
299*150812a8SEvalZero /**
300*150812a8SEvalZero * @brief Function for getting the state of a specific SAADC event.
301*150812a8SEvalZero *
302*150812a8SEvalZero * @param[in] saadc_event SAADC event.
303*150812a8SEvalZero *
304*150812a8SEvalZero * @return State of the specified SAADC event.
305*150812a8SEvalZero */
306*150812a8SEvalZero __STATIC_INLINE bool nrf_saadc_event_check(nrf_saadc_event_t saadc_event);
307*150812a8SEvalZero
308*150812a8SEvalZero /**
309*150812a8SEvalZero * @brief Function for clearing the specific SAADC event.
310*150812a8SEvalZero *
311*150812a8SEvalZero * @param[in] saadc_event SAADC event.
312*150812a8SEvalZero */
313*150812a8SEvalZero __STATIC_INLINE void nrf_saadc_event_clear(nrf_saadc_event_t saadc_event);
314*150812a8SEvalZero
315*150812a8SEvalZero /**
316*150812a8SEvalZero * @brief Function for getting the address of a specific SAADC event register.
317*150812a8SEvalZero *
318*150812a8SEvalZero * @param[in] saadc_event SAADC event.
319*150812a8SEvalZero *
320*150812a8SEvalZero * @return Address of the specified SAADC event.
321*150812a8SEvalZero */
322*150812a8SEvalZero __STATIC_INLINE uint32_t nrf_saadc_event_address_get(nrf_saadc_event_t saadc_event);
323*150812a8SEvalZero
324*150812a8SEvalZero #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
325*150812a8SEvalZero /**
326*150812a8SEvalZero * @brief Function for setting the subscribe configuration for a given
327*150812a8SEvalZero * SAADC task.
328*150812a8SEvalZero *
329*150812a8SEvalZero * @param[in] task Task for which to set the configuration.
330*150812a8SEvalZero * @param[in] channel Channel through which to subscribe events.
331*150812a8SEvalZero */
332*150812a8SEvalZero __STATIC_INLINE void nrf_saadc_subscribe_set(nrf_saadc_task_t task,
333*150812a8SEvalZero uint8_t channel);
334*150812a8SEvalZero
335*150812a8SEvalZero /**
336*150812a8SEvalZero * @brief Function for clearing the subscribe configuration for a given
337*150812a8SEvalZero * SAADC task.
338*150812a8SEvalZero *
339*150812a8SEvalZero * @param[in] task Task for which to clear the configuration.
340*150812a8SEvalZero */
341*150812a8SEvalZero __STATIC_INLINE void nrf_saadc_subscribe_clear(nrf_saadc_task_t task);
342*150812a8SEvalZero
343*150812a8SEvalZero /**
344*150812a8SEvalZero * @brief Function for setting the publish configuration for a given
345*150812a8SEvalZero * SAADC event.
346*150812a8SEvalZero *
347*150812a8SEvalZero * @param[in] event Event for which to set the configuration.
348*150812a8SEvalZero * @param[in] channel Channel through which to publish the event.
349*150812a8SEvalZero */
350*150812a8SEvalZero __STATIC_INLINE void nrf_saadc_publish_set(nrf_saadc_event_t event,
351*150812a8SEvalZero uint8_t channel);
352*150812a8SEvalZero
353*150812a8SEvalZero /**
354*150812a8SEvalZero * @brief Function for clearing the publish configuration for a given
355*150812a8SEvalZero * SAADC event.
356*150812a8SEvalZero *
357*150812a8SEvalZero * @param[in] event Event for which to clear the configuration.
358*150812a8SEvalZero */
359*150812a8SEvalZero __STATIC_INLINE void nrf_saadc_publish_clear(nrf_saadc_event_t event);
360*150812a8SEvalZero #endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
361*150812a8SEvalZero
362*150812a8SEvalZero /**
363*150812a8SEvalZero * @brief Function for getting the address of a specific SAADC limit event register.
364*150812a8SEvalZero *
365*150812a8SEvalZero * @param[in] channel Channel number.
366*150812a8SEvalZero * @param[in] limit_type Low limit or high limit.
367*150812a8SEvalZero *
368*150812a8SEvalZero * @return Address of the specified SAADC limit event.
369*150812a8SEvalZero */
370*150812a8SEvalZero __STATIC_INLINE volatile uint32_t * nrf_saadc_event_limit_address_get(uint8_t channel, nrf_saadc_limit_t limit_type);
371*150812a8SEvalZero
372*150812a8SEvalZero /**
373*150812a8SEvalZero * @brief Function for getting the SAADC channel monitoring limit events.
374*150812a8SEvalZero *
375*150812a8SEvalZero * @param[in] channel Channel number.
376*150812a8SEvalZero * @param[in] limit_type Low limit or high limit.
377*150812a8SEvalZero */
378*150812a8SEvalZero __STATIC_INLINE nrf_saadc_event_t nrf_saadc_event_limit_get(uint8_t channel, nrf_saadc_limit_t limit_type);
379*150812a8SEvalZero
380*150812a8SEvalZero /**
381*150812a8SEvalZero * @brief Function for configuring the input pins for a specific SAADC channel.
382*150812a8SEvalZero *
383*150812a8SEvalZero * @param[in] channel Channel number.
384*150812a8SEvalZero * @param[in] pselp Positive input.
385*150812a8SEvalZero * @param[in] pseln Negative input. Set to NRF_SAADC_INPUT_DISABLED in single ended mode.
386*150812a8SEvalZero */
387*150812a8SEvalZero __STATIC_INLINE void nrf_saadc_channel_input_set(uint8_t channel,
388*150812a8SEvalZero nrf_saadc_input_t pselp,
389*150812a8SEvalZero nrf_saadc_input_t pseln);
390*150812a8SEvalZero
391*150812a8SEvalZero /**
392*150812a8SEvalZero * @brief Function for configuring the positive input pin for a specific SAADC channel.
393*150812a8SEvalZero *
394*150812a8SEvalZero * @param[in] channel Channel number.
395*150812a8SEvalZero * @param[in] pselp Positive input.
396*150812a8SEvalZero */
397*150812a8SEvalZero __STATIC_INLINE void nrf_saadc_channel_pos_input_set(uint8_t channel,
398*150812a8SEvalZero nrf_saadc_input_t pselp);
399*150812a8SEvalZero
400*150812a8SEvalZero /**
401*150812a8SEvalZero * @brief Function for setting the SAADC channel monitoring limits.
402*150812a8SEvalZero *
403*150812a8SEvalZero * @param[in] channel Channel number.
404*150812a8SEvalZero * @param[in] low Low limit.
405*150812a8SEvalZero * @param[in] high High limit.
406*150812a8SEvalZero */
407*150812a8SEvalZero __STATIC_INLINE void nrf_saadc_channel_limits_set(uint8_t channel, int16_t low, int16_t high);
408*150812a8SEvalZero
409*150812a8SEvalZero /**
410*150812a8SEvalZero * @brief Function for enabling specified SAADC interrupts.
411*150812a8SEvalZero *
412*150812a8SEvalZero * @param[in] saadc_int_mask Interrupt(s) to enable.
413*150812a8SEvalZero */
414*150812a8SEvalZero __STATIC_INLINE void nrf_saadc_int_enable(uint32_t saadc_int_mask);
415*150812a8SEvalZero
416*150812a8SEvalZero /**
417*150812a8SEvalZero * @brief Function for retrieving the state of specified SAADC interrupts.
418*150812a8SEvalZero *
419*150812a8SEvalZero * @param[in] saadc_int_mask Interrupt(s) to check.
420*150812a8SEvalZero *
421*150812a8SEvalZero * @retval true If all specified interrupts are enabled.
422*150812a8SEvalZero * @retval false If at least one of the given interrupts is not enabled.
423*150812a8SEvalZero */
424*150812a8SEvalZero __STATIC_INLINE bool nrf_saadc_int_enable_check(uint32_t saadc_int_mask);
425*150812a8SEvalZero
426*150812a8SEvalZero /**
427*150812a8SEvalZero * @brief Function for disabling specified interrupts.
428*150812a8SEvalZero *
429*150812a8SEvalZero * @param saadc_int_mask Interrupt(s) to disable.
430*150812a8SEvalZero */
431*150812a8SEvalZero __STATIC_INLINE void nrf_saadc_int_disable(uint32_t saadc_int_mask);
432*150812a8SEvalZero
433*150812a8SEvalZero /**
434*150812a8SEvalZero * @brief Function for generating masks for SAADC channel limit interrupts.
435*150812a8SEvalZero *
436*150812a8SEvalZero * @param[in] channel SAADC channel number.
437*150812a8SEvalZero * @param[in] limit_type Limit type.
438*150812a8SEvalZero *
439*150812a8SEvalZero * @returns Interrupt mask.
440*150812a8SEvalZero */
441*150812a8SEvalZero __STATIC_INLINE uint32_t nrf_saadc_limit_int_get(uint8_t channel, nrf_saadc_limit_t limit_type);
442*150812a8SEvalZero
443*150812a8SEvalZero /**
444*150812a8SEvalZero * @brief Function for checking whether the SAADC is busy.
445*150812a8SEvalZero *
446*150812a8SEvalZero * This function checks whether the analog-to-digital converter is busy with a conversion.
447*150812a8SEvalZero *
448*150812a8SEvalZero * @retval true If the SAADC is busy.
449*150812a8SEvalZero * @retval false If the SAADC is not busy.
450*150812a8SEvalZero */
451*150812a8SEvalZero __STATIC_INLINE bool nrf_saadc_busy_check(void);
452*150812a8SEvalZero
453*150812a8SEvalZero /**
454*150812a8SEvalZero * @brief Function for enabling the SAADC.
455*150812a8SEvalZero *
456*150812a8SEvalZero * The analog-to-digital converter must be enabled before use.
457*150812a8SEvalZero */
458*150812a8SEvalZero __STATIC_INLINE void nrf_saadc_enable(void);
459*150812a8SEvalZero
460*150812a8SEvalZero /**
461*150812a8SEvalZero * @brief Function for disabling the SAADC.
462*150812a8SEvalZero */
463*150812a8SEvalZero __STATIC_INLINE void nrf_saadc_disable(void);
464*150812a8SEvalZero
465*150812a8SEvalZero /**
466*150812a8SEvalZero * @brief Function for checking if the SAADC is enabled.
467*150812a8SEvalZero *
468*150812a8SEvalZero * @retval true If the SAADC is enabled.
469*150812a8SEvalZero * @retval false If the SAADC is not enabled.
470*150812a8SEvalZero */
471*150812a8SEvalZero __STATIC_INLINE bool nrf_saadc_enable_check(void);
472*150812a8SEvalZero
473*150812a8SEvalZero /**
474*150812a8SEvalZero * @brief Function for initializing the SAADC result buffer.
475*150812a8SEvalZero *
476*150812a8SEvalZero * @param[in] p_buffer Pointer to the result buffer.
477*150812a8SEvalZero * @param[in] size Size of the buffer (in 16-bit samples).
478*150812a8SEvalZero */
479*150812a8SEvalZero __STATIC_INLINE void nrf_saadc_buffer_init(nrf_saadc_value_t * p_buffer,
480*150812a8SEvalZero uint32_t size);
481*150812a8SEvalZero
482*150812a8SEvalZero /**
483*150812a8SEvalZero * @brief Function for setting the SAADC result buffer pointer.
484*150812a8SEvalZero *
485*150812a8SEvalZero * @param[in] p_buffer Pointer to the result buffer.
486*150812a8SEvalZero */
487*150812a8SEvalZero __STATIC_INLINE void nrf_saadc_buffer_pointer_set(nrf_saadc_value_t * p_buffer);
488*150812a8SEvalZero
489*150812a8SEvalZero /**
490*150812a8SEvalZero * @brief Function for getting the SAADC result buffer pointer.
491*150812a8SEvalZero *
492*150812a8SEvalZero * @return Pointer to the result buffer.
493*150812a8SEvalZero */
494*150812a8SEvalZero __STATIC_INLINE nrf_saadc_value_t * nrf_saadc_buffer_pointer_get(void);
495*150812a8SEvalZero
496*150812a8SEvalZero /**
497*150812a8SEvalZero * @brief Function for getting the number of samples written to the result
498*150812a8SEvalZero * buffer since the previous START task.
499*150812a8SEvalZero *
500*150812a8SEvalZero * @returns Number of 16-bit samples written to the buffer.
501*150812a8SEvalZero */
502*150812a8SEvalZero __STATIC_INLINE uint16_t nrf_saadc_amount_get(void);
503*150812a8SEvalZero
504*150812a8SEvalZero /**
505*150812a8SEvalZero * @brief Function for setting the SAADC sample resolution.
506*150812a8SEvalZero *
507*150812a8SEvalZero * @param[in] resolution Bit resolution.
508*150812a8SEvalZero */
509*150812a8SEvalZero __STATIC_INLINE void nrf_saadc_resolution_set(nrf_saadc_resolution_t resolution);
510*150812a8SEvalZero
511*150812a8SEvalZero /**
512*150812a8SEvalZero * @brief Function for configuring the oversampling feature.
513*150812a8SEvalZero *
514*150812a8SEvalZero * @param[in] oversample Oversampling mode.
515*150812a8SEvalZero */
516*150812a8SEvalZero __STATIC_INLINE void nrf_saadc_oversample_set(nrf_saadc_oversample_t oversample);
517*150812a8SEvalZero
518*150812a8SEvalZero /**
519*150812a8SEvalZero * @brief Function for getting the oversampling feature configuration.
520*150812a8SEvalZero *
521*150812a8SEvalZero * @return Oversampling configuration.
522*150812a8SEvalZero */
523*150812a8SEvalZero __STATIC_INLINE nrf_saadc_oversample_t nrf_saadc_oversample_get(void);
524*150812a8SEvalZero
525*150812a8SEvalZero /**
526*150812a8SEvalZero * @brief Function for initializing the SAADC channel.
527*150812a8SEvalZero *
528*150812a8SEvalZero * @param[in] channel Channel number.
529*150812a8SEvalZero * @param[in] config Pointer to the channel configuration structure.
530*150812a8SEvalZero */
531*150812a8SEvalZero __STATIC_INLINE void nrf_saadc_channel_init(uint8_t channel,
532*150812a8SEvalZero nrf_saadc_channel_config_t const * const config);
533*150812a8SEvalZero
534*150812a8SEvalZero /**
535*150812a8SEvalZero * @brief Function for configuring the burst mode for the specified channel.
536*150812a8SEvalZero *
537*150812a8SEvalZero * @param[in] channel Channel number.
538*150812a8SEvalZero * @param[in] burst Burst mode setting.
539*150812a8SEvalZero */
540*150812a8SEvalZero __STATIC_INLINE void nrf_saadc_burst_set(uint8_t channel,
541*150812a8SEvalZero nrf_saadc_burst_t burst);
542*150812a8SEvalZero
543*150812a8SEvalZero #ifndef SUPPRESS_INLINE_IMPLEMENTATION
544*150812a8SEvalZero
nrf_saadc_task_trigger(nrf_saadc_task_t saadc_task)545*150812a8SEvalZero __STATIC_INLINE void nrf_saadc_task_trigger(nrf_saadc_task_t saadc_task)
546*150812a8SEvalZero {
547*150812a8SEvalZero *((volatile uint32_t *)((uint8_t *)NRF_SAADC + (uint32_t)saadc_task)) = 0x1UL;
548*150812a8SEvalZero }
549*150812a8SEvalZero
nrf_saadc_task_address_get(nrf_saadc_task_t saadc_task)550*150812a8SEvalZero __STATIC_INLINE uint32_t nrf_saadc_task_address_get(nrf_saadc_task_t saadc_task)
551*150812a8SEvalZero {
552*150812a8SEvalZero return (uint32_t)((uint8_t *)NRF_SAADC + (uint32_t)saadc_task);
553*150812a8SEvalZero }
554*150812a8SEvalZero
nrf_saadc_event_check(nrf_saadc_event_t saadc_event)555*150812a8SEvalZero __STATIC_INLINE bool nrf_saadc_event_check(nrf_saadc_event_t saadc_event)
556*150812a8SEvalZero {
557*150812a8SEvalZero return (bool)*(volatile uint32_t *)((uint8_t *)NRF_SAADC + (uint32_t)saadc_event);
558*150812a8SEvalZero }
559*150812a8SEvalZero
nrf_saadc_event_clear(nrf_saadc_event_t saadc_event)560*150812a8SEvalZero __STATIC_INLINE void nrf_saadc_event_clear(nrf_saadc_event_t saadc_event)
561*150812a8SEvalZero {
562*150812a8SEvalZero *((volatile uint32_t *)((uint8_t *)NRF_SAADC + (uint32_t)saadc_event)) = 0x0UL;
563*150812a8SEvalZero #if __CORTEX_M == 0x04
564*150812a8SEvalZero volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_SAADC + (uint32_t)saadc_event));
565*150812a8SEvalZero (void)dummy;
566*150812a8SEvalZero #endif
567*150812a8SEvalZero }
568*150812a8SEvalZero
nrf_saadc_event_address_get(nrf_saadc_event_t saadc_event)569*150812a8SEvalZero __STATIC_INLINE uint32_t nrf_saadc_event_address_get(nrf_saadc_event_t saadc_event)
570*150812a8SEvalZero {
571*150812a8SEvalZero return (uint32_t )((uint8_t *)NRF_SAADC + (uint32_t)saadc_event);
572*150812a8SEvalZero }
573*150812a8SEvalZero
574*150812a8SEvalZero #if defined(DPPI_PRESENT)
nrf_saadc_subscribe_set(nrf_saadc_task_t task,uint8_t channel)575*150812a8SEvalZero __STATIC_INLINE void nrf_saadc_subscribe_set(nrf_saadc_task_t task,
576*150812a8SEvalZero uint8_t channel)
577*150812a8SEvalZero {
578*150812a8SEvalZero *((volatile uint32_t *) ((uint8_t *) NRF_SAADC + (uint32_t) task + 0x80uL)) =
579*150812a8SEvalZero ((uint32_t)channel | SAADC_SUBSCRIBE_START_EN_Msk);
580*150812a8SEvalZero }
581*150812a8SEvalZero
nrf_saadc_subscribe_clear(nrf_saadc_task_t task)582*150812a8SEvalZero __STATIC_INLINE void nrf_saadc_subscribe_clear(nrf_saadc_task_t task)
583*150812a8SEvalZero {
584*150812a8SEvalZero *((volatile uint32_t *) ((uint8_t *) NRF_SAADC + (uint32_t) task + 0x80uL)) = 0;
585*150812a8SEvalZero }
586*150812a8SEvalZero
nrf_saadc_publish_set(nrf_saadc_event_t event,uint8_t channel)587*150812a8SEvalZero __STATIC_INLINE void nrf_saadc_publish_set(nrf_saadc_event_t event,
588*150812a8SEvalZero uint8_t channel)
589*150812a8SEvalZero {
590*150812a8SEvalZero *((volatile uint32_t *) ((uint8_t *) NRF_SAADC + (uint32_t) event + 0x80uL)) =
591*150812a8SEvalZero ((uint32_t)channel | SAADC_PUBLISH_STARTED_EN_Msk);
592*150812a8SEvalZero }
593*150812a8SEvalZero
nrf_saadc_publish_clear(nrf_saadc_event_t event)594*150812a8SEvalZero __STATIC_INLINE void nrf_saadc_publish_clear(nrf_saadc_event_t event)
595*150812a8SEvalZero {
596*150812a8SEvalZero *((volatile uint32_t *) ((uint8_t *) NRF_SAADC + (uint32_t) event + 0x80uL)) = 0;
597*150812a8SEvalZero }
598*150812a8SEvalZero #endif // defined(DPPI_PRESENT)
599*150812a8SEvalZero
nrf_saadc_event_limit_address_get(uint8_t channel,nrf_saadc_limit_t limit_type)600*150812a8SEvalZero __STATIC_INLINE volatile uint32_t * nrf_saadc_event_limit_address_get(uint8_t channel, nrf_saadc_limit_t limit_type)
601*150812a8SEvalZero {
602*150812a8SEvalZero NRFX_ASSERT(channel < NRF_SAADC_CHANNEL_COUNT);
603*150812a8SEvalZero if (limit_type == NRF_SAADC_LIMIT_HIGH)
604*150812a8SEvalZero {
605*150812a8SEvalZero return &NRF_SAADC->EVENTS_CH[channel].LIMITH;
606*150812a8SEvalZero }
607*150812a8SEvalZero else
608*150812a8SEvalZero {
609*150812a8SEvalZero return &NRF_SAADC->EVENTS_CH[channel].LIMITL;
610*150812a8SEvalZero }
611*150812a8SEvalZero }
612*150812a8SEvalZero
nrf_saadc_event_limit_get(uint8_t channel,nrf_saadc_limit_t limit_type)613*150812a8SEvalZero __STATIC_INLINE nrf_saadc_event_t nrf_saadc_event_limit_get(uint8_t channel, nrf_saadc_limit_t limit_type)
614*150812a8SEvalZero {
615*150812a8SEvalZero if (limit_type == NRF_SAADC_LIMIT_HIGH)
616*150812a8SEvalZero {
617*150812a8SEvalZero return (nrf_saadc_event_t)( (uint32_t) NRF_SAADC_EVENT_CH0_LIMITH +
618*150812a8SEvalZero (uint32_t) (NRF_SAADC_EVENT_CH1_LIMITH - NRF_SAADC_EVENT_CH0_LIMITH)
619*150812a8SEvalZero * (uint32_t) channel );
620*150812a8SEvalZero }
621*150812a8SEvalZero else
622*150812a8SEvalZero {
623*150812a8SEvalZero return (nrf_saadc_event_t)( (uint32_t) NRF_SAADC_EVENT_CH0_LIMITL +
624*150812a8SEvalZero (uint32_t) (NRF_SAADC_EVENT_CH1_LIMITL - NRF_SAADC_EVENT_CH0_LIMITL)
625*150812a8SEvalZero * (uint32_t) channel );
626*150812a8SEvalZero }
627*150812a8SEvalZero }
628*150812a8SEvalZero
nrf_saadc_channel_input_set(uint8_t channel,nrf_saadc_input_t pselp,nrf_saadc_input_t pseln)629*150812a8SEvalZero __STATIC_INLINE void nrf_saadc_channel_input_set(uint8_t channel,
630*150812a8SEvalZero nrf_saadc_input_t pselp,
631*150812a8SEvalZero nrf_saadc_input_t pseln)
632*150812a8SEvalZero {
633*150812a8SEvalZero NRF_SAADC->CH[channel].PSELN = pseln;
634*150812a8SEvalZero NRF_SAADC->CH[channel].PSELP = pselp;
635*150812a8SEvalZero }
636*150812a8SEvalZero
nrf_saadc_channel_pos_input_set(uint8_t channel,nrf_saadc_input_t pselp)637*150812a8SEvalZero __STATIC_INLINE void nrf_saadc_channel_pos_input_set(uint8_t channel,
638*150812a8SEvalZero nrf_saadc_input_t pselp)
639*150812a8SEvalZero {
640*150812a8SEvalZero NRF_SAADC->CH[channel].PSELP = pselp;
641*150812a8SEvalZero }
642*150812a8SEvalZero
nrf_saadc_channel_limits_set(uint8_t channel,int16_t low,int16_t high)643*150812a8SEvalZero __STATIC_INLINE void nrf_saadc_channel_limits_set(uint8_t channel, int16_t low, int16_t high)
644*150812a8SEvalZero {
645*150812a8SEvalZero NRF_SAADC->CH[channel].LIMIT = (
646*150812a8SEvalZero (((uint32_t) low << SAADC_CH_LIMIT_LOW_Pos) & SAADC_CH_LIMIT_LOW_Msk)
647*150812a8SEvalZero | (((uint32_t) high << SAADC_CH_LIMIT_HIGH_Pos) & SAADC_CH_LIMIT_HIGH_Msk));
648*150812a8SEvalZero }
649*150812a8SEvalZero
nrf_saadc_int_enable(uint32_t saadc_int_mask)650*150812a8SEvalZero __STATIC_INLINE void nrf_saadc_int_enable(uint32_t saadc_int_mask)
651*150812a8SEvalZero {
652*150812a8SEvalZero NRF_SAADC->INTENSET = saadc_int_mask;
653*150812a8SEvalZero }
654*150812a8SEvalZero
nrf_saadc_int_enable_check(uint32_t saadc_int_mask)655*150812a8SEvalZero __STATIC_INLINE bool nrf_saadc_int_enable_check(uint32_t saadc_int_mask)
656*150812a8SEvalZero {
657*150812a8SEvalZero return (bool)(NRF_SAADC->INTENSET & saadc_int_mask);
658*150812a8SEvalZero }
659*150812a8SEvalZero
nrf_saadc_int_disable(uint32_t saadc_int_mask)660*150812a8SEvalZero __STATIC_INLINE void nrf_saadc_int_disable(uint32_t saadc_int_mask)
661*150812a8SEvalZero {
662*150812a8SEvalZero NRF_SAADC->INTENCLR = saadc_int_mask;
663*150812a8SEvalZero }
664*150812a8SEvalZero
nrf_saadc_limit_int_get(uint8_t channel,nrf_saadc_limit_t limit_type)665*150812a8SEvalZero __STATIC_INLINE uint32_t nrf_saadc_limit_int_get(uint8_t channel, nrf_saadc_limit_t limit_type)
666*150812a8SEvalZero {
667*150812a8SEvalZero NRFX_ASSERT(channel < NRF_SAADC_CHANNEL_COUNT);
668*150812a8SEvalZero uint32_t mask = (limit_type == NRF_SAADC_LIMIT_LOW) ? NRF_SAADC_INT_CH0LIMITL : NRF_SAADC_INT_CH0LIMITH;
669*150812a8SEvalZero return mask << (channel * 2);
670*150812a8SEvalZero }
671*150812a8SEvalZero
nrf_saadc_busy_check(void)672*150812a8SEvalZero __STATIC_INLINE bool nrf_saadc_busy_check(void)
673*150812a8SEvalZero {
674*150812a8SEvalZero //return ((NRF_SAADC->STATUS & SAADC_STATUS_STATUS_Msk) == SAADC_STATUS_STATUS_Msk);
675*150812a8SEvalZero //simplified for performance
676*150812a8SEvalZero return NRF_SAADC->STATUS;
677*150812a8SEvalZero }
678*150812a8SEvalZero
nrf_saadc_enable(void)679*150812a8SEvalZero __STATIC_INLINE void nrf_saadc_enable(void)
680*150812a8SEvalZero {
681*150812a8SEvalZero NRF_SAADC->ENABLE = (SAADC_ENABLE_ENABLE_Enabled << SAADC_ENABLE_ENABLE_Pos);
682*150812a8SEvalZero }
683*150812a8SEvalZero
nrf_saadc_disable(void)684*150812a8SEvalZero __STATIC_INLINE void nrf_saadc_disable(void)
685*150812a8SEvalZero {
686*150812a8SEvalZero NRF_SAADC->ENABLE = (SAADC_ENABLE_ENABLE_Disabled << SAADC_ENABLE_ENABLE_Pos);
687*150812a8SEvalZero }
688*150812a8SEvalZero
nrf_saadc_enable_check(void)689*150812a8SEvalZero __STATIC_INLINE bool nrf_saadc_enable_check(void)
690*150812a8SEvalZero {
691*150812a8SEvalZero //simplified for performance
692*150812a8SEvalZero return NRF_SAADC->ENABLE;
693*150812a8SEvalZero }
694*150812a8SEvalZero
nrf_saadc_buffer_init(nrf_saadc_value_t * p_buffer,uint32_t size)695*150812a8SEvalZero __STATIC_INLINE void nrf_saadc_buffer_init(nrf_saadc_value_t * p_buffer,
696*150812a8SEvalZero uint32_t size)
697*150812a8SEvalZero {
698*150812a8SEvalZero NRF_SAADC->RESULT.PTR = (uint32_t)p_buffer;
699*150812a8SEvalZero NRF_SAADC->RESULT.MAXCNT = size;
700*150812a8SEvalZero }
701*150812a8SEvalZero
nrf_saadc_buffer_pointer_set(nrf_saadc_value_t * p_buffer)702*150812a8SEvalZero __STATIC_INLINE void nrf_saadc_buffer_pointer_set(nrf_saadc_value_t * p_buffer)
703*150812a8SEvalZero {
704*150812a8SEvalZero NRF_SAADC->RESULT.PTR = (uint32_t)p_buffer;
705*150812a8SEvalZero }
706*150812a8SEvalZero
nrf_saadc_buffer_pointer_get(void)707*150812a8SEvalZero __STATIC_INLINE nrf_saadc_value_t * nrf_saadc_buffer_pointer_get(void)
708*150812a8SEvalZero {
709*150812a8SEvalZero return (nrf_saadc_value_t *)NRF_SAADC->RESULT.PTR;
710*150812a8SEvalZero }
711*150812a8SEvalZero
nrf_saadc_amount_get(void)712*150812a8SEvalZero __STATIC_INLINE uint16_t nrf_saadc_amount_get(void)
713*150812a8SEvalZero {
714*150812a8SEvalZero return NRF_SAADC->RESULT.AMOUNT;
715*150812a8SEvalZero }
716*150812a8SEvalZero
nrf_saadc_resolution_set(nrf_saadc_resolution_t resolution)717*150812a8SEvalZero __STATIC_INLINE void nrf_saadc_resolution_set(nrf_saadc_resolution_t resolution)
718*150812a8SEvalZero {
719*150812a8SEvalZero NRF_SAADC->RESOLUTION = resolution;
720*150812a8SEvalZero }
721*150812a8SEvalZero
nrf_saadc_oversample_set(nrf_saadc_oversample_t oversample)722*150812a8SEvalZero __STATIC_INLINE void nrf_saadc_oversample_set(nrf_saadc_oversample_t oversample)
723*150812a8SEvalZero {
724*150812a8SEvalZero NRF_SAADC->OVERSAMPLE = oversample;
725*150812a8SEvalZero }
726*150812a8SEvalZero
nrf_saadc_oversample_get(void)727*150812a8SEvalZero __STATIC_INLINE nrf_saadc_oversample_t nrf_saadc_oversample_get(void)
728*150812a8SEvalZero {
729*150812a8SEvalZero return (nrf_saadc_oversample_t)NRF_SAADC->OVERSAMPLE;
730*150812a8SEvalZero }
731*150812a8SEvalZero
nrf_saadc_channel_init(uint8_t channel,nrf_saadc_channel_config_t const * const config)732*150812a8SEvalZero __STATIC_INLINE void nrf_saadc_channel_init(uint8_t channel,
733*150812a8SEvalZero nrf_saadc_channel_config_t const * const config)
734*150812a8SEvalZero {
735*150812a8SEvalZero NRF_SAADC->CH[channel].CONFIG =
736*150812a8SEvalZero ((config->resistor_p << SAADC_CH_CONFIG_RESP_Pos) & SAADC_CH_CONFIG_RESP_Msk)
737*150812a8SEvalZero | ((config->resistor_n << SAADC_CH_CONFIG_RESN_Pos) & SAADC_CH_CONFIG_RESN_Msk)
738*150812a8SEvalZero | ((config->gain << SAADC_CH_CONFIG_GAIN_Pos) & SAADC_CH_CONFIG_GAIN_Msk)
739*150812a8SEvalZero | ((config->reference << SAADC_CH_CONFIG_REFSEL_Pos) & SAADC_CH_CONFIG_REFSEL_Msk)
740*150812a8SEvalZero | ((config->acq_time << SAADC_CH_CONFIG_TACQ_Pos) & SAADC_CH_CONFIG_TACQ_Msk)
741*150812a8SEvalZero | ((config->mode << SAADC_CH_CONFIG_MODE_Pos) & SAADC_CH_CONFIG_MODE_Msk)
742*150812a8SEvalZero | ((config->burst << SAADC_CH_CONFIG_BURST_Pos) & SAADC_CH_CONFIG_BURST_Msk);
743*150812a8SEvalZero nrf_saadc_channel_input_set(channel, config->pin_p, config->pin_n);
744*150812a8SEvalZero }
745*150812a8SEvalZero
nrf_saadc_burst_set(uint8_t channel,nrf_saadc_burst_t burst)746*150812a8SEvalZero __STATIC_INLINE void nrf_saadc_burst_set(uint8_t channel,
747*150812a8SEvalZero nrf_saadc_burst_t burst)
748*150812a8SEvalZero {
749*150812a8SEvalZero NRF_SAADC->CH[channel].CONFIG =
750*150812a8SEvalZero (NRF_SAADC->CH[channel].CONFIG & ~SAADC_CH_CONFIG_BURST_Msk) |
751*150812a8SEvalZero (burst << SAADC_CH_CONFIG_BURST_Pos);
752*150812a8SEvalZero }
753*150812a8SEvalZero
754*150812a8SEvalZero #endif // SUPPRESS_INLINE_IMPLEMENTATION
755*150812a8SEvalZero
756*150812a8SEvalZero /** @} */
757*150812a8SEvalZero
758*150812a8SEvalZero #ifdef __cplusplus
759*150812a8SEvalZero }
760*150812a8SEvalZero #endif
761*150812a8SEvalZero
762*150812a8SEvalZero #endif // NRF_SAADC_H_
763