1 /*
2 * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice, this
9 * list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the copyright holder nor the names of its
16 * contributors may be used to endorse or promote products derived from this
17 * software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #ifndef NRF_PWM_H__
33 #define NRF_PWM_H__
34
35 #include <nrfx.h>
36
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40
41 /**
42 * @defgroup nrf_pwm_hal PWM HAL
43 * @{
44 * @ingroup nrf_pwm
45 * @brief Hardware access layer for managing the Pulse Width Modulation (PWM) peripheral.
46 */
47
48 /**
49 * @brief This value can be provided as a parameter for the @ref nrf_pwm_pins_set
50 * function call to specify that a given output channel shall not be
51 * connected to a physical pin.
52 */
53 #define NRF_PWM_PIN_NOT_CONNECTED 0xFFFFFFFF
54
55 /**
56 * @brief Number of channels in each Pointer to the peripheral registers structure.
57 */
58 #define NRF_PWM_CHANNEL_COUNT 4
59
60
61 /**
62 * @brief PWM tasks.
63 */
64 typedef enum
65 {
66 /*lint -save -e30*/
67 NRF_PWM_TASK_STOP = offsetof(NRF_PWM_Type, TASKS_STOP), ///< Stops PWM pulse generation on all channels at the end of the current PWM period, and stops the sequence playback.
68 NRF_PWM_TASK_SEQSTART0 = offsetof(NRF_PWM_Type, TASKS_SEQSTART[0]), ///< Starts playback of sequence 0.
69 NRF_PWM_TASK_SEQSTART1 = offsetof(NRF_PWM_Type, TASKS_SEQSTART[1]), ///< Starts playback of sequence 1.
70 NRF_PWM_TASK_NEXTSTEP = offsetof(NRF_PWM_Type, TASKS_NEXTSTEP) ///< Steps by one value in the current sequence if the decoder is set to @ref NRF_PWM_STEP_TRIGGERED mode.
71 /*lint -restore*/
72 } nrf_pwm_task_t;
73
74 /**
75 * @brief PWM events.
76 */
77 typedef enum
78 {
79 /*lint -save -e30*/
80 NRF_PWM_EVENT_STOPPED = offsetof(NRF_PWM_Type, EVENTS_STOPPED), ///< Response to STOP task, emitted when PWM pulses are no longer generated.
81 NRF_PWM_EVENT_SEQSTARTED0 = offsetof(NRF_PWM_Type, EVENTS_SEQSTARTED[0]), ///< First PWM period started on sequence 0.
82 NRF_PWM_EVENT_SEQSTARTED1 = offsetof(NRF_PWM_Type, EVENTS_SEQSTARTED[1]), ///< First PWM period started on sequence 1.
83 NRF_PWM_EVENT_SEQEND0 = offsetof(NRF_PWM_Type, EVENTS_SEQEND[0]), ///< Emitted at the end of every sequence 0 when its last value has been read from RAM.
84 NRF_PWM_EVENT_SEQEND1 = offsetof(NRF_PWM_Type, EVENTS_SEQEND[1]), ///< Emitted at the end of every sequence 1 when its last value has been read from RAM.
85 NRF_PWM_EVENT_PWMPERIODEND = offsetof(NRF_PWM_Type, EVENTS_PWMPERIODEND), ///< Emitted at the end of each PWM period.
86 NRF_PWM_EVENT_LOOPSDONE = offsetof(NRF_PWM_Type, EVENTS_LOOPSDONE) ///< Concatenated sequences have been played the requested number of times.
87 /*lint -restore*/
88 } nrf_pwm_event_t;
89
90 /**
91 * @brief PWM interrupts.
92 */
93 typedef enum
94 {
95 NRF_PWM_INT_STOPPED_MASK = PWM_INTENSET_STOPPED_Msk, ///< Interrupt on STOPPED event.
96 NRF_PWM_INT_SEQSTARTED0_MASK = PWM_INTENSET_SEQSTARTED0_Msk, ///< Interrupt on SEQSTARTED[0] event.
97 NRF_PWM_INT_SEQSTARTED1_MASK = PWM_INTENSET_SEQSTARTED1_Msk, ///< Interrupt on SEQSTARTED[1] event.
98 NRF_PWM_INT_SEQEND0_MASK = PWM_INTENSET_SEQEND0_Msk, ///< Interrupt on SEQEND[0] event.
99 NRF_PWM_INT_SEQEND1_MASK = PWM_INTENSET_SEQEND1_Msk, ///< Interrupt on SEQEND[1] event.
100 NRF_PWM_INT_PWMPERIODEND_MASK = PWM_INTENSET_PWMPERIODEND_Msk, ///< Interrupt on PWMPERIODEND event.
101 NRF_PWM_INT_LOOPSDONE_MASK = PWM_INTENSET_LOOPSDONE_Msk ///< Interrupt on LOOPSDONE event.
102 } nrf_pwm_int_mask_t;
103
104 /**
105 * @brief PWM shortcuts.
106 */
107 typedef enum
108 {
109 NRF_PWM_SHORT_SEQEND0_STOP_MASK = PWM_SHORTS_SEQEND0_STOP_Msk, ///< Shortcut between SEQEND[0] event and STOP task.
110 NRF_PWM_SHORT_SEQEND1_STOP_MASK = PWM_SHORTS_SEQEND1_STOP_Msk, ///< Shortcut between SEQEND[1] event and STOP task.
111 NRF_PWM_SHORT_LOOPSDONE_SEQSTART0_MASK = PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk, ///< Shortcut between LOOPSDONE event and SEQSTART[0] task.
112 NRF_PWM_SHORT_LOOPSDONE_SEQSTART1_MASK = PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk, ///< Shortcut between LOOPSDONE event and SEQSTART[1] task.
113 NRF_PWM_SHORT_LOOPSDONE_STOP_MASK = PWM_SHORTS_LOOPSDONE_STOP_Msk ///< Shortcut between LOOPSDONE event and STOP task.
114 } nrf_pwm_short_mask_t;
115
116 /**
117 * @brief PWM modes of operation.
118 */
119 typedef enum
120 {
121 NRF_PWM_MODE_UP = PWM_MODE_UPDOWN_Up, ///< Up counter (edge-aligned PWM duty cycle).
122 NRF_PWM_MODE_UP_AND_DOWN = PWM_MODE_UPDOWN_UpAndDown, ///< Up and down counter (center-aligned PWM duty cycle).
123 } nrf_pwm_mode_t;
124
125 /**
126 * @brief PWM base clock frequencies.
127 */
128 typedef enum
129 {
130 NRF_PWM_CLK_16MHz = PWM_PRESCALER_PRESCALER_DIV_1, ///< 16 MHz / 1 = 16 MHz.
131 NRF_PWM_CLK_8MHz = PWM_PRESCALER_PRESCALER_DIV_2, ///< 16 MHz / 2 = 8 MHz.
132 NRF_PWM_CLK_4MHz = PWM_PRESCALER_PRESCALER_DIV_4, ///< 16 MHz / 4 = 4 MHz.
133 NRF_PWM_CLK_2MHz = PWM_PRESCALER_PRESCALER_DIV_8, ///< 16 MHz / 8 = 2 MHz.
134 NRF_PWM_CLK_1MHz = PWM_PRESCALER_PRESCALER_DIV_16, ///< 16 MHz / 16 = 1 MHz.
135 NRF_PWM_CLK_500kHz = PWM_PRESCALER_PRESCALER_DIV_32, ///< 16 MHz / 32 = 500 kHz.
136 NRF_PWM_CLK_250kHz = PWM_PRESCALER_PRESCALER_DIV_64, ///< 16 MHz / 64 = 250 kHz.
137 NRF_PWM_CLK_125kHz = PWM_PRESCALER_PRESCALER_DIV_128 ///< 16 MHz / 128 = 125 kHz.
138 } nrf_pwm_clk_t;
139
140 /**
141 * @brief PWM decoder load modes.
142 *
143 * The selected mode determines how the sequence data is read from RAM and
144 * spread to the compare registers.
145 */
146 typedef enum
147 {
148 NRF_PWM_LOAD_COMMON = PWM_DECODER_LOAD_Common, ///< 1st half word (16-bit) used in all PWM channels (0-3).
149 NRF_PWM_LOAD_GROUPED = PWM_DECODER_LOAD_Grouped, ///< 1st half word (16-bit) used in channels 0 and 1; 2nd word in channels 2 and 3.
150 NRF_PWM_LOAD_INDIVIDUAL = PWM_DECODER_LOAD_Individual, ///< 1st half word (16-bit) used in channel 0; 2nd in channel 1; 3rd in channel 2; 4th in channel 3.
151 NRF_PWM_LOAD_WAVE_FORM = PWM_DECODER_LOAD_WaveForm ///< 1st half word (16-bit) used in channel 0; 2nd in channel 1; ... ; 4th as the top value for the pulse generator counter.
152 } nrf_pwm_dec_load_t;
153
154 /**
155 * @brief PWM decoder next step modes.
156 *
157 * The selected mode determines when the next value from the active sequence
158 * is loaded.
159 */
160 typedef enum
161 {
162 NRF_PWM_STEP_AUTO = PWM_DECODER_MODE_RefreshCount, ///< Automatically after the current value is played and repeated the requested number of times.
163 NRF_PWM_STEP_TRIGGERED = PWM_DECODER_MODE_NextStep ///< When the @ref NRF_PWM_TASK_NEXTSTEP task is triggered.
164 } nrf_pwm_dec_step_t;
165
166
167 /**
168 * @brief Type used for defining duty cycle values for a sequence
169 * loaded in @ref NRF_PWM_LOAD_COMMON mode.
170 */
171 typedef uint16_t nrf_pwm_values_common_t;
172
173 /**
174 * @brief Structure for defining duty cycle values for a sequence
175 * loaded in @ref NRF_PWM_LOAD_GROUPED mode.
176 */
177 typedef struct {
178 uint16_t group_0; ///< Duty cycle value for group 0 (channels 0 and 1).
179 uint16_t group_1; ///< Duty cycle value for group 1 (channels 2 and 3).
180 } nrf_pwm_values_grouped_t;
181
182 /**
183 * @brief Structure for defining duty cycle values for a sequence
184 * loaded in @ref NRF_PWM_LOAD_INDIVIDUAL mode.
185 */
186 typedef struct
187 {
188 uint16_t channel_0; ///< Duty cycle value for channel 0.
189 uint16_t channel_1; ///< Duty cycle value for channel 1.
190 uint16_t channel_2; ///< Duty cycle value for channel 2.
191 uint16_t channel_3; ///< Duty cycle value for channel 3.
192 } nrf_pwm_values_individual_t;
193
194 /**
195 * @brief Structure for defining duty cycle values for a sequence
196 * loaded in @ref NRF_PWM_LOAD_WAVE_FORM mode.
197 */
198 typedef struct {
199 uint16_t channel_0; ///< Duty cycle value for channel 0.
200 uint16_t channel_1; ///< Duty cycle value for channel 1.
201 uint16_t channel_2; ///< Duty cycle value for channel 2.
202 uint16_t counter_top; ///< Top value for the pulse generator counter.
203 } nrf_pwm_values_wave_form_t;
204
205 /**
206 * @brief Union grouping pointers to arrays of duty cycle values applicable to
207 * various loading modes.
208 */
209 typedef union {
210 nrf_pwm_values_common_t const * p_common; ///< Pointer to be used in @ref NRF_PWM_LOAD_COMMON mode.
211 nrf_pwm_values_grouped_t const * p_grouped; ///< Pointer to be used in @ref NRF_PWM_LOAD_GROUPED mode.
212 nrf_pwm_values_individual_t const * p_individual; ///< Pointer to be used in @ref NRF_PWM_LOAD_INDIVIDUAL mode.
213 nrf_pwm_values_wave_form_t const * p_wave_form; ///< Pointer to be used in @ref NRF_PWM_LOAD_WAVE_FORM mode.
214 uint16_t const * p_raw; ///< Pointer providing raw access to the values.
215 } nrf_pwm_values_t;
216
217 /**
218 * @brief Structure for defining a sequence of PWM duty cycles.
219 *
220 * When the sequence is set (by a call to @ref nrf_pwm_sequence_set), the
221 * provided duty cycle values are not copied. The @p values pointer is stored
222 * in the peripheral's internal register, and the values are loaded from RAM
223 * during the sequence playback. Therefore, you must ensure that the values
224 * do not change before and during the sequence playback (for example,
225 * the values cannot be placed in a local variable that is allocated on stack).
226 * If the sequence is played in a loop and the values should be updated
227 * before the next iteration, it is safe to modify them when the corresponding
228 * event signaling the end of sequence occurs (@ref NRF_PWM_EVENT_SEQEND0
229 * or @ref NRF_PWM_EVENT_SEQEND1, respectively).
230 *
231 * @note The @p repeats and @p end_delay values (which are written to the
232 * SEQ[n].REFRESH and SEQ[n].ENDDELAY registers in the peripheral,
233 * respectively) are ignored at the end of a complex sequence
234 * playback, indicated by the LOOPSDONE event.
235 * See the @linkProductSpecification52 for more information.
236 */
237 typedef struct
238 {
239 nrf_pwm_values_t values; ///< Pointer to an array with duty cycle values. This array must be in Data RAM.
240 /**< This field is defined as an union of pointers
241 * to provide a convenient way to define duty
242 * cycle values in various loading modes
243 * (see @ref nrf_pwm_dec_load_t).
244 * In each value, the most significant bit (15)
245 * determines the polarity of the output and the
246 * others (14-0) compose the 15-bit value to be
247 * compared with the pulse generator counter. */
248 uint16_t length; ///< Number of 16-bit values in the array pointed by @p values.
249 uint32_t repeats; ///< Number of times that each duty cycle should be repeated (after being played once). Ignored in @ref NRF_PWM_STEP_TRIGGERED mode.
250 uint32_t end_delay; ///< Additional time (in PWM periods) that the last duty cycle is to be kept after the sequence is played. Ignored in @ref NRF_PWM_STEP_TRIGGERED mode.
251 } nrf_pwm_sequence_t;
252
253 /**
254 * @brief Helper macro for calculating the number of 16-bit values in specified
255 * array of duty cycle values.
256 */
257 #define NRF_PWM_VALUES_LENGTH(array) (sizeof(array) / sizeof(uint16_t))
258
259
260 /**
261 * @brief Function for activating a specific PWM task.
262 *
263 * @param[in] p_reg Pointer to the peripheral registers structure.
264 * @param[in] task Task to activate.
265 */
266 __STATIC_INLINE void nrf_pwm_task_trigger(NRF_PWM_Type * p_reg,
267 nrf_pwm_task_t task);
268
269 /**
270 * @brief Function for getting the address of a specific PWM task register.
271 *
272 * @param[in] p_reg Pointer to the peripheral registers structure.
273 * @param[in] task Requested task.
274 *
275 * @return Address of the specified task register.
276 */
277 __STATIC_INLINE uint32_t nrf_pwm_task_address_get(NRF_PWM_Type const * p_reg,
278 nrf_pwm_task_t task);
279
280 /**
281 * @brief Function for clearing a specific PWM event.
282 *
283 * @param[in] p_reg Pointer to the peripheral registers structure.
284 * @param[in] event Event to clear.
285 */
286 __STATIC_INLINE void nrf_pwm_event_clear(NRF_PWM_Type * p_reg,
287 nrf_pwm_event_t event);
288
289 /**
290 * @brief Function for checking the state of a specific PWM event.
291 *
292 * @param[in] p_reg Pointer to the peripheral registers structure.
293 * @param[in] event Event to check.
294 *
295 * @retval true If the event is set.
296 * @retval false If the event is not set.
297 */
298 __STATIC_INLINE bool nrf_pwm_event_check(NRF_PWM_Type const * p_reg,
299 nrf_pwm_event_t event);
300
301 /**
302 * @brief Function for getting the address of a specific PWM event register.
303 *
304 * @param[in] p_reg Pointer to the peripheral registers structure.
305 * @param[in] event Requested event.
306 *
307 * @return Address of the specified event register.
308 */
309 __STATIC_INLINE uint32_t nrf_pwm_event_address_get(NRF_PWM_Type const * p_reg,
310 nrf_pwm_event_t event);
311
312 /**
313 * @brief Function for enabling specified shortcuts.
314 *
315 * @param[in] p_reg Pointer to the peripheral registers structure.
316 * @param[in] pwm_shorts_mask Shortcuts to enable.
317 */
318 __STATIC_INLINE void nrf_pwm_shorts_enable(NRF_PWM_Type * p_reg,
319 uint32_t pwm_shorts_mask);
320
321 /**
322 * @brief Function for disabling specified shortcuts.
323 *
324 * @param[in] p_reg Pointer to the peripheral registers structure.
325 * @param[in] pwm_shorts_mask Shortcuts to disable.
326 */
327 __STATIC_INLINE void nrf_pwm_shorts_disable(NRF_PWM_Type * p_reg,
328 uint32_t pwm_shorts_mask);
329
330 /**
331 * @brief Function for setting the configuration of PWM shortcuts.
332 *
333 * @param[in] p_reg Pointer to the peripheral registers structure.
334 * @param[in] pwm_shorts_mask Shortcuts configuration to set.
335 */
336 __STATIC_INLINE void nrf_pwm_shorts_set(NRF_PWM_Type * p_reg,
337 uint32_t pwm_shorts_mask);
338
339 /**
340 * @brief Function for enabling specified interrupts.
341 *
342 * @param[in] p_reg Pointer to the peripheral registers structure.
343 * @param[in] pwm_int_mask Interrupts to enable.
344 */
345 __STATIC_INLINE void nrf_pwm_int_enable(NRF_PWM_Type * p_reg,
346 uint32_t pwm_int_mask);
347
348 /**
349 * @brief Function for disabling specified interrupts.
350 *
351 * @param[in] p_reg Pointer to the peripheral registers structure.
352 * @param[in] pwm_int_mask Interrupts to disable.
353 */
354 __STATIC_INLINE void nrf_pwm_int_disable(NRF_PWM_Type * p_reg,
355 uint32_t pwm_int_mask);
356
357 /**
358 * @brief Function for setting the configuration of PWM interrupts.
359 *
360 * @param[in] p_reg Pointer to the peripheral registers structure.
361 * @param[in] pwm_int_mask Interrupts configuration to set.
362 */
363 __STATIC_INLINE void nrf_pwm_int_set(NRF_PWM_Type * p_reg,
364 uint32_t pwm_int_mask);
365
366 /**
367 * @brief Function for retrieving the state of a given interrupt.
368 *
369 * @param[in] p_reg Pointer to the peripheral registers structure.
370 * @param[in] pwm_int Interrupt to check.
371 *
372 * @retval true If the interrupt is enabled.
373 * @retval false If the interrupt is not enabled.
374 */
375 __STATIC_INLINE bool nrf_pwm_int_enable_check(NRF_PWM_Type const * p_reg,
376 nrf_pwm_int_mask_t pwm_int);
377
378 #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
379 /**
380 * @brief Function for setting the subscribe configuration for a given
381 * PWM task.
382 *
383 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
384 * @param[in] task Task for which to set the configuration.
385 * @param[in] channel Channel through which to subscribe events.
386 */
387 __STATIC_INLINE void nrf_pwm_subscribe_set(NRF_PWM_Type * p_reg,
388 nrf_pwm_task_t task,
389 uint8_t channel);
390
391 /**
392 * @brief Function for clearing the subscribe configuration for a given
393 * PWM task.
394 *
395 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
396 * @param[in] task Task for which to clear the configuration.
397 */
398 __STATIC_INLINE void nrf_pwm_subscribe_clear(NRF_PWM_Type * p_reg,
399 nrf_pwm_task_t task);
400
401 /**
402 * @brief Function for setting the publish configuration for a given
403 * PWM event.
404 *
405 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
406 * @param[in] event Event for which to set the configuration.
407 * @param[in] channel Channel through which to publish the event.
408 */
409 __STATIC_INLINE void nrf_pwm_publish_set(NRF_PWM_Type * p_reg,
410 nrf_pwm_event_t event,
411 uint8_t channel);
412
413 /**
414 * @brief Function for clearing the publish configuration for a given
415 * PWM event.
416 *
417 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
418 * @param[in] event Event for which to clear the configuration.
419 */
420 __STATIC_INLINE void nrf_pwm_publish_clear(NRF_PWM_Type * p_reg,
421 nrf_pwm_event_t event);
422 #endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
423
424 /**
425 * @brief Function for enabling the PWM peripheral.
426 *
427 * @param[in] p_reg Pointer to the peripheral registers structure.
428 */
429 __STATIC_INLINE void nrf_pwm_enable(NRF_PWM_Type * p_reg);
430
431 /**
432 * @brief Function for disabling the PWM peripheral.
433 *
434 * @param[in] p_reg Pointer to the peripheral registers structure.
435 */
436 __STATIC_INLINE void nrf_pwm_disable(NRF_PWM_Type * p_reg);
437
438 /**
439 * @brief Function for assigning pins to PWM output channels.
440 *
441 * Usage of all PWM output channels is optional. If a given channel is not
442 * needed, pass the @ref NRF_PWM_PIN_NOT_CONNECTED value instead of its pin
443 * number.
444 *
445 * @param[in] p_reg Pointer to the peripheral registers structure.
446 * @param[in] out_pins Array with pin numbers for individual PWM output channels.
447 */
448 __STATIC_INLINE void nrf_pwm_pins_set(NRF_PWM_Type * p_reg,
449 uint32_t out_pins[NRF_PWM_CHANNEL_COUNT]);
450
451 /**
452 * @brief Function for configuring the PWM peripheral.
453 *
454 * @param[in] p_reg Pointer to the peripheral registers structure.
455 * @param[in] base_clock Base clock frequency.
456 * @param[in] mode Operating mode of the pulse generator counter.
457 * @param[in] top_value Value up to which the pulse generator counter counts.
458 */
459 __STATIC_INLINE void nrf_pwm_configure(NRF_PWM_Type * p_reg,
460 nrf_pwm_clk_t base_clock,
461 nrf_pwm_mode_t mode,
462 uint16_t top_value);
463
464 /**
465 * @brief Function for defining a sequence of PWM duty cycles.
466 *
467 * @param[in] p_reg Pointer to the peripheral registers structure.
468 * @param[in] seq_id Identifier of the sequence (0 or 1).
469 * @param[in] p_seq Pointer to the sequence definition.
470 */
471 __STATIC_INLINE void nrf_pwm_sequence_set(NRF_PWM_Type * p_reg,
472 uint8_t seq_id,
473 nrf_pwm_sequence_t const * p_seq);
474
475 /**
476 * @brief Function for modifying the pointer to the duty cycle values
477 * in the specified sequence.
478 *
479 * @param[in] p_reg Pointer to the peripheral registers structure.
480 * @param[in] seq_id Identifier of the sequence (0 or 1).
481 * @param[in] p_values Pointer to an array with duty cycle values.
482 */
483 __STATIC_INLINE void nrf_pwm_seq_ptr_set(NRF_PWM_Type * p_reg,
484 uint8_t seq_id,
485 uint16_t const * p_values);
486
487 /**
488 * @brief Function for modifying the total number of duty cycle values
489 * in the specified sequence.
490 *
491 * @param[in] p_reg Pointer to the peripheral registers structure.
492 * @param[in] seq_id Identifier of the sequence (0 or 1).
493 * @param[in] length Number of duty cycle values.
494 */
495 __STATIC_INLINE void nrf_pwm_seq_cnt_set(NRF_PWM_Type * p_reg,
496 uint8_t seq_id,
497 uint16_t length);
498
499 /**
500 * @brief Function for modifying the additional number of PWM periods spent
501 * on each duty cycle value in the specified sequence.
502 *
503 * @param[in] p_reg Pointer to the peripheral registers structure.
504 * @param[in] seq_id Identifier of the sequence (0 or 1).
505 * @param[in] refresh Number of additional PWM periods for each duty cycle value.
506 */
507 __STATIC_INLINE void nrf_pwm_seq_refresh_set(NRF_PWM_Type * p_reg,
508 uint8_t seq_id,
509 uint32_t refresh);
510
511 /**
512 * @brief Function for modifying the additional time added after the sequence
513 * is played.
514 *
515 * @param[in] p_reg Pointer to the peripheral registers structure.
516 * @param[in] seq_id Identifier of the sequence (0 or 1).
517 * @param[in] end_delay Number of PWM periods added at the end of the sequence.
518 */
519 __STATIC_INLINE void nrf_pwm_seq_end_delay_set(NRF_PWM_Type * p_reg,
520 uint8_t seq_id,
521 uint32_t end_delay);
522
523 /**
524 * @brief Function for setting the mode of loading sequence data from RAM
525 * and advancing the sequence.
526 *
527 * @param[in] p_reg Pointer to the peripheral registers structure.
528 * @param[in] dec_load Mode of loading sequence data from RAM.
529 * @param[in] dec_step Mode of advancing the active sequence.
530 */
531 __STATIC_INLINE void nrf_pwm_decoder_set(NRF_PWM_Type * p_reg,
532 nrf_pwm_dec_load_t dec_load,
533 nrf_pwm_dec_step_t dec_step);
534
535 /**
536 * @brief Function for setting the number of times the sequence playback
537 * should be performed.
538 *
539 * This function applies to two-sequence playback (concatenated sequence 0 and 1).
540 * A single sequence can be played back only once.
541 *
542 * @param[in] p_reg Pointer to the peripheral registers structure.
543 * @param[in] loop_count Number of times to perform the sequence playback.
544 */
545 __STATIC_INLINE void nrf_pwm_loop_set(NRF_PWM_Type * p_reg,
546 uint16_t loop_count);
547
548
549 #ifndef SUPPRESS_INLINE_IMPLEMENTATION
550
nrf_pwm_task_trigger(NRF_PWM_Type * p_reg,nrf_pwm_task_t task)551 __STATIC_INLINE void nrf_pwm_task_trigger(NRF_PWM_Type * p_reg,
552 nrf_pwm_task_t task)
553 {
554 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
555 }
556
nrf_pwm_task_address_get(NRF_PWM_Type const * p_reg,nrf_pwm_task_t task)557 __STATIC_INLINE uint32_t nrf_pwm_task_address_get(NRF_PWM_Type const * p_reg,
558 nrf_pwm_task_t task)
559 {
560 return ((uint32_t)p_reg + (uint32_t)task);
561 }
562
nrf_pwm_event_clear(NRF_PWM_Type * p_reg,nrf_pwm_event_t event)563 __STATIC_INLINE void nrf_pwm_event_clear(NRF_PWM_Type * p_reg,
564 nrf_pwm_event_t event)
565 {
566 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
567 #if __CORTEX_M == 0x04
568 volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
569 (void)dummy;
570 #endif
571 }
572
nrf_pwm_event_check(NRF_PWM_Type const * p_reg,nrf_pwm_event_t event)573 __STATIC_INLINE bool nrf_pwm_event_check(NRF_PWM_Type const * p_reg,
574 nrf_pwm_event_t event)
575 {
576 return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
577 }
578
nrf_pwm_event_address_get(NRF_PWM_Type const * p_reg,nrf_pwm_event_t event)579 __STATIC_INLINE uint32_t nrf_pwm_event_address_get(NRF_PWM_Type const * p_reg,
580 nrf_pwm_event_t event)
581 {
582 return ((uint32_t)p_reg + (uint32_t)event);
583 }
584
nrf_pwm_shorts_enable(NRF_PWM_Type * p_reg,uint32_t pwm_shorts_mask)585 __STATIC_INLINE void nrf_pwm_shorts_enable(NRF_PWM_Type * p_reg,
586 uint32_t pwm_shorts_mask)
587 {
588 p_reg->SHORTS |= pwm_shorts_mask;
589 }
590
nrf_pwm_shorts_disable(NRF_PWM_Type * p_reg,uint32_t pwm_shorts_mask)591 __STATIC_INLINE void nrf_pwm_shorts_disable(NRF_PWM_Type * p_reg,
592 uint32_t pwm_shorts_mask)
593 {
594 p_reg->SHORTS &= ~(pwm_shorts_mask);
595 }
596
nrf_pwm_shorts_set(NRF_PWM_Type * p_reg,uint32_t pwm_shorts_mask)597 __STATIC_INLINE void nrf_pwm_shorts_set(NRF_PWM_Type * p_reg,
598 uint32_t pwm_shorts_mask)
599 {
600 p_reg->SHORTS = pwm_shorts_mask;
601 }
602
nrf_pwm_int_enable(NRF_PWM_Type * p_reg,uint32_t pwm_int_mask)603 __STATIC_INLINE void nrf_pwm_int_enable(NRF_PWM_Type * p_reg,
604 uint32_t pwm_int_mask)
605 {
606 p_reg->INTENSET = pwm_int_mask;
607 }
608
nrf_pwm_int_disable(NRF_PWM_Type * p_reg,uint32_t pwm_int_mask)609 __STATIC_INLINE void nrf_pwm_int_disable(NRF_PWM_Type * p_reg,
610 uint32_t pwm_int_mask)
611 {
612 p_reg->INTENCLR = pwm_int_mask;
613 }
614
nrf_pwm_int_set(NRF_PWM_Type * p_reg,uint32_t pwm_int_mask)615 __STATIC_INLINE void nrf_pwm_int_set(NRF_PWM_Type * p_reg,
616 uint32_t pwm_int_mask)
617 {
618 p_reg->INTEN = pwm_int_mask;
619 }
620
nrf_pwm_int_enable_check(NRF_PWM_Type const * p_reg,nrf_pwm_int_mask_t pwm_int)621 __STATIC_INLINE bool nrf_pwm_int_enable_check(NRF_PWM_Type const * p_reg,
622 nrf_pwm_int_mask_t pwm_int)
623 {
624 return (bool)(p_reg->INTENSET & pwm_int);
625 }
626
627 #if defined(DPPI_PRESENT)
nrf_pwm_subscribe_set(NRF_PWM_Type * p_reg,nrf_pwm_task_t task,uint8_t channel)628 __STATIC_INLINE void nrf_pwm_subscribe_set(NRF_PWM_Type * p_reg,
629 nrf_pwm_task_t task,
630 uint8_t channel)
631 {
632 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
633 ((uint32_t)channel | PWM_SUBSCRIBE_STOP_EN_Msk);
634 }
635
nrf_pwm_subscribe_clear(NRF_PWM_Type * p_reg,nrf_pwm_task_t task)636 __STATIC_INLINE void nrf_pwm_subscribe_clear(NRF_PWM_Type * p_reg,
637 nrf_pwm_task_t task)
638 {
639 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
640 }
641
nrf_pwm_publish_set(NRF_PWM_Type * p_reg,nrf_pwm_event_t event,uint8_t channel)642 __STATIC_INLINE void nrf_pwm_publish_set(NRF_PWM_Type * p_reg,
643 nrf_pwm_event_t event,
644 uint8_t channel)
645 {
646 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
647 ((uint32_t)channel | PWM_PUBLISH_STOPPED_EN_Msk);
648 }
649
nrf_pwm_publish_clear(NRF_PWM_Type * p_reg,nrf_pwm_event_t event)650 __STATIC_INLINE void nrf_pwm_publish_clear(NRF_PWM_Type * p_reg,
651 nrf_pwm_event_t event)
652 {
653 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0;
654 }
655 #endif // defined(DPPI_PRESENT)
656
nrf_pwm_enable(NRF_PWM_Type * p_reg)657 __STATIC_INLINE void nrf_pwm_enable(NRF_PWM_Type * p_reg)
658 {
659 p_reg->ENABLE = (PWM_ENABLE_ENABLE_Enabled << PWM_ENABLE_ENABLE_Pos);
660 }
661
nrf_pwm_disable(NRF_PWM_Type * p_reg)662 __STATIC_INLINE void nrf_pwm_disable(NRF_PWM_Type * p_reg)
663 {
664 p_reg->ENABLE = (PWM_ENABLE_ENABLE_Disabled << PWM_ENABLE_ENABLE_Pos);
665 }
666
nrf_pwm_pins_set(NRF_PWM_Type * p_reg,uint32_t out_pins[NRF_PWM_CHANNEL_COUNT])667 __STATIC_INLINE void nrf_pwm_pins_set(NRF_PWM_Type * p_reg,
668 uint32_t out_pins[NRF_PWM_CHANNEL_COUNT])
669 {
670 uint8_t i;
671 for (i = 0; i < NRF_PWM_CHANNEL_COUNT; ++i)
672 {
673 p_reg->PSEL.OUT[i] = out_pins[i];
674 }
675 }
676
nrf_pwm_configure(NRF_PWM_Type * p_reg,nrf_pwm_clk_t base_clock,nrf_pwm_mode_t mode,uint16_t top_value)677 __STATIC_INLINE void nrf_pwm_configure(NRF_PWM_Type * p_reg,
678 nrf_pwm_clk_t base_clock,
679 nrf_pwm_mode_t mode,
680 uint16_t top_value)
681 {
682 NRFX_ASSERT(top_value <= PWM_COUNTERTOP_COUNTERTOP_Msk);
683
684 p_reg->PRESCALER = base_clock;
685 p_reg->MODE = mode;
686 p_reg->COUNTERTOP = top_value;
687 }
688
nrf_pwm_sequence_set(NRF_PWM_Type * p_reg,uint8_t seq_id,nrf_pwm_sequence_t const * p_seq)689 __STATIC_INLINE void nrf_pwm_sequence_set(NRF_PWM_Type * p_reg,
690 uint8_t seq_id,
691 nrf_pwm_sequence_t const * p_seq)
692 {
693 NRFX_ASSERT(p_seq != NULL);
694
695 nrf_pwm_seq_ptr_set( p_reg, seq_id, p_seq->values.p_raw);
696 nrf_pwm_seq_cnt_set( p_reg, seq_id, p_seq->length);
697 nrf_pwm_seq_refresh_set( p_reg, seq_id, p_seq->repeats);
698 nrf_pwm_seq_end_delay_set(p_reg, seq_id, p_seq->end_delay);
699 }
700
nrf_pwm_seq_ptr_set(NRF_PWM_Type * p_reg,uint8_t seq_id,uint16_t const * p_values)701 __STATIC_INLINE void nrf_pwm_seq_ptr_set(NRF_PWM_Type * p_reg,
702 uint8_t seq_id,
703 uint16_t const * p_values)
704 {
705 NRFX_ASSERT(seq_id <= 1);
706 NRFX_ASSERT(p_values != NULL);
707 p_reg->SEQ[seq_id].PTR = (uint32_t)p_values;
708 }
709
nrf_pwm_seq_cnt_set(NRF_PWM_Type * p_reg,uint8_t seq_id,uint16_t length)710 __STATIC_INLINE void nrf_pwm_seq_cnt_set(NRF_PWM_Type * p_reg,
711 uint8_t seq_id,
712 uint16_t length)
713 {
714 NRFX_ASSERT(seq_id <= 1);
715 NRFX_ASSERT(length != 0);
716 NRFX_ASSERT(length <= PWM_SEQ_CNT_CNT_Msk);
717 p_reg->SEQ[seq_id].CNT = length;
718 }
719
nrf_pwm_seq_refresh_set(NRF_PWM_Type * p_reg,uint8_t seq_id,uint32_t refresh)720 __STATIC_INLINE void nrf_pwm_seq_refresh_set(NRF_PWM_Type * p_reg,
721 uint8_t seq_id,
722 uint32_t refresh)
723 {
724 NRFX_ASSERT(seq_id <= 1);
725 NRFX_ASSERT(refresh <= PWM_SEQ_REFRESH_CNT_Msk);
726 p_reg->SEQ[seq_id].REFRESH = refresh;
727 }
728
nrf_pwm_seq_end_delay_set(NRF_PWM_Type * p_reg,uint8_t seq_id,uint32_t end_delay)729 __STATIC_INLINE void nrf_pwm_seq_end_delay_set(NRF_PWM_Type * p_reg,
730 uint8_t seq_id,
731 uint32_t end_delay)
732 {
733 NRFX_ASSERT(seq_id <= 1);
734 NRFX_ASSERT(end_delay <= PWM_SEQ_ENDDELAY_CNT_Msk);
735 p_reg->SEQ[seq_id].ENDDELAY = end_delay;
736 }
737
nrf_pwm_decoder_set(NRF_PWM_Type * p_reg,nrf_pwm_dec_load_t dec_load,nrf_pwm_dec_step_t dec_step)738 __STATIC_INLINE void nrf_pwm_decoder_set(NRF_PWM_Type * p_reg,
739 nrf_pwm_dec_load_t dec_load,
740 nrf_pwm_dec_step_t dec_step)
741 {
742 p_reg->DECODER = ((uint32_t)dec_load << PWM_DECODER_LOAD_Pos) |
743 ((uint32_t)dec_step << PWM_DECODER_MODE_Pos);
744 }
745
nrf_pwm_loop_set(NRF_PWM_Type * p_reg,uint16_t loop_count)746 __STATIC_INLINE void nrf_pwm_loop_set(NRF_PWM_Type * p_reg,
747 uint16_t loop_count)
748 {
749 p_reg->LOOP = loop_count;
750 }
751
752 #endif // SUPPRESS_INLINE_IMPLEMENTATION
753
754 /** @} */
755
756 #ifdef __cplusplus
757 }
758 #endif
759
760 #endif // NRF_PWM_H__
761
762