xref: /nrf52832-nimble/nordic/nrfx/hal/nrf_pwm.h (revision 150812a83cab50279bd772ef6db1bfaf255f2c5b)
1*150812a8SEvalZero /*
2*150812a8SEvalZero  * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
3*150812a8SEvalZero  * All rights reserved.
4*150812a8SEvalZero  *
5*150812a8SEvalZero  * Redistribution and use in source and binary forms, with or without
6*150812a8SEvalZero  * modification, are permitted provided that the following conditions are met:
7*150812a8SEvalZero  *
8*150812a8SEvalZero  * 1. Redistributions of source code must retain the above copyright notice, this
9*150812a8SEvalZero  *    list of conditions and the following disclaimer.
10*150812a8SEvalZero  *
11*150812a8SEvalZero  * 2. Redistributions in binary form must reproduce the above copyright
12*150812a8SEvalZero  *    notice, this list of conditions and the following disclaimer in the
13*150812a8SEvalZero  *    documentation and/or other materials provided with the distribution.
14*150812a8SEvalZero  *
15*150812a8SEvalZero  * 3. Neither the name of the copyright holder nor the names of its
16*150812a8SEvalZero  *    contributors may be used to endorse or promote products derived from this
17*150812a8SEvalZero  *    software without specific prior written permission.
18*150812a8SEvalZero  *
19*150812a8SEvalZero  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20*150812a8SEvalZero  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21*150812a8SEvalZero  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22*150812a8SEvalZero  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23*150812a8SEvalZero  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24*150812a8SEvalZero  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25*150812a8SEvalZero  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26*150812a8SEvalZero  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27*150812a8SEvalZero  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28*150812a8SEvalZero  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29*150812a8SEvalZero  * POSSIBILITY OF SUCH DAMAGE.
30*150812a8SEvalZero  */
31*150812a8SEvalZero 
32*150812a8SEvalZero #ifndef NRF_PWM_H__
33*150812a8SEvalZero #define NRF_PWM_H__
34*150812a8SEvalZero 
35*150812a8SEvalZero #include <nrfx.h>
36*150812a8SEvalZero 
37*150812a8SEvalZero #ifdef __cplusplus
38*150812a8SEvalZero extern "C" {
39*150812a8SEvalZero #endif
40*150812a8SEvalZero 
41*150812a8SEvalZero /**
42*150812a8SEvalZero  * @defgroup nrf_pwm_hal PWM HAL
43*150812a8SEvalZero  * @{
44*150812a8SEvalZero  * @ingroup nrf_pwm
45*150812a8SEvalZero  * @brief   Hardware access layer for managing the Pulse Width Modulation (PWM) peripheral.
46*150812a8SEvalZero  */
47*150812a8SEvalZero 
48*150812a8SEvalZero /**
49*150812a8SEvalZero  * @brief This value can be provided as a parameter for the @ref nrf_pwm_pins_set
50*150812a8SEvalZero  *        function call to specify that a given output channel shall not be
51*150812a8SEvalZero  *        connected to a physical pin.
52*150812a8SEvalZero  */
53*150812a8SEvalZero #define NRF_PWM_PIN_NOT_CONNECTED   0xFFFFFFFF
54*150812a8SEvalZero 
55*150812a8SEvalZero /**
56*150812a8SEvalZero  * @brief Number of channels in each Pointer to the peripheral registers structure.
57*150812a8SEvalZero  */
58*150812a8SEvalZero #define NRF_PWM_CHANNEL_COUNT   4
59*150812a8SEvalZero 
60*150812a8SEvalZero 
61*150812a8SEvalZero /**
62*150812a8SEvalZero  * @brief PWM tasks.
63*150812a8SEvalZero  */
64*150812a8SEvalZero typedef enum
65*150812a8SEvalZero {
66*150812a8SEvalZero     /*lint -save -e30*/
67*150812a8SEvalZero     NRF_PWM_TASK_STOP      = offsetof(NRF_PWM_Type, TASKS_STOP),        ///< Stops PWM pulse generation on all channels at the end of the current PWM period, and stops the sequence playback.
68*150812a8SEvalZero     NRF_PWM_TASK_SEQSTART0 = offsetof(NRF_PWM_Type, TASKS_SEQSTART[0]), ///< Starts playback of sequence 0.
69*150812a8SEvalZero     NRF_PWM_TASK_SEQSTART1 = offsetof(NRF_PWM_Type, TASKS_SEQSTART[1]), ///< Starts playback of sequence 1.
70*150812a8SEvalZero     NRF_PWM_TASK_NEXTSTEP  = offsetof(NRF_PWM_Type, TASKS_NEXTSTEP)     ///< Steps by one value in the current sequence if the decoder is set to @ref NRF_PWM_STEP_TRIGGERED mode.
71*150812a8SEvalZero     /*lint -restore*/
72*150812a8SEvalZero } nrf_pwm_task_t;
73*150812a8SEvalZero 
74*150812a8SEvalZero /**
75*150812a8SEvalZero  * @brief PWM events.
76*150812a8SEvalZero  */
77*150812a8SEvalZero typedef enum
78*150812a8SEvalZero {
79*150812a8SEvalZero     /*lint -save -e30*/
80*150812a8SEvalZero     NRF_PWM_EVENT_STOPPED      = offsetof(NRF_PWM_Type, EVENTS_STOPPED),       ///< Response to STOP task, emitted when PWM pulses are no longer generated.
81*150812a8SEvalZero     NRF_PWM_EVENT_SEQSTARTED0  = offsetof(NRF_PWM_Type, EVENTS_SEQSTARTED[0]), ///< First PWM period started on sequence 0.
82*150812a8SEvalZero     NRF_PWM_EVENT_SEQSTARTED1  = offsetof(NRF_PWM_Type, EVENTS_SEQSTARTED[1]), ///< First PWM period started on sequence 1.
83*150812a8SEvalZero     NRF_PWM_EVENT_SEQEND0      = offsetof(NRF_PWM_Type, EVENTS_SEQEND[0]),     ///< Emitted at the end of every sequence 0 when its last value has been read from RAM.
84*150812a8SEvalZero     NRF_PWM_EVENT_SEQEND1      = offsetof(NRF_PWM_Type, EVENTS_SEQEND[1]),     ///< Emitted at the end of every sequence 1 when its last value has been read from RAM.
85*150812a8SEvalZero     NRF_PWM_EVENT_PWMPERIODEND = offsetof(NRF_PWM_Type, EVENTS_PWMPERIODEND),  ///< Emitted at the end of each PWM period.
86*150812a8SEvalZero     NRF_PWM_EVENT_LOOPSDONE    = offsetof(NRF_PWM_Type, EVENTS_LOOPSDONE)      ///< Concatenated sequences have been played the requested number of times.
87*150812a8SEvalZero     /*lint -restore*/
88*150812a8SEvalZero } nrf_pwm_event_t;
89*150812a8SEvalZero 
90*150812a8SEvalZero /**
91*150812a8SEvalZero  * @brief PWM interrupts.
92*150812a8SEvalZero  */
93*150812a8SEvalZero typedef enum
94*150812a8SEvalZero {
95*150812a8SEvalZero     NRF_PWM_INT_STOPPED_MASK      = PWM_INTENSET_STOPPED_Msk,      ///< Interrupt on STOPPED event.
96*150812a8SEvalZero     NRF_PWM_INT_SEQSTARTED0_MASK  = PWM_INTENSET_SEQSTARTED0_Msk,  ///< Interrupt on SEQSTARTED[0] event.
97*150812a8SEvalZero     NRF_PWM_INT_SEQSTARTED1_MASK  = PWM_INTENSET_SEQSTARTED1_Msk,  ///< Interrupt on SEQSTARTED[1] event.
98*150812a8SEvalZero     NRF_PWM_INT_SEQEND0_MASK      = PWM_INTENSET_SEQEND0_Msk,      ///< Interrupt on SEQEND[0] event.
99*150812a8SEvalZero     NRF_PWM_INT_SEQEND1_MASK      = PWM_INTENSET_SEQEND1_Msk,      ///< Interrupt on SEQEND[1] event.
100*150812a8SEvalZero     NRF_PWM_INT_PWMPERIODEND_MASK = PWM_INTENSET_PWMPERIODEND_Msk, ///< Interrupt on PWMPERIODEND event.
101*150812a8SEvalZero     NRF_PWM_INT_LOOPSDONE_MASK    = PWM_INTENSET_LOOPSDONE_Msk     ///< Interrupt on LOOPSDONE event.
102*150812a8SEvalZero } nrf_pwm_int_mask_t;
103*150812a8SEvalZero 
104*150812a8SEvalZero /**
105*150812a8SEvalZero  * @brief PWM shortcuts.
106*150812a8SEvalZero  */
107*150812a8SEvalZero typedef enum
108*150812a8SEvalZero {
109*150812a8SEvalZero     NRF_PWM_SHORT_SEQEND0_STOP_MASK        = PWM_SHORTS_SEQEND0_STOP_Msk,        ///< Shortcut between SEQEND[0] event and STOP task.
110*150812a8SEvalZero     NRF_PWM_SHORT_SEQEND1_STOP_MASK        = PWM_SHORTS_SEQEND1_STOP_Msk,        ///< Shortcut between SEQEND[1] event and STOP task.
111*150812a8SEvalZero     NRF_PWM_SHORT_LOOPSDONE_SEQSTART0_MASK = PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk, ///< Shortcut between LOOPSDONE event and SEQSTART[0] task.
112*150812a8SEvalZero     NRF_PWM_SHORT_LOOPSDONE_SEQSTART1_MASK = PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk, ///< Shortcut between LOOPSDONE event and SEQSTART[1] task.
113*150812a8SEvalZero     NRF_PWM_SHORT_LOOPSDONE_STOP_MASK      = PWM_SHORTS_LOOPSDONE_STOP_Msk       ///< Shortcut between LOOPSDONE event and STOP task.
114*150812a8SEvalZero } nrf_pwm_short_mask_t;
115*150812a8SEvalZero 
116*150812a8SEvalZero /**
117*150812a8SEvalZero  * @brief PWM modes of operation.
118*150812a8SEvalZero  */
119*150812a8SEvalZero typedef enum
120*150812a8SEvalZero {
121*150812a8SEvalZero     NRF_PWM_MODE_UP          = PWM_MODE_UPDOWN_Up,        ///< Up counter (edge-aligned PWM duty cycle).
122*150812a8SEvalZero     NRF_PWM_MODE_UP_AND_DOWN = PWM_MODE_UPDOWN_UpAndDown, ///< Up and down counter (center-aligned PWM duty cycle).
123*150812a8SEvalZero } nrf_pwm_mode_t;
124*150812a8SEvalZero 
125*150812a8SEvalZero /**
126*150812a8SEvalZero  * @brief PWM base clock frequencies.
127*150812a8SEvalZero  */
128*150812a8SEvalZero typedef enum
129*150812a8SEvalZero {
130*150812a8SEvalZero     NRF_PWM_CLK_16MHz  = PWM_PRESCALER_PRESCALER_DIV_1,  ///< 16 MHz / 1 = 16 MHz.
131*150812a8SEvalZero     NRF_PWM_CLK_8MHz   = PWM_PRESCALER_PRESCALER_DIV_2,  ///< 16 MHz / 2 = 8 MHz.
132*150812a8SEvalZero     NRF_PWM_CLK_4MHz   = PWM_PRESCALER_PRESCALER_DIV_4,  ///< 16 MHz / 4 = 4 MHz.
133*150812a8SEvalZero     NRF_PWM_CLK_2MHz   = PWM_PRESCALER_PRESCALER_DIV_8,  ///< 16 MHz / 8 = 2 MHz.
134*150812a8SEvalZero     NRF_PWM_CLK_1MHz   = PWM_PRESCALER_PRESCALER_DIV_16, ///< 16 MHz / 16 = 1 MHz.
135*150812a8SEvalZero     NRF_PWM_CLK_500kHz = PWM_PRESCALER_PRESCALER_DIV_32, ///< 16 MHz / 32 = 500 kHz.
136*150812a8SEvalZero     NRF_PWM_CLK_250kHz = PWM_PRESCALER_PRESCALER_DIV_64, ///< 16 MHz / 64 = 250 kHz.
137*150812a8SEvalZero     NRF_PWM_CLK_125kHz = PWM_PRESCALER_PRESCALER_DIV_128 ///< 16 MHz / 128 = 125 kHz.
138*150812a8SEvalZero } nrf_pwm_clk_t;
139*150812a8SEvalZero 
140*150812a8SEvalZero /**
141*150812a8SEvalZero  * @brief PWM decoder load modes.
142*150812a8SEvalZero  *
143*150812a8SEvalZero  * The selected mode determines how the sequence data is read from RAM and
144*150812a8SEvalZero  * spread to the compare registers.
145*150812a8SEvalZero  */
146*150812a8SEvalZero typedef enum
147*150812a8SEvalZero {
148*150812a8SEvalZero     NRF_PWM_LOAD_COMMON     = PWM_DECODER_LOAD_Common,     ///< 1st half word (16-bit) used in all PWM channels (0-3).
149*150812a8SEvalZero     NRF_PWM_LOAD_GROUPED    = PWM_DECODER_LOAD_Grouped,    ///< 1st half word (16-bit) used in channels 0 and 1; 2nd word in channels 2 and 3.
150*150812a8SEvalZero     NRF_PWM_LOAD_INDIVIDUAL = PWM_DECODER_LOAD_Individual, ///< 1st half word (16-bit) used in channel 0; 2nd in channel 1; 3rd in channel 2; 4th in channel 3.
151*150812a8SEvalZero     NRF_PWM_LOAD_WAVE_FORM  = PWM_DECODER_LOAD_WaveForm    ///< 1st half word (16-bit) used in channel 0; 2nd in channel 1; ... ; 4th as the top value for the pulse generator counter.
152*150812a8SEvalZero } nrf_pwm_dec_load_t;
153*150812a8SEvalZero 
154*150812a8SEvalZero /**
155*150812a8SEvalZero  * @brief PWM decoder next step modes.
156*150812a8SEvalZero  *
157*150812a8SEvalZero  * The selected mode determines when the next value from the active sequence
158*150812a8SEvalZero  * is loaded.
159*150812a8SEvalZero  */
160*150812a8SEvalZero typedef enum
161*150812a8SEvalZero {
162*150812a8SEvalZero     NRF_PWM_STEP_AUTO      = PWM_DECODER_MODE_RefreshCount, ///< Automatically after the current value is played and repeated the requested number of times.
163*150812a8SEvalZero     NRF_PWM_STEP_TRIGGERED = PWM_DECODER_MODE_NextStep      ///< When the @ref NRF_PWM_TASK_NEXTSTEP task is triggered.
164*150812a8SEvalZero } nrf_pwm_dec_step_t;
165*150812a8SEvalZero 
166*150812a8SEvalZero 
167*150812a8SEvalZero /**
168*150812a8SEvalZero  * @brief Type used for defining duty cycle values for a sequence
169*150812a8SEvalZero  *        loaded in @ref NRF_PWM_LOAD_COMMON mode.
170*150812a8SEvalZero  */
171*150812a8SEvalZero typedef uint16_t nrf_pwm_values_common_t;
172*150812a8SEvalZero 
173*150812a8SEvalZero /**
174*150812a8SEvalZero  * @brief Structure for defining duty cycle values for a sequence
175*150812a8SEvalZero  *        loaded in @ref NRF_PWM_LOAD_GROUPED mode.
176*150812a8SEvalZero  */
177*150812a8SEvalZero typedef struct {
178*150812a8SEvalZero     uint16_t group_0; ///< Duty cycle value for group 0 (channels 0 and 1).
179*150812a8SEvalZero     uint16_t group_1; ///< Duty cycle value for group 1 (channels 2 and 3).
180*150812a8SEvalZero } nrf_pwm_values_grouped_t;
181*150812a8SEvalZero 
182*150812a8SEvalZero /**
183*150812a8SEvalZero  * @brief Structure for defining duty cycle values for a sequence
184*150812a8SEvalZero  *        loaded in @ref NRF_PWM_LOAD_INDIVIDUAL mode.
185*150812a8SEvalZero  */
186*150812a8SEvalZero typedef struct
187*150812a8SEvalZero {
188*150812a8SEvalZero     uint16_t channel_0; ///< Duty cycle value for channel 0.
189*150812a8SEvalZero     uint16_t channel_1; ///< Duty cycle value for channel 1.
190*150812a8SEvalZero     uint16_t channel_2; ///< Duty cycle value for channel 2.
191*150812a8SEvalZero     uint16_t channel_3; ///< Duty cycle value for channel 3.
192*150812a8SEvalZero } nrf_pwm_values_individual_t;
193*150812a8SEvalZero 
194*150812a8SEvalZero /**
195*150812a8SEvalZero  * @brief Structure for defining duty cycle values for a sequence
196*150812a8SEvalZero  *        loaded in @ref NRF_PWM_LOAD_WAVE_FORM mode.
197*150812a8SEvalZero  */
198*150812a8SEvalZero typedef struct {
199*150812a8SEvalZero     uint16_t channel_0;   ///< Duty cycle value for channel 0.
200*150812a8SEvalZero     uint16_t channel_1;   ///< Duty cycle value for channel 1.
201*150812a8SEvalZero     uint16_t channel_2;   ///< Duty cycle value for channel 2.
202*150812a8SEvalZero     uint16_t counter_top; ///< Top value for the pulse generator counter.
203*150812a8SEvalZero } nrf_pwm_values_wave_form_t;
204*150812a8SEvalZero 
205*150812a8SEvalZero /**
206*150812a8SEvalZero  * @brief Union grouping pointers to arrays of duty cycle values applicable to
207*150812a8SEvalZero  *        various loading modes.
208*150812a8SEvalZero  */
209*150812a8SEvalZero typedef union {
210*150812a8SEvalZero     nrf_pwm_values_common_t     const * p_common;     ///< Pointer to be used in @ref NRF_PWM_LOAD_COMMON mode.
211*150812a8SEvalZero     nrf_pwm_values_grouped_t    const * p_grouped;    ///< Pointer to be used in @ref NRF_PWM_LOAD_GROUPED mode.
212*150812a8SEvalZero     nrf_pwm_values_individual_t const * p_individual; ///< Pointer to be used in @ref NRF_PWM_LOAD_INDIVIDUAL mode.
213*150812a8SEvalZero     nrf_pwm_values_wave_form_t  const * p_wave_form;  ///< Pointer to be used in @ref NRF_PWM_LOAD_WAVE_FORM mode.
214*150812a8SEvalZero     uint16_t                    const * p_raw;        ///< Pointer providing raw access to the values.
215*150812a8SEvalZero } nrf_pwm_values_t;
216*150812a8SEvalZero 
217*150812a8SEvalZero /**
218*150812a8SEvalZero  * @brief Structure for defining a sequence of PWM duty cycles.
219*150812a8SEvalZero  *
220*150812a8SEvalZero  * When the sequence is set (by a call to @ref nrf_pwm_sequence_set), the
221*150812a8SEvalZero  * provided duty cycle values are not copied. The @p values pointer is stored
222*150812a8SEvalZero  * in the peripheral's internal register, and the values are loaded from RAM
223*150812a8SEvalZero  * during the sequence playback. Therefore, you must ensure that the values
224*150812a8SEvalZero  * do not change before and during the sequence playback (for example,
225*150812a8SEvalZero  * the values cannot be placed in a local variable that is allocated on stack).
226*150812a8SEvalZero  * If the sequence is played in a loop and the values should be updated
227*150812a8SEvalZero  * before the next iteration, it is safe to modify them when the corresponding
228*150812a8SEvalZero  * event signaling the end of sequence occurs (@ref NRF_PWM_EVENT_SEQEND0
229*150812a8SEvalZero  * or @ref NRF_PWM_EVENT_SEQEND1, respectively).
230*150812a8SEvalZero  *
231*150812a8SEvalZero  * @note The @p repeats and @p end_delay values (which are written to the
232*150812a8SEvalZero  *       SEQ[n].REFRESH and SEQ[n].ENDDELAY registers in the peripheral,
233*150812a8SEvalZero  *       respectively) are ignored at the end of a complex sequence
234*150812a8SEvalZero  *       playback, indicated by the LOOPSDONE event.
235*150812a8SEvalZero  *       See the @linkProductSpecification52 for more information.
236*150812a8SEvalZero  */
237*150812a8SEvalZero typedef struct
238*150812a8SEvalZero {
239*150812a8SEvalZero     nrf_pwm_values_t values; ///< Pointer to an array with duty cycle values. This array must be in Data RAM.
240*150812a8SEvalZero                              /**< This field is defined as an union of pointers
241*150812a8SEvalZero                               *   to provide a convenient way to define duty
242*150812a8SEvalZero                               *   cycle values in various loading modes
243*150812a8SEvalZero                               *   (see @ref nrf_pwm_dec_load_t).
244*150812a8SEvalZero                               *   In each value, the most significant bit (15)
245*150812a8SEvalZero                               *   determines the polarity of the output and the
246*150812a8SEvalZero                               *   others (14-0) compose the 15-bit value to be
247*150812a8SEvalZero                               *   compared with the pulse generator counter. */
248*150812a8SEvalZero     uint16_t length;    ///< Number of 16-bit values in the array pointed by @p values.
249*150812a8SEvalZero     uint32_t repeats;   ///< Number of times that each duty cycle should be repeated (after being played once). Ignored in @ref NRF_PWM_STEP_TRIGGERED mode.
250*150812a8SEvalZero     uint32_t end_delay; ///< Additional time (in PWM periods) that the last duty cycle is to be kept after the sequence is played. Ignored in @ref NRF_PWM_STEP_TRIGGERED mode.
251*150812a8SEvalZero } nrf_pwm_sequence_t;
252*150812a8SEvalZero 
253*150812a8SEvalZero /**
254*150812a8SEvalZero  * @brief Helper macro for calculating the number of 16-bit values in specified
255*150812a8SEvalZero  *        array of duty cycle values.
256*150812a8SEvalZero  */
257*150812a8SEvalZero #define NRF_PWM_VALUES_LENGTH(array)  (sizeof(array) / sizeof(uint16_t))
258*150812a8SEvalZero 
259*150812a8SEvalZero 
260*150812a8SEvalZero /**
261*150812a8SEvalZero  * @brief Function for activating a specific PWM task.
262*150812a8SEvalZero  *
263*150812a8SEvalZero  * @param[in] p_reg Pointer to the peripheral registers structure.
264*150812a8SEvalZero  * @param[in] task  Task to activate.
265*150812a8SEvalZero  */
266*150812a8SEvalZero __STATIC_INLINE void nrf_pwm_task_trigger(NRF_PWM_Type * p_reg,
267*150812a8SEvalZero                                           nrf_pwm_task_t task);
268*150812a8SEvalZero 
269*150812a8SEvalZero /**
270*150812a8SEvalZero  * @brief Function for getting the address of a specific PWM task register.
271*150812a8SEvalZero  *
272*150812a8SEvalZero  * @param[in] p_reg Pointer to the peripheral registers structure.
273*150812a8SEvalZero  * @param[in] task  Requested task.
274*150812a8SEvalZero  *
275*150812a8SEvalZero  * @return Address of the specified task register.
276*150812a8SEvalZero  */
277*150812a8SEvalZero __STATIC_INLINE uint32_t nrf_pwm_task_address_get(NRF_PWM_Type const * p_reg,
278*150812a8SEvalZero                                                   nrf_pwm_task_t task);
279*150812a8SEvalZero 
280*150812a8SEvalZero /**
281*150812a8SEvalZero  * @brief Function for clearing a specific PWM event.
282*150812a8SEvalZero  *
283*150812a8SEvalZero  * @param[in] p_reg Pointer to the peripheral registers structure.
284*150812a8SEvalZero  * @param[in] event Event to clear.
285*150812a8SEvalZero  */
286*150812a8SEvalZero __STATIC_INLINE void nrf_pwm_event_clear(NRF_PWM_Type * p_reg,
287*150812a8SEvalZero                                          nrf_pwm_event_t event);
288*150812a8SEvalZero 
289*150812a8SEvalZero /**
290*150812a8SEvalZero  * @brief Function for checking the state of a specific PWM event.
291*150812a8SEvalZero  *
292*150812a8SEvalZero  * @param[in] p_reg Pointer to the peripheral registers structure.
293*150812a8SEvalZero  * @param[in] event Event to check.
294*150812a8SEvalZero  *
295*150812a8SEvalZero  * @retval true  If the event is set.
296*150812a8SEvalZero  * @retval false If the event is not set.
297*150812a8SEvalZero  */
298*150812a8SEvalZero __STATIC_INLINE bool nrf_pwm_event_check(NRF_PWM_Type const * p_reg,
299*150812a8SEvalZero                                          nrf_pwm_event_t event);
300*150812a8SEvalZero 
301*150812a8SEvalZero /**
302*150812a8SEvalZero  * @brief Function for getting the address of a specific PWM event register.
303*150812a8SEvalZero  *
304*150812a8SEvalZero  * @param[in] p_reg Pointer to the peripheral registers structure.
305*150812a8SEvalZero  * @param[in] event Requested event.
306*150812a8SEvalZero  *
307*150812a8SEvalZero  * @return Address of the specified event register.
308*150812a8SEvalZero  */
309*150812a8SEvalZero __STATIC_INLINE uint32_t nrf_pwm_event_address_get(NRF_PWM_Type const * p_reg,
310*150812a8SEvalZero                                                    nrf_pwm_event_t event);
311*150812a8SEvalZero 
312*150812a8SEvalZero /**
313*150812a8SEvalZero  * @brief Function for enabling specified shortcuts.
314*150812a8SEvalZero  *
315*150812a8SEvalZero  * @param[in] p_reg           Pointer to the peripheral registers structure.
316*150812a8SEvalZero  * @param[in] pwm_shorts_mask Shortcuts to enable.
317*150812a8SEvalZero  */
318*150812a8SEvalZero __STATIC_INLINE void nrf_pwm_shorts_enable(NRF_PWM_Type * p_reg,
319*150812a8SEvalZero                                            uint32_t pwm_shorts_mask);
320*150812a8SEvalZero 
321*150812a8SEvalZero /**
322*150812a8SEvalZero  * @brief Function for disabling specified shortcuts.
323*150812a8SEvalZero  *
324*150812a8SEvalZero  * @param[in] p_reg           Pointer to the peripheral registers structure.
325*150812a8SEvalZero  * @param[in] pwm_shorts_mask Shortcuts to disable.
326*150812a8SEvalZero  */
327*150812a8SEvalZero __STATIC_INLINE void nrf_pwm_shorts_disable(NRF_PWM_Type * p_reg,
328*150812a8SEvalZero                                             uint32_t pwm_shorts_mask);
329*150812a8SEvalZero 
330*150812a8SEvalZero /**
331*150812a8SEvalZero  * @brief Function for setting the configuration of PWM shortcuts.
332*150812a8SEvalZero  *
333*150812a8SEvalZero  * @param[in] p_reg           Pointer to the peripheral registers structure.
334*150812a8SEvalZero  * @param[in] pwm_shorts_mask Shortcuts configuration to set.
335*150812a8SEvalZero  */
336*150812a8SEvalZero __STATIC_INLINE void nrf_pwm_shorts_set(NRF_PWM_Type * p_reg,
337*150812a8SEvalZero                                         uint32_t pwm_shorts_mask);
338*150812a8SEvalZero 
339*150812a8SEvalZero /**
340*150812a8SEvalZero  * @brief Function for enabling specified interrupts.
341*150812a8SEvalZero  *
342*150812a8SEvalZero  * @param[in] p_reg        Pointer to the peripheral registers structure.
343*150812a8SEvalZero  * @param[in] pwm_int_mask Interrupts to enable.
344*150812a8SEvalZero  */
345*150812a8SEvalZero __STATIC_INLINE void nrf_pwm_int_enable(NRF_PWM_Type * p_reg,
346*150812a8SEvalZero                                         uint32_t pwm_int_mask);
347*150812a8SEvalZero 
348*150812a8SEvalZero /**
349*150812a8SEvalZero  * @brief Function for disabling specified interrupts.
350*150812a8SEvalZero  *
351*150812a8SEvalZero  * @param[in] p_reg        Pointer to the peripheral registers structure.
352*150812a8SEvalZero  * @param[in] pwm_int_mask Interrupts to disable.
353*150812a8SEvalZero  */
354*150812a8SEvalZero __STATIC_INLINE void nrf_pwm_int_disable(NRF_PWM_Type * p_reg,
355*150812a8SEvalZero                                          uint32_t pwm_int_mask);
356*150812a8SEvalZero 
357*150812a8SEvalZero /**
358*150812a8SEvalZero  * @brief Function for setting the configuration of PWM interrupts.
359*150812a8SEvalZero  *
360*150812a8SEvalZero  * @param[in] p_reg        Pointer to the peripheral registers structure.
361*150812a8SEvalZero  * @param[in] pwm_int_mask Interrupts configuration to set.
362*150812a8SEvalZero  */
363*150812a8SEvalZero __STATIC_INLINE void nrf_pwm_int_set(NRF_PWM_Type * p_reg,
364*150812a8SEvalZero                                      uint32_t pwm_int_mask);
365*150812a8SEvalZero 
366*150812a8SEvalZero /**
367*150812a8SEvalZero  * @brief Function for retrieving the state of a given interrupt.
368*150812a8SEvalZero  *
369*150812a8SEvalZero  * @param[in] p_reg   Pointer to the peripheral registers structure.
370*150812a8SEvalZero  * @param[in] pwm_int Interrupt to check.
371*150812a8SEvalZero  *
372*150812a8SEvalZero  * @retval true  If the interrupt is enabled.
373*150812a8SEvalZero  * @retval false If the interrupt is not enabled.
374*150812a8SEvalZero  */
375*150812a8SEvalZero __STATIC_INLINE bool nrf_pwm_int_enable_check(NRF_PWM_Type const * p_reg,
376*150812a8SEvalZero                                               nrf_pwm_int_mask_t pwm_int);
377*150812a8SEvalZero 
378*150812a8SEvalZero #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
379*150812a8SEvalZero /**
380*150812a8SEvalZero  * @brief Function for setting the subscribe configuration for a given
381*150812a8SEvalZero  *        PWM task.
382*150812a8SEvalZero  *
383*150812a8SEvalZero  * @param[in] p_reg   Pointer to the structure of registers of the peripheral.
384*150812a8SEvalZero  * @param[in] task    Task for which to set the configuration.
385*150812a8SEvalZero  * @param[in] channel Channel through which to subscribe events.
386*150812a8SEvalZero  */
387*150812a8SEvalZero __STATIC_INLINE void nrf_pwm_subscribe_set(NRF_PWM_Type * p_reg,
388*150812a8SEvalZero                                            nrf_pwm_task_t task,
389*150812a8SEvalZero                                            uint8_t        channel);
390*150812a8SEvalZero 
391*150812a8SEvalZero /**
392*150812a8SEvalZero  * @brief Function for clearing the subscribe configuration for a given
393*150812a8SEvalZero  *        PWM task.
394*150812a8SEvalZero  *
395*150812a8SEvalZero  * @param[in] p_reg Pointer to the structure of registers of the peripheral.
396*150812a8SEvalZero  * @param[in] task  Task for which to clear the configuration.
397*150812a8SEvalZero  */
398*150812a8SEvalZero __STATIC_INLINE void nrf_pwm_subscribe_clear(NRF_PWM_Type * p_reg,
399*150812a8SEvalZero                                              nrf_pwm_task_t task);
400*150812a8SEvalZero 
401*150812a8SEvalZero /**
402*150812a8SEvalZero  * @brief Function for setting the publish configuration for a given
403*150812a8SEvalZero  *        PWM event.
404*150812a8SEvalZero  *
405*150812a8SEvalZero  * @param[in] p_reg   Pointer to the structure of registers of the peripheral.
406*150812a8SEvalZero  * @param[in] event   Event for which to set the configuration.
407*150812a8SEvalZero  * @param[in] channel Channel through which to publish the event.
408*150812a8SEvalZero  */
409*150812a8SEvalZero __STATIC_INLINE void nrf_pwm_publish_set(NRF_PWM_Type *  p_reg,
410*150812a8SEvalZero                                          nrf_pwm_event_t event,
411*150812a8SEvalZero                                          uint8_t         channel);
412*150812a8SEvalZero 
413*150812a8SEvalZero /**
414*150812a8SEvalZero  * @brief Function for clearing the publish configuration for a given
415*150812a8SEvalZero  *        PWM event.
416*150812a8SEvalZero  *
417*150812a8SEvalZero  * @param[in] p_reg Pointer to the structure of registers of the peripheral.
418*150812a8SEvalZero  * @param[in] event Event for which to clear the configuration.
419*150812a8SEvalZero  */
420*150812a8SEvalZero __STATIC_INLINE void nrf_pwm_publish_clear(NRF_PWM_Type *  p_reg,
421*150812a8SEvalZero                                            nrf_pwm_event_t event);
422*150812a8SEvalZero #endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
423*150812a8SEvalZero 
424*150812a8SEvalZero /**
425*150812a8SEvalZero  * @brief Function for enabling the PWM peripheral.
426*150812a8SEvalZero  *
427*150812a8SEvalZero  * @param[in] p_reg Pointer to the peripheral registers structure.
428*150812a8SEvalZero  */
429*150812a8SEvalZero __STATIC_INLINE void nrf_pwm_enable(NRF_PWM_Type * p_reg);
430*150812a8SEvalZero 
431*150812a8SEvalZero /**
432*150812a8SEvalZero  * @brief Function for disabling the PWM peripheral.
433*150812a8SEvalZero  *
434*150812a8SEvalZero  * @param[in] p_reg Pointer to the peripheral registers structure.
435*150812a8SEvalZero  */
436*150812a8SEvalZero __STATIC_INLINE void nrf_pwm_disable(NRF_PWM_Type * p_reg);
437*150812a8SEvalZero 
438*150812a8SEvalZero /**
439*150812a8SEvalZero  * @brief Function for assigning pins to PWM output channels.
440*150812a8SEvalZero  *
441*150812a8SEvalZero  * Usage of all PWM output channels is optional. If a given channel is not
442*150812a8SEvalZero  * needed, pass the @ref NRF_PWM_PIN_NOT_CONNECTED value instead of its pin
443*150812a8SEvalZero  * number.
444*150812a8SEvalZero  *
445*150812a8SEvalZero  * @param[in] p_reg    Pointer to the peripheral registers structure.
446*150812a8SEvalZero  * @param[in] out_pins Array with pin numbers for individual PWM output channels.
447*150812a8SEvalZero  */
448*150812a8SEvalZero __STATIC_INLINE void nrf_pwm_pins_set(NRF_PWM_Type * p_reg,
449*150812a8SEvalZero                                       uint32_t out_pins[NRF_PWM_CHANNEL_COUNT]);
450*150812a8SEvalZero 
451*150812a8SEvalZero /**
452*150812a8SEvalZero  * @brief Function for configuring the PWM peripheral.
453*150812a8SEvalZero  *
454*150812a8SEvalZero  * @param[in] p_reg      Pointer to the peripheral registers structure.
455*150812a8SEvalZero  * @param[in] base_clock Base clock frequency.
456*150812a8SEvalZero  * @param[in] mode       Operating mode of the pulse generator counter.
457*150812a8SEvalZero  * @param[in] top_value  Value up to which the pulse generator counter counts.
458*150812a8SEvalZero  */
459*150812a8SEvalZero __STATIC_INLINE void nrf_pwm_configure(NRF_PWM_Type * p_reg,
460*150812a8SEvalZero                                        nrf_pwm_clk_t  base_clock,
461*150812a8SEvalZero                                        nrf_pwm_mode_t mode,
462*150812a8SEvalZero                                        uint16_t       top_value);
463*150812a8SEvalZero 
464*150812a8SEvalZero /**
465*150812a8SEvalZero  * @brief Function for defining a sequence of PWM duty cycles.
466*150812a8SEvalZero  *
467*150812a8SEvalZero  * @param[in] p_reg  Pointer to the peripheral registers structure.
468*150812a8SEvalZero  * @param[in] seq_id Identifier of the sequence (0 or 1).
469*150812a8SEvalZero  * @param[in] p_seq  Pointer to the sequence definition.
470*150812a8SEvalZero  */
471*150812a8SEvalZero __STATIC_INLINE void nrf_pwm_sequence_set(NRF_PWM_Type * p_reg,
472*150812a8SEvalZero                                           uint8_t                    seq_id,
473*150812a8SEvalZero                                           nrf_pwm_sequence_t const * p_seq);
474*150812a8SEvalZero 
475*150812a8SEvalZero /**
476*150812a8SEvalZero  * @brief Function for modifying the pointer to the duty cycle values
477*150812a8SEvalZero  *        in the specified sequence.
478*150812a8SEvalZero  *
479*150812a8SEvalZero  * @param[in] p_reg    Pointer to the peripheral registers structure.
480*150812a8SEvalZero  * @param[in] seq_id   Identifier of the sequence (0 or 1).
481*150812a8SEvalZero  * @param[in] p_values Pointer to an array with duty cycle values.
482*150812a8SEvalZero  */
483*150812a8SEvalZero __STATIC_INLINE void nrf_pwm_seq_ptr_set(NRF_PWM_Type * p_reg,
484*150812a8SEvalZero                                          uint8_t          seq_id,
485*150812a8SEvalZero                                          uint16_t const * p_values);
486*150812a8SEvalZero 
487*150812a8SEvalZero /**
488*150812a8SEvalZero  * @brief Function for modifying the total number of duty cycle values
489*150812a8SEvalZero  *        in the specified sequence.
490*150812a8SEvalZero  *
491*150812a8SEvalZero  * @param[in] p_reg  Pointer to the peripheral registers structure.
492*150812a8SEvalZero  * @param[in] seq_id Identifier of the sequence (0 or 1).
493*150812a8SEvalZero  * @param[in] length Number of duty cycle values.
494*150812a8SEvalZero  */
495*150812a8SEvalZero __STATIC_INLINE void nrf_pwm_seq_cnt_set(NRF_PWM_Type * p_reg,
496*150812a8SEvalZero                                          uint8_t  seq_id,
497*150812a8SEvalZero                                          uint16_t length);
498*150812a8SEvalZero 
499*150812a8SEvalZero /**
500*150812a8SEvalZero  * @brief Function for modifying the additional number of PWM periods spent
501*150812a8SEvalZero  *        on each duty cycle value in the specified sequence.
502*150812a8SEvalZero  *
503*150812a8SEvalZero  * @param[in] p_reg   Pointer to the peripheral registers structure.
504*150812a8SEvalZero  * @param[in] seq_id  Identifier of the sequence (0 or 1).
505*150812a8SEvalZero  * @param[in] refresh Number of additional PWM periods for each duty cycle value.
506*150812a8SEvalZero  */
507*150812a8SEvalZero __STATIC_INLINE void nrf_pwm_seq_refresh_set(NRF_PWM_Type * p_reg,
508*150812a8SEvalZero                                              uint8_t  seq_id,
509*150812a8SEvalZero                                              uint32_t refresh);
510*150812a8SEvalZero 
511*150812a8SEvalZero /**
512*150812a8SEvalZero  * @brief Function for modifying the additional time added after the sequence
513*150812a8SEvalZero  *        is played.
514*150812a8SEvalZero  *
515*150812a8SEvalZero  * @param[in] p_reg     Pointer to the peripheral registers structure.
516*150812a8SEvalZero  * @param[in] seq_id    Identifier of the sequence (0 or 1).
517*150812a8SEvalZero  * @param[in] end_delay Number of PWM periods added at the end of the sequence.
518*150812a8SEvalZero  */
519*150812a8SEvalZero __STATIC_INLINE void nrf_pwm_seq_end_delay_set(NRF_PWM_Type * p_reg,
520*150812a8SEvalZero                                                uint8_t  seq_id,
521*150812a8SEvalZero                                                uint32_t end_delay);
522*150812a8SEvalZero 
523*150812a8SEvalZero /**
524*150812a8SEvalZero  * @brief Function for setting the mode of loading sequence data from RAM
525*150812a8SEvalZero  *        and advancing the sequence.
526*150812a8SEvalZero  *
527*150812a8SEvalZero  * @param[in] p_reg    Pointer to the peripheral registers structure.
528*150812a8SEvalZero  * @param[in] dec_load Mode of loading sequence data from RAM.
529*150812a8SEvalZero  * @param[in] dec_step Mode of advancing the active sequence.
530*150812a8SEvalZero  */
531*150812a8SEvalZero __STATIC_INLINE void nrf_pwm_decoder_set(NRF_PWM_Type * p_reg,
532*150812a8SEvalZero                                          nrf_pwm_dec_load_t dec_load,
533*150812a8SEvalZero                                          nrf_pwm_dec_step_t dec_step);
534*150812a8SEvalZero 
535*150812a8SEvalZero /**
536*150812a8SEvalZero  * @brief Function for setting the number of times the sequence playback
537*150812a8SEvalZero  *        should be performed.
538*150812a8SEvalZero  *
539*150812a8SEvalZero  * This function applies to two-sequence playback (concatenated sequence 0 and 1).
540*150812a8SEvalZero  * A single sequence can be played back only once.
541*150812a8SEvalZero  *
542*150812a8SEvalZero  * @param[in] p_reg      Pointer to the peripheral registers structure.
543*150812a8SEvalZero  * @param[in] loop_count Number of times to perform the sequence playback.
544*150812a8SEvalZero  */
545*150812a8SEvalZero __STATIC_INLINE void nrf_pwm_loop_set(NRF_PWM_Type * p_reg,
546*150812a8SEvalZero                                       uint16_t loop_count);
547*150812a8SEvalZero 
548*150812a8SEvalZero 
549*150812a8SEvalZero #ifndef SUPPRESS_INLINE_IMPLEMENTATION
550*150812a8SEvalZero 
nrf_pwm_task_trigger(NRF_PWM_Type * p_reg,nrf_pwm_task_t task)551*150812a8SEvalZero __STATIC_INLINE void nrf_pwm_task_trigger(NRF_PWM_Type * p_reg,
552*150812a8SEvalZero                                           nrf_pwm_task_t task)
553*150812a8SEvalZero {
554*150812a8SEvalZero     *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
555*150812a8SEvalZero }
556*150812a8SEvalZero 
nrf_pwm_task_address_get(NRF_PWM_Type const * p_reg,nrf_pwm_task_t task)557*150812a8SEvalZero __STATIC_INLINE uint32_t nrf_pwm_task_address_get(NRF_PWM_Type const * p_reg,
558*150812a8SEvalZero                                                   nrf_pwm_task_t task)
559*150812a8SEvalZero {
560*150812a8SEvalZero     return ((uint32_t)p_reg + (uint32_t)task);
561*150812a8SEvalZero }
562*150812a8SEvalZero 
nrf_pwm_event_clear(NRF_PWM_Type * p_reg,nrf_pwm_event_t event)563*150812a8SEvalZero __STATIC_INLINE void nrf_pwm_event_clear(NRF_PWM_Type * p_reg,
564*150812a8SEvalZero                                          nrf_pwm_event_t event)
565*150812a8SEvalZero {
566*150812a8SEvalZero     *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
567*150812a8SEvalZero #if __CORTEX_M == 0x04
568*150812a8SEvalZero     volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
569*150812a8SEvalZero     (void)dummy;
570*150812a8SEvalZero #endif
571*150812a8SEvalZero }
572*150812a8SEvalZero 
nrf_pwm_event_check(NRF_PWM_Type const * p_reg,nrf_pwm_event_t event)573*150812a8SEvalZero __STATIC_INLINE bool nrf_pwm_event_check(NRF_PWM_Type const * p_reg,
574*150812a8SEvalZero                                          nrf_pwm_event_t event)
575*150812a8SEvalZero {
576*150812a8SEvalZero     return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
577*150812a8SEvalZero }
578*150812a8SEvalZero 
nrf_pwm_event_address_get(NRF_PWM_Type const * p_reg,nrf_pwm_event_t event)579*150812a8SEvalZero __STATIC_INLINE uint32_t nrf_pwm_event_address_get(NRF_PWM_Type const * p_reg,
580*150812a8SEvalZero                                                    nrf_pwm_event_t event)
581*150812a8SEvalZero {
582*150812a8SEvalZero     return ((uint32_t)p_reg + (uint32_t)event);
583*150812a8SEvalZero }
584*150812a8SEvalZero 
nrf_pwm_shorts_enable(NRF_PWM_Type * p_reg,uint32_t pwm_shorts_mask)585*150812a8SEvalZero __STATIC_INLINE void nrf_pwm_shorts_enable(NRF_PWM_Type * p_reg,
586*150812a8SEvalZero                                            uint32_t pwm_shorts_mask)
587*150812a8SEvalZero {
588*150812a8SEvalZero     p_reg->SHORTS |= pwm_shorts_mask;
589*150812a8SEvalZero }
590*150812a8SEvalZero 
nrf_pwm_shorts_disable(NRF_PWM_Type * p_reg,uint32_t pwm_shorts_mask)591*150812a8SEvalZero __STATIC_INLINE void nrf_pwm_shorts_disable(NRF_PWM_Type * p_reg,
592*150812a8SEvalZero                                             uint32_t pwm_shorts_mask)
593*150812a8SEvalZero {
594*150812a8SEvalZero     p_reg->SHORTS &= ~(pwm_shorts_mask);
595*150812a8SEvalZero }
596*150812a8SEvalZero 
nrf_pwm_shorts_set(NRF_PWM_Type * p_reg,uint32_t pwm_shorts_mask)597*150812a8SEvalZero __STATIC_INLINE void nrf_pwm_shorts_set(NRF_PWM_Type * p_reg,
598*150812a8SEvalZero                                         uint32_t pwm_shorts_mask)
599*150812a8SEvalZero {
600*150812a8SEvalZero     p_reg->SHORTS = pwm_shorts_mask;
601*150812a8SEvalZero }
602*150812a8SEvalZero 
nrf_pwm_int_enable(NRF_PWM_Type * p_reg,uint32_t pwm_int_mask)603*150812a8SEvalZero __STATIC_INLINE void nrf_pwm_int_enable(NRF_PWM_Type * p_reg,
604*150812a8SEvalZero                                         uint32_t pwm_int_mask)
605*150812a8SEvalZero {
606*150812a8SEvalZero     p_reg->INTENSET = pwm_int_mask;
607*150812a8SEvalZero }
608*150812a8SEvalZero 
nrf_pwm_int_disable(NRF_PWM_Type * p_reg,uint32_t pwm_int_mask)609*150812a8SEvalZero __STATIC_INLINE void nrf_pwm_int_disable(NRF_PWM_Type * p_reg,
610*150812a8SEvalZero                                          uint32_t pwm_int_mask)
611*150812a8SEvalZero {
612*150812a8SEvalZero     p_reg->INTENCLR = pwm_int_mask;
613*150812a8SEvalZero }
614*150812a8SEvalZero 
nrf_pwm_int_set(NRF_PWM_Type * p_reg,uint32_t pwm_int_mask)615*150812a8SEvalZero __STATIC_INLINE void nrf_pwm_int_set(NRF_PWM_Type * p_reg,
616*150812a8SEvalZero                                      uint32_t pwm_int_mask)
617*150812a8SEvalZero {
618*150812a8SEvalZero     p_reg->INTEN = pwm_int_mask;
619*150812a8SEvalZero }
620*150812a8SEvalZero 
nrf_pwm_int_enable_check(NRF_PWM_Type const * p_reg,nrf_pwm_int_mask_t pwm_int)621*150812a8SEvalZero __STATIC_INLINE bool nrf_pwm_int_enable_check(NRF_PWM_Type const * p_reg,
622*150812a8SEvalZero                                               nrf_pwm_int_mask_t pwm_int)
623*150812a8SEvalZero {
624*150812a8SEvalZero     return (bool)(p_reg->INTENSET & pwm_int);
625*150812a8SEvalZero }
626*150812a8SEvalZero 
627*150812a8SEvalZero #if defined(DPPI_PRESENT)
nrf_pwm_subscribe_set(NRF_PWM_Type * p_reg,nrf_pwm_task_t task,uint8_t channel)628*150812a8SEvalZero __STATIC_INLINE void nrf_pwm_subscribe_set(NRF_PWM_Type * p_reg,
629*150812a8SEvalZero                                            nrf_pwm_task_t task,
630*150812a8SEvalZero                                            uint8_t        channel)
631*150812a8SEvalZero {
632*150812a8SEvalZero     *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
633*150812a8SEvalZero             ((uint32_t)channel | PWM_SUBSCRIBE_STOP_EN_Msk);
634*150812a8SEvalZero }
635*150812a8SEvalZero 
nrf_pwm_subscribe_clear(NRF_PWM_Type * p_reg,nrf_pwm_task_t task)636*150812a8SEvalZero __STATIC_INLINE void nrf_pwm_subscribe_clear(NRF_PWM_Type * p_reg,
637*150812a8SEvalZero                                              nrf_pwm_task_t task)
638*150812a8SEvalZero {
639*150812a8SEvalZero     *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
640*150812a8SEvalZero }
641*150812a8SEvalZero 
nrf_pwm_publish_set(NRF_PWM_Type * p_reg,nrf_pwm_event_t event,uint8_t channel)642*150812a8SEvalZero __STATIC_INLINE void nrf_pwm_publish_set(NRF_PWM_Type *  p_reg,
643*150812a8SEvalZero                                          nrf_pwm_event_t event,
644*150812a8SEvalZero                                          uint8_t         channel)
645*150812a8SEvalZero {
646*150812a8SEvalZero     *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
647*150812a8SEvalZero             ((uint32_t)channel | PWM_PUBLISH_STOPPED_EN_Msk);
648*150812a8SEvalZero }
649*150812a8SEvalZero 
nrf_pwm_publish_clear(NRF_PWM_Type * p_reg,nrf_pwm_event_t event)650*150812a8SEvalZero __STATIC_INLINE void nrf_pwm_publish_clear(NRF_PWM_Type *  p_reg,
651*150812a8SEvalZero                                            nrf_pwm_event_t event)
652*150812a8SEvalZero {
653*150812a8SEvalZero     *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0;
654*150812a8SEvalZero }
655*150812a8SEvalZero #endif // defined(DPPI_PRESENT)
656*150812a8SEvalZero 
nrf_pwm_enable(NRF_PWM_Type * p_reg)657*150812a8SEvalZero __STATIC_INLINE void nrf_pwm_enable(NRF_PWM_Type * p_reg)
658*150812a8SEvalZero {
659*150812a8SEvalZero     p_reg->ENABLE = (PWM_ENABLE_ENABLE_Enabled << PWM_ENABLE_ENABLE_Pos);
660*150812a8SEvalZero }
661*150812a8SEvalZero 
nrf_pwm_disable(NRF_PWM_Type * p_reg)662*150812a8SEvalZero __STATIC_INLINE void nrf_pwm_disable(NRF_PWM_Type * p_reg)
663*150812a8SEvalZero {
664*150812a8SEvalZero     p_reg->ENABLE = (PWM_ENABLE_ENABLE_Disabled << PWM_ENABLE_ENABLE_Pos);
665*150812a8SEvalZero }
666*150812a8SEvalZero 
nrf_pwm_pins_set(NRF_PWM_Type * p_reg,uint32_t out_pins[NRF_PWM_CHANNEL_COUNT])667*150812a8SEvalZero __STATIC_INLINE void nrf_pwm_pins_set(NRF_PWM_Type * p_reg,
668*150812a8SEvalZero                                       uint32_t out_pins[NRF_PWM_CHANNEL_COUNT])
669*150812a8SEvalZero {
670*150812a8SEvalZero     uint8_t i;
671*150812a8SEvalZero     for (i = 0; i < NRF_PWM_CHANNEL_COUNT; ++i)
672*150812a8SEvalZero     {
673*150812a8SEvalZero         p_reg->PSEL.OUT[i] = out_pins[i];
674*150812a8SEvalZero     }
675*150812a8SEvalZero }
676*150812a8SEvalZero 
nrf_pwm_configure(NRF_PWM_Type * p_reg,nrf_pwm_clk_t base_clock,nrf_pwm_mode_t mode,uint16_t top_value)677*150812a8SEvalZero __STATIC_INLINE void nrf_pwm_configure(NRF_PWM_Type * p_reg,
678*150812a8SEvalZero                                        nrf_pwm_clk_t  base_clock,
679*150812a8SEvalZero                                        nrf_pwm_mode_t mode,
680*150812a8SEvalZero                                        uint16_t       top_value)
681*150812a8SEvalZero {
682*150812a8SEvalZero     NRFX_ASSERT(top_value <= PWM_COUNTERTOP_COUNTERTOP_Msk);
683*150812a8SEvalZero 
684*150812a8SEvalZero     p_reg->PRESCALER  = base_clock;
685*150812a8SEvalZero     p_reg->MODE       = mode;
686*150812a8SEvalZero     p_reg->COUNTERTOP = top_value;
687*150812a8SEvalZero }
688*150812a8SEvalZero 
nrf_pwm_sequence_set(NRF_PWM_Type * p_reg,uint8_t seq_id,nrf_pwm_sequence_t const * p_seq)689*150812a8SEvalZero __STATIC_INLINE void nrf_pwm_sequence_set(NRF_PWM_Type * p_reg,
690*150812a8SEvalZero                                           uint8_t                    seq_id,
691*150812a8SEvalZero                                           nrf_pwm_sequence_t const * p_seq)
692*150812a8SEvalZero {
693*150812a8SEvalZero     NRFX_ASSERT(p_seq != NULL);
694*150812a8SEvalZero 
695*150812a8SEvalZero     nrf_pwm_seq_ptr_set(      p_reg, seq_id, p_seq->values.p_raw);
696*150812a8SEvalZero     nrf_pwm_seq_cnt_set(      p_reg, seq_id, p_seq->length);
697*150812a8SEvalZero     nrf_pwm_seq_refresh_set(  p_reg, seq_id, p_seq->repeats);
698*150812a8SEvalZero     nrf_pwm_seq_end_delay_set(p_reg, seq_id, p_seq->end_delay);
699*150812a8SEvalZero }
700*150812a8SEvalZero 
nrf_pwm_seq_ptr_set(NRF_PWM_Type * p_reg,uint8_t seq_id,uint16_t const * p_values)701*150812a8SEvalZero __STATIC_INLINE void nrf_pwm_seq_ptr_set(NRF_PWM_Type * p_reg,
702*150812a8SEvalZero                                          uint8_t          seq_id,
703*150812a8SEvalZero                                          uint16_t const * p_values)
704*150812a8SEvalZero {
705*150812a8SEvalZero     NRFX_ASSERT(seq_id <= 1);
706*150812a8SEvalZero     NRFX_ASSERT(p_values != NULL);
707*150812a8SEvalZero     p_reg->SEQ[seq_id].PTR = (uint32_t)p_values;
708*150812a8SEvalZero }
709*150812a8SEvalZero 
nrf_pwm_seq_cnt_set(NRF_PWM_Type * p_reg,uint8_t seq_id,uint16_t length)710*150812a8SEvalZero __STATIC_INLINE void nrf_pwm_seq_cnt_set(NRF_PWM_Type * p_reg,
711*150812a8SEvalZero                                          uint8_t  seq_id,
712*150812a8SEvalZero                                          uint16_t length)
713*150812a8SEvalZero {
714*150812a8SEvalZero     NRFX_ASSERT(seq_id <= 1);
715*150812a8SEvalZero     NRFX_ASSERT(length != 0);
716*150812a8SEvalZero     NRFX_ASSERT(length <= PWM_SEQ_CNT_CNT_Msk);
717*150812a8SEvalZero     p_reg->SEQ[seq_id].CNT = length;
718*150812a8SEvalZero }
719*150812a8SEvalZero 
nrf_pwm_seq_refresh_set(NRF_PWM_Type * p_reg,uint8_t seq_id,uint32_t refresh)720*150812a8SEvalZero __STATIC_INLINE void nrf_pwm_seq_refresh_set(NRF_PWM_Type * p_reg,
721*150812a8SEvalZero                                              uint8_t  seq_id,
722*150812a8SEvalZero                                              uint32_t refresh)
723*150812a8SEvalZero {
724*150812a8SEvalZero     NRFX_ASSERT(seq_id <= 1);
725*150812a8SEvalZero     NRFX_ASSERT(refresh <= PWM_SEQ_REFRESH_CNT_Msk);
726*150812a8SEvalZero     p_reg->SEQ[seq_id].REFRESH  = refresh;
727*150812a8SEvalZero }
728*150812a8SEvalZero 
nrf_pwm_seq_end_delay_set(NRF_PWM_Type * p_reg,uint8_t seq_id,uint32_t end_delay)729*150812a8SEvalZero __STATIC_INLINE void nrf_pwm_seq_end_delay_set(NRF_PWM_Type * p_reg,
730*150812a8SEvalZero                                                uint8_t  seq_id,
731*150812a8SEvalZero                                                uint32_t end_delay)
732*150812a8SEvalZero {
733*150812a8SEvalZero     NRFX_ASSERT(seq_id <= 1);
734*150812a8SEvalZero     NRFX_ASSERT(end_delay <= PWM_SEQ_ENDDELAY_CNT_Msk);
735*150812a8SEvalZero     p_reg->SEQ[seq_id].ENDDELAY = end_delay;
736*150812a8SEvalZero }
737*150812a8SEvalZero 
nrf_pwm_decoder_set(NRF_PWM_Type * p_reg,nrf_pwm_dec_load_t dec_load,nrf_pwm_dec_step_t dec_step)738*150812a8SEvalZero __STATIC_INLINE void nrf_pwm_decoder_set(NRF_PWM_Type * p_reg,
739*150812a8SEvalZero                                          nrf_pwm_dec_load_t dec_load,
740*150812a8SEvalZero                                          nrf_pwm_dec_step_t dec_step)
741*150812a8SEvalZero {
742*150812a8SEvalZero     p_reg->DECODER = ((uint32_t)dec_load << PWM_DECODER_LOAD_Pos) |
743*150812a8SEvalZero                      ((uint32_t)dec_step << PWM_DECODER_MODE_Pos);
744*150812a8SEvalZero }
745*150812a8SEvalZero 
nrf_pwm_loop_set(NRF_PWM_Type * p_reg,uint16_t loop_count)746*150812a8SEvalZero __STATIC_INLINE void nrf_pwm_loop_set(NRF_PWM_Type * p_reg,
747*150812a8SEvalZero                                       uint16_t loop_count)
748*150812a8SEvalZero {
749*150812a8SEvalZero     p_reg->LOOP = loop_count;
750*150812a8SEvalZero }
751*150812a8SEvalZero 
752*150812a8SEvalZero #endif // SUPPRESS_INLINE_IMPLEMENTATION
753*150812a8SEvalZero 
754*150812a8SEvalZero /** @} */
755*150812a8SEvalZero 
756*150812a8SEvalZero #ifdef __cplusplus
757*150812a8SEvalZero }
758*150812a8SEvalZero #endif
759*150812a8SEvalZero 
760*150812a8SEvalZero #endif // NRF_PWM_H__
761*150812a8SEvalZero 
762