1 /*
2 * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice, this
9 * list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the copyright holder nor the names of its
16 * contributors may be used to endorse or promote products derived from this
17 * software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #ifndef NRF_POWER_H__
33 #define NRF_POWER_H__
34
35 #include <nrfx.h>
36
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40
41 /**
42 * @defgroup nrf_power_hal POWER HAL
43 * @{
44 * @ingroup nrf_power
45 * @brief Hardware access layer for managing the POWER peripheral.
46 */
47
48 #if defined(POWER_INTENSET_SLEEPENTER_Msk) || defined(__NRFX_DOXYGEN__)
49 /** @brief Auxiliary definition to mark the fact that sleep events are present */
50 #define NRF_POWER_HAS_SLEEPEVT 1
51 #else
52 #define NRF_POWER_HAS_SLEEPEVT 0
53 #endif // defined(POWER_INTENSET_SLEEPENTER_Msk) || defined(__NRFX_DOXYGEN__)
54
55 #if defined(POWER_USBREGSTATUS_VBUSDETECT_Msk) || defined(__NRFX_DOXYGEN__)
56 /** @brief Auxiliary definition to mark the fact that power module manages USB regulator */
57 #define NRF_POWER_HAS_USBREG 1
58 #else
59 #define NRF_POWER_HAS_USBREG 0
60 #endif // defined(POWER_USBREGSTATUS_VBUSDETECT_Msk) || defined(__NRFX_DOXYGEN__)
61
62 #if defined(POWER_POFCON_THRESHOLDVDDH_Msk) || defined(__NRFX_DOXYGEN__)
63 /** @brief Auxiliary definition to mark the fact that VDDH is present */
64 #define NRF_POWER_HAS_VDDH 1
65 #else
66 #define NRF_POWER_HAS_VDDH 0
67 #endif // defined(POWER_POFCON_THRESHOLDVDDH_Msk) || defined(__NRFX_DOXYGEN__)
68
69 #if defined(POWER_DCDCEN_DCDCEN_Msk) || defined(__NRFX_DOXYGEN__)
70 /** @brief Auxiliary definition to mark the fact that DCDCEN is present */
71 #define NRF_POWER_HAS_DCDCEN 1
72 #else
73 #define NRF_POWER_HAS_DCDCEN 0
74 #endif
75
76 #if defined(POWER_POFCON_THRESHOLD_Msk) || defined(__NRFX_DOXYGEN__)
77 /** @brief Auxiliary definition to mark the fact that POFCON is present */
78 #define NRF_POWER_HAS_POFCON 1
79 #else
80 #define NRF_POWER_HAS_POFCON 0
81 #endif
82
83 /** @brief POWER tasks. */
84 typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
85 {
86 NRF_POWER_TASK_CONSTLAT = offsetof(NRF_POWER_Type, TASKS_CONSTLAT), /**< Enable constant latency mode */
87 NRF_POWER_TASK_LOWPWR = offsetof(NRF_POWER_Type, TASKS_LOWPWR ), /**< Enable low power mode (variable latency) */
88 } nrf_power_task_t; /*lint -restore */
89
90 /** @brief POWER events. */
91 typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
92 {
93 #if NRF_POWER_HAS_POFCON
94 NRF_POWER_EVENT_POFWARN = offsetof(NRF_POWER_Type, EVENTS_POFWARN ), /**< Power failure warning */
95 #endif
96 #if NRF_POWER_HAS_SLEEPEVT
97 NRF_POWER_EVENT_SLEEPENTER = offsetof(NRF_POWER_Type, EVENTS_SLEEPENTER ), /**< CPU entered WFI/WFE sleep */
98 NRF_POWER_EVENT_SLEEPEXIT = offsetof(NRF_POWER_Type, EVENTS_SLEEPEXIT ), /**< CPU exited WFI/WFE sleep */
99 #endif
100 #if NRF_POWER_HAS_USBREG
101 NRF_POWER_EVENT_USBDETECTED = offsetof(NRF_POWER_Type, EVENTS_USBDETECTED), /**< Voltage supply detected on VBUS */
102 NRF_POWER_EVENT_USBREMOVED = offsetof(NRF_POWER_Type, EVENTS_USBREMOVED ), /**< Voltage supply removed from VBUS */
103 NRF_POWER_EVENT_USBPWRRDY = offsetof(NRF_POWER_Type, EVENTS_USBPWRRDY ), /**< USB 3.3 V supply ready */
104 #endif
105 } nrf_power_event_t; /*lint -restore */
106
107 /** @brief POWER interrupts. */
108 typedef enum
109 {
110 #if NRF_POWER_HAS_POFCON
111 NRF_POWER_INT_POFWARN_MASK = POWER_INTENSET_POFWARN_Msk , /**< Write '1' to Enable interrupt for POFWARN event */
112 #endif
113 #if NRF_POWER_HAS_SLEEPEVT
114 NRF_POWER_INT_SLEEPENTER_MASK = POWER_INTENSET_SLEEPENTER_Msk , /**< Write '1' to Enable interrupt for SLEEPENTER event */
115 NRF_POWER_INT_SLEEPEXIT_MASK = POWER_INTENSET_SLEEPEXIT_Msk , /**< Write '1' to Enable interrupt for SLEEPEXIT event */
116 #endif
117 #if NRF_POWER_HAS_USBREG
118 NRF_POWER_INT_USBDETECTED_MASK = POWER_INTENSET_USBDETECTED_Msk, /**< Write '1' to Enable interrupt for USBDETECTED event */
119 NRF_POWER_INT_USBREMOVED_MASK = POWER_INTENSET_USBREMOVED_Msk , /**< Write '1' to Enable interrupt for USBREMOVED event */
120 NRF_POWER_INT_USBPWRRDY_MASK = POWER_INTENSET_USBPWRRDY_Msk , /**< Write '1' to Enable interrupt for USBPWRRDY event */
121 #endif
122 } nrf_power_int_mask_t;
123
124 /** @brief Reset reason. */
125 typedef enum
126 {
127 NRF_POWER_RESETREAS_RESETPIN_MASK = POWER_RESETREAS_RESETPIN_Msk, /*!< Bit mask of RESETPIN field. *///!< NRF_POWER_RESETREAS_RESETPIN_MASK
128 NRF_POWER_RESETREAS_DOG_MASK = POWER_RESETREAS_DOG_Msk , /*!< Bit mask of DOG field. */ //!< NRF_POWER_RESETREAS_DOG_MASK
129 NRF_POWER_RESETREAS_SREQ_MASK = POWER_RESETREAS_SREQ_Msk , /*!< Bit mask of SREQ field. */ //!< NRF_POWER_RESETREAS_SREQ_MASK
130 NRF_POWER_RESETREAS_LOCKUP_MASK = POWER_RESETREAS_LOCKUP_Msk , /*!< Bit mask of LOCKUP field. */ //!< NRF_POWER_RESETREAS_LOCKUP_MASK
131 NRF_POWER_RESETREAS_OFF_MASK = POWER_RESETREAS_OFF_Msk , /*!< Bit mask of OFF field. */ //!< NRF_POWER_RESETREAS_OFF_MASK
132 #if defined(POWER_RESETREAS_LPCOMP_Msk) || defined(__NRFX_DOXYGEN__)
133 NRF_POWER_RESETREAS_LPCOMP_MASK = POWER_RESETREAS_LPCOMP_Msk , /*!< Bit mask of LPCOMP field. */ //!< NRF_POWER_RESETREAS_LPCOMP_MASK
134 #endif
135 NRF_POWER_RESETREAS_DIF_MASK = POWER_RESETREAS_DIF_Msk , /*!< Bit mask of DIF field. */ //!< NRF_POWER_RESETREAS_DIF_MASK
136 #if defined(POWER_RESETREAS_NFC_Msk) || defined(__NRFX_DOXYGEN__)
137 NRF_POWER_RESETREAS_NFC_MASK = POWER_RESETREAS_NFC_Msk , /*!< Bit mask of NFC field. */
138 #endif
139 #if defined(POWER_RESETREAS_VBUS_Msk) || defined(__NRFX_DOXYGEN__)
140 NRF_POWER_RESETREAS_VBUS_MASK = POWER_RESETREAS_VBUS_Msk , /*!< Bit mask of VBUS field. */
141 #endif
142 } nrf_power_resetreas_mask_t;
143
144 #if NRF_POWER_HAS_USBREG
145 /**
146 * @brief USBREGSTATUS register bit masks
147 *
148 * @sa nrf_power_usbregstatus_get
149 */
150 typedef enum
151 {
152 NRF_POWER_USBREGSTATUS_VBUSDETECT_MASK = POWER_USBREGSTATUS_VBUSDETECT_Msk, /**< USB detected or removed */
153 NRF_POWER_USBREGSTATUS_OUTPUTRDY_MASK = POWER_USBREGSTATUS_OUTPUTRDY_Msk /**< USB 3.3 V supply ready */
154 } nrf_power_usbregstatus_mask_t;
155 #endif // NRF_POWER_HAS_USBREG
156
157 #if defined(POWER_RAMSTATUS_RAMBLOCK0_Msk) || defined(__NRFX_DOXYGEN__)
158 /**
159 * @brief RAM blocks numbers
160 *
161 * @sa nrf_power_ramblock_mask_t
162 * @note
163 * Ram blocks has to been used in nrf51.
164 * In new CPU ram is divided into segments and this functionality is depreciated.
165 * For the newer MCU see the PS for mapping between internal RAM and RAM blocks,
166 * because this mapping is not 1:1, and functions related to old style blocks
167 * should not be used.
168 */
169 typedef enum
170 {
171 NRF_POWER_RAMBLOCK0 = POWER_RAMSTATUS_RAMBLOCK0_Pos,
172 NRF_POWER_RAMBLOCK1 = POWER_RAMSTATUS_RAMBLOCK1_Pos,
173 NRF_POWER_RAMBLOCK2 = POWER_RAMSTATUS_RAMBLOCK2_Pos,
174 NRF_POWER_RAMBLOCK3 = POWER_RAMSTATUS_RAMBLOCK3_Pos
175 } nrf_power_ramblock_t;
176
177 /**
178 * @brief RAM blocks masks
179 *
180 * @sa nrf_power_ramblock_t
181 */
182 typedef enum
183 {
184 NRF_POWER_RAMBLOCK0_MASK = POWER_RAMSTATUS_RAMBLOCK0_Msk,
185 NRF_POWER_RAMBLOCK1_MASK = POWER_RAMSTATUS_RAMBLOCK1_Msk,
186 NRF_POWER_RAMBLOCK2_MASK = POWER_RAMSTATUS_RAMBLOCK2_Msk,
187 NRF_POWER_RAMBLOCK3_MASK = POWER_RAMSTATUS_RAMBLOCK3_Msk
188 } nrf_power_ramblock_mask_t;
189 #endif // defined(POWER_RAMSTATUS_RAMBLOCK0_Msk) || defined(__NRFX_DOXYGEN__)
190
191 /**
192 * @brief RAM power state position of the bits
193 *
194 * @sa nrf_power_onoffram_mask_t
195 */
196 typedef enum
197 {
198 NRF_POWER_ONRAM0, /**< Keep RAM block 0 on or off in system ON Mode */
199 NRF_POWER_OFFRAM0, /**< Keep retention on RAM block 0 when RAM block is switched off */
200 NRF_POWER_ONRAM1, /**< Keep RAM block 1 on or off in system ON Mode */
201 NRF_POWER_OFFRAM1, /**< Keep retention on RAM block 1 when RAM block is switched off */
202 NRF_POWER_ONRAM2, /**< Keep RAM block 2 on or off in system ON Mode */
203 NRF_POWER_OFFRAM2, /**< Keep retention on RAM block 2 when RAM block is switched off */
204 NRF_POWER_ONRAM3, /**< Keep RAM block 3 on or off in system ON Mode */
205 NRF_POWER_OFFRAM3, /**< Keep retention on RAM block 3 when RAM block is switched off */
206 } nrf_power_onoffram_t;
207
208 /**
209 * @brief RAM power state bit masks
210 *
211 * @sa nrf_power_onoffram_t
212 */
213 typedef enum
214 {
215 NRF_POWER_ONRAM0_MASK = 1U << NRF_POWER_ONRAM0, /**< Keep RAM block 0 on or off in system ON Mode */
216 NRF_POWER_OFFRAM0_MASK = 1U << NRF_POWER_OFFRAM0, /**< Keep retention on RAM block 0 when RAM block is switched off */
217 NRF_POWER_ONRAM1_MASK = 1U << NRF_POWER_ONRAM1, /**< Keep RAM block 1 on or off in system ON Mode */
218 NRF_POWER_OFFRAM1_MASK = 1U << NRF_POWER_OFFRAM1, /**< Keep retention on RAM block 1 when RAM block is switched off */
219 NRF_POWER_ONRAM2_MASK = 1U << NRF_POWER_ONRAM2, /**< Keep RAM block 2 on or off in system ON Mode */
220 NRF_POWER_OFFRAM2_MASK = 1U << NRF_POWER_OFFRAM2, /**< Keep retention on RAM block 2 when RAM block is switched off */
221 NRF_POWER_ONRAM3_MASK = 1U << NRF_POWER_ONRAM3, /**< Keep RAM block 3 on or off in system ON Mode */
222 NRF_POWER_OFFRAM3_MASK = 1U << NRF_POWER_OFFRAM3, /**< Keep retention on RAM block 3 when RAM block is switched off */
223 } nrf_power_onoffram_mask_t;
224
225 #if NRF_POWER_HAS_POFCON
226 /** @brief Power failure comparator thresholds. */
227 typedef enum
228 {
229 NRF_POWER_POFTHR_V21 = POWER_POFCON_THRESHOLD_V21, /**< Set threshold to 2.1 V */
230 NRF_POWER_POFTHR_V23 = POWER_POFCON_THRESHOLD_V23, /**< Set threshold to 2.3 V */
231 NRF_POWER_POFTHR_V25 = POWER_POFCON_THRESHOLD_V25, /**< Set threshold to 2.5 V */
232 NRF_POWER_POFTHR_V27 = POWER_POFCON_THRESHOLD_V27, /**< Set threshold to 2.7 V */
233 #if defined(POWER_POFCON_THRESHOLD_V17) || defined(__NRFX_DOXYGEN__)
234 NRF_POWER_POFTHR_V17 = POWER_POFCON_THRESHOLD_V17, /**< Set threshold to 1.7 V */
235 NRF_POWER_POFTHR_V18 = POWER_POFCON_THRESHOLD_V18, /**< Set threshold to 1.8 V */
236 NRF_POWER_POFTHR_V19 = POWER_POFCON_THRESHOLD_V19, /**< Set threshold to 1.9 V */
237 NRF_POWER_POFTHR_V20 = POWER_POFCON_THRESHOLD_V20, /**< Set threshold to 2.0 V */
238 NRF_POWER_POFTHR_V22 = POWER_POFCON_THRESHOLD_V22, /**< Set threshold to 2.2 V */
239 NRF_POWER_POFTHR_V24 = POWER_POFCON_THRESHOLD_V24, /**< Set threshold to 2.4 V */
240 NRF_POWER_POFTHR_V26 = POWER_POFCON_THRESHOLD_V26, /**< Set threshold to 2.6 V */
241 NRF_POWER_POFTHR_V28 = POWER_POFCON_THRESHOLD_V28, /**< Set threshold to 2.8 V */
242 #endif // defined(POWER_POFCON_THRESHOLD_V17) || defined(__NRFX_DOXYGEN__)
243 } nrf_power_pof_thr_t;
244 #endif // NRF_POWER_HAS_POFCON
245
246 #if NRF_POWER_HAS_VDDH
247 /** @brief Power failure comparator thresholds for VDDH. */
248 typedef enum
249 {
250 NRF_POWER_POFTHRVDDH_V27 = POWER_POFCON_THRESHOLDVDDH_V27, /**< Set threshold to 2.7 V */
251 NRF_POWER_POFTHRVDDH_V28 = POWER_POFCON_THRESHOLDVDDH_V28, /**< Set threshold to 2.8 V */
252 NRF_POWER_POFTHRVDDH_V29 = POWER_POFCON_THRESHOLDVDDH_V29, /**< Set threshold to 2.9 V */
253 NRF_POWER_POFTHRVDDH_V30 = POWER_POFCON_THRESHOLDVDDH_V30, /**< Set threshold to 3.0 V */
254 NRF_POWER_POFTHRVDDH_V31 = POWER_POFCON_THRESHOLDVDDH_V31, /**< Set threshold to 3.1 V */
255 NRF_POWER_POFTHRVDDH_V32 = POWER_POFCON_THRESHOLDVDDH_V32, /**< Set threshold to 3.2 V */
256 NRF_POWER_POFTHRVDDH_V33 = POWER_POFCON_THRESHOLDVDDH_V33, /**< Set threshold to 3.3 V */
257 NRF_POWER_POFTHRVDDH_V34 = POWER_POFCON_THRESHOLDVDDH_V34, /**< Set threshold to 3.4 V */
258 NRF_POWER_POFTHRVDDH_V35 = POWER_POFCON_THRESHOLDVDDH_V35, /**< Set threshold to 3.5 V */
259 NRF_POWER_POFTHRVDDH_V36 = POWER_POFCON_THRESHOLDVDDH_V36, /**< Set threshold to 3.6 V */
260 NRF_POWER_POFTHRVDDH_V37 = POWER_POFCON_THRESHOLDVDDH_V37, /**< Set threshold to 3.7 V */
261 NRF_POWER_POFTHRVDDH_V38 = POWER_POFCON_THRESHOLDVDDH_V38, /**< Set threshold to 3.8 V */
262 NRF_POWER_POFTHRVDDH_V39 = POWER_POFCON_THRESHOLDVDDH_V39, /**< Set threshold to 3.9 V */
263 NRF_POWER_POFTHRVDDH_V40 = POWER_POFCON_THRESHOLDVDDH_V40, /**< Set threshold to 4.0 V */
264 NRF_POWER_POFTHRVDDH_V41 = POWER_POFCON_THRESHOLDVDDH_V41, /**< Set threshold to 4.1 V */
265 NRF_POWER_POFTHRVDDH_V42 = POWER_POFCON_THRESHOLDVDDH_V42, /**< Set threshold to 4.2 V */
266 } nrf_power_pof_thrvddh_t;
267
268 /** @brief Main regulator status. */
269 typedef enum
270 {
271 NRF_POWER_MAINREGSTATUS_NORMAL = POWER_MAINREGSTATUS_MAINREGSTATUS_Normal, /**< Normal voltage mode. Voltage supplied on VDD. */
272 NRF_POWER_MAINREGSTATUS_HIGH = POWER_MAINREGSTATUS_MAINREGSTATUS_High /**< High voltage mode. Voltage supplied on VDDH. */
273 } nrf_power_mainregstatus_t;
274
275 #endif // NRF_POWER_HAS_VDDH
276
277 #if defined(POWER_RAM_POWER_S0POWER_Msk) || defined(__NRFX_DOXYGEN__)
278 /**
279 * @brief Bit positions for RAMPOWER register
280 *
281 * All possible bits described, even if they are not used in selected MCU.
282 */
283 typedef enum
284 {
285 /** Keep RAM section S0 ON in System ON mode */
286 NRF_POWER_RAMPOWER_S0POWER = POWER_RAM_POWER_S0POWER_Pos,
287 NRF_POWER_RAMPOWER_S1POWER, /**< Keep RAM section S1 ON in System ON mode */
288 NRF_POWER_RAMPOWER_S2POWER, /**< Keep RAM section S2 ON in System ON mode */
289 NRF_POWER_RAMPOWER_S3POWER, /**< Keep RAM section S3 ON in System ON mode */
290 NRF_POWER_RAMPOWER_S4POWER, /**< Keep RAM section S4 ON in System ON mode */
291 NRF_POWER_RAMPOWER_S5POWER, /**< Keep RAM section S5 ON in System ON mode */
292 NRF_POWER_RAMPOWER_S6POWER, /**< Keep RAM section S6 ON in System ON mode */
293 NRF_POWER_RAMPOWER_S7POWER, /**< Keep RAM section S7 ON in System ON mode */
294 NRF_POWER_RAMPOWER_S8POWER, /**< Keep RAM section S8 ON in System ON mode */
295 NRF_POWER_RAMPOWER_S9POWER, /**< Keep RAM section S9 ON in System ON mode */
296 NRF_POWER_RAMPOWER_S10POWER, /**< Keep RAM section S10 ON in System ON mode */
297 NRF_POWER_RAMPOWER_S11POWER, /**< Keep RAM section S11 ON in System ON mode */
298 NRF_POWER_RAMPOWER_S12POWER, /**< Keep RAM section S12 ON in System ON mode */
299 NRF_POWER_RAMPOWER_S13POWER, /**< Keep RAM section S13 ON in System ON mode */
300 NRF_POWER_RAMPOWER_S14POWER, /**< Keep RAM section S14 ON in System ON mode */
301 NRF_POWER_RAMPOWER_S15POWER, /**< Keep RAM section S15 ON in System ON mode */
302
303 /** Keep section retention in OFF mode when section is OFF */
304 NRF_POWER_RAMPOWER_S0RETENTION = POWER_RAM_POWER_S0RETENTION_Pos,
305 NRF_POWER_RAMPOWER_S1RETENTION, /**< Keep section retention in OFF mode when section is OFF */
306 NRF_POWER_RAMPOWER_S2RETENTION, /**< Keep section retention in OFF mode when section is OFF */
307 NRF_POWER_RAMPOWER_S3RETENTION, /**< Keep section retention in OFF mode when section is OFF */
308 NRF_POWER_RAMPOWER_S4RETENTION, /**< Keep section retention in OFF mode when section is OFF */
309 NRF_POWER_RAMPOWER_S5RETENTION, /**< Keep section retention in OFF mode when section is OFF */
310 NRF_POWER_RAMPOWER_S6RETENTION, /**< Keep section retention in OFF mode when section is OFF */
311 NRF_POWER_RAMPOWER_S7RETENTION, /**< Keep section retention in OFF mode when section is OFF */
312 NRF_POWER_RAMPOWER_S8RETENTION, /**< Keep section retention in OFF mode when section is OFF */
313 NRF_POWER_RAMPOWER_S9RETENTION, /**< Keep section retention in OFF mode when section is OFF */
314 NRF_POWER_RAMPOWER_S10RETENTION, /**< Keep section retention in OFF mode when section is OFF */
315 NRF_POWER_RAMPOWER_S11RETENTION, /**< Keep section retention in OFF mode when section is OFF */
316 NRF_POWER_RAMPOWER_S12RETENTION, /**< Keep section retention in OFF mode when section is OFF */
317 NRF_POWER_RAMPOWER_S13RETENTION, /**< Keep section retention in OFF mode when section is OFF */
318 NRF_POWER_RAMPOWER_S14RETENTION, /**< Keep section retention in OFF mode when section is OFF */
319 NRF_POWER_RAMPOWER_S15RETENTION, /**< Keep section retention in OFF mode when section is OFF */
320 } nrf_power_rampower_t;
321
322 /**
323 * @brief Bit masks for RAMPOWER register
324 *
325 * All possible bits described, even if they are not used in selected MCU.
326 */
327 typedef enum
328 {
329 NRF_POWER_RAMPOWER_S0POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S0POWER ,
330 NRF_POWER_RAMPOWER_S1POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S1POWER ,
331 NRF_POWER_RAMPOWER_S2POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S2POWER ,
332 NRF_POWER_RAMPOWER_S3POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S3POWER ,
333 NRF_POWER_RAMPOWER_S4POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S4POWER ,
334 NRF_POWER_RAMPOWER_S5POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S5POWER ,
335 NRF_POWER_RAMPOWER_S7POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S7POWER ,
336 NRF_POWER_RAMPOWER_S8POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S8POWER ,
337 NRF_POWER_RAMPOWER_S9POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S9POWER ,
338 NRF_POWER_RAMPOWER_S10POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S10POWER,
339 NRF_POWER_RAMPOWER_S11POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S11POWER,
340 NRF_POWER_RAMPOWER_S12POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S12POWER,
341 NRF_POWER_RAMPOWER_S13POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S13POWER,
342 NRF_POWER_RAMPOWER_S14POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S14POWER,
343 NRF_POWER_RAMPOWER_S15POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S15POWER,
344
345 NRF_POWER_RAMPOWER_S0RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S0RETENTION ,
346 NRF_POWER_RAMPOWER_S1RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S1RETENTION ,
347 NRF_POWER_RAMPOWER_S2RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S2RETENTION ,
348 NRF_POWER_RAMPOWER_S3RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S3RETENTION ,
349 NRF_POWER_RAMPOWER_S4RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S4RETENTION ,
350 NRF_POWER_RAMPOWER_S5RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S5RETENTION ,
351 NRF_POWER_RAMPOWER_S7RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S7RETENTION ,
352 NRF_POWER_RAMPOWER_S8RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S8RETENTION ,
353 NRF_POWER_RAMPOWER_S9RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S9RETENTION ,
354 NRF_POWER_RAMPOWER_S10RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S10RETENTION,
355 NRF_POWER_RAMPOWER_S11RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S11RETENTION,
356 NRF_POWER_RAMPOWER_S12RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S12RETENTION,
357 NRF_POWER_RAMPOWER_S13RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S13RETENTION,
358 NRF_POWER_RAMPOWER_S14RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S14RETENTION,
359 NRF_POWER_RAMPOWER_S15RETENTION_MASK = (int)(1UL << NRF_POWER_RAMPOWER_S15RETENTION),
360 } nrf_power_rampower_mask_t;
361 #endif // defined(POWER_RAM_POWER_S0POWER_Msk) || defined(__NRFX_DOXYGEN__)
362
363 /**
364 * @brief Function for activating a specific POWER task.
365 *
366 * @param[in] task Task.
367 */
368 __STATIC_INLINE void nrf_power_task_trigger(nrf_power_task_t task);
369
370 /**
371 * @brief Function for returning the address of a specific POWER task register.
372 *
373 * @param[in] task Task.
374 *
375 * @return Task address.
376 */
377 __STATIC_INLINE uint32_t nrf_power_task_address_get(nrf_power_task_t task);
378
379 /**
380 * @brief Function for clearing a specific event.
381 *
382 * @param[in] event Event.
383 */
384 __STATIC_INLINE void nrf_power_event_clear(nrf_power_event_t event);
385
386 /**
387 * @brief Function for returning the state of a specific event.
388 *
389 * @param[in] event Event.
390 *
391 * @retval true If the event is set.
392 * @retval false If the event is not set.
393 */
394 __STATIC_INLINE bool nrf_power_event_check(nrf_power_event_t event);
395
396 /**
397 * @brief Function for getting and clearing the state of specific event
398 *
399 * This function checks the state of the event and clears it.
400 *
401 * @param[in] event Event.
402 *
403 * @retval true If the event was set.
404 * @retval false If the event was not set.
405 */
406 __STATIC_INLINE bool nrf_power_event_get_and_clear(nrf_power_event_t event);
407
408 /**
409 * @brief Function for returning the address of a specific POWER event register.
410 *
411 * @param[in] event Event.
412 *
413 * @return Address.
414 */
415 __STATIC_INLINE uint32_t nrf_power_event_address_get(nrf_power_event_t event);
416
417 /**
418 * @brief Function for enabling selected interrupts.
419 *
420 * @param[in] int_mask Interrupts mask.
421 */
422 __STATIC_INLINE void nrf_power_int_enable(uint32_t int_mask);
423
424 /**
425 * @brief Function for retrieving the state of selected interrupts.
426 *
427 * @param[in] int_mask Interrupts mask.
428 *
429 * @retval true If any of selected interrupts is enabled.
430 * @retval false If none of selected interrupts is enabled.
431 */
432 __STATIC_INLINE bool nrf_power_int_enable_check(uint32_t int_mask);
433
434 /**
435 * @brief Function for retrieving the information about enabled interrupts.
436 *
437 * @return The flags of enabled interrupts.
438 */
439 __STATIC_INLINE uint32_t nrf_power_int_enable_get(void);
440
441 /**
442 * @brief Function for disabling selected interrupts.
443 *
444 * @param[in] int_mask Interrupts mask.
445 */
446 __STATIC_INLINE void nrf_power_int_disable(uint32_t int_mask);
447
448 #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
449 /**
450 * @brief Function for setting the subscribe configuration for a given
451 * POWER task.
452 *
453 * @param[in] task Task for which to set the configuration.
454 * @param[in] channel Channel through which to subscribe events.
455 */
456 __STATIC_INLINE void nrf_power_subscribe_set(nrf_power_task_t task,
457 uint8_t channel);
458
459 /**
460 * @brief Function for clearing the subscribe configuration for a given
461 * POWER task.
462 *
463 * @param[in] task Task for which to clear the configuration.
464 */
465 __STATIC_INLINE void nrf_power_subscribe_clear(nrf_power_task_t task);
466
467 /**
468 * @brief Function for setting the publish configuration for a given
469 * POWER event.
470 *
471 * @param[in] event Event for which to set the configuration.
472 * @param[in] channel Channel through which to publish the event.
473 */
474 __STATIC_INLINE void nrf_power_publish_set(nrf_power_event_t event,
475 uint8_t channel);
476
477 /**
478 * @brief Function for clearing the publish configuration for a given
479 * POWER event.
480 *
481 * @param[in] event Event for which to clear the configuration.
482 */
483 __STATIC_INLINE void nrf_power_publish_clear(nrf_power_event_t event);
484 #endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
485
486 /**
487 * @brief Get reset reason mask
488 *
489 * Function returns the reset reason.
490 * Unless cleared, the RESETREAS register is cumulative.
491 * A field is cleared by writing '1' to it (see @ref nrf_power_resetreas_clear).
492 * If none of the reset sources are flagged,
493 * this indicates that the chip was reset from the on-chip reset generator,
494 * which indicates a power-on-reset or a brown out reset.
495 *
496 * @return The mask of reset reasons constructed with @ref nrf_power_resetreas_mask_t.
497 */
498 __STATIC_INLINE uint32_t nrf_power_resetreas_get(void);
499
500 /**
501 * @brief Clear selected reset reason field
502 *
503 * Function clears selected reset reason fields.
504 *
505 * @param[in] mask The mask constructed from @ref nrf_power_resetreas_mask_t enumerator values.
506 * @sa nrf_power_resetreas_get
507 */
508 __STATIC_INLINE void nrf_power_resetreas_clear(uint32_t mask);
509
510 #if defined(POWER_POWERSTATUS_LTEMODEM_Msk) || defined(__NRFX_DOXYGEN__)
511 /**
512 * @brief Function for getting power status of the LTE Modem domain.
513 *
514 * @retval true If the LTE Modem domain is powered on.
515 * @retval false If the LTE Modem domain is powered off.
516 */
517 __STATIC_INLINE bool nrf_power_powerstatus_get(void);
518 #endif
519
520 #if defined(POWER_RAMSTATUS_RAMBLOCK0_Msk) || defined(__NRFX_DOXYGEN__)
521 /**
522 * @brief Get RAMSTATUS register
523 *
524 * Returns the masks of RAM blocks that are powered ON.
525 *
526 * @return Value with bits sets according to masks in @ref nrf_power_ramblock_mask_t.
527 */
528 __STATIC_INLINE uint32_t nrf_power_ramstatus_get(void);
529 #endif // defined(POWER_RAMSTATUS_RAMBLOCK0_Msk) || defined(__NRFX_DOXYGEN__)
530
531 #if defined(POWER_SYSTEMOFF_SYSTEMOFF_Enter)
532 /**
533 * @brief Go to system OFF
534 *
535 * This function puts the CPU into system off mode.
536 * The only way to wake up the CPU is by reset.
537 *
538 * @note This function never returns.
539 */
540 __STATIC_INLINE void nrf_power_system_off(void);
541 #endif // defined(POWER_SYSTEMOFF_SYSTEMOFF_Enter)
542
543 #if NRF_POWER_HAS_POFCON
544 /**
545 * @brief Set power failure comparator configuration
546 *
547 * Sets power failure comparator threshold and enable/disable flag.
548 *
549 * @param[in] enabled Set to true if power failure comparator should be enabled.
550 * @param[in] thr Set the voltage threshold value.
551 *
552 * @note
553 * If VDDH settings is present in the device, this function would
554 * clear it settings (set to the lowest voltage).
555 * Use @ref nrf_power_pofcon_vddh_set function to set new value.
556 */
557 __STATIC_INLINE void nrf_power_pofcon_set(bool enabled, nrf_power_pof_thr_t thr);
558
559 /**
560 * @brief Get power failure comparator configuration
561 *
562 * Get power failure comparator threshold and enable bit.
563 *
564 * @param[out] p_enabled Function would set this boolean variable to true
565 * if power failure comparator is enabled.
566 * The pointer can be NULL if we do not need this information.
567 *
568 * @return Threshold setting for power failure comparator
569 */
570 __STATIC_INLINE nrf_power_pof_thr_t nrf_power_pofcon_get(bool * p_enabled);
571 #endif // NRF_POWER_HAS_POFCON
572
573 #if NRF_POWER_HAS_VDDH
574 /**
575 * @brief Set VDDH power failure comparator threshold
576 *
577 * @param[in] thr Threshold to be set
578 */
579 __STATIC_INLINE void nrf_power_pofcon_vddh_set(nrf_power_pof_thrvddh_t thr);
580
581 /**
582 * @brief Get VDDH power failure comparator threshold
583 *
584 * @return VDDH threshold currently configured
585 */
586 __STATIC_INLINE nrf_power_pof_thrvddh_t nrf_power_pofcon_vddh_get(void);
587 #endif // NRF_POWER_HAS_VDDH
588
589 /**
590 * @brief Set general purpose retention register
591 *
592 * @param[in] val Value to be set in the register
593 */
594 __STATIC_INLINE void nrf_power_gpregret_set(uint8_t val);
595
596 /**
597 * @brief Get general purpose retention register
598 *
599 * @return The value from the register
600 */
601 __STATIC_INLINE uint8_t nrf_power_gpregret_get(void);
602
603 #if defined(POWER_GPREGRET2_GPREGRET_Msk) || defined(__NRFX_DOXYGEN__)
604 /**
605 * @brief Set general purpose retention register 2
606 *
607 * @note This register is not available in nrf51 MCU family
608 *
609 * @param[in] val Value to be set in the register
610 */
611 __STATIC_INLINE void nrf_power_gpregret2_set(uint8_t val);
612
613 /**
614 * @brief Get general purpose retention register 2
615 *
616 * @note This register is not available in all MCUs.
617 *
618 * @return The value from the register
619 */
620 __STATIC_INLINE uint8_t nrf_power_gpregret2_get(void);
621 #endif // defined(POWER_GPREGRET2_GPREGRET_Msk) || defined(__NRFX_DOXYGEN__)
622
623 /**
624 * @brief Function for getting value of the particular general purpose retention register
625 *
626 * @param[in] reg_num General purpose retention register number.
627 *
628 * @return The value from the register
629 */
630 __STATIC_INLINE uint8_t nrf_power_gpregret_ext_get(uint8_t reg_num);
631
632 /**
633 * @brief Function for setting particular general purpose retention register.
634 *
635 * @param[in] reg_num General purpose retention register number.
636 * @param[in] val Value to be set in the register
637 */
638 __STATIC_INLINE void nrf_power_gpregret_ext_set(uint8_t reg_num,
639 uint8_t val);
640
641 #if NRF_POWER_HAS_DCDCEN
642 /**
643 * @brief Enable or disable DCDC converter
644 *
645 * @note
646 * If the device consist of high voltage power input (VDDH) this setting
647 * would relate to the converter on low voltage side (1.3 V output).
648 *
649 * @param[in] enable Set true to enable or false to disable DCDC converter.
650 */
651 __STATIC_INLINE void nrf_power_dcdcen_set(bool enable);
652
653 /**
654 * @brief Get the state of DCDC converter
655 *
656 * @note
657 * If the device consist of high voltage power input (VDDH) this setting
658 * would relate to the converter on low voltage side (1.3 V output).
659 *
660 * @retval true Converter is enabled
661 * @retval false Converter is disabled
662 */
663 __STATIC_INLINE bool nrf_power_dcdcen_get(void);
664 #endif // NRF_POWER_HAS_DCDCEN
665
666 #if defined(POWER_RAM_POWER_S0POWER_Msk) || defined(__NRFX_DOXYGEN__)
667 /**
668 * @brief Turn ON sections in selected RAM block.
669 *
670 * This function turns ON sections in block and also block retention.
671 *
672 * @sa nrf_power_rampower_mask_t
673 * @sa nrf_power_rampower_mask_off
674 *
675 * @param[in] block RAM block index.
676 * @param[in] section_mask Mask of the sections created by merging
677 * @ref nrf_power_rampower_mask_t flags.
678 */
679 __STATIC_INLINE void nrf_power_rampower_mask_on(uint8_t block, uint32_t section_mask);
680
681 /**
682 * @brief Turn ON sections in selected RAM block.
683 *
684 * This function turns OFF sections in block and also block retention.
685 *
686 * @sa nrf_power_rampower_mask_t
687 * @sa nrf_power_rampower_mask_off
688 *
689 * @param[in] block RAM block index.
690 * @param[in] section_mask Mask of the sections created by merging
691 * @ref nrf_power_rampower_mask_t flags.
692 */
693 __STATIC_INLINE void nrf_power_rampower_mask_off(uint8_t block, uint32_t section_mask);
694
695 /**
696 * @brief Get the mask of ON and retention sections in selected RAM block.
697 *
698 * @param[in] block RAM block index.
699 *
700 * @return Mask of sections state composed from @ref nrf_power_rampower_mask_t flags.
701 */
702 __STATIC_INLINE uint32_t nrf_power_rampower_mask_get(uint8_t block);
703 #endif /* defined(POWER_RAM_POWER_S0POWER_Msk) || defined(__NRFX_DOXYGEN__) */
704
705 #if NRF_POWER_HAS_VDDH
706 /**
707 * @brief Enable of disable DCDC converter on VDDH
708 *
709 * @param[in] enable Set true to enable or false to disable DCDC converter.
710 */
711 __STATIC_INLINE void nrf_power_dcdcen_vddh_set(bool enable);
712
713 /**
714 * @brief Get the state of DCDC converter on VDDH
715 *
716 * @retval true Converter is enabled
717 * @retval false Converter is disabled
718 */
719 __STATIC_INLINE bool nrf_power_dcdcen_vddh_get(void);
720
721 /**
722 * @brief Get main supply status
723 *
724 * @return Current main supply status
725 */
726 __STATIC_INLINE nrf_power_mainregstatus_t nrf_power_mainregstatus_get(void);
727 #endif // NRF_POWER_HAS_VDDH
728
729 #if NRF_POWER_HAS_USBREG
730 /**
731 * @brief Get the whole USBREGSTATUS register
732 *
733 * @return The USBREGSTATUS register value.
734 * Use @ref nrf_power_usbregstatus_mask_t values for bit masking.
735 *
736 * @sa nrf_power_usbregstatus_vbusdet_get
737 * @sa nrf_power_usbregstatus_outrdy_get
738 */
739 __STATIC_INLINE uint32_t nrf_power_usbregstatus_get(void);
740
741 /**
742 * @brief VBUS input detection status
743 *
744 * USBDETECTED and USBREMOVED events are derived from this information
745 *
746 * @retval false VBUS voltage below valid threshold
747 * @retval true VBUS voltage above valid threshold
748 *
749 * @sa nrf_power_usbregstatus_get
750 */
751 __STATIC_INLINE bool nrf_power_usbregstatus_vbusdet_get(void);
752
753 /**
754 * @brief USB supply output settling time elapsed
755 *
756 * @retval false USBREG output settling time not elapsed
757 * @retval true USBREG output settling time elapsed
758 * (same information as USBPWRRDY event)
759 *
760 * @sa nrf_power_usbregstatus_get
761 */
762 __STATIC_INLINE bool nrf_power_usbregstatus_outrdy_get(void);
763 #endif // NRF_POWER_HAS_USBREG
764
765 #ifndef SUPPRESS_INLINE_IMPLEMENTATION
766
nrf_power_task_trigger(nrf_power_task_t task)767 __STATIC_INLINE void nrf_power_task_trigger(nrf_power_task_t task)
768 {
769 *((volatile uint32_t *)((uint8_t *)NRF_POWER + (uint32_t)task)) = 0x1UL;
770 }
771
nrf_power_task_address_get(nrf_power_task_t task)772 __STATIC_INLINE uint32_t nrf_power_task_address_get(nrf_power_task_t task)
773 {
774 return ((uint32_t)NRF_POWER + (uint32_t)task);
775 }
776
nrf_power_event_clear(nrf_power_event_t event)777 __STATIC_INLINE void nrf_power_event_clear(nrf_power_event_t event)
778 {
779 *((volatile uint32_t *)((uint8_t *)NRF_POWER + (uint32_t)event)) = 0x0UL;
780 #if __CORTEX_M == 0x04
781 volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_POWER + (uint32_t)event));
782 (void)dummy;
783 #endif
784 }
785
nrf_power_event_check(nrf_power_event_t event)786 __STATIC_INLINE bool nrf_power_event_check(nrf_power_event_t event)
787 {
788 return (bool)*(volatile uint32_t *)((uint8_t *)NRF_POWER + (uint32_t)event);
789 }
790
nrf_power_event_get_and_clear(nrf_power_event_t event)791 __STATIC_INLINE bool nrf_power_event_get_and_clear(nrf_power_event_t event)
792 {
793 bool ret = nrf_power_event_check(event);
794 if (ret)
795 {
796 nrf_power_event_clear(event);
797 }
798 return ret;
799 }
800
nrf_power_event_address_get(nrf_power_event_t event)801 __STATIC_INLINE uint32_t nrf_power_event_address_get(nrf_power_event_t event)
802 {
803 return ((uint32_t)NRF_POWER + (uint32_t)event);
804 }
805
nrf_power_int_enable(uint32_t int_mask)806 __STATIC_INLINE void nrf_power_int_enable(uint32_t int_mask)
807 {
808 NRF_POWER->INTENSET = int_mask;
809 }
810
nrf_power_int_enable_check(uint32_t int_mask)811 __STATIC_INLINE bool nrf_power_int_enable_check(uint32_t int_mask)
812 {
813 return (bool)(NRF_POWER->INTENSET & int_mask);
814 }
815
nrf_power_int_enable_get(void)816 __STATIC_INLINE uint32_t nrf_power_int_enable_get(void)
817 {
818 return NRF_POWER->INTENSET;
819 }
820
nrf_power_int_disable(uint32_t int_mask)821 __STATIC_INLINE void nrf_power_int_disable(uint32_t int_mask)
822 {
823 NRF_POWER->INTENCLR = int_mask;
824 }
825
826 #if defined(DPPI_PRESENT)
nrf_power_subscribe_set(nrf_power_task_t task,uint8_t channel)827 __STATIC_INLINE void nrf_power_subscribe_set(nrf_power_task_t task,
828 uint8_t channel)
829 {
830 *((volatile uint32_t *) ((uint8_t *) NRF_POWER + (uint32_t) task + 0x80uL)) =
831 ((uint32_t)channel | POWER_SUBSCRIBE_CONSTLAT_EN_Msk);
832 }
833
nrf_power_subscribe_clear(nrf_power_task_t task)834 __STATIC_INLINE void nrf_power_subscribe_clear(nrf_power_task_t task)
835 {
836 *((volatile uint32_t *) ((uint8_t *) NRF_POWER + (uint32_t) task + 0x80uL)) = 0;
837 }
838
nrf_power_publish_set(nrf_power_event_t event,uint8_t channel)839 __STATIC_INLINE void nrf_power_publish_set(nrf_power_event_t event,
840 uint8_t channel)
841 {
842 *((volatile uint32_t *) ((uint8_t *) NRF_POWER + (uint32_t) event + 0x80uL)) =
843 ((uint32_t)channel | POWER_PUBLISH_SLEEPENTER_EN_Msk);
844 }
845
nrf_power_publish_clear(nrf_power_event_t event)846 __STATIC_INLINE void nrf_power_publish_clear(nrf_power_event_t event)
847 {
848 *((volatile uint32_t *) ((uint8_t *) NRF_POWER + (uint32_t) event + 0x80uL)) = 0;
849 }
850 #endif // defined(DPPI_PRESENT)
851
nrf_power_resetreas_get(void)852 __STATIC_INLINE uint32_t nrf_power_resetreas_get(void)
853 {
854 return NRF_POWER->RESETREAS;
855 }
856
nrf_power_resetreas_clear(uint32_t mask)857 __STATIC_INLINE void nrf_power_resetreas_clear(uint32_t mask)
858 {
859 NRF_POWER->RESETREAS = mask;
860 }
861
862 #if defined(POWER_POWERSTATUS_LTEMODEM_Msk)
nrf_power_powerstatus_get(void)863 __STATIC_INLINE bool nrf_power_powerstatus_get(void)
864 {
865 return (NRF_POWER->POWERSTATUS & POWER_POWERSTATUS_LTEMODEM_Msk) ==
866 (POWER_POWERSTATUS_LTEMODEM_ON << POWER_POWERSTATUS_LTEMODEM_Pos);
867 }
868 #endif // (POWER_POWERSTATUS_LTEMODEM_Msk)
869
870 #if defined(POWER_RAMSTATUS_RAMBLOCK0_Msk)
nrf_power_ramstatus_get(void)871 __STATIC_INLINE uint32_t nrf_power_ramstatus_get(void)
872 {
873 return NRF_POWER->RAMSTATUS;
874 }
875 #endif // defined(POWER_RAMSTATUS_RAMBLOCK0_Msk)
876
877 #if defined(POWER_SYSTEMOFF_SYSTEMOFF_Enter)
nrf_power_system_off(void)878 __STATIC_INLINE void nrf_power_system_off(void)
879 {
880 NRF_POWER->SYSTEMOFF = POWER_SYSTEMOFF_SYSTEMOFF_Enter;
881 __DSB();
882
883 /* Solution for simulated System OFF in debug mode */
884 while (true)
885 {
886 __WFE();
887 }
888 }
889 #endif // defined(POWER_SYSTEMOFF_SYSTEMOFF_Enter)
890
891 #if NRF_POWER_HAS_POFCON
nrf_power_pofcon_set(bool enabled,nrf_power_pof_thr_t thr)892 __STATIC_INLINE void nrf_power_pofcon_set(bool enabled, nrf_power_pof_thr_t thr)
893 {
894 NRFX_ASSERT(thr == (thr & (POWER_POFCON_THRESHOLD_Msk >> POWER_POFCON_THRESHOLD_Pos)));
895 #if NRF_POWER_HAS_VDDH
896 uint32_t pofcon = NRF_POWER->POFCON;
897 pofcon &= ~(POWER_POFCON_THRESHOLD_Msk | POWER_POFCON_POF_Msk);
898 pofcon |=
899 #else // NRF_POWER_HAS_VDDH
900 NRF_POWER->POFCON =
901 #endif
902 (((uint32_t)thr) << POWER_POFCON_THRESHOLD_Pos) |
903 (enabled ?
904 (POWER_POFCON_POF_Enabled << POWER_POFCON_POF_Pos)
905 :
906 (POWER_POFCON_POF_Disabled << POWER_POFCON_POF_Pos));
907 #if NRF_POWER_HAS_VDDH
908 NRF_POWER->POFCON = pofcon;
909 #endif
910 }
911
nrf_power_pofcon_get(bool * p_enabled)912 __STATIC_INLINE nrf_power_pof_thr_t nrf_power_pofcon_get(bool * p_enabled)
913 {
914 uint32_t pofcon = NRF_POWER->POFCON;
915 if (NULL != p_enabled)
916 {
917 (*p_enabled) = ((pofcon & POWER_POFCON_POF_Msk) >> POWER_POFCON_POF_Pos)
918 == POWER_POFCON_POF_Enabled;
919 }
920 return (nrf_power_pof_thr_t)((pofcon & POWER_POFCON_THRESHOLD_Msk) >>
921 POWER_POFCON_THRESHOLD_Pos);
922 }
923 #endif // NRF_POWER_HAS_POFCON
924
925 #if NRF_POWER_HAS_VDDH
nrf_power_pofcon_vddh_set(nrf_power_pof_thrvddh_t thr)926 __STATIC_INLINE void nrf_power_pofcon_vddh_set(nrf_power_pof_thrvddh_t thr)
927 {
928 NRFX_ASSERT(thr == (thr & (POWER_POFCON_THRESHOLDVDDH_Msk >> POWER_POFCON_THRESHOLDVDDH_Pos)));
929 uint32_t pofcon = NRF_POWER->POFCON;
930 pofcon &= ~POWER_POFCON_THRESHOLDVDDH_Msk;
931 pofcon |= (((uint32_t)thr) << POWER_POFCON_THRESHOLDVDDH_Pos);
932 NRF_POWER->POFCON = pofcon;
933 }
934
nrf_power_pofcon_vddh_get(void)935 __STATIC_INLINE nrf_power_pof_thrvddh_t nrf_power_pofcon_vddh_get(void)
936 {
937 return (nrf_power_pof_thrvddh_t)((NRF_POWER->POFCON &
938 POWER_POFCON_THRESHOLDVDDH_Msk) >> POWER_POFCON_THRESHOLDVDDH_Pos);
939 }
940 #endif // NRF_POWER_HAS_VDDH
941
nrf_power_gpregret_set(uint8_t val)942 __STATIC_INLINE void nrf_power_gpregret_set(uint8_t val)
943 {
944 volatile uint32_t * p_gpregret;
945 if (sizeof(NRF_POWER->GPREGRET) > sizeof(uint32_t))
946 {
947 p_gpregret = &((volatile uint32_t *)NRF_POWER->GPREGRET)[0];
948 }
949 else
950 {
951 p_gpregret = &((volatile uint32_t *)&NRF_POWER->GPREGRET)[0];
952 }
953 *p_gpregret = val;
954 }
955
nrf_power_gpregret_get(void)956 __STATIC_INLINE uint8_t nrf_power_gpregret_get(void)
957 {
958 volatile uint32_t * p_gpregret;
959 if (sizeof(NRF_POWER->GPREGRET) > sizeof(uint32_t))
960 {
961 p_gpregret = &((volatile uint32_t *)NRF_POWER->GPREGRET)[0];
962 }
963 else
964 {
965 p_gpregret = &((volatile uint32_t *)&NRF_POWER->GPREGRET)[0];
966 }
967 return *p_gpregret;
968 }
969
nrf_power_gpregret_ext_set(uint8_t reg_num,uint8_t val)970 __STATIC_INLINE void nrf_power_gpregret_ext_set(uint8_t reg_num, uint8_t val)
971 {
972 #ifdef NRF91_SERIES
973 NRF_POWER->GPREGRET[reg_num] = val;
974 #else
975 NRFX_ASSERT(reg_num < 1);
976 NRF_POWER->GPREGRET = val;
977 #endif
978 }
979
nrf_power_gpregret_ext_get(uint8_t reg_num)980 __STATIC_INLINE uint8_t nrf_power_gpregret_ext_get(uint8_t reg_num)
981 {
982 #ifdef NRF91_SERIES
983 return NRF_POWER->GPREGRET[reg_num];
984 #else
985 NRFX_ASSERT(reg_num < 1);
986 return NRF_POWER->GPREGRET;
987 #endif
988 }
989
990 #if defined(POWER_GPREGRET2_GPREGRET_Msk)
nrf_power_gpregret2_set(uint8_t val)991 __STATIC_INLINE void nrf_power_gpregret2_set(uint8_t val)
992 {
993 NRF_POWER->GPREGRET2 = val;
994 }
995
nrf_power_gpregret2_get(void)996 __STATIC_INLINE uint8_t nrf_power_gpregret2_get(void)
997 {
998 return NRF_POWER->GPREGRET2;
999 }
1000 #endif
1001
1002 #if NRF_POWER_HAS_DCDCEN
nrf_power_dcdcen_set(bool enable)1003 __STATIC_INLINE void nrf_power_dcdcen_set(bool enable)
1004 {
1005 NRF_POWER->DCDCEN = (enable ?
1006 POWER_DCDCEN_DCDCEN_Enabled : POWER_DCDCEN_DCDCEN_Disabled) <<
1007 POWER_DCDCEN_DCDCEN_Pos;
1008 }
1009
nrf_power_dcdcen_get(void)1010 __STATIC_INLINE bool nrf_power_dcdcen_get(void)
1011 {
1012 return (NRF_POWER->DCDCEN & POWER_DCDCEN_DCDCEN_Msk)
1013 ==
1014 (POWER_DCDCEN_DCDCEN_Enabled << POWER_DCDCEN_DCDCEN_Pos);
1015 }
1016 #endif // NRF_POWER_HAS_DCDCEN
1017
1018 #if defined(POWER_RAM_POWER_S0POWER_Msk)
nrf_power_rampower_mask_on(uint8_t block,uint32_t section_mask)1019 __STATIC_INLINE void nrf_power_rampower_mask_on(uint8_t block, uint32_t section_mask)
1020 {
1021 NRFX_ASSERT(block < NRFX_ARRAY_SIZE(NRF_POWER->RAM));
1022 NRF_POWER->RAM[block].POWERSET = section_mask;
1023 }
1024
nrf_power_rampower_mask_off(uint8_t block,uint32_t section_mask)1025 __STATIC_INLINE void nrf_power_rampower_mask_off(uint8_t block, uint32_t section_mask)
1026 {
1027 NRFX_ASSERT(block < NRFX_ARRAY_SIZE(NRF_POWER->RAM));
1028 NRF_POWER->RAM[block].POWERCLR = section_mask;
1029 }
1030
nrf_power_rampower_mask_get(uint8_t block)1031 __STATIC_INLINE uint32_t nrf_power_rampower_mask_get(uint8_t block)
1032 {
1033 NRFX_ASSERT(block < NRFX_ARRAY_SIZE(NRF_POWER->RAM));
1034 return NRF_POWER->RAM[block].POWER;
1035 }
1036 #endif /* defined(POWER_RAM_POWER_S0POWER_Msk) */
1037
1038 #if NRF_POWER_HAS_VDDH
nrf_power_dcdcen_vddh_set(bool enable)1039 __STATIC_INLINE void nrf_power_dcdcen_vddh_set(bool enable)
1040 {
1041 NRF_POWER->DCDCEN0 = (enable ?
1042 POWER_DCDCEN0_DCDCEN_Enabled : POWER_DCDCEN0_DCDCEN_Disabled) <<
1043 POWER_DCDCEN0_DCDCEN_Pos;
1044 }
1045
nrf_power_dcdcen_vddh_get(void)1046 __STATIC_INLINE bool nrf_power_dcdcen_vddh_get(void)
1047 {
1048 return (NRF_POWER->DCDCEN0 & POWER_DCDCEN0_DCDCEN_Msk)
1049 ==
1050 (POWER_DCDCEN0_DCDCEN_Enabled << POWER_DCDCEN0_DCDCEN_Pos);
1051 }
1052
nrf_power_mainregstatus_get(void)1053 __STATIC_INLINE nrf_power_mainregstatus_t nrf_power_mainregstatus_get(void)
1054 {
1055 return (nrf_power_mainregstatus_t)(((NRF_POWER->MAINREGSTATUS) &
1056 POWER_MAINREGSTATUS_MAINREGSTATUS_Msk) >>
1057 POWER_MAINREGSTATUS_MAINREGSTATUS_Pos);
1058 }
1059 #endif // NRF_POWER_HAS_VDDH
1060
1061 #if NRF_POWER_HAS_USBREG
nrf_power_usbregstatus_get(void)1062 __STATIC_INLINE uint32_t nrf_power_usbregstatus_get(void)
1063 {
1064 return NRF_POWER->USBREGSTATUS;
1065 }
1066
nrf_power_usbregstatus_vbusdet_get(void)1067 __STATIC_INLINE bool nrf_power_usbregstatus_vbusdet_get(void)
1068 {
1069 return (nrf_power_usbregstatus_get() &
1070 NRF_POWER_USBREGSTATUS_VBUSDETECT_MASK) != 0;
1071 }
1072
nrf_power_usbregstatus_outrdy_get(void)1073 __STATIC_INLINE bool nrf_power_usbregstatus_outrdy_get(void)
1074 {
1075 return (nrf_power_usbregstatus_get() &
1076 NRF_POWER_USBREGSTATUS_OUTPUTRDY_MASK) != 0;
1077 }
1078 #endif // NRF_POWER_HAS_USBREG
1079
1080 #endif // SUPPRESS_INLINE_IMPLEMENTATION
1081
1082 /** @} */
1083
1084 #ifdef __cplusplus
1085 }
1086 #endif
1087
1088 #endif // NRF_POWER_H__
1089