1*150812a8SEvalZero /*
2*150812a8SEvalZero * Copyright (c) 2012 - 2018, Nordic Semiconductor ASA
3*150812a8SEvalZero * All rights reserved.
4*150812a8SEvalZero *
5*150812a8SEvalZero * Redistribution and use in source and binary forms, with or without
6*150812a8SEvalZero * modification, are permitted provided that the following conditions are met:
7*150812a8SEvalZero *
8*150812a8SEvalZero * 1. Redistributions of source code must retain the above copyright notice, this
9*150812a8SEvalZero * list of conditions and the following disclaimer.
10*150812a8SEvalZero *
11*150812a8SEvalZero * 2. Redistributions in binary form must reproduce the above copyright
12*150812a8SEvalZero * notice, this list of conditions and the following disclaimer in the
13*150812a8SEvalZero * documentation and/or other materials provided with the distribution.
14*150812a8SEvalZero *
15*150812a8SEvalZero * 3. Neither the name of the copyright holder nor the names of its
16*150812a8SEvalZero * contributors may be used to endorse or promote products derived from this
17*150812a8SEvalZero * software without specific prior written permission.
18*150812a8SEvalZero *
19*150812a8SEvalZero * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20*150812a8SEvalZero * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21*150812a8SEvalZero * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22*150812a8SEvalZero * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23*150812a8SEvalZero * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24*150812a8SEvalZero * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25*150812a8SEvalZero * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26*150812a8SEvalZero * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27*150812a8SEvalZero * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28*150812a8SEvalZero * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29*150812a8SEvalZero * POSSIBILITY OF SUCH DAMAGE.
30*150812a8SEvalZero */
31*150812a8SEvalZero /**
32*150812a8SEvalZero *@file
33*150812a8SEvalZero *@brief NMVC driver implementation
34*150812a8SEvalZero */
35*150812a8SEvalZero
36*150812a8SEvalZero #include <nrfx.h>
37*150812a8SEvalZero #include "nrf_nvmc.h"
38*150812a8SEvalZero
wait_for_flash_ready(void)39*150812a8SEvalZero static inline void wait_for_flash_ready(void)
40*150812a8SEvalZero {
41*150812a8SEvalZero while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {;}
42*150812a8SEvalZero }
43*150812a8SEvalZero
nrf_nvmc_page_erase(uint32_t address)44*150812a8SEvalZero void nrf_nvmc_page_erase(uint32_t address)
45*150812a8SEvalZero {
46*150812a8SEvalZero // Enable erase.
47*150812a8SEvalZero NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Een;
48*150812a8SEvalZero __ISB();
49*150812a8SEvalZero __DSB();
50*150812a8SEvalZero
51*150812a8SEvalZero // Erase the page
52*150812a8SEvalZero NRF_NVMC->ERASEPAGE = address;
53*150812a8SEvalZero wait_for_flash_ready();
54*150812a8SEvalZero
55*150812a8SEvalZero NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren;
56*150812a8SEvalZero __ISB();
57*150812a8SEvalZero __DSB();
58*150812a8SEvalZero }
59*150812a8SEvalZero
60*150812a8SEvalZero
nrf_nvmc_write_byte(uint32_t address,uint8_t value)61*150812a8SEvalZero void nrf_nvmc_write_byte(uint32_t address, uint8_t value)
62*150812a8SEvalZero {
63*150812a8SEvalZero uint32_t byte_shift = address & (uint32_t)0x03;
64*150812a8SEvalZero uint32_t address32 = address & ~byte_shift; // Address to the word this byte is in.
65*150812a8SEvalZero uint32_t value32 = (*(uint32_t*)address32 & ~((uint32_t)0xFF << (byte_shift << (uint32_t)3)));
66*150812a8SEvalZero value32 = value32 + ((uint32_t)value << (byte_shift << 3));
67*150812a8SEvalZero
68*150812a8SEvalZero // Enable write.
69*150812a8SEvalZero NRF_NVMC->CONFIG = (NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos);
70*150812a8SEvalZero __ISB();
71*150812a8SEvalZero __DSB();
72*150812a8SEvalZero
73*150812a8SEvalZero *(uint32_t*)address32 = value32;
74*150812a8SEvalZero wait_for_flash_ready();
75*150812a8SEvalZero
76*150812a8SEvalZero NRF_NVMC->CONFIG = (NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos);
77*150812a8SEvalZero __ISB();
78*150812a8SEvalZero __DSB();
79*150812a8SEvalZero }
80*150812a8SEvalZero
nrf_nvmc_write_word(uint32_t address,uint32_t value)81*150812a8SEvalZero void nrf_nvmc_write_word(uint32_t address, uint32_t value)
82*150812a8SEvalZero {
83*150812a8SEvalZero // Enable write.
84*150812a8SEvalZero NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen;
85*150812a8SEvalZero __ISB();
86*150812a8SEvalZero __DSB();
87*150812a8SEvalZero
88*150812a8SEvalZero *(uint32_t*)address = value;
89*150812a8SEvalZero wait_for_flash_ready();
90*150812a8SEvalZero
91*150812a8SEvalZero NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren;
92*150812a8SEvalZero __ISB();
93*150812a8SEvalZero __DSB();
94*150812a8SEvalZero }
95*150812a8SEvalZero
nrf_nvmc_write_bytes(uint32_t address,const uint8_t * src,uint32_t num_bytes)96*150812a8SEvalZero void nrf_nvmc_write_bytes(uint32_t address, const uint8_t * src, uint32_t num_bytes)
97*150812a8SEvalZero {
98*150812a8SEvalZero uint32_t i;
99*150812a8SEvalZero for (i = 0; i < num_bytes; i++)
100*150812a8SEvalZero {
101*150812a8SEvalZero nrf_nvmc_write_byte(address + i,src[i]);
102*150812a8SEvalZero }
103*150812a8SEvalZero }
104*150812a8SEvalZero
nrf_nvmc_write_words(uint32_t address,const uint32_t * src,uint32_t num_words)105*150812a8SEvalZero void nrf_nvmc_write_words(uint32_t address, const uint32_t * src, uint32_t num_words)
106*150812a8SEvalZero {
107*150812a8SEvalZero uint32_t i;
108*150812a8SEvalZero
109*150812a8SEvalZero // Enable write.
110*150812a8SEvalZero NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen;
111*150812a8SEvalZero __ISB();
112*150812a8SEvalZero __DSB();
113*150812a8SEvalZero
114*150812a8SEvalZero for (i = 0; i < num_words; i++)
115*150812a8SEvalZero {
116*150812a8SEvalZero ((uint32_t*)address)[i] = src[i];
117*150812a8SEvalZero wait_for_flash_ready();
118*150812a8SEvalZero }
119*150812a8SEvalZero
120*150812a8SEvalZero NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren;
121*150812a8SEvalZero __ISB();
122*150812a8SEvalZero __DSB();
123*150812a8SEvalZero }
124*150812a8SEvalZero
125