1 /*
2 * Copyright (c) 2018, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice, this
9 * list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the copyright holder nor the names of its
16 * contributors may be used to endorse or promote products derived from this
17 * software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #ifndef NRF_KMU_H__
33 #define NRF_KMU_H__
34
35 #include <nrfx.h>
36
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40
41 /**
42 * @defgroup nrf_kmu_hal KMU HAL
43 * @{
44 * @ingroup nrf_kmu
45 * @brief Hardware access layer for managing the Key Management Unit (KMU) peripheral.
46 */
47
48 /** @brief KMU tasks. */
49 typedef enum
50 {
51 NRF_KMU_TASK_PUSH_KEYSLOT = offsetof(NRF_KMU_Type, TASKS_PUSH_KEYSLOT), ///< Push a key slot over secure APB.
52 } nrf_kmu_task_t;
53
54 /** @brief KMU events. */
55 typedef enum
56 {
57 NRF_KMU_EVENT_KEYSLOT_PUSHED = offsetof(NRF_KMU_Type, EVENTS_KEYSLOT_PUSHED), ///< Key successfully pushed over secure APB.
58 NRF_KMU_EVENT_KEYSLOT_REVOKED = offsetof(NRF_KMU_Type, EVENTS_KEYSLOT_REVOKED), ///< Key has been revoked and cannot be tasked for selection.
59 NRF_KMU_EVENT_KEYSLOT_ERROR = offsetof(NRF_KMU_Type, EVENTS_KEYSLOT_ERROR) ///< No key slot selected or no destination address defined or error during push mechanism.
60 } nrf_kmu_event_t;
61
62 /** @brief KMU interrupts. */
63 typedef enum
64 {
65 NRF_KMU_INT_PUSHED_MASK = KMU_INTEN_KEYSLOT_PUSHED_Msk, ///< Interrupt on KEYSLOT_PUSHED event.
66 NRF_KMU_INT_REVOKED_MASK = KMU_INTEN_KEYSLOT_REVOKED_Msk, ///< Interrupt on KEYSLOT_REVOKED event.
67 NRF_KMU_INT_ERROR_MASK = KMU_INTEN_KEYSLOT_ERROR_Msk ///< Interrupt on KEYSLOT_ERROR event.
68 } nrf_kmu_int_mask_t;
69
70 /** @brief KMU operation status. */
71 typedef enum
72 {
73 NRF_KMU_STATUS_BLOCKED_MASK = KMU_STATUS_BLOCKED_Msk, ///< Access violation detected and blocked.
74 NRF_KMU_STATUS_SELECTED_MASK = KMU_STATUS_SELECTED_Msk, ///< Key slot ID successfully selected by KMU
75 } nrf_kmu_status_t;
76
77
78 /**
79 * @brief Function for activating a specific KMU task.
80 *
81 * @param[in] p_reg Pointer to the peripheral registers structure.
82 * @param[in] task Task to activate.
83 */
84 __STATIC_INLINE void nrf_kmu_task_trigger(NRF_KMU_Type * p_reg, nrf_kmu_task_t task);
85
86 /**
87 * @brief Function for getting the address of a specific KMU task register.
88 *
89 * @param[in] p_reg Pointer to the peripheral registers structure.
90 * @param[in] task Requested task.
91 *
92 * @return Address of the specified task register.
93 */
94 __STATIC_INLINE uint32_t nrf_kmu_task_address_get(NRF_KMU_Type const * p_reg, nrf_kmu_task_t task);
95
96 /**
97 * @brief Function for clearing a specific KMU event.
98 *
99 * @param[in] p_reg Pointer to the peripheral registers structure.
100 * @param[in] event Event to clear.
101 */
102 __STATIC_INLINE void nrf_kmu_event_clear(NRF_KMU_Type * p_reg, nrf_kmu_event_t event);
103
104 /**
105 * @brief Function for checking the state of a specific KMU event.
106 *
107 * @param[in] p_reg Pointer to the peripheral registers structure.
108 * @param[in] event Event to check.
109 *
110 * @retval true If the event is set.
111 * @retval false If the event is not set.
112 */
113 __STATIC_INLINE bool nrf_kmu_event_check(NRF_KMU_Type const * p_reg, nrf_kmu_event_t event);
114
115 /**
116 * @brief Function for getting the address of a specific KMU event register.
117 *
118 * @param[in] p_reg Pointer to the peripheral registers structure.
119 * @param[in] event Requested event.
120 *
121 * @return Address of the specified event register.
122 */
123 __STATIC_INLINE uint32_t nrf_kmu_event_address_get(NRF_KMU_Type const * p_reg,
124 nrf_kmu_event_t event);
125
126 /**
127 * @brief Function for enabling specified interrupts.
128 *
129 * @param[in] p_reg Pointer to the peripheral registers structure.
130 * @param[in] mask Interrupts to enable.
131 */
132 __STATIC_INLINE void nrf_kmu_int_enable(NRF_KMU_Type * p_reg, uint32_t mask);
133
134 /**
135 * @brief Function for disabling specified interrupts.
136 *
137 * @param[in] p_reg Pointer to the peripheral registers structure.
138 * @param[in] mask Interrupts to disable.
139 */
140 __STATIC_INLINE void nrf_kmu_int_disable(NRF_KMU_Type * p_reg, uint32_t mask);
141
142 /**
143 * @brief Function for retrieving the state of a given interrupt.
144 *
145 * @param[in] p_reg Pointer to the peripheral registers structure.
146 * @param[in] kmu_int Interrupt to check.
147 *
148 * @retval true If the interrupt is enabled.
149 * @retval false If the interrupt is not enabled.
150 */
151 __STATIC_INLINE bool nrf_kmu_int_enable_check(NRF_KMU_Type const * p_reg,
152 nrf_kmu_int_mask_t kmu_int);
153
154 /**
155 * @brief Function for retrieving the state of interrupts.
156 *
157 * Function returns bitmask. Please use @ref nrf_kmu_int_mask_t to check interrupts status.
158 *
159 * @param[in] p_reg Pointer to the peripheral registers structure.
160 *
161 * @return Bitmask with pending interrupts bits.
162 */
163 __STATIC_INLINE uint32_t nrf_kmu_intpend_get(NRF_KMU_Type const * p_reg);
164
165 /**
166 * @brief Function for getting status bits of the KMU operation.
167 *
168 * Function returns bitmask. Please use @ref nrf_kmu_status_t to check operations status.
169 *
170 * @param[in] p_reg Pointer to the peripheral registers structure.
171 *
172 * @return Bitmask with operation status bits.
173 */
174 __STATIC_INLINE uint32_t nrf_kmu_status_get(NRF_KMU_Type const * p_reg);
175
176 /**
177 * @brief Function for selecting the key slot ID.
178 *
179 * @param[in] p_reg Pointer to the peripheral registers structure.
180 * @param[in] keyslot_id Key slot ID to be read over AHB or pushed over
181 * secure APB when TASKS_PUSH_KEYSLOT is started.
182 */
183 __STATIC_INLINE void nrf_kmu_keyslot_set(NRF_KMU_Type * p_reg, uint8_t keyslot_id);
184
185 /**
186 * @brief Function for getting the key slot ID.
187 *
188 * @param[in] p_reg Pointer to the peripheral registers structure.
189 *
190 * @return Key slot ID.
191 */
192 __STATIC_INLINE uint8_t nrf_kmu_keyslot_get(NRF_KMU_Type const * p_reg);
193
194
195 #ifndef SUPPRESS_INLINE_IMPLEMENTATION
196
nrf_kmu_task_trigger(NRF_KMU_Type * p_reg,nrf_kmu_task_t task)197 __STATIC_INLINE void nrf_kmu_task_trigger(NRF_KMU_Type * p_reg, nrf_kmu_task_t task)
198 {
199 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
200 }
201
nrf_kmu_task_address_get(NRF_KMU_Type const * p_reg,nrf_kmu_task_t task)202 __STATIC_INLINE uint32_t nrf_kmu_task_address_get(NRF_KMU_Type const * p_reg, nrf_kmu_task_t task)
203 {
204 return ((uint32_t)p_reg + (uint32_t)task);
205 }
206
nrf_kmu_event_clear(NRF_KMU_Type * p_reg,nrf_kmu_event_t event)207 __STATIC_INLINE void nrf_kmu_event_clear(NRF_KMU_Type * p_reg, nrf_kmu_event_t event)
208 {
209 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
210 volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
211 (void)dummy;
212 }
213
nrf_kmu_event_check(NRF_KMU_Type const * p_reg,nrf_kmu_event_t event)214 __STATIC_INLINE bool nrf_kmu_event_check(NRF_KMU_Type const * p_reg, nrf_kmu_event_t event)
215 {
216 return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
217 }
218
nrf_kmu_event_address_get(NRF_KMU_Type const * p_reg,nrf_kmu_event_t event)219 __STATIC_INLINE uint32_t nrf_kmu_event_address_get(NRF_KMU_Type const * p_reg,
220 nrf_kmu_event_t event)
221 {
222 return ((uint32_t)p_reg + (uint32_t)event);
223 }
224
nrf_kmu_int_enable(NRF_KMU_Type * p_reg,uint32_t mask)225 __STATIC_INLINE void nrf_kmu_int_enable(NRF_KMU_Type * p_reg, uint32_t mask)
226 {
227 p_reg->INTENSET = mask;
228 }
229
nrf_kmu_int_disable(NRF_KMU_Type * p_reg,uint32_t mask)230 __STATIC_INLINE void nrf_kmu_int_disable(NRF_KMU_Type * p_reg, uint32_t mask)
231 {
232 p_reg->INTENCLR = mask;
233 }
234
nrf_kmu_int_enable_check(NRF_KMU_Type const * p_reg,nrf_kmu_int_mask_t kmu_int)235 __STATIC_INLINE bool nrf_kmu_int_enable_check(NRF_KMU_Type const * p_reg,
236 nrf_kmu_int_mask_t kmu_int)
237 {
238 return (bool)(p_reg->INTENSET & kmu_int);
239 }
240
nrf_kmu_intpend_get(NRF_KMU_Type const * p_reg)241 __STATIC_INLINE uint32_t nrf_kmu_intpend_get(NRF_KMU_Type const * p_reg)
242 {
243 return p_reg->INTPEND;
244 }
245
nrf_kmu_status_get(NRF_KMU_Type const * p_reg)246 __STATIC_INLINE uint32_t nrf_kmu_status_get(NRF_KMU_Type const * p_reg)
247 {
248 return p_reg->STATUS;
249 }
250
nrf_kmu_keyslot_set(NRF_KMU_Type * p_reg,uint8_t keyslot_id)251 __STATIC_INLINE void nrf_kmu_keyslot_set(NRF_KMU_Type * p_reg, uint8_t keyslot_id)
252 {
253 p_reg->SELECTKEYSLOT = (uint32_t) keyslot_id;
254 }
255
nrf_kmu_keyslot_get(NRF_KMU_Type const * p_reg)256 __STATIC_INLINE uint8_t nrf_kmu_keyslot_get(NRF_KMU_Type const * p_reg)
257 {
258 return (uint8_t) p_reg->SELECTKEYSLOT;
259 }
260
261 #endif // SUPPRESS_INLINE_IMPLEMENTATION
262
263 /** @} */
264
265 #ifdef __cplusplus
266 }
267 #endif
268
269 #endif // NRF_KMU_H__
270