xref: /nrf52832-nimble/nordic/nrfx/hal/nrf_kmu.h (revision 150812a83cab50279bd772ef6db1bfaf255f2c5b)
1*150812a8SEvalZero /*
2*150812a8SEvalZero  * Copyright (c) 2018, Nordic Semiconductor ASA
3*150812a8SEvalZero  * All rights reserved.
4*150812a8SEvalZero  *
5*150812a8SEvalZero  * Redistribution and use in source and binary forms, with or without
6*150812a8SEvalZero  * modification, are permitted provided that the following conditions are met:
7*150812a8SEvalZero  *
8*150812a8SEvalZero  * 1. Redistributions of source code must retain the above copyright notice, this
9*150812a8SEvalZero  *    list of conditions and the following disclaimer.
10*150812a8SEvalZero  *
11*150812a8SEvalZero  * 2. Redistributions in binary form must reproduce the above copyright
12*150812a8SEvalZero  *    notice, this list of conditions and the following disclaimer in the
13*150812a8SEvalZero  *    documentation and/or other materials provided with the distribution.
14*150812a8SEvalZero  *
15*150812a8SEvalZero  * 3. Neither the name of the copyright holder nor the names of its
16*150812a8SEvalZero  *    contributors may be used to endorse or promote products derived from this
17*150812a8SEvalZero  *    software without specific prior written permission.
18*150812a8SEvalZero  *
19*150812a8SEvalZero  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20*150812a8SEvalZero  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21*150812a8SEvalZero  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22*150812a8SEvalZero  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23*150812a8SEvalZero  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24*150812a8SEvalZero  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25*150812a8SEvalZero  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26*150812a8SEvalZero  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27*150812a8SEvalZero  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28*150812a8SEvalZero  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29*150812a8SEvalZero  * POSSIBILITY OF SUCH DAMAGE.
30*150812a8SEvalZero  */
31*150812a8SEvalZero 
32*150812a8SEvalZero #ifndef NRF_KMU_H__
33*150812a8SEvalZero #define NRF_KMU_H__
34*150812a8SEvalZero 
35*150812a8SEvalZero #include <nrfx.h>
36*150812a8SEvalZero 
37*150812a8SEvalZero #ifdef __cplusplus
38*150812a8SEvalZero extern "C" {
39*150812a8SEvalZero #endif
40*150812a8SEvalZero 
41*150812a8SEvalZero /**
42*150812a8SEvalZero  * @defgroup nrf_kmu_hal KMU HAL
43*150812a8SEvalZero  * @{
44*150812a8SEvalZero  * @ingroup nrf_kmu
45*150812a8SEvalZero  * @brief   Hardware access layer for managing the Key Management Unit (KMU) peripheral.
46*150812a8SEvalZero  */
47*150812a8SEvalZero 
48*150812a8SEvalZero /** @brief KMU tasks. */
49*150812a8SEvalZero typedef enum
50*150812a8SEvalZero {
51*150812a8SEvalZero     NRF_KMU_TASK_PUSH_KEYSLOT = offsetof(NRF_KMU_Type, TASKS_PUSH_KEYSLOT), ///< Push a key slot over secure APB.
52*150812a8SEvalZero } nrf_kmu_task_t;
53*150812a8SEvalZero 
54*150812a8SEvalZero /** @brief KMU events. */
55*150812a8SEvalZero typedef enum
56*150812a8SEvalZero {
57*150812a8SEvalZero     NRF_KMU_EVENT_KEYSLOT_PUSHED  = offsetof(NRF_KMU_Type, EVENTS_KEYSLOT_PUSHED),  ///< Key successfully pushed over secure APB.
58*150812a8SEvalZero     NRF_KMU_EVENT_KEYSLOT_REVOKED = offsetof(NRF_KMU_Type, EVENTS_KEYSLOT_REVOKED), ///< Key has been revoked and cannot be tasked for selection.
59*150812a8SEvalZero     NRF_KMU_EVENT_KEYSLOT_ERROR   = offsetof(NRF_KMU_Type, EVENTS_KEYSLOT_ERROR)    ///< No key slot selected or no destination address defined or error during push mechanism.
60*150812a8SEvalZero } nrf_kmu_event_t;
61*150812a8SEvalZero 
62*150812a8SEvalZero /** @brief KMU interrupts. */
63*150812a8SEvalZero typedef enum
64*150812a8SEvalZero {
65*150812a8SEvalZero     NRF_KMU_INT_PUSHED_MASK  = KMU_INTEN_KEYSLOT_PUSHED_Msk,  ///< Interrupt on KEYSLOT_PUSHED event.
66*150812a8SEvalZero     NRF_KMU_INT_REVOKED_MASK = KMU_INTEN_KEYSLOT_REVOKED_Msk, ///< Interrupt on KEYSLOT_REVOKED event.
67*150812a8SEvalZero     NRF_KMU_INT_ERROR_MASK   = KMU_INTEN_KEYSLOT_ERROR_Msk    ///< Interrupt on KEYSLOT_ERROR event.
68*150812a8SEvalZero } nrf_kmu_int_mask_t;
69*150812a8SEvalZero 
70*150812a8SEvalZero /** @brief KMU operation status. */
71*150812a8SEvalZero typedef enum
72*150812a8SEvalZero {
73*150812a8SEvalZero     NRF_KMU_STATUS_BLOCKED_MASK  = KMU_STATUS_BLOCKED_Msk,  ///< Access violation detected and blocked.
74*150812a8SEvalZero     NRF_KMU_STATUS_SELECTED_MASK = KMU_STATUS_SELECTED_Msk, ///< Key slot ID successfully selected by KMU
75*150812a8SEvalZero } nrf_kmu_status_t;
76*150812a8SEvalZero 
77*150812a8SEvalZero 
78*150812a8SEvalZero /**
79*150812a8SEvalZero  * @brief Function for activating a specific KMU task.
80*150812a8SEvalZero  *
81*150812a8SEvalZero  * @param[in] p_reg Pointer to the peripheral registers structure.
82*150812a8SEvalZero  * @param[in] task  Task to activate.
83*150812a8SEvalZero  */
84*150812a8SEvalZero __STATIC_INLINE void nrf_kmu_task_trigger(NRF_KMU_Type * p_reg, nrf_kmu_task_t task);
85*150812a8SEvalZero 
86*150812a8SEvalZero /**
87*150812a8SEvalZero  * @brief Function for getting the address of a specific KMU task register.
88*150812a8SEvalZero  *
89*150812a8SEvalZero  * @param[in] p_reg Pointer to the peripheral registers structure.
90*150812a8SEvalZero  * @param[in] task  Requested task.
91*150812a8SEvalZero  *
92*150812a8SEvalZero  * @return Address of the specified task register.
93*150812a8SEvalZero  */
94*150812a8SEvalZero __STATIC_INLINE uint32_t nrf_kmu_task_address_get(NRF_KMU_Type const * p_reg, nrf_kmu_task_t task);
95*150812a8SEvalZero 
96*150812a8SEvalZero /**
97*150812a8SEvalZero  * @brief Function for clearing a specific KMU event.
98*150812a8SEvalZero  *
99*150812a8SEvalZero  * @param[in] p_reg Pointer to the peripheral registers structure.
100*150812a8SEvalZero  * @param[in] event Event to clear.
101*150812a8SEvalZero  */
102*150812a8SEvalZero __STATIC_INLINE void nrf_kmu_event_clear(NRF_KMU_Type * p_reg, nrf_kmu_event_t event);
103*150812a8SEvalZero 
104*150812a8SEvalZero /**
105*150812a8SEvalZero  * @brief Function for checking the state of a specific KMU event.
106*150812a8SEvalZero  *
107*150812a8SEvalZero  * @param[in] p_reg Pointer to the peripheral registers structure.
108*150812a8SEvalZero  * @param[in] event Event to check.
109*150812a8SEvalZero  *
110*150812a8SEvalZero  * @retval true  If the event is set.
111*150812a8SEvalZero  * @retval false If the event is not set.
112*150812a8SEvalZero  */
113*150812a8SEvalZero __STATIC_INLINE bool nrf_kmu_event_check(NRF_KMU_Type const * p_reg, nrf_kmu_event_t event);
114*150812a8SEvalZero 
115*150812a8SEvalZero /**
116*150812a8SEvalZero  * @brief Function for getting the address of a specific KMU event register.
117*150812a8SEvalZero  *
118*150812a8SEvalZero  * @param[in] p_reg Pointer to the peripheral registers structure.
119*150812a8SEvalZero  * @param[in] event Requested event.
120*150812a8SEvalZero  *
121*150812a8SEvalZero  * @return Address of the specified event register.
122*150812a8SEvalZero  */
123*150812a8SEvalZero __STATIC_INLINE uint32_t nrf_kmu_event_address_get(NRF_KMU_Type const * p_reg,
124*150812a8SEvalZero                                                    nrf_kmu_event_t      event);
125*150812a8SEvalZero 
126*150812a8SEvalZero /**
127*150812a8SEvalZero  * @brief Function for enabling specified interrupts.
128*150812a8SEvalZero  *
129*150812a8SEvalZero  * @param[in] p_reg Pointer to the peripheral registers structure.
130*150812a8SEvalZero  * @param[in] mask  Interrupts to enable.
131*150812a8SEvalZero  */
132*150812a8SEvalZero __STATIC_INLINE void nrf_kmu_int_enable(NRF_KMU_Type * p_reg, uint32_t mask);
133*150812a8SEvalZero 
134*150812a8SEvalZero /**
135*150812a8SEvalZero  * @brief Function for disabling specified interrupts.
136*150812a8SEvalZero  *
137*150812a8SEvalZero  * @param[in] p_reg Pointer to the peripheral registers structure.
138*150812a8SEvalZero  * @param[in] mask  Interrupts to disable.
139*150812a8SEvalZero  */
140*150812a8SEvalZero __STATIC_INLINE void nrf_kmu_int_disable(NRF_KMU_Type * p_reg, uint32_t mask);
141*150812a8SEvalZero 
142*150812a8SEvalZero /**
143*150812a8SEvalZero  * @brief Function for retrieving the state of a given interrupt.
144*150812a8SEvalZero  *
145*150812a8SEvalZero  * @param[in] p_reg   Pointer to the peripheral registers structure.
146*150812a8SEvalZero  * @param[in] kmu_int Interrupt to check.
147*150812a8SEvalZero  *
148*150812a8SEvalZero  * @retval true  If the interrupt is enabled.
149*150812a8SEvalZero  * @retval false If the interrupt is not enabled.
150*150812a8SEvalZero  */
151*150812a8SEvalZero __STATIC_INLINE bool nrf_kmu_int_enable_check(NRF_KMU_Type const * p_reg,
152*150812a8SEvalZero                                               nrf_kmu_int_mask_t   kmu_int);
153*150812a8SEvalZero 
154*150812a8SEvalZero /**
155*150812a8SEvalZero  * @brief Function for retrieving the state of interrupts.
156*150812a8SEvalZero  *
157*150812a8SEvalZero  * Function returns bitmask. Please use @ref nrf_kmu_int_mask_t to check interrupts status.
158*150812a8SEvalZero  *
159*150812a8SEvalZero  * @param[in] p_reg Pointer to the peripheral registers structure.
160*150812a8SEvalZero  *
161*150812a8SEvalZero  * @return Bitmask with pending interrupts bits.
162*150812a8SEvalZero  */
163*150812a8SEvalZero __STATIC_INLINE uint32_t nrf_kmu_intpend_get(NRF_KMU_Type const * p_reg);
164*150812a8SEvalZero 
165*150812a8SEvalZero /**
166*150812a8SEvalZero  * @brief Function for getting status bits of the KMU operation.
167*150812a8SEvalZero  *
168*150812a8SEvalZero  * Function returns bitmask. Please use @ref nrf_kmu_status_t to check operations status.
169*150812a8SEvalZero  *
170*150812a8SEvalZero  * @param[in] p_reg Pointer to the peripheral registers structure.
171*150812a8SEvalZero  *
172*150812a8SEvalZero  * @return Bitmask with operation status bits.
173*150812a8SEvalZero  */
174*150812a8SEvalZero __STATIC_INLINE uint32_t nrf_kmu_status_get(NRF_KMU_Type const * p_reg);
175*150812a8SEvalZero 
176*150812a8SEvalZero /**
177*150812a8SEvalZero  * @brief Function for selecting the key slot ID.
178*150812a8SEvalZero  *
179*150812a8SEvalZero  * @param[in] p_reg      Pointer to the peripheral registers structure.
180*150812a8SEvalZero  * @param[in] keyslot_id Key slot ID to be read over AHB or pushed over
181*150812a8SEvalZero  *                       secure APB when TASKS_PUSH_KEYSLOT is started.
182*150812a8SEvalZero  */
183*150812a8SEvalZero __STATIC_INLINE void nrf_kmu_keyslot_set(NRF_KMU_Type * p_reg, uint8_t keyslot_id);
184*150812a8SEvalZero 
185*150812a8SEvalZero /**
186*150812a8SEvalZero  * @brief Function for getting the key slot ID.
187*150812a8SEvalZero  *
188*150812a8SEvalZero  * @param[in] p_reg Pointer to the peripheral registers structure.
189*150812a8SEvalZero  *
190*150812a8SEvalZero  * @return Key slot ID.
191*150812a8SEvalZero  */
192*150812a8SEvalZero __STATIC_INLINE uint8_t nrf_kmu_keyslot_get(NRF_KMU_Type const * p_reg);
193*150812a8SEvalZero 
194*150812a8SEvalZero 
195*150812a8SEvalZero #ifndef SUPPRESS_INLINE_IMPLEMENTATION
196*150812a8SEvalZero 
nrf_kmu_task_trigger(NRF_KMU_Type * p_reg,nrf_kmu_task_t task)197*150812a8SEvalZero __STATIC_INLINE void nrf_kmu_task_trigger(NRF_KMU_Type * p_reg, nrf_kmu_task_t task)
198*150812a8SEvalZero {
199*150812a8SEvalZero     *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
200*150812a8SEvalZero }
201*150812a8SEvalZero 
nrf_kmu_task_address_get(NRF_KMU_Type const * p_reg,nrf_kmu_task_t task)202*150812a8SEvalZero __STATIC_INLINE uint32_t nrf_kmu_task_address_get(NRF_KMU_Type const * p_reg, nrf_kmu_task_t task)
203*150812a8SEvalZero {
204*150812a8SEvalZero     return ((uint32_t)p_reg + (uint32_t)task);
205*150812a8SEvalZero }
206*150812a8SEvalZero 
nrf_kmu_event_clear(NRF_KMU_Type * p_reg,nrf_kmu_event_t event)207*150812a8SEvalZero __STATIC_INLINE void nrf_kmu_event_clear(NRF_KMU_Type * p_reg, nrf_kmu_event_t event)
208*150812a8SEvalZero {
209*150812a8SEvalZero     *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
210*150812a8SEvalZero     volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
211*150812a8SEvalZero     (void)dummy;
212*150812a8SEvalZero }
213*150812a8SEvalZero 
nrf_kmu_event_check(NRF_KMU_Type const * p_reg,nrf_kmu_event_t event)214*150812a8SEvalZero __STATIC_INLINE bool nrf_kmu_event_check(NRF_KMU_Type const * p_reg, nrf_kmu_event_t event)
215*150812a8SEvalZero {
216*150812a8SEvalZero     return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
217*150812a8SEvalZero }
218*150812a8SEvalZero 
nrf_kmu_event_address_get(NRF_KMU_Type const * p_reg,nrf_kmu_event_t event)219*150812a8SEvalZero __STATIC_INLINE uint32_t nrf_kmu_event_address_get(NRF_KMU_Type const * p_reg,
220*150812a8SEvalZero                                                    nrf_kmu_event_t      event)
221*150812a8SEvalZero {
222*150812a8SEvalZero     return ((uint32_t)p_reg + (uint32_t)event);
223*150812a8SEvalZero }
224*150812a8SEvalZero 
nrf_kmu_int_enable(NRF_KMU_Type * p_reg,uint32_t mask)225*150812a8SEvalZero __STATIC_INLINE void nrf_kmu_int_enable(NRF_KMU_Type * p_reg, uint32_t mask)
226*150812a8SEvalZero {
227*150812a8SEvalZero     p_reg->INTENSET = mask;
228*150812a8SEvalZero }
229*150812a8SEvalZero 
nrf_kmu_int_disable(NRF_KMU_Type * p_reg,uint32_t mask)230*150812a8SEvalZero __STATIC_INLINE void nrf_kmu_int_disable(NRF_KMU_Type * p_reg, uint32_t mask)
231*150812a8SEvalZero {
232*150812a8SEvalZero     p_reg->INTENCLR = mask;
233*150812a8SEvalZero }
234*150812a8SEvalZero 
nrf_kmu_int_enable_check(NRF_KMU_Type const * p_reg,nrf_kmu_int_mask_t kmu_int)235*150812a8SEvalZero __STATIC_INLINE bool nrf_kmu_int_enable_check(NRF_KMU_Type const * p_reg,
236*150812a8SEvalZero                                               nrf_kmu_int_mask_t   kmu_int)
237*150812a8SEvalZero {
238*150812a8SEvalZero     return (bool)(p_reg->INTENSET & kmu_int);
239*150812a8SEvalZero }
240*150812a8SEvalZero 
nrf_kmu_intpend_get(NRF_KMU_Type const * p_reg)241*150812a8SEvalZero __STATIC_INLINE uint32_t nrf_kmu_intpend_get(NRF_KMU_Type const * p_reg)
242*150812a8SEvalZero {
243*150812a8SEvalZero     return p_reg->INTPEND;
244*150812a8SEvalZero }
245*150812a8SEvalZero 
nrf_kmu_status_get(NRF_KMU_Type const * p_reg)246*150812a8SEvalZero __STATIC_INLINE uint32_t nrf_kmu_status_get(NRF_KMU_Type const * p_reg)
247*150812a8SEvalZero {
248*150812a8SEvalZero     return p_reg->STATUS;
249*150812a8SEvalZero }
250*150812a8SEvalZero 
nrf_kmu_keyslot_set(NRF_KMU_Type * p_reg,uint8_t keyslot_id)251*150812a8SEvalZero __STATIC_INLINE void nrf_kmu_keyslot_set(NRF_KMU_Type * p_reg, uint8_t keyslot_id)
252*150812a8SEvalZero {
253*150812a8SEvalZero     p_reg->SELECTKEYSLOT = (uint32_t) keyslot_id;
254*150812a8SEvalZero }
255*150812a8SEvalZero 
nrf_kmu_keyslot_get(NRF_KMU_Type const * p_reg)256*150812a8SEvalZero __STATIC_INLINE uint8_t nrf_kmu_keyslot_get(NRF_KMU_Type const * p_reg)
257*150812a8SEvalZero {
258*150812a8SEvalZero     return (uint8_t) p_reg->SELECTKEYSLOT;
259*150812a8SEvalZero }
260*150812a8SEvalZero 
261*150812a8SEvalZero #endif // SUPPRESS_INLINE_IMPLEMENTATION
262*150812a8SEvalZero 
263*150812a8SEvalZero /** @} */
264*150812a8SEvalZero 
265*150812a8SEvalZero #ifdef __cplusplus
266*150812a8SEvalZero }
267*150812a8SEvalZero #endif
268*150812a8SEvalZero 
269*150812a8SEvalZero #endif // NRF_KMU_H__
270