1*150812a8SEvalZero /*
2*150812a8SEvalZero * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
3*150812a8SEvalZero * All rights reserved.
4*150812a8SEvalZero *
5*150812a8SEvalZero * Redistribution and use in source and binary forms, with or without
6*150812a8SEvalZero * modification, are permitted provided that the following conditions are met:
7*150812a8SEvalZero *
8*150812a8SEvalZero * 1. Redistributions of source code must retain the above copyright notice, this
9*150812a8SEvalZero * list of conditions and the following disclaimer.
10*150812a8SEvalZero *
11*150812a8SEvalZero * 2. Redistributions in binary form must reproduce the above copyright
12*150812a8SEvalZero * notice, this list of conditions and the following disclaimer in the
13*150812a8SEvalZero * documentation and/or other materials provided with the distribution.
14*150812a8SEvalZero *
15*150812a8SEvalZero * 3. Neither the name of the copyright holder nor the names of its
16*150812a8SEvalZero * contributors may be used to endorse or promote products derived from this
17*150812a8SEvalZero * software without specific prior written permission.
18*150812a8SEvalZero *
19*150812a8SEvalZero * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20*150812a8SEvalZero * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21*150812a8SEvalZero * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22*150812a8SEvalZero * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23*150812a8SEvalZero * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24*150812a8SEvalZero * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25*150812a8SEvalZero * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26*150812a8SEvalZero * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27*150812a8SEvalZero * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28*150812a8SEvalZero * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29*150812a8SEvalZero * POSSIBILITY OF SUCH DAMAGE.
30*150812a8SEvalZero */
31*150812a8SEvalZero
32*150812a8SEvalZero #ifndef NRF_GPIOTE_H__
33*150812a8SEvalZero #define NRF_GPIOTE_H__
34*150812a8SEvalZero
35*150812a8SEvalZero #include <nrfx.h>
36*150812a8SEvalZero
37*150812a8SEvalZero #ifdef __cplusplus
38*150812a8SEvalZero extern "C" {
39*150812a8SEvalZero #endif
40*150812a8SEvalZero
41*150812a8SEvalZero /**
42*150812a8SEvalZero * @defgroup nrf_gpiote_hal GPIOTE HAL
43*150812a8SEvalZero * @{
44*150812a8SEvalZero * @ingroup nrf_gpiote
45*150812a8SEvalZero * @brief Hardware access layer for managing the GPIOTE peripheral.
46*150812a8SEvalZero */
47*150812a8SEvalZero
48*150812a8SEvalZero #ifdef GPIOTE_CONFIG_PORT_Msk
49*150812a8SEvalZero #define GPIOTE_CONFIG_PORT_PIN_Msk (GPIOTE_CONFIG_PORT_Msk | GPIOTE_CONFIG_PSEL_Msk)
50*150812a8SEvalZero #else
51*150812a8SEvalZero #define GPIOTE_CONFIG_PORT_PIN_Msk GPIOTE_CONFIG_PSEL_Msk
52*150812a8SEvalZero #endif
53*150812a8SEvalZero
54*150812a8SEvalZero /**
55*150812a8SEvalZero * @enum nrf_gpiote_polarity_t
56*150812a8SEvalZero * @brief Polarity for the GPIOTE channel.
57*150812a8SEvalZero */
58*150812a8SEvalZero typedef enum
59*150812a8SEvalZero {
60*150812a8SEvalZero NRF_GPIOTE_POLARITY_LOTOHI = GPIOTE_CONFIG_POLARITY_LoToHi, ///< Low to high.
61*150812a8SEvalZero NRF_GPIOTE_POLARITY_HITOLO = GPIOTE_CONFIG_POLARITY_HiToLo, ///< High to low.
62*150812a8SEvalZero NRF_GPIOTE_POLARITY_TOGGLE = GPIOTE_CONFIG_POLARITY_Toggle ///< Toggle.
63*150812a8SEvalZero } nrf_gpiote_polarity_t;
64*150812a8SEvalZero
65*150812a8SEvalZero
66*150812a8SEvalZero /**
67*150812a8SEvalZero * @enum nrf_gpiote_outinit_t
68*150812a8SEvalZero * @brief Initial output value for the GPIOTE channel.
69*150812a8SEvalZero */
70*150812a8SEvalZero typedef enum
71*150812a8SEvalZero {
72*150812a8SEvalZero NRF_GPIOTE_INITIAL_VALUE_LOW = GPIOTE_CONFIG_OUTINIT_Low, ///< Low to high.
73*150812a8SEvalZero NRF_GPIOTE_INITIAL_VALUE_HIGH = GPIOTE_CONFIG_OUTINIT_High ///< High to low.
74*150812a8SEvalZero } nrf_gpiote_outinit_t;
75*150812a8SEvalZero
76*150812a8SEvalZero /**
77*150812a8SEvalZero * @brief Tasks.
78*150812a8SEvalZero */
79*150812a8SEvalZero typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
80*150812a8SEvalZero {
81*150812a8SEvalZero NRF_GPIOTE_TASKS_OUT_0 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[0]), /**< Out task 0.*/
82*150812a8SEvalZero NRF_GPIOTE_TASKS_OUT_1 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[1]), /**< Out task 1.*/
83*150812a8SEvalZero NRF_GPIOTE_TASKS_OUT_2 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[2]), /**< Out task 2.*/
84*150812a8SEvalZero NRF_GPIOTE_TASKS_OUT_3 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[3]), /**< Out task 3.*/
85*150812a8SEvalZero #if (GPIOTE_CH_NUM > 4) || defined(__NRFX_DOXYGEN__)
86*150812a8SEvalZero NRF_GPIOTE_TASKS_OUT_4 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[4]), /**< Out task 4.*/
87*150812a8SEvalZero NRF_GPIOTE_TASKS_OUT_5 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[5]), /**< Out task 5.*/
88*150812a8SEvalZero NRF_GPIOTE_TASKS_OUT_6 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[6]), /**< Out task 6.*/
89*150812a8SEvalZero NRF_GPIOTE_TASKS_OUT_7 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[7]), /**< Out task 7.*/
90*150812a8SEvalZero #endif
91*150812a8SEvalZero #if defined(GPIOTE_FEATURE_SET_PRESENT) || defined(__NRFX_DOXYGEN__)
92*150812a8SEvalZero NRF_GPIOTE_TASKS_SET_0 = offsetof(NRF_GPIOTE_Type, TASKS_SET[0]), /**< Set task 0.*/
93*150812a8SEvalZero NRF_GPIOTE_TASKS_SET_1 = offsetof(NRF_GPIOTE_Type, TASKS_SET[1]), /**< Set task 1.*/
94*150812a8SEvalZero NRF_GPIOTE_TASKS_SET_2 = offsetof(NRF_GPIOTE_Type, TASKS_SET[2]), /**< Set task 2.*/
95*150812a8SEvalZero NRF_GPIOTE_TASKS_SET_3 = offsetof(NRF_GPIOTE_Type, TASKS_SET[3]), /**< Set task 3.*/
96*150812a8SEvalZero NRF_GPIOTE_TASKS_SET_4 = offsetof(NRF_GPIOTE_Type, TASKS_SET[4]), /**< Set task 4.*/
97*150812a8SEvalZero NRF_GPIOTE_TASKS_SET_5 = offsetof(NRF_GPIOTE_Type, TASKS_SET[5]), /**< Set task 5.*/
98*150812a8SEvalZero NRF_GPIOTE_TASKS_SET_6 = offsetof(NRF_GPIOTE_Type, TASKS_SET[6]), /**< Set task 6.*/
99*150812a8SEvalZero NRF_GPIOTE_TASKS_SET_7 = offsetof(NRF_GPIOTE_Type, TASKS_SET[7]), /**< Set task 7.*/
100*150812a8SEvalZero #endif
101*150812a8SEvalZero #if defined(GPIOTE_FEATURE_CLR_PRESENT) || defined(__NRFX_DOXYGEN__)
102*150812a8SEvalZero NRF_GPIOTE_TASKS_CLR_0 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[0]), /**< Clear task 0.*/
103*150812a8SEvalZero NRF_GPIOTE_TASKS_CLR_1 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[1]), /**< Clear task 1.*/
104*150812a8SEvalZero NRF_GPIOTE_TASKS_CLR_2 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[2]), /**< Clear task 2.*/
105*150812a8SEvalZero NRF_GPIOTE_TASKS_CLR_3 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[3]), /**< Clear task 3.*/
106*150812a8SEvalZero NRF_GPIOTE_TASKS_CLR_4 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[4]), /**< Clear task 4.*/
107*150812a8SEvalZero NRF_GPIOTE_TASKS_CLR_5 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[5]), /**< Clear task 5.*/
108*150812a8SEvalZero NRF_GPIOTE_TASKS_CLR_6 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[6]), /**< Clear task 6.*/
109*150812a8SEvalZero NRF_GPIOTE_TASKS_CLR_7 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[7]), /**< Clear task 7.*/
110*150812a8SEvalZero #endif
111*150812a8SEvalZero /*lint -restore*/
112*150812a8SEvalZero } nrf_gpiote_tasks_t;
113*150812a8SEvalZero
114*150812a8SEvalZero /**
115*150812a8SEvalZero * @brief Events.
116*150812a8SEvalZero */
117*150812a8SEvalZero typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
118*150812a8SEvalZero {
119*150812a8SEvalZero NRF_GPIOTE_EVENTS_IN_0 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[0]), /**< In event 0.*/
120*150812a8SEvalZero NRF_GPIOTE_EVENTS_IN_1 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[1]), /**< In event 1.*/
121*150812a8SEvalZero NRF_GPIOTE_EVENTS_IN_2 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[2]), /**< In event 2.*/
122*150812a8SEvalZero NRF_GPIOTE_EVENTS_IN_3 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[3]), /**< In event 3.*/
123*150812a8SEvalZero #if (GPIOTE_CH_NUM > 4) || defined(__NRFX_DOXYGEN__)
124*150812a8SEvalZero NRF_GPIOTE_EVENTS_IN_4 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[4]), /**< In event 4.*/
125*150812a8SEvalZero NRF_GPIOTE_EVENTS_IN_5 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[5]), /**< In event 5.*/
126*150812a8SEvalZero NRF_GPIOTE_EVENTS_IN_6 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[6]), /**< In event 6.*/
127*150812a8SEvalZero NRF_GPIOTE_EVENTS_IN_7 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[7]), /**< In event 7.*/
128*150812a8SEvalZero #endif
129*150812a8SEvalZero NRF_GPIOTE_EVENTS_PORT = offsetof(NRF_GPIOTE_Type, EVENTS_PORT), /**< Port event.*/
130*150812a8SEvalZero /*lint -restore*/
131*150812a8SEvalZero } nrf_gpiote_events_t;
132*150812a8SEvalZero
133*150812a8SEvalZero /**
134*150812a8SEvalZero * @enum nrf_gpiote_int_t
135*150812a8SEvalZero * @brief GPIOTE interrupts.
136*150812a8SEvalZero */
137*150812a8SEvalZero typedef enum
138*150812a8SEvalZero {
139*150812a8SEvalZero NRF_GPIOTE_INT_IN0_MASK = GPIOTE_INTENSET_IN0_Msk, /**< GPIOTE interrupt from IN0. */
140*150812a8SEvalZero NRF_GPIOTE_INT_IN1_MASK = GPIOTE_INTENSET_IN1_Msk, /**< GPIOTE interrupt from IN1. */
141*150812a8SEvalZero NRF_GPIOTE_INT_IN2_MASK = GPIOTE_INTENSET_IN2_Msk, /**< GPIOTE interrupt from IN2. */
142*150812a8SEvalZero NRF_GPIOTE_INT_IN3_MASK = GPIOTE_INTENSET_IN3_Msk, /**< GPIOTE interrupt from IN3. */
143*150812a8SEvalZero #if (GPIOTE_CH_NUM > 4) || defined(__NRFX_DOXYGEN__)
144*150812a8SEvalZero NRF_GPIOTE_INT_IN4_MASK = GPIOTE_INTENSET_IN4_Msk, /**< GPIOTE interrupt from IN4. */
145*150812a8SEvalZero NRF_GPIOTE_INT_IN5_MASK = GPIOTE_INTENSET_IN5_Msk, /**< GPIOTE interrupt from IN5. */
146*150812a8SEvalZero NRF_GPIOTE_INT_IN6_MASK = GPIOTE_INTENSET_IN6_Msk, /**< GPIOTE interrupt from IN6. */
147*150812a8SEvalZero NRF_GPIOTE_INT_IN7_MASK = GPIOTE_INTENSET_IN7_Msk, /**< GPIOTE interrupt from IN7. */
148*150812a8SEvalZero #endif
149*150812a8SEvalZero NRF_GPIOTE_INT_PORT_MASK = (int)GPIOTE_INTENSET_PORT_Msk, /**< GPIOTE interrupt from PORT event. */
150*150812a8SEvalZero } nrf_gpiote_int_t;
151*150812a8SEvalZero
152*150812a8SEvalZero #define NRF_GPIOTE_INT_IN_MASK (NRF_GPIOTE_INT_IN0_MASK | NRF_GPIOTE_INT_IN1_MASK |\
153*150812a8SEvalZero NRF_GPIOTE_INT_IN2_MASK | NRF_GPIOTE_INT_IN3_MASK)
154*150812a8SEvalZero #if (GPIOTE_CH_NUM > 4)
155*150812a8SEvalZero #undef NRF_GPIOTE_INT_IN_MASK
156*150812a8SEvalZero #define NRF_GPIOTE_INT_IN_MASK (NRF_GPIOTE_INT_IN0_MASK | NRF_GPIOTE_INT_IN1_MASK |\
157*150812a8SEvalZero NRF_GPIOTE_INT_IN2_MASK | NRF_GPIOTE_INT_IN3_MASK |\
158*150812a8SEvalZero NRF_GPIOTE_INT_IN4_MASK | NRF_GPIOTE_INT_IN5_MASK |\
159*150812a8SEvalZero NRF_GPIOTE_INT_IN6_MASK | NRF_GPIOTE_INT_IN7_MASK)
160*150812a8SEvalZero #endif
161*150812a8SEvalZero
162*150812a8SEvalZero /**
163*150812a8SEvalZero * @brief Function for activating a specific GPIOTE task.
164*150812a8SEvalZero *
165*150812a8SEvalZero * @param[in] task Task.
166*150812a8SEvalZero */
167*150812a8SEvalZero __STATIC_INLINE void nrf_gpiote_task_set(nrf_gpiote_tasks_t task);
168*150812a8SEvalZero
169*150812a8SEvalZero /**
170*150812a8SEvalZero * @brief Function for getting the address of a specific GPIOTE task.
171*150812a8SEvalZero *
172*150812a8SEvalZero * @param[in] task Task.
173*150812a8SEvalZero *
174*150812a8SEvalZero * @returns Address.
175*150812a8SEvalZero */
176*150812a8SEvalZero __STATIC_INLINE uint32_t nrf_gpiote_task_addr_get(nrf_gpiote_tasks_t task);
177*150812a8SEvalZero
178*150812a8SEvalZero /**
179*150812a8SEvalZero * @brief Function for getting the state of a specific GPIOTE event.
180*150812a8SEvalZero *
181*150812a8SEvalZero * @param[in] event Event.
182*150812a8SEvalZero */
183*150812a8SEvalZero __STATIC_INLINE bool nrf_gpiote_event_is_set(nrf_gpiote_events_t event);
184*150812a8SEvalZero
185*150812a8SEvalZero /**
186*150812a8SEvalZero * @brief Function for clearing a specific GPIOTE event.
187*150812a8SEvalZero *
188*150812a8SEvalZero * @param[in] event Event.
189*150812a8SEvalZero */
190*150812a8SEvalZero __STATIC_INLINE void nrf_gpiote_event_clear(nrf_gpiote_events_t event);
191*150812a8SEvalZero
192*150812a8SEvalZero /**
193*150812a8SEvalZero * @brief Function for getting the address of a specific GPIOTE event.
194*150812a8SEvalZero *
195*150812a8SEvalZero * @param[in] event Event.
196*150812a8SEvalZero *
197*150812a8SEvalZero * @return Address
198*150812a8SEvalZero */
199*150812a8SEvalZero __STATIC_INLINE uint32_t nrf_gpiote_event_addr_get(nrf_gpiote_events_t event);
200*150812a8SEvalZero
201*150812a8SEvalZero /**@brief Function for enabling interrupts.
202*150812a8SEvalZero *
203*150812a8SEvalZero * @param[in] mask Interrupt mask to be enabled.
204*150812a8SEvalZero */
205*150812a8SEvalZero __STATIC_INLINE void nrf_gpiote_int_enable(uint32_t mask);
206*150812a8SEvalZero
207*150812a8SEvalZero /**@brief Function for disabling interrupts.
208*150812a8SEvalZero *
209*150812a8SEvalZero * @param[in] mask Interrupt mask to be disabled.
210*150812a8SEvalZero */
211*150812a8SEvalZero __STATIC_INLINE void nrf_gpiote_int_disable(uint32_t mask);
212*150812a8SEvalZero
213*150812a8SEvalZero /**@brief Function for checking if interrupts are enabled.
214*150812a8SEvalZero *
215*150812a8SEvalZero * @param[in] mask Mask of interrupt flags to check.
216*150812a8SEvalZero *
217*150812a8SEvalZero * @return Mask with enabled interrupts.
218*150812a8SEvalZero */
219*150812a8SEvalZero __STATIC_INLINE uint32_t nrf_gpiote_int_is_enabled(uint32_t mask);
220*150812a8SEvalZero
221*150812a8SEvalZero #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
222*150812a8SEvalZero /**
223*150812a8SEvalZero * @brief Function for setting the subscribe configuration for a given
224*150812a8SEvalZero * GPIOTE task.
225*150812a8SEvalZero *
226*150812a8SEvalZero * @param[in] task Task for which to set the configuration.
227*150812a8SEvalZero * @param[in] channel Channel through which to subscribe events.
228*150812a8SEvalZero */
229*150812a8SEvalZero __STATIC_INLINE void nrf_gpiote_subscribe_set(nrf_gpiote_tasks_t task,
230*150812a8SEvalZero uint8_t channel);
231*150812a8SEvalZero
232*150812a8SEvalZero /**
233*150812a8SEvalZero * @brief Function for clearing the subscribe configuration for a given
234*150812a8SEvalZero * GPIOTE task.
235*150812a8SEvalZero *
236*150812a8SEvalZero * @param[in] task Task for which to clear the configuration.
237*150812a8SEvalZero */
238*150812a8SEvalZero __STATIC_INLINE void nrf_gpiote_subscribe_clear(nrf_gpiote_tasks_t task);
239*150812a8SEvalZero
240*150812a8SEvalZero /**
241*150812a8SEvalZero * @brief Function for setting the publish configuration for a given
242*150812a8SEvalZero * GPIOTE event.
243*150812a8SEvalZero *
244*150812a8SEvalZero * @param[in] event Event for which to set the configuration.
245*150812a8SEvalZero * @param[in] channel Channel through which to publish the event.
246*150812a8SEvalZero */
247*150812a8SEvalZero __STATIC_INLINE void nrf_gpiote_publish_set(nrf_gpiote_events_t event,
248*150812a8SEvalZero uint8_t channel);
249*150812a8SEvalZero
250*150812a8SEvalZero /**
251*150812a8SEvalZero * @brief Function for clearing the publish configuration for a given
252*150812a8SEvalZero * GPIOTE event.
253*150812a8SEvalZero *
254*150812a8SEvalZero * @param[in] event Event for which to clear the configuration.
255*150812a8SEvalZero */
256*150812a8SEvalZero __STATIC_INLINE void nrf_gpiote_publish_clear(nrf_gpiote_events_t event);
257*150812a8SEvalZero #endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
258*150812a8SEvalZero
259*150812a8SEvalZero /**@brief Function for enabling a GPIOTE event.
260*150812a8SEvalZero *
261*150812a8SEvalZero * @param[in] idx Task-Event index.
262*150812a8SEvalZero */
263*150812a8SEvalZero __STATIC_INLINE void nrf_gpiote_event_enable(uint32_t idx);
264*150812a8SEvalZero
265*150812a8SEvalZero /**@brief Function for disabling a GPIOTE event.
266*150812a8SEvalZero *
267*150812a8SEvalZero * @param[in] idx Task-Event index.
268*150812a8SEvalZero */
269*150812a8SEvalZero __STATIC_INLINE void nrf_gpiote_event_disable(uint32_t idx);
270*150812a8SEvalZero
271*150812a8SEvalZero /**@brief Function for configuring a GPIOTE event.
272*150812a8SEvalZero *
273*150812a8SEvalZero * @param[in] idx Task-Event index.
274*150812a8SEvalZero * @param[in] pin Pin associated with event.
275*150812a8SEvalZero * @param[in] polarity Transition that should generate an event.
276*150812a8SEvalZero */
277*150812a8SEvalZero __STATIC_INLINE void nrf_gpiote_event_configure(uint32_t idx, uint32_t pin,
278*150812a8SEvalZero nrf_gpiote_polarity_t polarity);
279*150812a8SEvalZero
280*150812a8SEvalZero /**@brief Function for getting the pin associated with a GPIOTE event.
281*150812a8SEvalZero *
282*150812a8SEvalZero * @param[in] idx Task-Event index.
283*150812a8SEvalZero *
284*150812a8SEvalZero * @return Pin number.
285*150812a8SEvalZero */
286*150812a8SEvalZero __STATIC_INLINE uint32_t nrf_gpiote_event_pin_get(uint32_t idx);
287*150812a8SEvalZero
288*150812a8SEvalZero /**@brief Function for getting the polarity associated with a GPIOTE event.
289*150812a8SEvalZero *
290*150812a8SEvalZero * @param[in] idx Task-Event index.
291*150812a8SEvalZero *
292*150812a8SEvalZero * @return Polarity.
293*150812a8SEvalZero */
294*150812a8SEvalZero __STATIC_INLINE nrf_gpiote_polarity_t nrf_gpiote_event_polarity_get(uint32_t idx);
295*150812a8SEvalZero
296*150812a8SEvalZero /**@brief Function for enabling a GPIOTE task.
297*150812a8SEvalZero *
298*150812a8SEvalZero * @param[in] idx Task-Event index.
299*150812a8SEvalZero */
300*150812a8SEvalZero __STATIC_INLINE void nrf_gpiote_task_enable(uint32_t idx);
301*150812a8SEvalZero
302*150812a8SEvalZero /**@brief Function for disabling a GPIOTE task.
303*150812a8SEvalZero *
304*150812a8SEvalZero * @param[in] idx Task-Event index.
305*150812a8SEvalZero */
306*150812a8SEvalZero __STATIC_INLINE void nrf_gpiote_task_disable(uint32_t idx);
307*150812a8SEvalZero
308*150812a8SEvalZero /**@brief Function for configuring a GPIOTE task.
309*150812a8SEvalZero * @note Function is not configuring mode field so task is disabled after this function is called.
310*150812a8SEvalZero *
311*150812a8SEvalZero * @param[in] idx Task-Event index.
312*150812a8SEvalZero * @param[in] pin Pin associated with event.
313*150812a8SEvalZero * @param[in] polarity Transition that should generate an event.
314*150812a8SEvalZero * @param[in] init_val Initial value of the pin.
315*150812a8SEvalZero */
316*150812a8SEvalZero __STATIC_INLINE void nrf_gpiote_task_configure(uint32_t idx, uint32_t pin,
317*150812a8SEvalZero nrf_gpiote_polarity_t polarity,
318*150812a8SEvalZero nrf_gpiote_outinit_t init_val);
319*150812a8SEvalZero
320*150812a8SEvalZero /**@brief Function for forcing a specific state on the pin connected to GPIOTE.
321*150812a8SEvalZero *
322*150812a8SEvalZero * @param[in] idx Task-Event index.
323*150812a8SEvalZero * @param[in] init_val Pin state.
324*150812a8SEvalZero */
325*150812a8SEvalZero __STATIC_INLINE void nrf_gpiote_task_force(uint32_t idx, nrf_gpiote_outinit_t init_val);
326*150812a8SEvalZero
327*150812a8SEvalZero /**@brief Function for resetting a GPIOTE task event configuration to the default state.
328*150812a8SEvalZero *
329*150812a8SEvalZero * @param[in] idx Task-Event index.
330*150812a8SEvalZero */
331*150812a8SEvalZero __STATIC_INLINE void nrf_gpiote_te_default(uint32_t idx);
332*150812a8SEvalZero
333*150812a8SEvalZero /**@brief Function for checking if particular Task-Event is enabled.
334*150812a8SEvalZero *
335*150812a8SEvalZero * @param[in] idx Task-Event index.
336*150812a8SEvalZero *
337*150812a8SEvalZero * @retval true If the Task-Event mode is set to Task or Event.
338*150812a8SEvalZero * @retval false If the Task-Event mode is set to Disabled.
339*150812a8SEvalZero */
340*150812a8SEvalZero __STATIC_INLINE bool nrf_gpiote_te_is_enabled(uint32_t idx);
341*150812a8SEvalZero
342*150812a8SEvalZero #ifndef SUPPRESS_INLINE_IMPLEMENTATION
nrf_gpiote_task_set(nrf_gpiote_tasks_t task)343*150812a8SEvalZero __STATIC_INLINE void nrf_gpiote_task_set(nrf_gpiote_tasks_t task)
344*150812a8SEvalZero {
345*150812a8SEvalZero *(__IO uint32_t *)((uint32_t)NRF_GPIOTE + task) = 0x1UL;
346*150812a8SEvalZero }
347*150812a8SEvalZero
nrf_gpiote_task_addr_get(nrf_gpiote_tasks_t task)348*150812a8SEvalZero __STATIC_INLINE uint32_t nrf_gpiote_task_addr_get(nrf_gpiote_tasks_t task)
349*150812a8SEvalZero {
350*150812a8SEvalZero return ((uint32_t)NRF_GPIOTE + task);
351*150812a8SEvalZero }
352*150812a8SEvalZero
nrf_gpiote_event_is_set(nrf_gpiote_events_t event)353*150812a8SEvalZero __STATIC_INLINE bool nrf_gpiote_event_is_set(nrf_gpiote_events_t event)
354*150812a8SEvalZero {
355*150812a8SEvalZero return (*(uint32_t *)nrf_gpiote_event_addr_get(event) == 0x1UL) ? true : false;
356*150812a8SEvalZero }
357*150812a8SEvalZero
nrf_gpiote_event_clear(nrf_gpiote_events_t event)358*150812a8SEvalZero __STATIC_INLINE void nrf_gpiote_event_clear(nrf_gpiote_events_t event)
359*150812a8SEvalZero {
360*150812a8SEvalZero *(uint32_t *)nrf_gpiote_event_addr_get(event) = 0;
361*150812a8SEvalZero #if __CORTEX_M == 0x04
362*150812a8SEvalZero volatile uint32_t dummy = *((volatile uint32_t *)nrf_gpiote_event_addr_get(event));
363*150812a8SEvalZero (void)dummy;
364*150812a8SEvalZero #endif
365*150812a8SEvalZero }
366*150812a8SEvalZero
nrf_gpiote_event_addr_get(nrf_gpiote_events_t event)367*150812a8SEvalZero __STATIC_INLINE uint32_t nrf_gpiote_event_addr_get(nrf_gpiote_events_t event)
368*150812a8SEvalZero {
369*150812a8SEvalZero return ((uint32_t)NRF_GPIOTE + event);
370*150812a8SEvalZero }
371*150812a8SEvalZero
nrf_gpiote_int_enable(uint32_t mask)372*150812a8SEvalZero __STATIC_INLINE void nrf_gpiote_int_enable(uint32_t mask)
373*150812a8SEvalZero {
374*150812a8SEvalZero NRF_GPIOTE->INTENSET = mask;
375*150812a8SEvalZero }
376*150812a8SEvalZero
nrf_gpiote_int_disable(uint32_t mask)377*150812a8SEvalZero __STATIC_INLINE void nrf_gpiote_int_disable(uint32_t mask)
378*150812a8SEvalZero {
379*150812a8SEvalZero NRF_GPIOTE->INTENCLR = mask;
380*150812a8SEvalZero }
381*150812a8SEvalZero
nrf_gpiote_int_is_enabled(uint32_t mask)382*150812a8SEvalZero __STATIC_INLINE uint32_t nrf_gpiote_int_is_enabled(uint32_t mask)
383*150812a8SEvalZero {
384*150812a8SEvalZero return (NRF_GPIOTE->INTENSET & mask);
385*150812a8SEvalZero }
386*150812a8SEvalZero
387*150812a8SEvalZero #if defined(DPPI_PRESENT)
nrf_gpiote_subscribe_set(nrf_gpiote_tasks_t task,uint8_t channel)388*150812a8SEvalZero __STATIC_INLINE void nrf_gpiote_subscribe_set(nrf_gpiote_tasks_t task,
389*150812a8SEvalZero uint8_t channel)
390*150812a8SEvalZero {
391*150812a8SEvalZero *((volatile uint32_t *) ((uint8_t *) NRF_GPIOTE + (uint32_t) task + 0x80uL)) =
392*150812a8SEvalZero ((uint32_t)channel | GPIOTE_SUBSCRIBE_OUT_EN_Msk);
393*150812a8SEvalZero }
394*150812a8SEvalZero
nrf_gpiote_subscribe_clear(nrf_gpiote_tasks_t task)395*150812a8SEvalZero __STATIC_INLINE void nrf_gpiote_subscribe_clear(nrf_gpiote_tasks_t task)
396*150812a8SEvalZero {
397*150812a8SEvalZero *((volatile uint32_t *) ((uint8_t *) NRF_GPIOTE + (uint32_t) task + 0x80uL)) = 0;
398*150812a8SEvalZero }
399*150812a8SEvalZero
nrf_gpiote_publish_set(nrf_gpiote_events_t event,uint8_t channel)400*150812a8SEvalZero __STATIC_INLINE void nrf_gpiote_publish_set(nrf_gpiote_events_t event,
401*150812a8SEvalZero uint8_t channel)
402*150812a8SEvalZero {
403*150812a8SEvalZero *((volatile uint32_t *) ((uint8_t *) NRF_GPIOTE + (uint32_t) event + 0x80uL)) =
404*150812a8SEvalZero ((uint32_t)channel | GPIOTE_PUBLISH_IN_EN_Msk);
405*150812a8SEvalZero }
406*150812a8SEvalZero
nrf_gpiote_publish_clear(nrf_gpiote_events_t event)407*150812a8SEvalZero __STATIC_INLINE void nrf_gpiote_publish_clear(nrf_gpiote_events_t event)
408*150812a8SEvalZero {
409*150812a8SEvalZero *((volatile uint32_t *) ((uint8_t *) NRF_GPIOTE + (uint32_t) event + 0x80uL)) = 0;
410*150812a8SEvalZero }
411*150812a8SEvalZero #endif // defined(DPPI_PRESENT)
412*150812a8SEvalZero
nrf_gpiote_event_enable(uint32_t idx)413*150812a8SEvalZero __STATIC_INLINE void nrf_gpiote_event_enable(uint32_t idx)
414*150812a8SEvalZero {
415*150812a8SEvalZero NRF_GPIOTE->CONFIG[idx] |= GPIOTE_CONFIG_MODE_Event;
416*150812a8SEvalZero }
417*150812a8SEvalZero
nrf_gpiote_event_disable(uint32_t idx)418*150812a8SEvalZero __STATIC_INLINE void nrf_gpiote_event_disable(uint32_t idx)
419*150812a8SEvalZero {
420*150812a8SEvalZero NRF_GPIOTE->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Event;
421*150812a8SEvalZero }
422*150812a8SEvalZero
nrf_gpiote_event_configure(uint32_t idx,uint32_t pin,nrf_gpiote_polarity_t polarity)423*150812a8SEvalZero __STATIC_INLINE void nrf_gpiote_event_configure(uint32_t idx, uint32_t pin, nrf_gpiote_polarity_t polarity)
424*150812a8SEvalZero {
425*150812a8SEvalZero NRF_GPIOTE->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk | GPIOTE_CONFIG_POLARITY_Msk);
426*150812a8SEvalZero NRF_GPIOTE->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
427*150812a8SEvalZero ((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk);
428*150812a8SEvalZero }
429*150812a8SEvalZero
nrf_gpiote_event_pin_get(uint32_t idx)430*150812a8SEvalZero __STATIC_INLINE uint32_t nrf_gpiote_event_pin_get(uint32_t idx)
431*150812a8SEvalZero {
432*150812a8SEvalZero return ((NRF_GPIOTE->CONFIG[idx] & GPIOTE_CONFIG_PORT_PIN_Msk) >> GPIOTE_CONFIG_PSEL_Pos);
433*150812a8SEvalZero }
434*150812a8SEvalZero
nrf_gpiote_event_polarity_get(uint32_t idx)435*150812a8SEvalZero __STATIC_INLINE nrf_gpiote_polarity_t nrf_gpiote_event_polarity_get(uint32_t idx)
436*150812a8SEvalZero {
437*150812a8SEvalZero return (nrf_gpiote_polarity_t)((NRF_GPIOTE->CONFIG[idx] & GPIOTE_CONFIG_POLARITY_Msk) >> GPIOTE_CONFIG_POLARITY_Pos);
438*150812a8SEvalZero }
439*150812a8SEvalZero
nrf_gpiote_task_enable(uint32_t idx)440*150812a8SEvalZero __STATIC_INLINE void nrf_gpiote_task_enable(uint32_t idx)
441*150812a8SEvalZero {
442*150812a8SEvalZero uint32_t final_config = NRF_GPIOTE->CONFIG[idx] | GPIOTE_CONFIG_MODE_Task;
443*150812a8SEvalZero #ifdef NRF51
444*150812a8SEvalZero /* Workaround for the OUTINIT PAN. When nrf_gpiote_task_config() is called a glitch happens
445*150812a8SEvalZero on the GPIO if the GPIO in question is already assigned to GPIOTE and the pin is in the
446*150812a8SEvalZero correct state in GPIOTE but not in the OUT register. */
447*150812a8SEvalZero /* Configure channel to not existing, not connected to the pin, and configure as a tasks that will set it to proper level */
448*150812a8SEvalZero NRF_GPIOTE->CONFIG[idx] = final_config | (((31) << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk);
449*150812a8SEvalZero __NOP();
450*150812a8SEvalZero __NOP();
451*150812a8SEvalZero __NOP();
452*150812a8SEvalZero #endif
453*150812a8SEvalZero NRF_GPIOTE->CONFIG[idx] = final_config;
454*150812a8SEvalZero }
455*150812a8SEvalZero
nrf_gpiote_task_disable(uint32_t idx)456*150812a8SEvalZero __STATIC_INLINE void nrf_gpiote_task_disable(uint32_t idx)
457*150812a8SEvalZero {
458*150812a8SEvalZero NRF_GPIOTE->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Task;
459*150812a8SEvalZero }
460*150812a8SEvalZero
nrf_gpiote_task_configure(uint32_t idx,uint32_t pin,nrf_gpiote_polarity_t polarity,nrf_gpiote_outinit_t init_val)461*150812a8SEvalZero __STATIC_INLINE void nrf_gpiote_task_configure(uint32_t idx, uint32_t pin,
462*150812a8SEvalZero nrf_gpiote_polarity_t polarity,
463*150812a8SEvalZero nrf_gpiote_outinit_t init_val)
464*150812a8SEvalZero {
465*150812a8SEvalZero NRF_GPIOTE->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk |
466*150812a8SEvalZero GPIOTE_CONFIG_POLARITY_Msk |
467*150812a8SEvalZero GPIOTE_CONFIG_OUTINIT_Msk);
468*150812a8SEvalZero
469*150812a8SEvalZero NRF_GPIOTE->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
470*150812a8SEvalZero ((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk) |
471*150812a8SEvalZero ((init_val << GPIOTE_CONFIG_OUTINIT_Pos) & GPIOTE_CONFIG_OUTINIT_Msk);
472*150812a8SEvalZero }
473*150812a8SEvalZero
nrf_gpiote_task_force(uint32_t idx,nrf_gpiote_outinit_t init_val)474*150812a8SEvalZero __STATIC_INLINE void nrf_gpiote_task_force(uint32_t idx, nrf_gpiote_outinit_t init_val)
475*150812a8SEvalZero {
476*150812a8SEvalZero NRF_GPIOTE->CONFIG[idx] = (NRF_GPIOTE->CONFIG[idx] & ~GPIOTE_CONFIG_OUTINIT_Msk)
477*150812a8SEvalZero | ((init_val << GPIOTE_CONFIG_OUTINIT_Pos) & GPIOTE_CONFIG_OUTINIT_Msk);
478*150812a8SEvalZero }
479*150812a8SEvalZero
nrf_gpiote_te_default(uint32_t idx)480*150812a8SEvalZero __STATIC_INLINE void nrf_gpiote_te_default(uint32_t idx)
481*150812a8SEvalZero {
482*150812a8SEvalZero NRF_GPIOTE->CONFIG[idx] = 0;
483*150812a8SEvalZero }
484*150812a8SEvalZero
nrf_gpiote_te_is_enabled(uint32_t idx)485*150812a8SEvalZero __STATIC_INLINE bool nrf_gpiote_te_is_enabled(uint32_t idx)
486*150812a8SEvalZero {
487*150812a8SEvalZero return (NRF_GPIOTE->CONFIG[idx] & GPIOTE_CONFIG_MODE_Msk) != GPIOTE_CONFIG_MODE_Disabled;
488*150812a8SEvalZero }
489*150812a8SEvalZero #endif //SUPPRESS_INLINE_IMPLEMENTATION
490*150812a8SEvalZero
491*150812a8SEvalZero /** @} */
492*150812a8SEvalZero
493*150812a8SEvalZero #ifdef __cplusplus
494*150812a8SEvalZero }
495*150812a8SEvalZero #endif
496*150812a8SEvalZero
497*150812a8SEvalZero #endif
498