1 /*
2 * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice, this
9 * list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the copyright holder nor the names of its
16 * contributors may be used to endorse or promote products derived from this
17 * software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #ifndef NRF_GPIO_H__
33 #define NRF_GPIO_H__
34
35 #include <nrfx.h>
36
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40
41 /**
42 * @defgroup nrf_gpio_hal GPIO HAL
43 * @{
44 * @ingroup nrf_gpio
45 * @brief Hardware access layer for managing the GPIO peripheral.
46 */
47
48 #ifndef NRF_P0
49 #define NRF_P0 NRF_GPIO
50 #endif
51
52 #if (GPIO_COUNT == 1)
53 #define NUMBER_OF_PINS (P0_PIN_NUM)
54 #define GPIO_REG_LIST {NRF_P0}
55 #elif (GPIO_COUNT == 2)
56 #define NUMBER_OF_PINS (P0_PIN_NUM + P1_PIN_NUM)
57 #define GPIO_REG_LIST {NRF_P0, NRF_P1}
58 #else
59 #error "Not supported."
60 #endif
61
62
63 /**
64 * @brief Macro for mapping port and pin numbers to values understandable for nrf_gpio functions.
65 */
66 #define NRF_GPIO_PIN_MAP(port, pin) (((port) << 5) | ((pin) & 0x1F))
67
68 /**
69 * @brief Pin direction definitions.
70 */
71 typedef enum
72 {
73 NRF_GPIO_PIN_DIR_INPUT = GPIO_PIN_CNF_DIR_Input, ///< Input.
74 NRF_GPIO_PIN_DIR_OUTPUT = GPIO_PIN_CNF_DIR_Output ///< Output.
75 } nrf_gpio_pin_dir_t;
76
77 /**
78 * @brief Connection of input buffer.
79 */
80 typedef enum
81 {
82 NRF_GPIO_PIN_INPUT_CONNECT = GPIO_PIN_CNF_INPUT_Connect, ///< Connect input buffer.
83 NRF_GPIO_PIN_INPUT_DISCONNECT = GPIO_PIN_CNF_INPUT_Disconnect ///< Disconnect input buffer.
84 } nrf_gpio_pin_input_t;
85
86 /**
87 * @brief Enumerator used for selecting the pin to be pulled down or up at the time of pin configuration.
88 */
89 typedef enum
90 {
91 NRF_GPIO_PIN_NOPULL = GPIO_PIN_CNF_PULL_Disabled, ///< Pin pull-up resistor disabled.
92 NRF_GPIO_PIN_PULLDOWN = GPIO_PIN_CNF_PULL_Pulldown, ///< Pin pull-down resistor enabled.
93 NRF_GPIO_PIN_PULLUP = GPIO_PIN_CNF_PULL_Pullup, ///< Pin pull-up resistor enabled.
94 } nrf_gpio_pin_pull_t;
95
96 /**
97 * @brief Enumerator used for selecting output drive mode.
98 */
99 typedef enum
100 {
101 NRF_GPIO_PIN_S0S1 = GPIO_PIN_CNF_DRIVE_S0S1, ///< !< Standard '0', standard '1'.
102 NRF_GPIO_PIN_H0S1 = GPIO_PIN_CNF_DRIVE_H0S1, ///< !< High-drive '0', standard '1'.
103 NRF_GPIO_PIN_S0H1 = GPIO_PIN_CNF_DRIVE_S0H1, ///< !< Standard '0', high-drive '1'.
104 NRF_GPIO_PIN_H0H1 = GPIO_PIN_CNF_DRIVE_H0H1, ///< !< High drive '0', high-drive '1'.
105 NRF_GPIO_PIN_D0S1 = GPIO_PIN_CNF_DRIVE_D0S1, ///< !< Disconnect '0' standard '1'.
106 NRF_GPIO_PIN_D0H1 = GPIO_PIN_CNF_DRIVE_D0H1, ///< !< Disconnect '0', high-drive '1'.
107 NRF_GPIO_PIN_S0D1 = GPIO_PIN_CNF_DRIVE_S0D1, ///< !< Standard '0', disconnect '1'.
108 NRF_GPIO_PIN_H0D1 = GPIO_PIN_CNF_DRIVE_H0D1, ///< !< High-drive '0', disconnect '1'.
109 } nrf_gpio_pin_drive_t;
110
111 /**
112 * @brief Enumerator used for selecting the pin to sense high or low level on the pin input.
113 */
114 typedef enum
115 {
116 NRF_GPIO_PIN_NOSENSE = GPIO_PIN_CNF_SENSE_Disabled, ///< Pin sense level disabled.
117 NRF_GPIO_PIN_SENSE_LOW = GPIO_PIN_CNF_SENSE_Low, ///< Pin sense low level.
118 NRF_GPIO_PIN_SENSE_HIGH = GPIO_PIN_CNF_SENSE_High, ///< Pin sense high level.
119 } nrf_gpio_pin_sense_t;
120
121 /**
122 * @brief Function for configuring the GPIO pin range as output pins with normal drive strength.
123 * This function can be used to configure pin range as simple output with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases).
124 *
125 * @param pin_range_start Specifies the start number (inclusive) in the range of pin numbers to be configured (allowed values 0-30).
126 *
127 * @param pin_range_end Specifies the end number (inclusive) in the range of pin numbers to be configured (allowed values 0-30).
128 *
129 * @note For configuring only one pin as output, use @ref nrf_gpio_cfg_output.
130 * Sense capability on the pin is disabled and input is disconnected from the buffer as the pins are configured as output.
131 */
132 __STATIC_INLINE void nrf_gpio_range_cfg_output(uint32_t pin_range_start, uint32_t pin_range_end);
133
134 /**
135 * @brief Function for configuring the GPIO pin range as input pins with given initial value set, hiding inner details.
136 * This function can be used to configure pin range as simple input.
137 *
138 * @param pin_range_start Specifies the start number (inclusive) in the range of pin numbers to be configured (allowed values 0-30).
139 *
140 * @param pin_range_end Specifies the end number (inclusive) in the range of pin numbers to be configured (allowed values 0-30).
141 *
142 * @param pull_config State of the pin range pull resistor (no pull, pulled down, or pulled high).
143 *
144 * @note For configuring only one pin as input, use @ref nrf_gpio_cfg_input.
145 * Sense capability on the pin is disabled and input is connected to buffer so that the GPIO->IN register is readable.
146 */
147 __STATIC_INLINE void nrf_gpio_range_cfg_input(uint32_t pin_range_start,
148 uint32_t pin_range_end,
149 nrf_gpio_pin_pull_t pull_config);
150
151 /**
152 * @brief Pin configuration function.
153 *
154 * The main pin configuration function.
155 * This function allows to set any aspect in PIN_CNF register.
156 * @param pin_number Specifies the pin number.
157 * @param dir Pin direction.
158 * @param input Connect or disconnect the input buffer.
159 * @param pull Pull configuration.
160 * @param drive Drive configuration.
161 * @param sense Pin sensing mechanism.
162 */
163 __STATIC_INLINE void nrf_gpio_cfg(
164 uint32_t pin_number,
165 nrf_gpio_pin_dir_t dir,
166 nrf_gpio_pin_input_t input,
167 nrf_gpio_pin_pull_t pull,
168 nrf_gpio_pin_drive_t drive,
169 nrf_gpio_pin_sense_t sense);
170
171 /**
172 * @brief Function for configuring the given GPIO pin number as output, hiding inner details.
173 * This function can be used to configure a pin as simple output with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases).
174 *
175 * @param pin_number Specifies the pin number.
176 *
177 * @note Sense capability on the pin is disabled and input is disconnected from the buffer as the pins are configured as output.
178 */
179 __STATIC_INLINE void nrf_gpio_cfg_output(uint32_t pin_number);
180
181 /**
182 * @brief Function for configuring the given GPIO pin number as input, hiding inner details.
183 * This function can be used to configure a pin as simple input.
184 *
185 * @param pin_number Specifies the pin number.
186 * @param pull_config State of the pin range pull resistor (no pull, pulled down, or pulled high).
187 *
188 * @note Sense capability on the pin is disabled and input is connected to buffer so that the GPIO->IN register is readable.
189 */
190 __STATIC_INLINE void nrf_gpio_cfg_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config);
191
192 /**
193 * @brief Function for resetting pin configuration to its default state.
194 *
195 * @param pin_number Specifies the pin number.
196 */
197 __STATIC_INLINE void nrf_gpio_cfg_default(uint32_t pin_number);
198
199 /**
200 * @brief Function for configuring the given GPIO pin number as a watcher. Only input is connected.
201 *
202 * @param pin_number Specifies the pin number.
203 *
204 */
205 __STATIC_INLINE void nrf_gpio_cfg_watcher(uint32_t pin_number);
206
207 /**
208 * @brief Function for disconnecting input for the given GPIO.
209 *
210 * @param pin_number Specifies the pin number.
211 *
212 */
213 __STATIC_INLINE void nrf_gpio_input_disconnect(uint32_t pin_number);
214
215 /**
216 * @brief Function for configuring the given GPIO pin number as input, hiding inner details.
217 * This function can be used to configure pin range as simple input.
218 * Sense capability on the pin is configurable and input is connected to buffer so that the GPIO->IN register is readable.
219 *
220 * @param pin_number Specifies the pin number.
221 * @param pull_config State of the pin pull resistor (no pull, pulled down, or pulled high).
222 * @param sense_config Sense level of the pin (no sense, sense low, or sense high).
223 */
224 __STATIC_INLINE void nrf_gpio_cfg_sense_input(uint32_t pin_number,
225 nrf_gpio_pin_pull_t pull_config,
226 nrf_gpio_pin_sense_t sense_config);
227
228 /**
229 * @brief Function for configuring sense level for the given GPIO.
230 *
231 * @param pin_number Specifies the pin number.
232 * @param sense_config Sense configuration.
233 *
234 */
235 __STATIC_INLINE void nrf_gpio_cfg_sense_set(uint32_t pin_number, nrf_gpio_pin_sense_t sense_config);
236
237 /**
238 * @brief Function for setting the direction for a GPIO pin.
239 *
240 * @param pin_number Specifies the pin number for which to set the direction.
241 *
242 * @param direction Specifies the direction.
243 */
244 __STATIC_INLINE void nrf_gpio_pin_dir_set(uint32_t pin_number, nrf_gpio_pin_dir_t direction);
245
246 /**
247 * @brief Function for setting a GPIO pin.
248 *
249 * Note that the pin must be configured as an output for this function to have any effect.
250 *
251 * @param pin_number Specifies the pin number to set.
252 */
253 __STATIC_INLINE void nrf_gpio_pin_set(uint32_t pin_number);
254
255 /**
256 * @brief Function for clearing a GPIO pin.
257 *
258 * Note that the pin must be configured as an output for this
259 * function to have any effect.
260 *
261 * @param pin_number Specifies the pin number to clear.
262 */
263 __STATIC_INLINE void nrf_gpio_pin_clear(uint32_t pin_number);
264
265 /**
266 * @brief Function for toggling a GPIO pin.
267 *
268 * Note that the pin must be configured as an output for this
269 * function to have any effect.
270 *
271 * @param pin_number Specifies the pin number to toggle.
272 */
273 __STATIC_INLINE void nrf_gpio_pin_toggle(uint32_t pin_number);
274
275 /**
276 * @brief Function for writing a value to a GPIO pin.
277 *
278 * Note that the pin must be configured as an output for this
279 * function to have any effect.
280 *
281 * @param pin_number Specifies the pin number to write.
282 *
283 * @param value Specifies the value to be written to the pin.
284 * @arg 0 Clears the pin.
285 * @arg >=1 Sets the pin.
286 */
287 __STATIC_INLINE void nrf_gpio_pin_write(uint32_t pin_number, uint32_t value);
288
289 /**
290 * @brief Function for reading the input level of a GPIO pin.
291 *
292 * Note that the pin must have input connected for the value
293 * returned from this function to be valid.
294 *
295 * @param pin_number Specifies the pin number to read.
296 *
297 * @return 0 if the pin input level is low. Positive value if the pin is high.
298 */
299 __STATIC_INLINE uint32_t nrf_gpio_pin_read(uint32_t pin_number);
300
301 /**
302 * @brief Function for reading the output level of a GPIO pin.
303 *
304 * @param pin_number Specifies the pin number to read.
305 *
306 * @return 0 if the pin output level is low. Positive value if pin output is high.
307 */
308 __STATIC_INLINE uint32_t nrf_gpio_pin_out_read(uint32_t pin_number);
309
310 /**
311 * @brief Function for reading the sense configuration of a GPIO pin.
312 *
313 * @param pin_number Specifies the pin number to read.
314 *
315 * @retval Sense configuration.
316 */
317 __STATIC_INLINE nrf_gpio_pin_sense_t nrf_gpio_pin_sense_get(uint32_t pin_number);
318
319 /**
320 * @brief Function for reading the direction configuration of a GPIO pin.
321 *
322 * @param pin_number Specifies the pin number to read.
323 *
324 * @retval Direction configuration.
325 */
326 __STATIC_INLINE nrf_gpio_pin_dir_t nrf_gpio_pin_dir_get(uint32_t pin_number);
327
328 /**
329 * @brief Function for reading the pull configuration of a GPIO pin.
330 *
331 * @param pin_number Specifies the pin number to read.
332 *
333 * @retval Pull configuration.
334 */
335 __STATIC_INLINE nrf_gpio_pin_pull_t nrf_gpio_pin_pull_get(uint32_t pin_number);
336
337 /**
338 * @brief Function for setting output direction on selected pins on a given port.
339 *
340 * @param p_reg Pointer to the peripheral registers structure.
341 * @param out_mask Mask specifying the pins to set as output.
342 *
343 */
344 __STATIC_INLINE void nrf_gpio_port_dir_output_set(NRF_GPIO_Type * p_reg, uint32_t out_mask);
345
346 /**
347 * @brief Function for setting input direction on selected pins on a given port.
348 *
349 * @param p_reg Pointer to the peripheral registers structure.
350 * @param in_mask Mask specifying the pins to set as input.
351 *
352 */
353 __STATIC_INLINE void nrf_gpio_port_dir_input_set(NRF_GPIO_Type * p_reg, uint32_t in_mask);
354
355 /**
356 * @brief Function for writing the direction configuration of GPIO pins in a given port.
357 *
358 * @param p_reg Pointer to the peripheral registers structure.
359 * @param dir_mask Mask specifying the direction of pins. Bit set means that the given pin is configured as output.
360 *
361 */
362 __STATIC_INLINE void nrf_gpio_port_dir_write(NRF_GPIO_Type * p_reg, uint32_t dir_mask);
363
364 /**
365 * @brief Function for reading the direction configuration of a GPIO port.
366 *
367 * @param p_reg Pointer to the peripheral registers structure.
368 *
369 * @retval Pin configuration of the current direction settings. Bit set means that the given pin is configured as output.
370 */
371 __STATIC_INLINE uint32_t nrf_gpio_port_dir_read(NRF_GPIO_Type const * p_reg);
372
373 /**
374 * @brief Function for reading the input signals of GPIO pins on a given port.
375 *
376 * @param p_reg Pointer to the peripheral registers structure.
377 *
378 * @retval Port input values.
379 */
380 __STATIC_INLINE uint32_t nrf_gpio_port_in_read(NRF_GPIO_Type const * p_reg);
381
382 /**
383 * @brief Function for reading the output signals of GPIO pins of a given port.
384 *
385 * @param p_reg Pointer to the peripheral registers structure.
386 *
387 * @retval Port output values.
388 */
389 __STATIC_INLINE uint32_t nrf_gpio_port_out_read(NRF_GPIO_Type const * p_reg);
390
391 /**
392 * @brief Function for writing the GPIO pins output on a given port.
393 *
394 * @param p_reg Pointer to the peripheral registers structure.
395 * @param value Output port mask.
396 *
397 */
398 __STATIC_INLINE void nrf_gpio_port_out_write(NRF_GPIO_Type * p_reg, uint32_t value);
399
400 /**
401 * @brief Function for setting high level on selected GPIO pins of a given port.
402 *
403 * @param p_reg Pointer to the peripheral registers structure.
404 * @param set_mask Mask with pins to set as logical high level.
405 *
406 */
407 __STATIC_INLINE void nrf_gpio_port_out_set(NRF_GPIO_Type * p_reg, uint32_t set_mask);
408
409 /**
410 * @brief Function for setting low level on selected GPIO pins of a given port.
411 *
412 * @param p_reg Pointer to the peripheral registers structure.
413 * @param clr_mask Mask with pins to set as logical low level.
414 *
415 */
416 __STATIC_INLINE void nrf_gpio_port_out_clear(NRF_GPIO_Type * p_reg, uint32_t clr_mask);
417
418 /**
419 * @brief Function for reading pins state of multiple consecutive ports.
420 *
421 * @param start_port Index of the first port to read.
422 * @param length Number of ports to read.
423 * @param p_masks Pointer to output array where port states will be stored.
424 */
425 __STATIC_INLINE void nrf_gpio_ports_read(uint32_t start_port, uint32_t length, uint32_t * p_masks);
426
427 #if defined(GPIO_DETECTMODE_DETECTMODE_LDETECT) || defined(__NRF_DOXYGEN__)
428 /**
429 * @brief Function for reading latch state of multiple consecutive ports.
430 *
431 * @param start_port Index of the first port to read.
432 * @param length Number of ports to read.
433 * @param p_masks Pointer to output array where latch states will be stored.
434 */
435 __STATIC_INLINE void nrf_gpio_latches_read(uint32_t start_port, uint32_t length,
436 uint32_t * p_masks);
437
438 /**
439 * @brief Function for reading latch state of single pin.
440 *
441 * @param pin_number Pin number.
442 * @return 0 if latch is not set. Positive value otherwise.
443 *
444 */
445 __STATIC_INLINE uint32_t nrf_gpio_pin_latch_get(uint32_t pin_number);
446
447 /**
448 * @brief Function for clearing latch state of a single pin.
449 *
450 * @param pin_number Pin number.
451 *
452 */
453 __STATIC_INLINE void nrf_gpio_pin_latch_clear(uint32_t pin_number);
454 #endif
455
456 #ifndef SUPPRESS_INLINE_IMPLEMENTATION
457
458 /**
459 * @brief Function for extracting port and relative pin number from absolute pin number.
460 *
461 * @param[inout] Pointer to absolute pin number which is overriden by relative to port pin number.
462 *
463 * @return Pointer to port register set.
464 *
465 */
nrf_gpio_pin_port_decode(uint32_t * p_pin)466 __STATIC_INLINE NRF_GPIO_Type * nrf_gpio_pin_port_decode(uint32_t * p_pin)
467 {
468 NRFX_ASSERT(*p_pin < NUMBER_OF_PINS);
469 #if (GPIO_COUNT == 1)
470 return NRF_P0;
471 #else
472 if (*p_pin < P0_PIN_NUM)
473 {
474 return NRF_P0;
475 }
476 else
477 {
478 *p_pin = *p_pin & (P0_PIN_NUM - 1);
479 return NRF_P1;
480 }
481 #endif
482 }
483
484
nrf_gpio_range_cfg_output(uint32_t pin_range_start,uint32_t pin_range_end)485 __STATIC_INLINE void nrf_gpio_range_cfg_output(uint32_t pin_range_start, uint32_t pin_range_end)
486 {
487 /*lint -e{845} // A zero has been given as right argument to operator '|'" */
488 for (; pin_range_start <= pin_range_end; pin_range_start++)
489 {
490 nrf_gpio_cfg_output(pin_range_start);
491 }
492 }
493
494
nrf_gpio_range_cfg_input(uint32_t pin_range_start,uint32_t pin_range_end,nrf_gpio_pin_pull_t pull_config)495 __STATIC_INLINE void nrf_gpio_range_cfg_input(uint32_t pin_range_start,
496 uint32_t pin_range_end,
497 nrf_gpio_pin_pull_t pull_config)
498 {
499 /*lint -e{845} // A zero has been given as right argument to operator '|'" */
500 for (; pin_range_start <= pin_range_end; pin_range_start++)
501 {
502 nrf_gpio_cfg_input(pin_range_start, pull_config);
503 }
504 }
505
506
nrf_gpio_cfg(uint32_t pin_number,nrf_gpio_pin_dir_t dir,nrf_gpio_pin_input_t input,nrf_gpio_pin_pull_t pull,nrf_gpio_pin_drive_t drive,nrf_gpio_pin_sense_t sense)507 __STATIC_INLINE void nrf_gpio_cfg(
508 uint32_t pin_number,
509 nrf_gpio_pin_dir_t dir,
510 nrf_gpio_pin_input_t input,
511 nrf_gpio_pin_pull_t pull,
512 nrf_gpio_pin_drive_t drive,
513 nrf_gpio_pin_sense_t sense)
514 {
515 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
516
517 reg->PIN_CNF[pin_number] = ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos)
518 | ((uint32_t)input << GPIO_PIN_CNF_INPUT_Pos)
519 | ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)
520 | ((uint32_t)drive << GPIO_PIN_CNF_DRIVE_Pos)
521 | ((uint32_t)sense << GPIO_PIN_CNF_SENSE_Pos);
522 }
523
524
nrf_gpio_cfg_output(uint32_t pin_number)525 __STATIC_INLINE void nrf_gpio_cfg_output(uint32_t pin_number)
526 {
527 nrf_gpio_cfg(
528 pin_number,
529 NRF_GPIO_PIN_DIR_OUTPUT,
530 NRF_GPIO_PIN_INPUT_DISCONNECT,
531 NRF_GPIO_PIN_NOPULL,
532 NRF_GPIO_PIN_S0S1,
533 NRF_GPIO_PIN_NOSENSE);
534 }
535
536
nrf_gpio_cfg_input(uint32_t pin_number,nrf_gpio_pin_pull_t pull_config)537 __STATIC_INLINE void nrf_gpio_cfg_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config)
538 {
539 nrf_gpio_cfg(
540 pin_number,
541 NRF_GPIO_PIN_DIR_INPUT,
542 NRF_GPIO_PIN_INPUT_CONNECT,
543 pull_config,
544 NRF_GPIO_PIN_S0S1,
545 NRF_GPIO_PIN_NOSENSE);
546 }
547
548
nrf_gpio_cfg_default(uint32_t pin_number)549 __STATIC_INLINE void nrf_gpio_cfg_default(uint32_t pin_number)
550 {
551 nrf_gpio_cfg(
552 pin_number,
553 NRF_GPIO_PIN_DIR_INPUT,
554 NRF_GPIO_PIN_INPUT_DISCONNECT,
555 NRF_GPIO_PIN_NOPULL,
556 NRF_GPIO_PIN_S0S1,
557 NRF_GPIO_PIN_NOSENSE);
558 }
559
560
nrf_gpio_cfg_watcher(uint32_t pin_number)561 __STATIC_INLINE void nrf_gpio_cfg_watcher(uint32_t pin_number)
562 {
563 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
564 /*lint -e{845} // A zero has been given as right argument to operator '|'" */
565 uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_INPUT_Msk;
566
567 reg->PIN_CNF[pin_number] = cnf | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos);
568 }
569
570
nrf_gpio_input_disconnect(uint32_t pin_number)571 __STATIC_INLINE void nrf_gpio_input_disconnect(uint32_t pin_number)
572 {
573 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
574 /*lint -e{845} // A zero has been given as right argument to operator '|'" */
575 uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_INPUT_Msk;
576
577 reg->PIN_CNF[pin_number] = cnf | (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos);
578 }
579
580
nrf_gpio_cfg_sense_input(uint32_t pin_number,nrf_gpio_pin_pull_t pull_config,nrf_gpio_pin_sense_t sense_config)581 __STATIC_INLINE void nrf_gpio_cfg_sense_input(uint32_t pin_number,
582 nrf_gpio_pin_pull_t pull_config,
583 nrf_gpio_pin_sense_t sense_config)
584 {
585 nrf_gpio_cfg(
586 pin_number,
587 NRF_GPIO_PIN_DIR_INPUT,
588 NRF_GPIO_PIN_INPUT_CONNECT,
589 pull_config,
590 NRF_GPIO_PIN_S0S1,
591 sense_config);
592 }
593
594
nrf_gpio_cfg_sense_set(uint32_t pin_number,nrf_gpio_pin_sense_t sense_config)595 __STATIC_INLINE void nrf_gpio_cfg_sense_set(uint32_t pin_number, nrf_gpio_pin_sense_t sense_config)
596 {
597 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
598
599 /*lint -e{845} // A zero has been given as right argument to operator '|'" */
600 reg->PIN_CNF[pin_number] &= ~GPIO_PIN_CNF_SENSE_Msk;
601 reg->PIN_CNF[pin_number] |= (sense_config << GPIO_PIN_CNF_SENSE_Pos);
602 }
603
604
nrf_gpio_pin_dir_set(uint32_t pin_number,nrf_gpio_pin_dir_t direction)605 __STATIC_INLINE void nrf_gpio_pin_dir_set(uint32_t pin_number, nrf_gpio_pin_dir_t direction)
606 {
607 if (direction == NRF_GPIO_PIN_DIR_INPUT)
608 {
609 nrf_gpio_cfg(
610 pin_number,
611 NRF_GPIO_PIN_DIR_INPUT,
612 NRF_GPIO_PIN_INPUT_CONNECT,
613 NRF_GPIO_PIN_NOPULL,
614 NRF_GPIO_PIN_S0S1,
615 NRF_GPIO_PIN_NOSENSE);
616 }
617 else
618 {
619 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
620 reg->DIRSET = (1UL << pin_number);
621 }
622 }
623
624
nrf_gpio_pin_set(uint32_t pin_number)625 __STATIC_INLINE void nrf_gpio_pin_set(uint32_t pin_number)
626 {
627 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
628
629 nrf_gpio_port_out_set(reg, 1UL << pin_number);
630 }
631
632
nrf_gpio_pin_clear(uint32_t pin_number)633 __STATIC_INLINE void nrf_gpio_pin_clear(uint32_t pin_number)
634 {
635 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
636
637 nrf_gpio_port_out_clear(reg, 1UL << pin_number);
638 }
639
640
nrf_gpio_pin_toggle(uint32_t pin_number)641 __STATIC_INLINE void nrf_gpio_pin_toggle(uint32_t pin_number)
642 {
643 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
644 uint32_t pins_state = reg->OUT;
645
646 reg->OUTSET = (~pins_state & (1UL << pin_number));
647 reg->OUTCLR = (pins_state & (1UL << pin_number));
648 }
649
650
nrf_gpio_pin_write(uint32_t pin_number,uint32_t value)651 __STATIC_INLINE void nrf_gpio_pin_write(uint32_t pin_number, uint32_t value)
652 {
653 if (value == 0)
654 {
655 nrf_gpio_pin_clear(pin_number);
656 }
657 else
658 {
659 nrf_gpio_pin_set(pin_number);
660 }
661 }
662
663
nrf_gpio_pin_read(uint32_t pin_number)664 __STATIC_INLINE uint32_t nrf_gpio_pin_read(uint32_t pin_number)
665 {
666 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
667
668 return ((nrf_gpio_port_in_read(reg) >> pin_number) & 1UL);
669 }
670
671
nrf_gpio_pin_out_read(uint32_t pin_number)672 __STATIC_INLINE uint32_t nrf_gpio_pin_out_read(uint32_t pin_number)
673 {
674 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
675
676 return ((nrf_gpio_port_out_read(reg) >> pin_number) & 1UL);
677 }
678
679
nrf_gpio_pin_sense_get(uint32_t pin_number)680 __STATIC_INLINE nrf_gpio_pin_sense_t nrf_gpio_pin_sense_get(uint32_t pin_number)
681 {
682 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
683
684 return (nrf_gpio_pin_sense_t)((reg->PIN_CNF[pin_number] &
685 GPIO_PIN_CNF_SENSE_Msk) >> GPIO_PIN_CNF_SENSE_Pos);
686 }
687
688
nrf_gpio_pin_dir_get(uint32_t pin_number)689 __STATIC_INLINE nrf_gpio_pin_dir_t nrf_gpio_pin_dir_get(uint32_t pin_number)
690 {
691 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
692
693 return (nrf_gpio_pin_dir_t)((reg->PIN_CNF[pin_number] &
694 GPIO_PIN_CNF_DIR_Msk) >> GPIO_PIN_CNF_DIR_Pos);
695 }
696
697
nrf_gpio_pin_pull_get(uint32_t pin_number)698 __STATIC_INLINE nrf_gpio_pin_pull_t nrf_gpio_pin_pull_get(uint32_t pin_number)
699 {
700 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
701
702 return (nrf_gpio_pin_pull_t)((reg->PIN_CNF[pin_number] &
703 GPIO_PIN_CNF_PULL_Msk) >> GPIO_PIN_CNF_PULL_Pos);
704 }
705
706
nrf_gpio_port_dir_output_set(NRF_GPIO_Type * p_reg,uint32_t out_mask)707 __STATIC_INLINE void nrf_gpio_port_dir_output_set(NRF_GPIO_Type * p_reg, uint32_t out_mask)
708 {
709 p_reg->DIRSET = out_mask;
710 }
711
712
nrf_gpio_port_dir_input_set(NRF_GPIO_Type * p_reg,uint32_t in_mask)713 __STATIC_INLINE void nrf_gpio_port_dir_input_set(NRF_GPIO_Type * p_reg, uint32_t in_mask)
714 {
715 p_reg->DIRCLR = in_mask;
716 }
717
718
nrf_gpio_port_dir_write(NRF_GPIO_Type * p_reg,uint32_t value)719 __STATIC_INLINE void nrf_gpio_port_dir_write(NRF_GPIO_Type * p_reg, uint32_t value)
720 {
721 p_reg->DIR = value;
722 }
723
724
nrf_gpio_port_dir_read(NRF_GPIO_Type const * p_reg)725 __STATIC_INLINE uint32_t nrf_gpio_port_dir_read(NRF_GPIO_Type const * p_reg)
726 {
727 return p_reg->DIR;
728 }
729
730
nrf_gpio_port_in_read(NRF_GPIO_Type const * p_reg)731 __STATIC_INLINE uint32_t nrf_gpio_port_in_read(NRF_GPIO_Type const * p_reg)
732 {
733 return p_reg->IN;
734 }
735
736
nrf_gpio_port_out_read(NRF_GPIO_Type const * p_reg)737 __STATIC_INLINE uint32_t nrf_gpio_port_out_read(NRF_GPIO_Type const * p_reg)
738 {
739 return p_reg->OUT;
740 }
741
742
nrf_gpio_port_out_write(NRF_GPIO_Type * p_reg,uint32_t value)743 __STATIC_INLINE void nrf_gpio_port_out_write(NRF_GPIO_Type * p_reg, uint32_t value)
744 {
745 p_reg->OUT = value;
746 }
747
748
nrf_gpio_port_out_set(NRF_GPIO_Type * p_reg,uint32_t set_mask)749 __STATIC_INLINE void nrf_gpio_port_out_set(NRF_GPIO_Type * p_reg, uint32_t set_mask)
750 {
751 p_reg->OUTSET = set_mask;
752 }
753
754
nrf_gpio_port_out_clear(NRF_GPIO_Type * p_reg,uint32_t clr_mask)755 __STATIC_INLINE void nrf_gpio_port_out_clear(NRF_GPIO_Type * p_reg, uint32_t clr_mask)
756 {
757 p_reg->OUTCLR = clr_mask;
758 }
759
760
nrf_gpio_ports_read(uint32_t start_port,uint32_t length,uint32_t * p_masks)761 __STATIC_INLINE void nrf_gpio_ports_read(uint32_t start_port, uint32_t length, uint32_t * p_masks)
762 {
763 NRF_GPIO_Type * gpio_regs[GPIO_COUNT] = GPIO_REG_LIST;
764
765 NRFX_ASSERT(start_port + length <= GPIO_COUNT);
766 uint32_t i;
767
768 for (i = start_port; i < (start_port + length); i++)
769 {
770 *p_masks = nrf_gpio_port_in_read(gpio_regs[i]);
771 p_masks++;
772 }
773 }
774
775
776 #ifdef GPIO_DETECTMODE_DETECTMODE_LDETECT
nrf_gpio_latches_read(uint32_t start_port,uint32_t length,uint32_t * p_masks)777 __STATIC_INLINE void nrf_gpio_latches_read(uint32_t start_port, uint32_t length, uint32_t * p_masks)
778 {
779 NRF_GPIO_Type * gpio_regs[GPIO_COUNT] = GPIO_REG_LIST;
780 uint32_t i;
781
782 for (i = start_port; i < (start_port + length); i++)
783 {
784 *p_masks = gpio_regs[i]->LATCH;
785 p_masks++;
786 }
787 }
788
789
nrf_gpio_pin_latch_get(uint32_t pin_number)790 __STATIC_INLINE uint32_t nrf_gpio_pin_latch_get(uint32_t pin_number)
791 {
792 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
793
794 return (reg->LATCH & (1 << pin_number)) ? 1 : 0;
795 }
796
797
nrf_gpio_pin_latch_clear(uint32_t pin_number)798 __STATIC_INLINE void nrf_gpio_pin_latch_clear(uint32_t pin_number)
799 {
800 NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
801
802 reg->LATCH = (1 << pin_number);
803 }
804
805
806 #endif
807 #endif // SUPPRESS_INLINE_IMPLEMENTATION
808
809 /** @} */
810
811 #ifdef __cplusplus
812 }
813 #endif
814
815 #endif // NRF_GPIO_H__
816