1*150812a8SEvalZero /*
2*150812a8SEvalZero * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
3*150812a8SEvalZero * All rights reserved.
4*150812a8SEvalZero *
5*150812a8SEvalZero * Redistribution and use in source and binary forms, with or without
6*150812a8SEvalZero * modification, are permitted provided that the following conditions are met:
7*150812a8SEvalZero *
8*150812a8SEvalZero * 1. Redistributions of source code must retain the above copyright notice, this
9*150812a8SEvalZero * list of conditions and the following disclaimer.
10*150812a8SEvalZero *
11*150812a8SEvalZero * 2. Redistributions in binary form must reproduce the above copyright
12*150812a8SEvalZero * notice, this list of conditions and the following disclaimer in the
13*150812a8SEvalZero * documentation and/or other materials provided with the distribution.
14*150812a8SEvalZero *
15*150812a8SEvalZero * 3. Neither the name of the copyright holder nor the names of its
16*150812a8SEvalZero * contributors may be used to endorse or promote products derived from this
17*150812a8SEvalZero * software without specific prior written permission.
18*150812a8SEvalZero *
19*150812a8SEvalZero * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20*150812a8SEvalZero * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21*150812a8SEvalZero * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22*150812a8SEvalZero * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23*150812a8SEvalZero * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24*150812a8SEvalZero * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25*150812a8SEvalZero * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26*150812a8SEvalZero * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27*150812a8SEvalZero * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28*150812a8SEvalZero * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29*150812a8SEvalZero * POSSIBILITY OF SUCH DAMAGE.
30*150812a8SEvalZero */
31*150812a8SEvalZero
32*150812a8SEvalZero #ifndef NRF_EGU_H__
33*150812a8SEvalZero #define NRF_EGU_H__
34*150812a8SEvalZero
35*150812a8SEvalZero #include <nrfx.h>
36*150812a8SEvalZero
37*150812a8SEvalZero #ifdef __cplusplus
38*150812a8SEvalZero extern "C" {
39*150812a8SEvalZero #endif
40*150812a8SEvalZero
41*150812a8SEvalZero /**
42*150812a8SEvalZero * @defgroup nrf_egu_hal EGU HAL
43*150812a8SEvalZero * @{
44*150812a8SEvalZero * @ingroup nrf_swi_egu
45*150812a8SEvalZero * @brief Hardware access layer for managing the Event Generator Unit (EGU) peripheral.
46*150812a8SEvalZero */
47*150812a8SEvalZero
48*150812a8SEvalZero /**
49*150812a8SEvalZero * @enum nrf_egu_task_t
50*150812a8SEvalZero * @brief EGU tasks.
51*150812a8SEvalZero */
52*150812a8SEvalZero typedef enum
53*150812a8SEvalZero {
54*150812a8SEvalZero /*lint -save -e30 -esym(628,__INTADDR__)*/
55*150812a8SEvalZero NRF_EGU_TASK_TRIGGER0 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[0]), /**< Trigger 0 for triggering the corresponding TRIGGERED[0] event. */
56*150812a8SEvalZero NRF_EGU_TASK_TRIGGER1 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[1]), /**< Trigger 1 for triggering the corresponding TRIGGERED[1] event. */
57*150812a8SEvalZero NRF_EGU_TASK_TRIGGER2 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[2]), /**< Trigger 2 for triggering the corresponding TRIGGERED[2] event. */
58*150812a8SEvalZero NRF_EGU_TASK_TRIGGER3 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[3]), /**< Trigger 3 for triggering the corresponding TRIGGERED[3] event. */
59*150812a8SEvalZero NRF_EGU_TASK_TRIGGER4 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[4]), /**< Trigger 4 for triggering the corresponding TRIGGERED[4] event. */
60*150812a8SEvalZero NRF_EGU_TASK_TRIGGER5 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[5]), /**< Trigger 5 for triggering the corresponding TRIGGERED[5] event. */
61*150812a8SEvalZero NRF_EGU_TASK_TRIGGER6 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[6]), /**< Trigger 6 for triggering the corresponding TRIGGERED[6] event. */
62*150812a8SEvalZero NRF_EGU_TASK_TRIGGER7 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[7]), /**< Trigger 7 for triggering the corresponding TRIGGERED[7] event. */
63*150812a8SEvalZero NRF_EGU_TASK_TRIGGER8 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[8]), /**< Trigger 8 for triggering the corresponding TRIGGERED[8] event. */
64*150812a8SEvalZero NRF_EGU_TASK_TRIGGER9 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[9]), /**< Trigger 9 for triggering the corresponding TRIGGERED[9] event. */
65*150812a8SEvalZero NRF_EGU_TASK_TRIGGER10 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[10]), /**< Trigger 10 for triggering the corresponding TRIGGERED[10] event. */
66*150812a8SEvalZero NRF_EGU_TASK_TRIGGER11 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[11]), /**< Trigger 11 for triggering the corresponding TRIGGERED[11] event. */
67*150812a8SEvalZero NRF_EGU_TASK_TRIGGER12 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[12]), /**< Trigger 12 for triggering the corresponding TRIGGERED[12] event. */
68*150812a8SEvalZero NRF_EGU_TASK_TRIGGER13 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[13]), /**< Trigger 13 for triggering the corresponding TRIGGERED[13] event. */
69*150812a8SEvalZero NRF_EGU_TASK_TRIGGER14 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[14]), /**< Trigger 14 for triggering the corresponding TRIGGERED[14] event. */
70*150812a8SEvalZero NRF_EGU_TASK_TRIGGER15 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[15]) /**< Trigger 15 for triggering the corresponding TRIGGERED[15] event. */
71*150812a8SEvalZero /*lint -restore*/
72*150812a8SEvalZero } nrf_egu_task_t;
73*150812a8SEvalZero
74*150812a8SEvalZero /**
75*150812a8SEvalZero * @enum nrf_egu_event_t
76*150812a8SEvalZero * @brief EGU events.
77*150812a8SEvalZero */
78*150812a8SEvalZero typedef enum
79*150812a8SEvalZero {
80*150812a8SEvalZero /*lint -save -e30 -esym(628,__INTADDR__)*/
81*150812a8SEvalZero NRF_EGU_EVENT_TRIGGERED0 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[0]), /**< Event number 0 generated by triggering the corresponding TRIGGER[0] task. */
82*150812a8SEvalZero NRF_EGU_EVENT_TRIGGERED1 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[1]), /**< Event number 1 generated by triggering the corresponding TRIGGER[1] task. */
83*150812a8SEvalZero NRF_EGU_EVENT_TRIGGERED2 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[2]), /**< Event number 2 generated by triggering the corresponding TRIGGER[2] task. */
84*150812a8SEvalZero NRF_EGU_EVENT_TRIGGERED3 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[3]), /**< Event number 3 generated by triggering the corresponding TRIGGER[3] task. */
85*150812a8SEvalZero NRF_EGU_EVENT_TRIGGERED4 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[4]), /**< Event number 4 generated by triggering the corresponding TRIGGER[4] task. */
86*150812a8SEvalZero NRF_EGU_EVENT_TRIGGERED5 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[5]), /**< Event number 5 generated by triggering the corresponding TRIGGER[5] task. */
87*150812a8SEvalZero NRF_EGU_EVENT_TRIGGERED6 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[6]), /**< Event number 6 generated by triggering the corresponding TRIGGER[6] task. */
88*150812a8SEvalZero NRF_EGU_EVENT_TRIGGERED7 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[7]), /**< Event number 7 generated by triggering the corresponding TRIGGER[7] task. */
89*150812a8SEvalZero NRF_EGU_EVENT_TRIGGERED8 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[8]), /**< Event number 8 generated by triggering the corresponding TRIGGER[8] task. */
90*150812a8SEvalZero NRF_EGU_EVENT_TRIGGERED9 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[9]), /**< Event number 9 generated by triggering the corresponding TRIGGER[9] task. */
91*150812a8SEvalZero NRF_EGU_EVENT_TRIGGERED10 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[10]), /**< Event number 10 generated by triggering the corresponding TRIGGER[10] task. */
92*150812a8SEvalZero NRF_EGU_EVENT_TRIGGERED11 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[11]), /**< Event number 11 generated by triggering the corresponding TRIGGER[11] task. */
93*150812a8SEvalZero NRF_EGU_EVENT_TRIGGERED12 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[12]), /**< Event number 12 generated by triggering the corresponding TRIGGER[12] task. */
94*150812a8SEvalZero NRF_EGU_EVENT_TRIGGERED13 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[13]), /**< Event number 13 generated by triggering the corresponding TRIGGER[13] task. */
95*150812a8SEvalZero NRF_EGU_EVENT_TRIGGERED14 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[14]), /**< Event number 14 generated by triggering the corresponding TRIGGER[14] task. */
96*150812a8SEvalZero NRF_EGU_EVENT_TRIGGERED15 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[15]) /**< Event number 15 generated by triggering the corresponding TRIGGER[15] task. */
97*150812a8SEvalZero /*lint -restore*/
98*150812a8SEvalZero } nrf_egu_event_t;
99*150812a8SEvalZero
100*150812a8SEvalZero /**
101*150812a8SEvalZero * @enum nrf_egu_int_mask_t
102*150812a8SEvalZero * @brief EGU interrupts.
103*150812a8SEvalZero */
104*150812a8SEvalZero typedef enum
105*150812a8SEvalZero {
106*150812a8SEvalZero NRF_EGU_INT_TRIGGERED0 = EGU_INTENSET_TRIGGERED0_Msk, /**< Interrupt on EVENTS_TRIGGERED[0] event. */
107*150812a8SEvalZero NRF_EGU_INT_TRIGGERED1 = EGU_INTENSET_TRIGGERED1_Msk, /**< Interrupt on EVENTS_TRIGGERED[1] event. */
108*150812a8SEvalZero NRF_EGU_INT_TRIGGERED2 = EGU_INTENSET_TRIGGERED2_Msk, /**< Interrupt on EVENTS_TRIGGERED[2] event. */
109*150812a8SEvalZero NRF_EGU_INT_TRIGGERED3 = EGU_INTENSET_TRIGGERED3_Msk, /**< Interrupt on EVENTS_TRIGGERED[3] event. */
110*150812a8SEvalZero NRF_EGU_INT_TRIGGERED4 = EGU_INTENSET_TRIGGERED4_Msk, /**< Interrupt on EVENTS_TRIGGERED[4] event. */
111*150812a8SEvalZero NRF_EGU_INT_TRIGGERED5 = EGU_INTENSET_TRIGGERED5_Msk, /**< Interrupt on EVENTS_TRIGGERED[5] event. */
112*150812a8SEvalZero NRF_EGU_INT_TRIGGERED6 = EGU_INTENSET_TRIGGERED6_Msk, /**< Interrupt on EVENTS_TRIGGERED[6] event. */
113*150812a8SEvalZero NRF_EGU_INT_TRIGGERED7 = EGU_INTENSET_TRIGGERED7_Msk, /**< Interrupt on EVENTS_TRIGGERED[7] event. */
114*150812a8SEvalZero NRF_EGU_INT_TRIGGERED8 = EGU_INTENSET_TRIGGERED8_Msk, /**< Interrupt on EVENTS_TRIGGERED[8] event. */
115*150812a8SEvalZero NRF_EGU_INT_TRIGGERED9 = EGU_INTENSET_TRIGGERED9_Msk, /**< Interrupt on EVENTS_TRIGGERED[9] event. */
116*150812a8SEvalZero NRF_EGU_INT_TRIGGERED10 = EGU_INTENSET_TRIGGERED10_Msk, /**< Interrupt on EVENTS_TRIGGERED[10] event. */
117*150812a8SEvalZero NRF_EGU_INT_TRIGGERED11 = EGU_INTENSET_TRIGGERED11_Msk, /**< Interrupt on EVENTS_TRIGGERED[11] event. */
118*150812a8SEvalZero NRF_EGU_INT_TRIGGERED12 = EGU_INTENSET_TRIGGERED12_Msk, /**< Interrupt on EVENTS_TRIGGERED[12] event. */
119*150812a8SEvalZero NRF_EGU_INT_TRIGGERED13 = EGU_INTENSET_TRIGGERED13_Msk, /**< Interrupt on EVENTS_TRIGGERED[13] event. */
120*150812a8SEvalZero NRF_EGU_INT_TRIGGERED14 = EGU_INTENSET_TRIGGERED14_Msk, /**< Interrupt on EVENTS_TRIGGERED[14] event. */
121*150812a8SEvalZero NRF_EGU_INT_TRIGGERED15 = EGU_INTENSET_TRIGGERED15_Msk, /**< Interrupt on EVENTS_TRIGGERED[15] event. */
122*150812a8SEvalZero NRF_EGU_INT_ALL = 0xFFFFuL
123*150812a8SEvalZero } nrf_egu_int_mask_t;
124*150812a8SEvalZero
125*150812a8SEvalZero /**@brief Function for getting max channel number of given EGU.
126*150812a8SEvalZero *
127*150812a8SEvalZero * @param NRF_EGUx EGU instance.
128*150812a8SEvalZero *
129*150812a8SEvalZero * @returns number of available channels.
130*150812a8SEvalZero */
131*150812a8SEvalZero __STATIC_INLINE uint32_t nrf_egu_channel_count(NRF_EGU_Type * NRF_EGUx);
132*150812a8SEvalZero
133*150812a8SEvalZero /**
134*150812a8SEvalZero * @brief Function for triggering a specific EGU task.
135*150812a8SEvalZero *
136*150812a8SEvalZero * @param NRF_EGUx EGU instance.
137*150812a8SEvalZero * @param egu_task EGU task.
138*150812a8SEvalZero */
139*150812a8SEvalZero __STATIC_INLINE void nrf_egu_task_trigger(NRF_EGU_Type * NRF_EGUx, nrf_egu_task_t egu_task);
140*150812a8SEvalZero
141*150812a8SEvalZero /**
142*150812a8SEvalZero * @brief Function for returning the address of a specific EGU task register.
143*150812a8SEvalZero *
144*150812a8SEvalZero * @param NRF_EGUx EGU instance.
145*150812a8SEvalZero * @param egu_task EGU task.
146*150812a8SEvalZero */
147*150812a8SEvalZero __STATIC_INLINE uint32_t * nrf_egu_task_address_get(NRF_EGU_Type * NRF_EGUx,
148*150812a8SEvalZero nrf_egu_task_t egu_task);
149*150812a8SEvalZero
150*150812a8SEvalZero /**
151*150812a8SEvalZero * @brief Function for returning the address of a specific EGU TRIGGER task register.
152*150812a8SEvalZero *
153*150812a8SEvalZero * @param NRF_EGUx EGU instance.
154*150812a8SEvalZero * @param channel Channel number.
155*150812a8SEvalZero */
156*150812a8SEvalZero __STATIC_INLINE uint32_t * nrf_egu_task_trigger_address_get(NRF_EGU_Type * NRF_EGUx,
157*150812a8SEvalZero uint8_t channel);
158*150812a8SEvalZero
159*150812a8SEvalZero /**
160*150812a8SEvalZero * @brief Function for returning the specific EGU TRIGGER task.
161*150812a8SEvalZero *
162*150812a8SEvalZero * @param NRF_EGUx EGU instance.
163*150812a8SEvalZero * @param channel Channel number.
164*150812a8SEvalZero */
165*150812a8SEvalZero __STATIC_INLINE nrf_egu_task_t nrf_egu_task_trigger_get(NRF_EGU_Type * NRF_EGUx, uint8_t channel);
166*150812a8SEvalZero
167*150812a8SEvalZero /**
168*150812a8SEvalZero * @brief Function for returning the state of a specific EGU event.
169*150812a8SEvalZero *
170*150812a8SEvalZero * @param NRF_EGUx EGU instance.
171*150812a8SEvalZero * @param egu_event EGU event to check.
172*150812a8SEvalZero */
173*150812a8SEvalZero __STATIC_INLINE bool nrf_egu_event_check(NRF_EGU_Type * NRF_EGUx,
174*150812a8SEvalZero nrf_egu_event_t egu_event);
175*150812a8SEvalZero
176*150812a8SEvalZero /**
177*150812a8SEvalZero * @brief Function for clearing a specific EGU event.
178*150812a8SEvalZero *
179*150812a8SEvalZero * @param NRF_EGUx EGU instance.
180*150812a8SEvalZero * @param egu_event EGU event to clear.
181*150812a8SEvalZero */
182*150812a8SEvalZero __STATIC_INLINE void nrf_egu_event_clear(NRF_EGU_Type * NRF_EGUx,
183*150812a8SEvalZero nrf_egu_event_t egu_event);
184*150812a8SEvalZero
185*150812a8SEvalZero /**
186*150812a8SEvalZero * @brief Function for returning the address of a specific EGU event register.
187*150812a8SEvalZero *
188*150812a8SEvalZero * @param NRF_EGUx EGU instance.
189*150812a8SEvalZero * @param egu_event EGU event.
190*150812a8SEvalZero */
191*150812a8SEvalZero __STATIC_INLINE uint32_t * nrf_egu_event_address_get(NRF_EGU_Type * NRF_EGUx,
192*150812a8SEvalZero nrf_egu_event_t egu_event);
193*150812a8SEvalZero
194*150812a8SEvalZero /**
195*150812a8SEvalZero * @brief Function for returning the address of a specific EGU TRIGGERED event register.
196*150812a8SEvalZero *
197*150812a8SEvalZero * @param NRF_EGUx EGU instance.
198*150812a8SEvalZero * @param channel Channel number.
199*150812a8SEvalZero */
200*150812a8SEvalZero __STATIC_INLINE uint32_t * nrf_egu_event_triggered_address_get(NRF_EGU_Type * NRF_EGUx,
201*150812a8SEvalZero uint8_t channel);
202*150812a8SEvalZero
203*150812a8SEvalZero /**
204*150812a8SEvalZero * @brief Function for returning the specific EGU TRIGGERED event.
205*150812a8SEvalZero *
206*150812a8SEvalZero * @param NRF_EGUx EGU instance.
207*150812a8SEvalZero * @param channel Channel number.
208*150812a8SEvalZero */
209*150812a8SEvalZero __STATIC_INLINE nrf_egu_event_t nrf_egu_event_triggered_get(NRF_EGU_Type * NRF_EGUx,
210*150812a8SEvalZero uint8_t channel);
211*150812a8SEvalZero
212*150812a8SEvalZero /**
213*150812a8SEvalZero * @brief Function for enabling one or more specific EGU interrupts.
214*150812a8SEvalZero *
215*150812a8SEvalZero * @param NRF_EGUx EGU instance.
216*150812a8SEvalZero * @param egu_int_mask Interrupts to enable.
217*150812a8SEvalZero */
218*150812a8SEvalZero __STATIC_INLINE void nrf_egu_int_enable(NRF_EGU_Type * NRF_EGUx, uint32_t egu_int_mask);
219*150812a8SEvalZero
220*150812a8SEvalZero /**
221*150812a8SEvalZero * @brief Function for retrieving the state of one or more EGU interrupts.
222*150812a8SEvalZero *
223*150812a8SEvalZero * @param NRF_EGUx EGU instance.
224*150812a8SEvalZero * @param egu_int_mask Interrupts to check.
225*150812a8SEvalZero *
226*150812a8SEvalZero * @retval true If all of the specified interrupts are enabled.
227*150812a8SEvalZero * @retval false If at least one of the specified interrupts is disabled.
228*150812a8SEvalZero */
229*150812a8SEvalZero __STATIC_INLINE bool nrf_egu_int_enable_check(NRF_EGU_Type * NRF_EGUx, uint32_t egu_int_mask);
230*150812a8SEvalZero
231*150812a8SEvalZero /**
232*150812a8SEvalZero * @brief Function for disabling one or more specific EGU interrupts.
233*150812a8SEvalZero *
234*150812a8SEvalZero * @param NRF_EGUx EGU instance.
235*150812a8SEvalZero * @param egu_int_mask Interrupts to disable.
236*150812a8SEvalZero */
237*150812a8SEvalZero __STATIC_INLINE void nrf_egu_int_disable(NRF_EGU_Type * NRF_EGUx, uint32_t egu_int_mask);
238*150812a8SEvalZero
239*150812a8SEvalZero /**
240*150812a8SEvalZero * @brief Function for retrieving one or more specific EGU interrupts.
241*150812a8SEvalZero *
242*150812a8SEvalZero * @param NRF_EGUx EGU instance.
243*150812a8SEvalZero * @param channel Channel number.
244*150812a8SEvalZero *
245*150812a8SEvalZero * @returns EGU interrupt mask.
246*150812a8SEvalZero */
247*150812a8SEvalZero __STATIC_INLINE nrf_egu_int_mask_t nrf_egu_int_get(NRF_EGU_Type * NRF_EGUx, uint8_t channel);
248*150812a8SEvalZero
249*150812a8SEvalZero #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
250*150812a8SEvalZero /**
251*150812a8SEvalZero * @brief Function for setting the subscribe configuration for a given
252*150812a8SEvalZero * EGU task.
253*150812a8SEvalZero *
254*150812a8SEvalZero * @param[in] p_reg Pointer to the structure of registers of the peripheral.
255*150812a8SEvalZero * @param[in] task Task for which to set the configuration.
256*150812a8SEvalZero * @param[in] channel Channel through which to subscribe events.
257*150812a8SEvalZero */
258*150812a8SEvalZero __STATIC_INLINE void nrf_egu_subscribe_set(NRF_EGU_Type * p_reg,
259*150812a8SEvalZero nrf_egu_task_t task,
260*150812a8SEvalZero uint8_t channel);
261*150812a8SEvalZero
262*150812a8SEvalZero /**
263*150812a8SEvalZero * @brief Function for clearing the subscribe configuration for a given
264*150812a8SEvalZero * EGU task.
265*150812a8SEvalZero *
266*150812a8SEvalZero * @param[in] p_reg Pointer to the structure of registers of the peripheral.
267*150812a8SEvalZero * @param[in] task Task for which to clear the configuration.
268*150812a8SEvalZero */
269*150812a8SEvalZero __STATIC_INLINE void nrf_egu_subscribe_clear(NRF_EGU_Type * p_reg,
270*150812a8SEvalZero nrf_egu_task_t task);
271*150812a8SEvalZero
272*150812a8SEvalZero /**
273*150812a8SEvalZero * @brief Function for setting the publish configuration for a given
274*150812a8SEvalZero * EGU event.
275*150812a8SEvalZero *
276*150812a8SEvalZero * @param[in] p_reg Pointer to the structure of registers of the peripheral.
277*150812a8SEvalZero * @param[in] event Event for which to set the configuration.
278*150812a8SEvalZero * @param[in] channel Channel through which to publish the event.
279*150812a8SEvalZero */
280*150812a8SEvalZero __STATIC_INLINE void nrf_egu_publish_set(NRF_EGU_Type * p_reg,
281*150812a8SEvalZero nrf_egu_event_t event,
282*150812a8SEvalZero uint8_t channel);
283*150812a8SEvalZero
284*150812a8SEvalZero /**
285*150812a8SEvalZero * @brief Function for clearing the publish configuration for a given
286*150812a8SEvalZero * EGU event.
287*150812a8SEvalZero *
288*150812a8SEvalZero * @param[in] p_reg Pointer to the structure of registers of the peripheral.
289*150812a8SEvalZero * @param[in] event Event for which to clear the configuration.
290*150812a8SEvalZero */
291*150812a8SEvalZero __STATIC_INLINE void nrf_egu_publish_clear(NRF_EGU_Type * p_reg,
292*150812a8SEvalZero nrf_egu_event_t event);
293*150812a8SEvalZero #endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
294*150812a8SEvalZero
295*150812a8SEvalZero #ifndef SUPPRESS_INLINE_IMPLEMENTATION
296*150812a8SEvalZero
nrf_egu_channel_count(NRF_EGU_Type * NRF_EGUx)297*150812a8SEvalZero __STATIC_INLINE uint32_t nrf_egu_channel_count(NRF_EGU_Type * NRF_EGUx)
298*150812a8SEvalZero {
299*150812a8SEvalZero if (NRF_EGUx == NRF_EGU0){
300*150812a8SEvalZero return EGU0_CH_NUM;
301*150812a8SEvalZero }
302*150812a8SEvalZero if (NRF_EGUx == NRF_EGU1){
303*150812a8SEvalZero return EGU1_CH_NUM;
304*150812a8SEvalZero }
305*150812a8SEvalZero #if EGU_COUNT > 2
306*150812a8SEvalZero if (NRF_EGUx == NRF_EGU2){
307*150812a8SEvalZero return EGU2_CH_NUM;
308*150812a8SEvalZero }
309*150812a8SEvalZero if (NRF_EGUx == NRF_EGU3){
310*150812a8SEvalZero return EGU3_CH_NUM;
311*150812a8SEvalZero }
312*150812a8SEvalZero if (NRF_EGUx == NRF_EGU4){
313*150812a8SEvalZero return EGU4_CH_NUM;
314*150812a8SEvalZero }
315*150812a8SEvalZero if (NRF_EGUx == NRF_EGU5){
316*150812a8SEvalZero return EGU5_CH_NUM;
317*150812a8SEvalZero }
318*150812a8SEvalZero #endif
319*150812a8SEvalZero return 0;
320*150812a8SEvalZero }
321*150812a8SEvalZero
nrf_egu_task_trigger(NRF_EGU_Type * NRF_EGUx,nrf_egu_task_t egu_task)322*150812a8SEvalZero __STATIC_INLINE void nrf_egu_task_trigger(NRF_EGU_Type * NRF_EGUx, nrf_egu_task_t egu_task)
323*150812a8SEvalZero {
324*150812a8SEvalZero NRFX_ASSERT(NRF_EGUx);
325*150812a8SEvalZero *((volatile uint32_t *)((uint8_t *)NRF_EGUx + (uint32_t)egu_task)) = 0x1UL;
326*150812a8SEvalZero }
327*150812a8SEvalZero
nrf_egu_task_address_get(NRF_EGU_Type * NRF_EGUx,nrf_egu_task_t egu_task)328*150812a8SEvalZero __STATIC_INLINE uint32_t * nrf_egu_task_address_get(NRF_EGU_Type * NRF_EGUx,
329*150812a8SEvalZero nrf_egu_task_t egu_task)
330*150812a8SEvalZero {
331*150812a8SEvalZero NRFX_ASSERT(NRF_EGUx);
332*150812a8SEvalZero return (uint32_t *)((uint8_t *)NRF_EGUx + (uint32_t)egu_task);
333*150812a8SEvalZero }
334*150812a8SEvalZero
nrf_egu_task_trigger_address_get(NRF_EGU_Type * NRF_EGUx,uint8_t channel)335*150812a8SEvalZero __STATIC_INLINE uint32_t * nrf_egu_task_trigger_address_get(NRF_EGU_Type * NRF_EGUx,
336*150812a8SEvalZero uint8_t channel)
337*150812a8SEvalZero {
338*150812a8SEvalZero NRFX_ASSERT(NRF_EGUx);
339*150812a8SEvalZero NRFX_ASSERT(channel < nrf_egu_channel_count(NRF_EGUx));
340*150812a8SEvalZero return (uint32_t*)&NRF_EGUx->TASKS_TRIGGER[channel];
341*150812a8SEvalZero }
342*150812a8SEvalZero
nrf_egu_task_trigger_get(NRF_EGU_Type * NRF_EGUx,uint8_t channel)343*150812a8SEvalZero __STATIC_INLINE nrf_egu_task_t nrf_egu_task_trigger_get(NRF_EGU_Type * NRF_EGUx, uint8_t channel)
344*150812a8SEvalZero {
345*150812a8SEvalZero NRFX_ASSERT(NRF_EGUx);
346*150812a8SEvalZero NRFX_ASSERT(channel < nrf_egu_channel_count(NRF_EGUx));
347*150812a8SEvalZero return (nrf_egu_task_t)((uint32_t) NRF_EGU_TASK_TRIGGER0 + (channel * sizeof(uint32_t)));
348*150812a8SEvalZero }
349*150812a8SEvalZero
nrf_egu_event_check(NRF_EGU_Type * NRF_EGUx,nrf_egu_event_t egu_event)350*150812a8SEvalZero __STATIC_INLINE bool nrf_egu_event_check(NRF_EGU_Type * NRF_EGUx,
351*150812a8SEvalZero nrf_egu_event_t egu_event)
352*150812a8SEvalZero {
353*150812a8SEvalZero NRFX_ASSERT(NRF_EGUx);
354*150812a8SEvalZero return (bool)*(volatile uint32_t *)((uint8_t *)NRF_EGUx + (uint32_t)egu_event);
355*150812a8SEvalZero }
356*150812a8SEvalZero
nrf_egu_event_clear(NRF_EGU_Type * NRF_EGUx,nrf_egu_event_t egu_event)357*150812a8SEvalZero __STATIC_INLINE void nrf_egu_event_clear(NRF_EGU_Type * NRF_EGUx,
358*150812a8SEvalZero nrf_egu_event_t egu_event)
359*150812a8SEvalZero {
360*150812a8SEvalZero NRFX_ASSERT(NRF_EGUx);
361*150812a8SEvalZero *((volatile uint32_t *)((uint8_t *)NRF_EGUx + (uint32_t)egu_event)) = 0x0UL;
362*150812a8SEvalZero #if __CORTEX_M == 0x04
363*150812a8SEvalZero volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_EGUx + (uint32_t)egu_event));
364*150812a8SEvalZero (void)dummy;
365*150812a8SEvalZero #endif
366*150812a8SEvalZero }
367*150812a8SEvalZero
nrf_egu_event_address_get(NRF_EGU_Type * NRF_EGUx,nrf_egu_event_t egu_event)368*150812a8SEvalZero __STATIC_INLINE uint32_t * nrf_egu_event_address_get(NRF_EGU_Type * NRF_EGUx,
369*150812a8SEvalZero nrf_egu_event_t egu_event)
370*150812a8SEvalZero {
371*150812a8SEvalZero NRFX_ASSERT(NRF_EGUx);
372*150812a8SEvalZero return (uint32_t *)((uint8_t *)NRF_EGUx + (uint32_t)egu_event);
373*150812a8SEvalZero }
374*150812a8SEvalZero
nrf_egu_event_triggered_address_get(NRF_EGU_Type * NRF_EGUx,uint8_t channel)375*150812a8SEvalZero __STATIC_INLINE uint32_t * nrf_egu_event_triggered_address_get(NRF_EGU_Type * NRF_EGUx,
376*150812a8SEvalZero uint8_t channel)
377*150812a8SEvalZero {
378*150812a8SEvalZero NRFX_ASSERT(NRF_EGUx);
379*150812a8SEvalZero NRFX_ASSERT(channel < nrf_egu_channel_count(NRF_EGUx));
380*150812a8SEvalZero return (uint32_t*)&NRF_EGUx->EVENTS_TRIGGERED[channel];
381*150812a8SEvalZero }
382*150812a8SEvalZero
nrf_egu_event_triggered_get(NRF_EGU_Type * NRF_EGUx,uint8_t channel)383*150812a8SEvalZero __STATIC_INLINE nrf_egu_event_t nrf_egu_event_triggered_get(NRF_EGU_Type * NRF_EGUx,
384*150812a8SEvalZero uint8_t channel)
385*150812a8SEvalZero {
386*150812a8SEvalZero NRFX_ASSERT(NRF_EGUx);
387*150812a8SEvalZero NRFX_ASSERT(channel < nrf_egu_channel_count(NRF_EGUx));
388*150812a8SEvalZero return (nrf_egu_event_t)((uint32_t) NRF_EGU_EVENT_TRIGGERED0 + (channel * sizeof(uint32_t)));
389*150812a8SEvalZero }
390*150812a8SEvalZero
nrf_egu_int_enable(NRF_EGU_Type * NRF_EGUx,uint32_t egu_int_mask)391*150812a8SEvalZero __STATIC_INLINE void nrf_egu_int_enable(NRF_EGU_Type * NRF_EGUx, uint32_t egu_int_mask)
392*150812a8SEvalZero {
393*150812a8SEvalZero NRFX_ASSERT(NRF_EGUx);
394*150812a8SEvalZero NRF_EGUx->INTENSET = egu_int_mask;
395*150812a8SEvalZero }
396*150812a8SEvalZero
nrf_egu_int_enable_check(NRF_EGU_Type * NRF_EGUx,uint32_t egu_int_mask)397*150812a8SEvalZero __STATIC_INLINE bool nrf_egu_int_enable_check(NRF_EGU_Type * NRF_EGUx, uint32_t egu_int_mask)
398*150812a8SEvalZero {
399*150812a8SEvalZero NRFX_ASSERT(NRF_EGUx);
400*150812a8SEvalZero return (bool)(NRF_EGUx->INTENSET & egu_int_mask);
401*150812a8SEvalZero }
402*150812a8SEvalZero
nrf_egu_int_disable(NRF_EGU_Type * NRF_EGUx,uint32_t egu_int_mask)403*150812a8SEvalZero __STATIC_INLINE void nrf_egu_int_disable(NRF_EGU_Type * NRF_EGUx, uint32_t egu_int_mask)
404*150812a8SEvalZero {
405*150812a8SEvalZero NRFX_ASSERT(NRF_EGUx);
406*150812a8SEvalZero NRF_EGUx->INTENCLR = egu_int_mask;
407*150812a8SEvalZero }
408*150812a8SEvalZero
nrf_egu_int_get(NRF_EGU_Type * NRF_EGUx,uint8_t channel)409*150812a8SEvalZero __STATIC_INLINE nrf_egu_int_mask_t nrf_egu_int_get(NRF_EGU_Type * NRF_EGUx, uint8_t channel)
410*150812a8SEvalZero {
411*150812a8SEvalZero NRFX_ASSERT(NRF_EGUx);
412*150812a8SEvalZero NRFX_ASSERT(channel < nrf_egu_channel_count(NRF_EGUx));
413*150812a8SEvalZero return (nrf_egu_int_mask_t)((uint32_t) (EGU_INTENSET_TRIGGERED0_Msk << channel));
414*150812a8SEvalZero }
415*150812a8SEvalZero
416*150812a8SEvalZero #if defined(DPPI_PRESENT)
nrf_egu_subscribe_set(NRF_EGU_Type * p_reg,nrf_egu_task_t task,uint8_t channel)417*150812a8SEvalZero __STATIC_INLINE void nrf_egu_subscribe_set(NRF_EGU_Type * p_reg,
418*150812a8SEvalZero nrf_egu_task_t task,
419*150812a8SEvalZero uint8_t channel)
420*150812a8SEvalZero {
421*150812a8SEvalZero *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
422*150812a8SEvalZero ((uint32_t)channel | EGU_SUBSCRIBE_TRIGGER_EN_Msk);
423*150812a8SEvalZero }
424*150812a8SEvalZero
nrf_egu_subscribe_clear(NRF_EGU_Type * p_reg,nrf_egu_task_t task)425*150812a8SEvalZero __STATIC_INLINE void nrf_egu_subscribe_clear(NRF_EGU_Type * p_reg,
426*150812a8SEvalZero nrf_egu_task_t task)
427*150812a8SEvalZero {
428*150812a8SEvalZero *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
429*150812a8SEvalZero }
430*150812a8SEvalZero
nrf_egu_publish_set(NRF_EGU_Type * p_reg,nrf_egu_event_t event,uint8_t channel)431*150812a8SEvalZero __STATIC_INLINE void nrf_egu_publish_set(NRF_EGU_Type * p_reg,
432*150812a8SEvalZero nrf_egu_event_t event,
433*150812a8SEvalZero uint8_t channel)
434*150812a8SEvalZero {
435*150812a8SEvalZero *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
436*150812a8SEvalZero ((uint32_t)channel | EGU_PUBLISH_TRIGGERED_EN_Msk);
437*150812a8SEvalZero }
438*150812a8SEvalZero
nrf_egu_publish_clear(NRF_EGU_Type * p_reg,nrf_egu_event_t event)439*150812a8SEvalZero __STATIC_INLINE void nrf_egu_publish_clear(NRF_EGU_Type * p_reg,
440*150812a8SEvalZero nrf_egu_event_t event)
441*150812a8SEvalZero {
442*150812a8SEvalZero *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0;
443*150812a8SEvalZero }
444*150812a8SEvalZero #endif // defined(DPPI_PRESENT)
445*150812a8SEvalZero
446*150812a8SEvalZero #endif // SUPPRESS_INLINE_IMPLEMENTATION
447*150812a8SEvalZero
448*150812a8SEvalZero /** @} */
449*150812a8SEvalZero
450*150812a8SEvalZero #ifdef __cplusplus
451*150812a8SEvalZero }
452*150812a8SEvalZero #endif
453*150812a8SEvalZero
454*150812a8SEvalZero #endif
455