1 /*
2 * Copyright (c) 2018, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice, this
9 * list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the copyright holder nor the names of its
16 * contributors may be used to endorse or promote products derived from this
17 * software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #ifndef NRF_DPPI_H__
33 #define NRF_DPPI_H__
34
35 #include <nrfx.h>
36
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40
41 /**
42 * @defgroup nrf_dppi_hal DPPI Controller HAL
43 * @{
44 * @ingroup nrf_dppi
45 * @brief Hardware access layer for managing the Distributed Programmable Peripheral
46 * Interconnect Controller (DPPIC).
47 */
48
49 /** @brief DPPI channel groups. */
50 typedef enum
51 {
52 NRF_DPPI_CHANNEL_GROUP0 = 0, /**< Channel group 0. */
53 NRF_DPPI_CHANNEL_GROUP1 = 1, /**< Channel group 1. */
54 NRF_DPPI_CHANNEL_GROUP2 = 2, /**< Channel group 2. */
55 NRF_DPPI_CHANNEL_GROUP3 = 3, /**< Channel group 3. */
56 NRF_DPPI_CHANNEL_GROUP4 = 4, /**< Channel group 4. */
57 NRF_DPPI_CHANNEL_GROUP5 = 5 /**< Channel group 5. */
58 } nrf_dppi_channel_group_t;
59
60 /** @brief DPPI tasks. */
61 typedef enum
62 {
63 NRF_DPPI_TASK_CHG0_EN = offsetof(NRF_DPPIC_Type, TASKS_CHG[0].EN), /**< Enable channel group 0. */
64 NRF_DPPI_TASK_CHG0_DIS = offsetof(NRF_DPPIC_Type, TASKS_CHG[0].DIS), /**< Disable channel group 0. */
65 NRF_DPPI_TASK_CHG1_EN = offsetof(NRF_DPPIC_Type, TASKS_CHG[1].EN), /**< Enable channel group 1. */
66 NRF_DPPI_TASK_CHG1_DIS = offsetof(NRF_DPPIC_Type, TASKS_CHG[1].DIS), /**< Disable channel group 1. */
67 NRF_DPPI_TASK_CHG2_EN = offsetof(NRF_DPPIC_Type, TASKS_CHG[2].EN), /**< Enable channel group 2. */
68 NRF_DPPI_TASK_CHG2_DIS = offsetof(NRF_DPPIC_Type, TASKS_CHG[2].DIS), /**< Disable channel group 2. */
69 NRF_DPPI_TASK_CHG3_EN = offsetof(NRF_DPPIC_Type, TASKS_CHG[3].EN), /**< Enable channel group 3. */
70 NRF_DPPI_TASK_CHG3_DIS = offsetof(NRF_DPPIC_Type, TASKS_CHG[3].DIS), /**< Disable channel group 3. */
71 NRF_DPPI_TASK_CHG4_EN = offsetof(NRF_DPPIC_Type, TASKS_CHG[4].EN), /**< Enable channel group 4. */
72 NRF_DPPI_TASK_CHG4_DIS = offsetof(NRF_DPPIC_Type, TASKS_CHG[4].DIS), /**< Disable channel group 4. */
73 NRF_DPPI_TASK_CHG5_EN = offsetof(NRF_DPPIC_Type, TASKS_CHG[5].EN), /**< Enable channel group 5. */
74 NRF_DPPI_TASK_CHG5_DIS = offsetof(NRF_DPPIC_Type, TASKS_CHG[5].DIS) /**< Disable channel group 5. */
75 } nrf_dppi_task_t;
76
77 /**
78 * @brief Function for activating a DPPI task.
79 *
80 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
81 * @param[in] dppi_task Task to activate.
82 */
83 __STATIC_INLINE void nrf_dppi_task_trigger(NRF_DPPIC_Type * p_reg, nrf_dppi_task_t dppi_task);
84
85 /**
86 * @brief Function for checking the state of a specific DPPI channel.
87 *
88 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
89 * @param[in] channel Channel to check.
90 *
91 * @retval true If the channel is enabled.
92 * @retval false If the channel is not enabled.
93 */
94 __STATIC_INLINE bool nrf_dppi_channel_check(NRF_DPPIC_Type const * p_reg, uint8_t channel);
95
96 /**
97 * @brief Function for enabling multiple DPPI channels.
98 *
99 * The bits in @c mask value correspond to particular channels. It means that
100 * writing 1 to bit 0 enables channel 0, writing 1 to bit 1 enables channel 1 etc.
101 *
102 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
103 * @param[in] mask Channel mask.
104 */
105 __STATIC_INLINE void nrf_dppi_channels_enable(NRF_DPPIC_Type * p_reg, uint32_t mask);
106
107 /**
108 * @brief Function for disabling multiple DPPI channels.
109 *
110 * The bits in @c mask value correspond to particular channels. It means that
111 * writing 1 to bit 0 disables channel 0, writing 1 to bit 1 disables channel 1 etc.
112 *
113 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
114 * @param[in] mask Channel mask.
115 */
116 __STATIC_INLINE void nrf_dppi_channels_disable(NRF_DPPIC_Type * p_reg, uint32_t mask);
117
118 /**
119 * @brief Function for disabling all DPPI channels.
120 *
121 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
122 */
123 __STATIC_INLINE void nrf_dppi_channels_disable_all(NRF_DPPIC_Type * p_reg);
124
125 /**
126 * @brief Function for setting the subscribe configuration for a given
127 * DPPI task.
128 *
129 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
130 * @param[in] task Task for which to set the configuration.
131 * @param[in] channel Channel through which to subscribe events.
132 */
133 __STATIC_INLINE void nrf_dppi_subscribe_set(NRF_DPPIC_Type * p_reg,
134 nrf_dppi_task_t task,
135 uint8_t channel);
136
137 /**
138 * @brief Function for clearing the subscribe configuration for a given
139 * DPPI task.
140 *
141 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
142 * @param[in] task Task for which to clear the configuration.
143 */
144 __STATIC_INLINE void nrf_dppi_subscribe_clear(NRF_DPPIC_Type * p_reg, nrf_dppi_task_t task);
145
146 /**
147 * @brief Function for including multiple DPPI channels in a channel group.
148 *
149 * @details This function adds all specified channels to the group.
150 * The bits in @p channel_mask value correspond to particular channels. It means that
151 * writing 1 to bit 0 includes channel 0, writing 1 to bit 1 includes channel 1 etc.
152 *
153 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
154 * @param[in] channel_mask Channels to be included in the group.
155 * @param[in] channel_group Channel group.
156 */
157 __STATIC_INLINE void nrf_dppi_channels_include_in_group(NRF_DPPIC_Type * p_reg,
158 uint32_t channel_mask,
159 nrf_dppi_channel_group_t channel_group);
160
161 /**
162 * @brief Function for removing multiple DPPI channels from a channel group.
163 *
164 * @details This function removes all specified channels from the group.
165 * The bits in @c channel_mask value correspond to particular channels. It means that
166 * writing 1 to bit 0 removes channel 0, writing 1 to bit 1 removes channel 1 etc.
167 *
168 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
169 * @param[in] channel_mask Channels to be removed from the group.
170 * @param[in] channel_group Channel group.
171 */
172 __STATIC_INLINE void nrf_dppi_channels_remove_from_group(NRF_DPPIC_Type * p_reg,
173 uint32_t channel_mask,
174 nrf_dppi_channel_group_t channel_group);
175
176 /**
177 * @brief Function for removing all DPPI channels from a channel group.
178 *
179 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
180 * @param[in] group Channel group.
181 */
182 __STATIC_INLINE void nrf_dppi_group_clear(NRF_DPPIC_Type * p_reg,
183 nrf_dppi_channel_group_t group);
184
185 /**
186 * @brief Function for enabling a channel group.
187 *
188 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
189 * @param[in] group Channel group.
190 */
191 __STATIC_INLINE void nrf_dppi_group_enable(NRF_DPPIC_Type * p_reg,
192 nrf_dppi_channel_group_t group);
193
194 /**
195 * @brief Function for disabling a channel group.
196 *
197 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
198 * @param[in] group Channel group.
199 */
200 __STATIC_INLINE void nrf_dppi_group_disable(NRF_DPPIC_Type * p_reg,
201 nrf_dppi_channel_group_t group);
202
203
204 #ifndef SUPPRESS_INLINE_IMPLEMENTATION
205
nrf_dppi_task_trigger(NRF_DPPIC_Type * p_reg,nrf_dppi_task_t dppi_task)206 __STATIC_INLINE void nrf_dppi_task_trigger(NRF_DPPIC_Type * p_reg, nrf_dppi_task_t dppi_task)
207 {
208 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) dppi_task)) = 1;
209 }
210
nrf_dppi_channel_check(NRF_DPPIC_Type const * p_reg,uint8_t channel)211 __STATIC_INLINE bool nrf_dppi_channel_check(NRF_DPPIC_Type const * p_reg, uint8_t channel)
212 {
213 return ((p_reg->CHEN & (DPPIC_CHEN_CH0_Enabled << (DPPIC_CHEN_CH0_Pos + channel))) != 0);
214 }
215
nrf_dppi_channels_disable_all(NRF_DPPIC_Type * p_reg)216 __STATIC_INLINE void nrf_dppi_channels_disable_all(NRF_DPPIC_Type * p_reg)
217 {
218 p_reg->CHENCLR = 0xFFFFFFFFuL;
219 }
220
nrf_dppi_channels_enable(NRF_DPPIC_Type * p_reg,uint32_t mask)221 __STATIC_INLINE void nrf_dppi_channels_enable(NRF_DPPIC_Type * p_reg, uint32_t mask)
222 {
223 p_reg->CHENSET = mask;
224 }
225
nrf_dppi_channels_disable(NRF_DPPIC_Type * p_reg,uint32_t mask)226 __STATIC_INLINE void nrf_dppi_channels_disable(NRF_DPPIC_Type * p_reg, uint32_t mask)
227 {
228 p_reg->CHENCLR = mask;
229 }
230
nrf_dppi_subscribe_set(NRF_DPPIC_Type * p_reg,nrf_dppi_task_t task,uint8_t channel)231 __STATIC_INLINE void nrf_dppi_subscribe_set(NRF_DPPIC_Type * p_reg,
232 nrf_dppi_task_t task,
233 uint8_t channel)
234 {
235 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
236 ((uint32_t)channel | DPPIC_SUBSCRIBE_CHG_EN_EN_Msk);
237 }
238
nrf_dppi_subscribe_clear(NRF_DPPIC_Type * p_reg,nrf_dppi_task_t task)239 __STATIC_INLINE void nrf_dppi_subscribe_clear(NRF_DPPIC_Type * p_reg, nrf_dppi_task_t task)
240 {
241 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
242 }
243
nrf_dppi_channels_include_in_group(NRF_DPPIC_Type * p_reg,uint32_t channel_mask,nrf_dppi_channel_group_t channel_group)244 __STATIC_INLINE void nrf_dppi_channels_include_in_group(NRF_DPPIC_Type * p_reg,
245 uint32_t channel_mask,
246 nrf_dppi_channel_group_t channel_group)
247 {
248 p_reg->CHG[(uint32_t) channel_group] =
249 p_reg->CHG[(uint32_t) channel_group] | (channel_mask);
250 }
251
nrf_dppi_channels_remove_from_group(NRF_DPPIC_Type * p_reg,uint32_t channel_mask,nrf_dppi_channel_group_t channel_group)252 __STATIC_INLINE void nrf_dppi_channels_remove_from_group(NRF_DPPIC_Type * p_reg,
253 uint32_t channel_mask,
254 nrf_dppi_channel_group_t channel_group)
255 {
256 p_reg->CHG[(uint32_t) channel_group] =
257 p_reg->CHG[(uint32_t) channel_group] & ~(channel_mask);
258 }
259
nrf_dppi_group_clear(NRF_DPPIC_Type * p_reg,nrf_dppi_channel_group_t group)260 __STATIC_INLINE void nrf_dppi_group_clear(NRF_DPPIC_Type * p_reg,
261 nrf_dppi_channel_group_t group)
262 {
263 p_reg->CHG[(uint32_t) group] = 0;
264 }
265
nrf_dppi_group_enable(NRF_DPPIC_Type * p_reg,nrf_dppi_channel_group_t group)266 __STATIC_INLINE void nrf_dppi_group_enable(NRF_DPPIC_Type * p_reg, nrf_dppi_channel_group_t group)
267 {
268 p_reg->TASKS_CHG[(uint32_t) group].EN = 1;
269 }
270
nrf_dppi_group_disable(NRF_DPPIC_Type * p_reg,nrf_dppi_channel_group_t group)271 __STATIC_INLINE void nrf_dppi_group_disable(NRF_DPPIC_Type * p_reg,
272 nrf_dppi_channel_group_t group)
273 {
274 p_reg->TASKS_CHG[(uint32_t) group].DIS = 1;
275 }
276
277 #endif // SUPPRESS_INLINE_IMPLEMENTATION
278
279 /** @} */
280
281 #ifdef __cplusplus
282 }
283 #endif
284
285 #endif // NRF_DPPIC_H__
286