1*150812a8SEvalZero /*
2*150812a8SEvalZero * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
3*150812a8SEvalZero * All rights reserved.
4*150812a8SEvalZero *
5*150812a8SEvalZero * Redistribution and use in source and binary forms, with or without
6*150812a8SEvalZero * modification, are permitted provided that the following conditions are met:
7*150812a8SEvalZero *
8*150812a8SEvalZero * 1. Redistributions of source code must retain the above copyright notice, this
9*150812a8SEvalZero * list of conditions and the following disclaimer.
10*150812a8SEvalZero *
11*150812a8SEvalZero * 2. Redistributions in binary form must reproduce the above copyright
12*150812a8SEvalZero * notice, this list of conditions and the following disclaimer in the
13*150812a8SEvalZero * documentation and/or other materials provided with the distribution.
14*150812a8SEvalZero *
15*150812a8SEvalZero * 3. Neither the name of the copyright holder nor the names of its
16*150812a8SEvalZero * contributors may be used to endorse or promote products derived from this
17*150812a8SEvalZero * software without specific prior written permission.
18*150812a8SEvalZero *
19*150812a8SEvalZero * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20*150812a8SEvalZero * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21*150812a8SEvalZero * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22*150812a8SEvalZero * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23*150812a8SEvalZero * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24*150812a8SEvalZero * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25*150812a8SEvalZero * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26*150812a8SEvalZero * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27*150812a8SEvalZero * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28*150812a8SEvalZero * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29*150812a8SEvalZero * POSSIBILITY OF SUCH DAMAGE.
30*150812a8SEvalZero */
31*150812a8SEvalZero
32*150812a8SEvalZero #include <nrfx.h>
33*150812a8SEvalZero
34*150812a8SEvalZero #if NRFX_CHECK(NRFX_QDEC_ENABLED)
35*150812a8SEvalZero
36*150812a8SEvalZero #include <nrfx_qdec.h>
37*150812a8SEvalZero #include <hal/nrf_gpio.h>
38*150812a8SEvalZero
39*150812a8SEvalZero #define NRFX_LOG_MODULE QDEC
40*150812a8SEvalZero #include <nrfx_log.h>
41*150812a8SEvalZero
42*150812a8SEvalZero #define EVT_TO_STR(event) \
43*150812a8SEvalZero (event == NRF_QDEC_EVENT_SAMPLERDY ? "NRF_QDEC_EVENT_SAMPLERDY" : \
44*150812a8SEvalZero (event == NRF_QDEC_EVENT_REPORTRDY ? "NRF_QDEC_EVENT_REPORTRDY" : \
45*150812a8SEvalZero (event == NRF_QDEC_EVENT_ACCOF ? "NRF_QDEC_EVENT_ACCOF" : \
46*150812a8SEvalZero "UNKNOWN EVENT")))
47*150812a8SEvalZero
48*150812a8SEvalZero
49*150812a8SEvalZero static nrfx_qdec_event_handler_t m_qdec_event_handler = NULL;
50*150812a8SEvalZero static nrfx_drv_state_t m_state = NRFX_DRV_STATE_UNINITIALIZED;
51*150812a8SEvalZero
nrfx_qdec_irq_handler(void)52*150812a8SEvalZero void nrfx_qdec_irq_handler(void)
53*150812a8SEvalZero {
54*150812a8SEvalZero nrfx_qdec_event_t event;
55*150812a8SEvalZero if ( nrf_qdec_event_check(NRF_QDEC_EVENT_SAMPLERDY) &&
56*150812a8SEvalZero nrf_qdec_int_enable_check(NRF_QDEC_INT_SAMPLERDY_MASK) )
57*150812a8SEvalZero {
58*150812a8SEvalZero nrf_qdec_event_clear(NRF_QDEC_EVENT_SAMPLERDY);
59*150812a8SEvalZero NRFX_LOG_DEBUG("Event: %s.", EVT_TO_STR(NRF_QDEC_EVENT_SAMPLERDY));
60*150812a8SEvalZero
61*150812a8SEvalZero event.type = NRF_QDEC_EVENT_SAMPLERDY;
62*150812a8SEvalZero event.data.sample.value = (int8_t)nrf_qdec_sample_get();
63*150812a8SEvalZero m_qdec_event_handler(event);
64*150812a8SEvalZero }
65*150812a8SEvalZero
66*150812a8SEvalZero if ( nrf_qdec_event_check(NRF_QDEC_EVENT_REPORTRDY) &&
67*150812a8SEvalZero nrf_qdec_int_enable_check(NRF_QDEC_INT_REPORTRDY_MASK) )
68*150812a8SEvalZero {
69*150812a8SEvalZero nrf_qdec_event_clear(NRF_QDEC_EVENT_REPORTRDY);
70*150812a8SEvalZero NRFX_LOG_DEBUG("Event: %s.", EVT_TO_STR(NRF_QDEC_EVENT_REPORTRDY));
71*150812a8SEvalZero
72*150812a8SEvalZero event.type = NRF_QDEC_EVENT_REPORTRDY;
73*150812a8SEvalZero
74*150812a8SEvalZero event.data.report.acc = (int16_t)nrf_qdec_accread_get();
75*150812a8SEvalZero event.data.report.accdbl = (uint16_t)nrf_qdec_accdblread_get();
76*150812a8SEvalZero m_qdec_event_handler(event);
77*150812a8SEvalZero }
78*150812a8SEvalZero
79*150812a8SEvalZero if ( nrf_qdec_event_check(NRF_QDEC_EVENT_ACCOF) &&
80*150812a8SEvalZero nrf_qdec_int_enable_check(NRF_QDEC_INT_ACCOF_MASK) )
81*150812a8SEvalZero {
82*150812a8SEvalZero nrf_qdec_event_clear(NRF_QDEC_EVENT_ACCOF);
83*150812a8SEvalZero NRFX_LOG_DEBUG("Event: %s.", EVT_TO_STR(NRF_QDEC_EVENT_ACCOF));
84*150812a8SEvalZero
85*150812a8SEvalZero event.type = NRF_QDEC_EVENT_ACCOF;
86*150812a8SEvalZero m_qdec_event_handler(event);
87*150812a8SEvalZero }
88*150812a8SEvalZero }
89*150812a8SEvalZero
90*150812a8SEvalZero
nrfx_qdec_init(nrfx_qdec_config_t const * p_config,nrfx_qdec_event_handler_t event_handler)91*150812a8SEvalZero nrfx_err_t nrfx_qdec_init(nrfx_qdec_config_t const * p_config,
92*150812a8SEvalZero nrfx_qdec_event_handler_t event_handler)
93*150812a8SEvalZero {
94*150812a8SEvalZero NRFX_ASSERT(p_config);
95*150812a8SEvalZero NRFX_ASSERT(event_handler);
96*150812a8SEvalZero nrfx_err_t err_code;
97*150812a8SEvalZero
98*150812a8SEvalZero if (m_state != NRFX_DRV_STATE_UNINITIALIZED)
99*150812a8SEvalZero {
100*150812a8SEvalZero err_code = NRFX_ERROR_INVALID_STATE;
101*150812a8SEvalZero NRFX_LOG_WARNING("Function: %s, error code: %s.",
102*150812a8SEvalZero __func__,
103*150812a8SEvalZero NRFX_LOG_ERROR_STRING_GET(err_code));
104*150812a8SEvalZero return err_code;
105*150812a8SEvalZero }
106*150812a8SEvalZero
107*150812a8SEvalZero m_qdec_event_handler = event_handler;
108*150812a8SEvalZero
109*150812a8SEvalZero nrf_qdec_sampleper_set(p_config->sampleper);
110*150812a8SEvalZero nrf_gpio_cfg_input(p_config->psela, NRF_GPIO_PIN_NOPULL);
111*150812a8SEvalZero nrf_gpio_cfg_input(p_config->pselb, NRF_GPIO_PIN_NOPULL);
112*150812a8SEvalZero if (p_config->pselled != NRF_QDEC_LED_NOT_CONNECTED)
113*150812a8SEvalZero {
114*150812a8SEvalZero nrf_gpio_cfg_input(p_config->pselled, NRF_GPIO_PIN_NOPULL);
115*150812a8SEvalZero nrf_qdec_ledpre_set(p_config->ledpre);
116*150812a8SEvalZero nrf_qdec_ledpol_set(p_config->ledpol);
117*150812a8SEvalZero }
118*150812a8SEvalZero nrf_qdec_pio_assign(p_config->psela, p_config->pselb, p_config->pselled);
119*150812a8SEvalZero nrf_qdec_shorts_enable(NRF_QDEC_SHORT_REPORTRDY_READCLRACC_MASK);
120*150812a8SEvalZero
121*150812a8SEvalZero if (p_config->dbfen)
122*150812a8SEvalZero {
123*150812a8SEvalZero nrf_qdec_dbfen_enable();
124*150812a8SEvalZero }
125*150812a8SEvalZero else
126*150812a8SEvalZero {
127*150812a8SEvalZero nrf_qdec_dbfen_disable();
128*150812a8SEvalZero }
129*150812a8SEvalZero
130*150812a8SEvalZero uint32_t int_mask = NRF_QDEC_INT_ACCOF_MASK;
131*150812a8SEvalZero
132*150812a8SEvalZero if (p_config->reportper != NRF_QDEC_REPORTPER_DISABLED)
133*150812a8SEvalZero {
134*150812a8SEvalZero nrf_qdec_reportper_set(p_config->reportper);
135*150812a8SEvalZero int_mask |= NRF_QDEC_INT_REPORTRDY_MASK;
136*150812a8SEvalZero }
137*150812a8SEvalZero
138*150812a8SEvalZero if (p_config->sample_inten)
139*150812a8SEvalZero {
140*150812a8SEvalZero int_mask |= NRF_QDEC_INT_SAMPLERDY_MASK;
141*150812a8SEvalZero }
142*150812a8SEvalZero
143*150812a8SEvalZero nrf_qdec_int_enable(int_mask);
144*150812a8SEvalZero NRFX_IRQ_PRIORITY_SET(QDEC_IRQn, p_config->interrupt_priority);
145*150812a8SEvalZero NRFX_IRQ_ENABLE(QDEC_IRQn);
146*150812a8SEvalZero
147*150812a8SEvalZero m_state = NRFX_DRV_STATE_INITIALIZED;
148*150812a8SEvalZero
149*150812a8SEvalZero err_code = NRFX_SUCCESS;
150*150812a8SEvalZero NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
151*150812a8SEvalZero return err_code;
152*150812a8SEvalZero }
153*150812a8SEvalZero
nrfx_qdec_uninit(void)154*150812a8SEvalZero void nrfx_qdec_uninit(void)
155*150812a8SEvalZero {
156*150812a8SEvalZero NRFX_ASSERT(m_state != NRFX_DRV_STATE_UNINITIALIZED);
157*150812a8SEvalZero nrfx_qdec_disable();
158*150812a8SEvalZero NRFX_IRQ_DISABLE(QDEC_IRQn);
159*150812a8SEvalZero m_state = NRFX_DRV_STATE_UNINITIALIZED;
160*150812a8SEvalZero NRFX_LOG_INFO("Uninitialized.");
161*150812a8SEvalZero }
162*150812a8SEvalZero
nrfx_qdec_enable(void)163*150812a8SEvalZero void nrfx_qdec_enable(void)
164*150812a8SEvalZero {
165*150812a8SEvalZero NRFX_ASSERT(m_state == NRFX_DRV_STATE_INITIALIZED);
166*150812a8SEvalZero nrf_qdec_enable();
167*150812a8SEvalZero nrf_qdec_task_trigger(NRF_QDEC_TASK_START);
168*150812a8SEvalZero m_state = NRFX_DRV_STATE_POWERED_ON;
169*150812a8SEvalZero NRFX_LOG_INFO("Enabled.");
170*150812a8SEvalZero }
171*150812a8SEvalZero
nrfx_qdec_disable(void)172*150812a8SEvalZero void nrfx_qdec_disable(void)
173*150812a8SEvalZero {
174*150812a8SEvalZero NRFX_ASSERT(m_state == NRFX_DRV_STATE_POWERED_ON);
175*150812a8SEvalZero nrf_qdec_task_trigger(NRF_QDEC_TASK_STOP);
176*150812a8SEvalZero nrf_qdec_disable();
177*150812a8SEvalZero m_state = NRFX_DRV_STATE_INITIALIZED;
178*150812a8SEvalZero NRFX_LOG_INFO("Disabled.");
179*150812a8SEvalZero }
180*150812a8SEvalZero
nrfx_qdec_accumulators_read(int16_t * p_acc,int16_t * p_accdbl)181*150812a8SEvalZero void nrfx_qdec_accumulators_read(int16_t * p_acc, int16_t * p_accdbl)
182*150812a8SEvalZero {
183*150812a8SEvalZero NRFX_ASSERT(m_state == NRFX_DRV_STATE_POWERED_ON);
184*150812a8SEvalZero nrf_qdec_task_trigger(NRF_QDEC_TASK_READCLRACC);
185*150812a8SEvalZero
186*150812a8SEvalZero *p_acc = (int16_t)nrf_qdec_accread_get();
187*150812a8SEvalZero *p_accdbl = (int16_t)nrf_qdec_accdblread_get();
188*150812a8SEvalZero
189*150812a8SEvalZero NRFX_LOG_DEBUG("Accumulators data, ACC register:");
190*150812a8SEvalZero NRFX_LOG_HEXDUMP_DEBUG((uint8_t *)p_acc, sizeof(p_acc[0]));
191*150812a8SEvalZero NRFX_LOG_DEBUG("Accumulators data, ACCDBL register:");
192*150812a8SEvalZero NRFX_LOG_HEXDUMP_DEBUG((uint8_t *)p_accdbl, sizeof(p_accdbl[0]));
193*150812a8SEvalZero }
194*150812a8SEvalZero
195*150812a8SEvalZero #endif // NRFX_CHECK(NRFX_QDEC_ENABLED)
196