1*150812a8SEvalZero /*
2*150812a8SEvalZero * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA
3*150812a8SEvalZero * All rights reserved.
4*150812a8SEvalZero *
5*150812a8SEvalZero * Redistribution and use in source and binary forms, with or without
6*150812a8SEvalZero * modification, are permitted provided that the following conditions are met:
7*150812a8SEvalZero *
8*150812a8SEvalZero * 1. Redistributions of source code must retain the above copyright notice, this
9*150812a8SEvalZero * list of conditions and the following disclaimer.
10*150812a8SEvalZero *
11*150812a8SEvalZero * 2. Redistributions in binary form must reproduce the above copyright
12*150812a8SEvalZero * notice, this list of conditions and the following disclaimer in the
13*150812a8SEvalZero * documentation and/or other materials provided with the distribution.
14*150812a8SEvalZero *
15*150812a8SEvalZero * 3. Neither the name of the copyright holder nor the names of its
16*150812a8SEvalZero * contributors may be used to endorse or promote products derived from this
17*150812a8SEvalZero * software without specific prior written permission.
18*150812a8SEvalZero *
19*150812a8SEvalZero * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20*150812a8SEvalZero * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21*150812a8SEvalZero * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22*150812a8SEvalZero * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23*150812a8SEvalZero * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24*150812a8SEvalZero * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25*150812a8SEvalZero * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26*150812a8SEvalZero * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27*150812a8SEvalZero * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28*150812a8SEvalZero * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29*150812a8SEvalZero * POSSIBILITY OF SUCH DAMAGE.
30*150812a8SEvalZero */
31*150812a8SEvalZero
32*150812a8SEvalZero #ifndef NRFX_WDT_H__
33*150812a8SEvalZero #define NRFX_WDT_H__
34*150812a8SEvalZero
35*150812a8SEvalZero #include <nrfx.h>
36*150812a8SEvalZero #include <hal/nrf_wdt.h>
37*150812a8SEvalZero
38*150812a8SEvalZero #ifdef __cplusplus
39*150812a8SEvalZero extern "C" {
40*150812a8SEvalZero #endif
41*150812a8SEvalZero
42*150812a8SEvalZero /**
43*150812a8SEvalZero * @defgroup nrfx_wdt WDT driver
44*150812a8SEvalZero * @{
45*150812a8SEvalZero * @ingroup nrf_wdt
46*150812a8SEvalZero * @brief Watchdog Timer (WDT) peripheral driver.
47*150812a8SEvalZero */
48*150812a8SEvalZero
49*150812a8SEvalZero #if !NRFX_CHECK(NRFX_WDT_CONFIG_NO_IRQ) || defined(__NRFX_DOXYGEN__)
50*150812a8SEvalZero /**
51*150812a8SEvalZero * @brief WDT instance interrupt priority configuration.
52*150812a8SEvalZero */
53*150812a8SEvalZero #define NRFX_WDT_IRQ_CONFIG .interrupt_priority = NRFX_WDT_CONFIG_IRQ_PRIORITY
54*150812a8SEvalZero #else
55*150812a8SEvalZero #define NRFX_WDT_IRQ_CONFIG
56*150812a8SEvalZero #endif
57*150812a8SEvalZero
58*150812a8SEvalZero /**@brief Struct for WDT initialization. */
59*150812a8SEvalZero typedef struct
60*150812a8SEvalZero {
61*150812a8SEvalZero nrf_wdt_behaviour_t behaviour; /**< WDT behaviour when CPU in sleep/halt mode. */
62*150812a8SEvalZero uint32_t reload_value; /**< WDT reload value in ms. */
63*150812a8SEvalZero #if !NRFX_CHECK(NRFX_WDT_CONFIG_NO_IRQ) || defined(__NRFX_DOXYGEN__)
64*150812a8SEvalZero uint8_t interrupt_priority; /**< WDT interrupt priority */
65*150812a8SEvalZero #endif
66*150812a8SEvalZero } nrfx_wdt_config_t;
67*150812a8SEvalZero
68*150812a8SEvalZero /**@brief WDT event handler function type. */
69*150812a8SEvalZero typedef void (*nrfx_wdt_event_handler_t)(void);
70*150812a8SEvalZero
71*150812a8SEvalZero /**@brief WDT channel id type. */
72*150812a8SEvalZero typedef nrf_wdt_rr_register_t nrfx_wdt_channel_id;
73*150812a8SEvalZero
74*150812a8SEvalZero #define NRFX_WDT_DEAFULT_CONFIG \
75*150812a8SEvalZero { \
76*150812a8SEvalZero .behaviour = (nrf_wdt_behaviour_t)NRFX_WDT_CONFIG_BEHAVIOUR, \
77*150812a8SEvalZero .reload_value = NRFX_WDT_CONFIG_RELOAD_VALUE, \
78*150812a8SEvalZero NRFX_WDT_IRQ_CONFIG \
79*150812a8SEvalZero }
80*150812a8SEvalZero /**
81*150812a8SEvalZero * @brief This function initializes watchdog.
82*150812a8SEvalZero *
83*150812a8SEvalZero * @param[in] p_config Pointer to the structure with initial configuration.
84*150812a8SEvalZero * @param[in] wdt_event_handler Event handler provided by the user. Ignored when
85*150812a8SEvalZero * @ref NRFX_WDT_CONFIG_NO_IRQ option is enabled.
86*150812a8SEvalZero *
87*150812a8SEvalZero * @return NRFX_SUCCESS on success, otherwise an error code.
88*150812a8SEvalZero */
89*150812a8SEvalZero nrfx_err_t nrfx_wdt_init(nrfx_wdt_config_t const * p_config,
90*150812a8SEvalZero nrfx_wdt_event_handler_t wdt_event_handler);
91*150812a8SEvalZero
92*150812a8SEvalZero /**
93*150812a8SEvalZero * @brief This function allocate watchdog channel.
94*150812a8SEvalZero *
95*150812a8SEvalZero * @note This function can not be called after nrfx_wdt_start(void).
96*150812a8SEvalZero *
97*150812a8SEvalZero * @param[out] p_channel_id ID of granted channel.
98*150812a8SEvalZero *
99*150812a8SEvalZero * @return NRFX_SUCCESS on success, otherwise an error code.
100*150812a8SEvalZero */
101*150812a8SEvalZero nrfx_err_t nrfx_wdt_channel_alloc(nrfx_wdt_channel_id * p_channel_id);
102*150812a8SEvalZero
103*150812a8SEvalZero /**
104*150812a8SEvalZero * @brief This function starts watchdog.
105*150812a8SEvalZero *
106*150812a8SEvalZero * @note After calling this function the watchdog is started, so the user needs to feed all allocated
107*150812a8SEvalZero * watchdog channels to avoid reset. At least one watchdog channel has to be allocated.
108*150812a8SEvalZero */
109*150812a8SEvalZero void nrfx_wdt_enable(void);
110*150812a8SEvalZero
111*150812a8SEvalZero /**
112*150812a8SEvalZero * @brief This function feeds the watchdog.
113*150812a8SEvalZero *
114*150812a8SEvalZero * @details Function feeds all allocated watchdog channels.
115*150812a8SEvalZero */
116*150812a8SEvalZero void nrfx_wdt_feed(void);
117*150812a8SEvalZero
118*150812a8SEvalZero /**
119*150812a8SEvalZero * @brief This function feeds the invidual watchdog channel.
120*150812a8SEvalZero *
121*150812a8SEvalZero * @param[in] channel_id ID of watchdog channel.
122*150812a8SEvalZero */
123*150812a8SEvalZero void nrfx_wdt_channel_feed(nrfx_wdt_channel_id channel_id);
124*150812a8SEvalZero
125*150812a8SEvalZero /**@brief Function for returning a requested task address for the wdt driver module.
126*150812a8SEvalZero *
127*150812a8SEvalZero * @param[in] task One of the peripheral tasks.
128*150812a8SEvalZero *
129*150812a8SEvalZero * @retval Task address.
130*150812a8SEvalZero */
nrfx_wdt_ppi_task_addr(nrf_wdt_task_t task)131*150812a8SEvalZero __STATIC_INLINE uint32_t nrfx_wdt_ppi_task_addr(nrf_wdt_task_t task)
132*150812a8SEvalZero {
133*150812a8SEvalZero return nrf_wdt_task_address_get(task);
134*150812a8SEvalZero }
135*150812a8SEvalZero
136*150812a8SEvalZero /**@brief Function for returning a requested event address for the wdt driver module.
137*150812a8SEvalZero *
138*150812a8SEvalZero * @param[in] event One of the peripheral events.
139*150812a8SEvalZero *
140*150812a8SEvalZero * @retval Event address
141*150812a8SEvalZero */
nrfx_wdt_ppi_event_addr(nrf_wdt_event_t event)142*150812a8SEvalZero __STATIC_INLINE uint32_t nrfx_wdt_ppi_event_addr(nrf_wdt_event_t event)
143*150812a8SEvalZero {
144*150812a8SEvalZero return nrf_wdt_event_address_get(event);
145*150812a8SEvalZero }
146*150812a8SEvalZero
147*150812a8SEvalZero
148*150812a8SEvalZero #if !NRFX_CHECK(NRFX_WDT_CONFIG_NO_IRQ)
149*150812a8SEvalZero void nrfx_wdt_irq_handler(void);
150*150812a8SEvalZero #endif
151*150812a8SEvalZero
152*150812a8SEvalZero
153*150812a8SEvalZero /** @} */
154*150812a8SEvalZero
155*150812a8SEvalZero #ifdef __cplusplus
156*150812a8SEvalZero }
157*150812a8SEvalZero #endif
158*150812a8SEvalZero
159*150812a8SEvalZero #endif
160*150812a8SEvalZero
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