1*150812a8SEvalZero /*
2*150812a8SEvalZero * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
3*150812a8SEvalZero * All rights reserved.
4*150812a8SEvalZero *
5*150812a8SEvalZero * Redistribution and use in source and binary forms, with or without
6*150812a8SEvalZero * modification, are permitted provided that the following conditions are met:
7*150812a8SEvalZero *
8*150812a8SEvalZero * 1. Redistributions of source code must retain the above copyright notice, this
9*150812a8SEvalZero * list of conditions and the following disclaimer.
10*150812a8SEvalZero *
11*150812a8SEvalZero * 2. Redistributions in binary form must reproduce the above copyright
12*150812a8SEvalZero * notice, this list of conditions and the following disclaimer in the
13*150812a8SEvalZero * documentation and/or other materials provided with the distribution.
14*150812a8SEvalZero *
15*150812a8SEvalZero * 3. Neither the name of the copyright holder nor the names of its
16*150812a8SEvalZero * contributors may be used to endorse or promote products derived from this
17*150812a8SEvalZero * software without specific prior written permission.
18*150812a8SEvalZero *
19*150812a8SEvalZero * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20*150812a8SEvalZero * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21*150812a8SEvalZero * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22*150812a8SEvalZero * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23*150812a8SEvalZero * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24*150812a8SEvalZero * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25*150812a8SEvalZero * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26*150812a8SEvalZero * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27*150812a8SEvalZero * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28*150812a8SEvalZero * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29*150812a8SEvalZero * POSSIBILITY OF SUCH DAMAGE.
30*150812a8SEvalZero */
31*150812a8SEvalZero
32*150812a8SEvalZero #ifndef NRFX_SWI_H__
33*150812a8SEvalZero #define NRFX_SWI_H__
34*150812a8SEvalZero
35*150812a8SEvalZero #include <nrfx.h>
36*150812a8SEvalZero
37*150812a8SEvalZero #if NRFX_CHECK(NRFX_EGU_ENABLED)
38*150812a8SEvalZero #include <hal/nrf_egu.h>
39*150812a8SEvalZero #endif
40*150812a8SEvalZero
41*150812a8SEvalZero #ifndef SWI_COUNT
42*150812a8SEvalZero #define SWI_COUNT EGU_COUNT
43*150812a8SEvalZero #endif
44*150812a8SEvalZero
45*150812a8SEvalZero #ifdef __cplusplus
46*150812a8SEvalZero extern "C" {
47*150812a8SEvalZero #endif
48*150812a8SEvalZero
49*150812a8SEvalZero /**
50*150812a8SEvalZero * @defgroup nrfx_swi SWI driver
51*150812a8SEvalZero * @{
52*150812a8SEvalZero * @ingroup nrf_swi_egu
53*150812a8SEvalZero *
54*150812a8SEvalZero * @brief Driver for managing software interrupts (SWI).
55*150812a8SEvalZero */
56*150812a8SEvalZero
57*150812a8SEvalZero /** @brief SWI instance. */
58*150812a8SEvalZero typedef uint8_t nrfx_swi_t;
59*150812a8SEvalZero
60*150812a8SEvalZero /**
61*150812a8SEvalZero * @brief SWI user flags.
62*150812a8SEvalZero *
63*150812a8SEvalZero * User flags are set during the SWI trigger and passed to the callback function as an argument.
64*150812a8SEvalZero */
65*150812a8SEvalZero typedef uint16_t nrfx_swi_flags_t;
66*150812a8SEvalZero
67*150812a8SEvalZero /** @brief Unallocated instance value. */
68*150812a8SEvalZero #define NRFX_SWI_UNALLOCATED ((nrfx_swi_t)0xFFuL)
69*150812a8SEvalZero
70*150812a8SEvalZero /** @brief Default SWI priority. */
71*150812a8SEvalZero #define NRFX_SWI_DEFAULT_PRIORITY APP_IRQ_PRIORITY_LOWEST
72*150812a8SEvalZero
73*150812a8SEvalZero /**
74*150812a8SEvalZero * @brief SWI handler function.
75*150812a8SEvalZero *
76*150812a8SEvalZero * @param swi SWI instance.
77*150812a8SEvalZero * @param flags User flags.
78*150812a8SEvalZero */
79*150812a8SEvalZero typedef void (*nrfx_swi_handler_t)(nrfx_swi_t swi, nrfx_swi_flags_t flags);
80*150812a8SEvalZero
81*150812a8SEvalZero
82*150812a8SEvalZero /**
83*150812a8SEvalZero * @brief Function for allocating the first unused SWI instance and setting a handler.
84*150812a8SEvalZero *
85*150812a8SEvalZero * If provided handler is not NULL, an allocated SWI has its interrupt enabled by default.
86*150812a8SEvalZero * The interrupt can be disabled by @ref nrfx_swi_int_disable.
87*150812a8SEvalZero *
88*150812a8SEvalZero * @param[out] p_swi Points to a place where the allocated SWI instance
89*150812a8SEvalZero * number is to be stored.
90*150812a8SEvalZero * @param[in] event_handler Event handler function.
91*150812a8SEvalZero * If NULL, no interrupt will be enabled.
92*150812a8SEvalZero * It can be NULL only if the EGU driver is enabled.
93*150812a8SEvalZero * For classic SWI, it must be a valid handler pointer.
94*150812a8SEvalZero * @param[in] irq_priority Interrupt priority.
95*150812a8SEvalZero *
96*150812a8SEvalZero * @retval NRFX_SUCCESS If the SWI was successfully allocated.
97*150812a8SEvalZero * @retval NRFX_ERROR_NO_MEM If there is no available SWI to be used.
98*150812a8SEvalZero */
99*150812a8SEvalZero nrfx_err_t nrfx_swi_alloc(nrfx_swi_t * p_swi,
100*150812a8SEvalZero nrfx_swi_handler_t event_handler,
101*150812a8SEvalZero uint32_t irq_priority);
102*150812a8SEvalZero
103*150812a8SEvalZero /**
104*150812a8SEvalZero * @brief Function for disabling an allocated SWI interrupt.
105*150812a8SEvalZero *
106*150812a8SEvalZero * Use @ref nrfx_swi_int_enable to re-enable the interrupt.
107*150812a8SEvalZero *
108*150812a8SEvalZero * @param[in] swi SWI instance.
109*150812a8SEvalZero */
110*150812a8SEvalZero void nrfx_swi_int_disable(nrfx_swi_t swi);
111*150812a8SEvalZero
112*150812a8SEvalZero /**
113*150812a8SEvalZero * @brief Function for enabling an allocated SWI interrupt.
114*150812a8SEvalZero *
115*150812a8SEvalZero * @param[in] swi SWI instance.
116*150812a8SEvalZero */
117*150812a8SEvalZero void nrfx_swi_int_enable(nrfx_swi_t swi);
118*150812a8SEvalZero
119*150812a8SEvalZero /**
120*150812a8SEvalZero * @brief Function for freeing a previously allocated SWI.
121*150812a8SEvalZero *
122*150812a8SEvalZero * @param[in,out] p_swi SWI instance to free. The value is changed to
123*150812a8SEvalZero * @ref NRFX_SWI_UNALLOCATED on success.
124*150812a8SEvalZero */
125*150812a8SEvalZero void nrfx_swi_free(nrfx_swi_t * p_swi);
126*150812a8SEvalZero
127*150812a8SEvalZero /** @brief Function for freeing all allocated SWIs. */
128*150812a8SEvalZero void nrfx_swi_all_free(void);
129*150812a8SEvalZero
130*150812a8SEvalZero /**
131*150812a8SEvalZero * @brief Function for triggering the SWI.
132*150812a8SEvalZero *
133*150812a8SEvalZero * @param[in] swi SWI to trigger.
134*150812a8SEvalZero * @param[in] flag_number Number of user flag to trigger.
135*150812a8SEvalZero */
136*150812a8SEvalZero void nrfx_swi_trigger(nrfx_swi_t swi,
137*150812a8SEvalZero uint8_t flag_number);
138*150812a8SEvalZero
139*150812a8SEvalZero /**
140*150812a8SEvalZero * @brief Function for checking if the specified SWI is currently allocated.
141*150812a8SEvalZero *
142*150812a8SEvalZero * @param[in] swi SWI instance.
143*150812a8SEvalZero *
144*150812a8SEvalZero * @retval true If the SWI instance is allocated.
145*150812a8SEvalZero * @retval false Otherwise.
146*150812a8SEvalZero */
147*150812a8SEvalZero bool nrfx_swi_is_allocated(nrfx_swi_t swi);
148*150812a8SEvalZero
149*150812a8SEvalZero #if NRFX_CHECK(NRFX_EGU_ENABLED) || defined(__NRFX_DOXYGEN__)
150*150812a8SEvalZero
151*150812a8SEvalZero /**
152*150812a8SEvalZero * @brief Function for returning the base address of the EGU peripheral
153*150812a8SEvalZero * associated with the specified SWI instance.
154*150812a8SEvalZero *
155*150812a8SEvalZero * @param[in] swi SWI instance.
156*150812a8SEvalZero *
157*150812a8SEvalZero * @returns EGU base address or NULL if the specified SWI instance number
158*150812a8SEvalZero * is too high.
159*150812a8SEvalZero */
nrfx_swi_egu_instance_get(nrfx_swi_t swi)160*150812a8SEvalZero __STATIC_INLINE NRF_EGU_Type * nrfx_swi_egu_instance_get(nrfx_swi_t swi)
161*150812a8SEvalZero {
162*150812a8SEvalZero #if (EGU_COUNT < SWI_COUNT)
163*150812a8SEvalZero if (swi >= EGU_COUNT)
164*150812a8SEvalZero {
165*150812a8SEvalZero return NULL;
166*150812a8SEvalZero }
167*150812a8SEvalZero #endif
168*150812a8SEvalZero uint32_t offset = ((uint32_t)swi) * ((uint32_t)NRF_EGU1 - (uint32_t)NRF_EGU0);
169*150812a8SEvalZero return (NRF_EGU_Type *)((uint32_t)NRF_EGU0 + offset);
170*150812a8SEvalZero }
171*150812a8SEvalZero
172*150812a8SEvalZero /**
173*150812a8SEvalZero * @brief Function for returning the EGU trigger task address.
174*150812a8SEvalZero *
175*150812a8SEvalZero * @param[in] swi SWI instance.
176*150812a8SEvalZero * @param[in] channel Number of the EGU channel.
177*150812a8SEvalZero *
178*150812a8SEvalZero * @returns Address of EGU trigger task.
179*150812a8SEvalZero */
nrfx_swi_task_trigger_address_get(nrfx_swi_t swi,uint8_t channel)180*150812a8SEvalZero __STATIC_INLINE uint32_t nrfx_swi_task_trigger_address_get(nrfx_swi_t swi,
181*150812a8SEvalZero uint8_t channel)
182*150812a8SEvalZero {
183*150812a8SEvalZero NRFX_ASSERT(nrfx_swi_is_allocated(swi));
184*150812a8SEvalZero
185*150812a8SEvalZero NRF_EGU_Type * p_egu = nrfx_swi_egu_instance_get(swi);
186*150812a8SEvalZero #if (EGU_COUNT < SWI_COUNT)
187*150812a8SEvalZero if (p_egu == NULL)
188*150812a8SEvalZero {
189*150812a8SEvalZero return 0;
190*150812a8SEvalZero }
191*150812a8SEvalZero #endif
192*150812a8SEvalZero
193*150812a8SEvalZero return (uint32_t)nrf_egu_task_trigger_address_get(p_egu, channel);
194*150812a8SEvalZero }
195*150812a8SEvalZero
196*150812a8SEvalZero /**
197*150812a8SEvalZero * @brief Function for returning the EGU triggered event address.
198*150812a8SEvalZero *
199*150812a8SEvalZero * @param[in] swi SWI instance.
200*150812a8SEvalZero * @param[in] channel Number of the EGU channel.
201*150812a8SEvalZero *
202*150812a8SEvalZero * @returns Address of EGU triggered event.
203*150812a8SEvalZero */
nrfx_swi_event_triggered_address_get(nrfx_swi_t swi,uint8_t channel)204*150812a8SEvalZero __STATIC_INLINE uint32_t nrfx_swi_event_triggered_address_get(nrfx_swi_t swi,
205*150812a8SEvalZero uint8_t channel)
206*150812a8SEvalZero {
207*150812a8SEvalZero NRFX_ASSERT(nrfx_swi_is_allocated(swi));
208*150812a8SEvalZero
209*150812a8SEvalZero NRF_EGU_Type * p_egu = nrfx_swi_egu_instance_get(swi);
210*150812a8SEvalZero #if (EGU_COUNT < SWI_COUNT)
211*150812a8SEvalZero if (p_egu == NULL)
212*150812a8SEvalZero {
213*150812a8SEvalZero return 0;
214*150812a8SEvalZero }
215*150812a8SEvalZero #endif
216*150812a8SEvalZero
217*150812a8SEvalZero return (uint32_t)nrf_egu_event_triggered_address_get(p_egu, channel);
218*150812a8SEvalZero }
219*150812a8SEvalZero
220*150812a8SEvalZero #endif // NRFX_CHECK(NRFX_EGU_ENABLED) || defined(__NRFX_DOXYGEN__)
221*150812a8SEvalZero
222*150812a8SEvalZero
223*150812a8SEvalZero void nrfx_swi_0_irq_handler(void);
224*150812a8SEvalZero void nrfx_swi_1_irq_handler(void);
225*150812a8SEvalZero void nrfx_swi_2_irq_handler(void);
226*150812a8SEvalZero void nrfx_swi_3_irq_handler(void);
227*150812a8SEvalZero void nrfx_swi_4_irq_handler(void);
228*150812a8SEvalZero void nrfx_swi_5_irq_handler(void);
229*150812a8SEvalZero
230*150812a8SEvalZero /** @} */
231*150812a8SEvalZero
232*150812a8SEvalZero #ifdef __cplusplus
233*150812a8SEvalZero }
234*150812a8SEvalZero #endif
235*150812a8SEvalZero
236*150812a8SEvalZero #endif // NRFX_SWI_H__
237