1# SPDX-License-Identifier: GPL-2.0-only
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/iommu/rockchip,iommu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Rockchip IOMMU
8
9maintainers:
10  - Heiko Stuebner <[email protected]>
11
12description: |+
13  A Rockchip DRM iommu translates io virtual addresses to physical addresses for
14  its master device. Each slave device is bound to a single master device and
15  shares its clocks, power domain and irq.
16
17  For information on assigning IOMMU controller to its peripheral devices,
18  see generic IOMMU bindings.
19
20properties:
21  compatible:
22    oneOf:
23      - enum:
24          - rockchip,iommu
25          - rockchip,rk3568-iommu
26      - items:
27          - enum:
28              - rockchip,rk3576-iommu
29              - rockchip,rk3588-iommu
30          - const: rockchip,rk3568-iommu
31
32  reg:
33    items:
34      - description: configuration registers for MMU instance 0
35      - description: configuration registers for MMU instance 1
36    minItems: 1
37
38  interrupts:
39    items:
40      - description: interruption for MMU instance 0
41      - description: interruption for MMU instance 1
42    minItems: 1
43
44  clocks:
45    items:
46      - description: Core clock
47      - description: Interface clock
48
49  clock-names:
50    items:
51      - const: aclk
52      - const: iface
53
54  "#iommu-cells":
55    const: 0
56
57  power-domains:
58    maxItems: 1
59
60  rockchip,disable-mmu-reset:
61    $ref: /schemas/types.yaml#/definitions/flag
62    description: |
63      Do not use the mmu reset operation.
64      Some mmu instances may produce unexpected results
65      when the reset operation is used.
66
67required:
68  - compatible
69  - reg
70  - interrupts
71  - clocks
72  - clock-names
73  - "#iommu-cells"
74
75additionalProperties: false
76
77examples:
78  - |
79    #include <dt-bindings/clock/rk3399-cru.h>
80    #include <dt-bindings/interrupt-controller/arm-gic.h>
81
82    vopl_mmu: iommu@ff940300 {
83      compatible = "rockchip,iommu";
84      reg = <0xff940300 0x100>;
85      interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
86      clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
87      clock-names = "aclk", "iface";
88      #iommu-cells = <0>;
89    };
90