1 /* 2 * Copyright (C) 2014 BlueKitchen GmbH 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. Neither the name of the copyright holders nor the names of 14 * contributors may be used to endorse or promote products derived 15 * from this software without specific prior written permission. 16 * 4. Any redistribution, use, or modification is done solely for 17 * personal benefit and not for any commercial purpose or for 18 * monetary gain. 19 * 20 * THIS SOFTWARE IS PROVIDED BY BLUEKITCHEN GMBH AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 23 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL MATTHIAS 24 * RINGWALD OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 26 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 27 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 28 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 29 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 30 * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * Please inquire about commercial licensing options at 34 * [email protected] 35 * 36 */ 37 38 /* 39 * hci_h4_transport.c 40 * 41 * HCI Transport API implementation for basic H4 protocol over POSIX 42 * 43 * Created by Matthias Ringwald on 4/29/09. 44 */ 45 46 #include "btstack_config.h" 47 48 #include "btstack_debug.h" 49 #include "hci.h" 50 #include "hci_transport.h" 51 #include "btstack_uart_block.h" 52 53 // #ifdef HAVE_EHCILL 54 // #error "HCI Transport H4 POSIX does not support eHCILL yet. Please remove HAVE_EHCILL from your btstack-config.h" 55 // #endif 56 57 #ifdef HAVE_EHCILL 58 59 // eHCILL commands 60 #define EHCILL_GO_TO_SLEEP_IND 0x030 61 #define EHCILL_GO_TO_SLEEP_ACK 0x031 62 #define EHCILL_WAKE_UP_IND 0x032 63 #define EHCILL_WAKE_UP_ACK 0x033 64 65 static void hci_transport_h4_ehcill_handle(uint8_t action); 66 static void hci_transport_h4_ehcill_reset_statemachine(void); 67 static void hci_transport_h4_ehcill_send_ehcill_command(void); 68 static void hci_transport_h4_ehcill_sleep_ack_timer_setup(void); 69 static int hci_transport_h4_ehcill_outgoing_packet_ready(void); 70 static void hci_transport_h4_ehcill_reactivate_rx(void); 71 static void hci_transport_h4_echill_send_wakeup_ind(void); 72 73 typedef enum { 74 EHCILL_STATE_SLEEP, 75 EHCILL_STATE_W4_ACK, 76 EHCILL_STATE_AWAKE 77 } EHCILL_STATE; 78 79 // eHCILL state machine 80 static EHCILL_STATE ehcill_state; 81 static uint8_t ehcill_command_to_send; 82 static uint8_t * ehcill_defer_rx_buffer; 83 static uint16_t ehcill_defer_rx_size = 0; 84 85 // work around for eHCILL problem 86 static btstack_timer_source_t ehcill_sleep_ack_timer; 87 88 #endif 89 90 // assert pre-buffer for packet type is available 91 #if !defined(HCI_OUTGOING_PRE_BUFFER_SIZE) || (HCI_OUTGOING_PRE_BUFFER_SIZE == 0) 92 #error HCI_OUTGOING_PRE_BUFFER_SIZE not defined. Please update hci.h 93 #endif 94 95 static void dummy_handler(uint8_t packet_type, uint8_t *packet, uint16_t size); 96 97 typedef enum { 98 H4_W4_PACKET_TYPE, 99 H4_W4_EVENT_HEADER, 100 H4_W4_ACL_HEADER, 101 H4_W4_SCO_HEADER, 102 H4_W4_PAYLOAD, 103 } H4_STATE; 104 105 typedef enum { 106 TX_IDLE = 1, 107 TX_W4_PACKET_SENT, 108 #ifdef HAVE_EHCILL 109 TX_W4_WAKEUP, 110 TX_W2_EHCILL_SEND, 111 TX_W4_EHCILL_SENT, 112 #endif 113 } TX_STATE; 114 115 // UART Driver + Config 116 static const btstack_uart_block_t * btstack_uart; 117 static btstack_uart_config_t uart_config; 118 119 // write state 120 static TX_STATE tx_state; // updated from block_sent callback 121 static uint8_t * tx_data; 122 static uint16_t tx_len; // 0 == no outgoing packet 123 static uint8_t packet_sent_event[] = { HCI_EVENT_TRANSPORT_PACKET_SENT, 0}; 124 125 static void (*packet_handler)(uint8_t packet_type, uint8_t *packet, uint16_t size) = dummy_handler; 126 127 // packet reader state machine 128 static H4_STATE h4_state; 129 static int bytes_to_read; 130 static int read_pos; 131 132 // incoming packet buffer 133 static uint8_t hci_packet_with_pre_buffer[HCI_INCOMING_PRE_BUFFER_SIZE + 1 + HCI_PACKET_BUFFER_SIZE]; // packet type + max(acl header + acl payload, event header + event data) 134 static uint8_t * hci_packet = &hci_packet_with_pre_buffer[HCI_INCOMING_PRE_BUFFER_SIZE]; 135 136 static int hci_transport_h4_set_baudrate(uint32_t baudrate){ 137 log_info("hci_transport_h4_set_baudrate %u", baudrate); 138 return btstack_uart->set_baudrate(baudrate); 139 } 140 141 static void hci_transport_h4_reset_statemachine(void){ 142 h4_state = H4_W4_PACKET_TYPE; 143 read_pos = 0; 144 bytes_to_read = 1; 145 } 146 147 static void hci_transport_h4_trigger_next_read(void){ 148 // trigger next read 149 btstack_uart->receive_block(&hci_packet[read_pos], bytes_to_read); 150 } 151 152 static void hci_transport_h4_block_read(void){ 153 154 read_pos += bytes_to_read; 155 156 switch (h4_state) { 157 case H4_W4_PACKET_TYPE: 158 switch (hci_packet[0]){ 159 case HCI_EVENT_PACKET: 160 bytes_to_read = HCI_EVENT_HEADER_SIZE; 161 h4_state = H4_W4_EVENT_HEADER; 162 break; 163 case HCI_ACL_DATA_PACKET: 164 bytes_to_read = HCI_ACL_HEADER_SIZE; 165 h4_state = H4_W4_ACL_HEADER; 166 break; 167 case HCI_SCO_DATA_PACKET: 168 bytes_to_read = HCI_SCO_HEADER_SIZE; 169 h4_state = H4_W4_SCO_HEADER; 170 break; 171 #ifdef HAVE_EHCILL 172 case EHCILL_GO_TO_SLEEP_IND: 173 case EHCILL_GO_TO_SLEEP_ACK: 174 case EHCILL_WAKE_UP_IND: 175 case EHCILL_WAKE_UP_ACK: 176 bytes_to_read = 1; 177 hci_transport_h4_ehcill_handle(hci_packet[0]); 178 break; 179 #endif 180 default: 181 log_error("h4_process: invalid packet type 0x%02x", hci_packet[0]); 182 hci_transport_h4_reset_statemachine(); 183 break; 184 } 185 break; 186 187 case H4_W4_EVENT_HEADER: 188 bytes_to_read = hci_packet[2]; 189 h4_state = H4_W4_PAYLOAD; 190 break; 191 192 case H4_W4_ACL_HEADER: 193 bytes_to_read = little_endian_read_16( hci_packet, 3); 194 // check ACL length 195 if (HCI_ACL_HEADER_SIZE + bytes_to_read > HCI_PACKET_BUFFER_SIZE){ 196 log_error("h4_process: invalid ACL payload len %u - only space for %u", bytes_to_read, HCI_PACKET_BUFFER_SIZE - HCI_ACL_HEADER_SIZE); 197 hci_transport_h4_reset_statemachine(); 198 break; 199 } 200 h4_state = H4_W4_PAYLOAD; 201 break; 202 203 case H4_W4_SCO_HEADER: 204 bytes_to_read = hci_packet[3]; 205 h4_state = H4_W4_PAYLOAD; 206 break; 207 208 case H4_W4_PAYLOAD: 209 packet_handler(hci_packet[0], &hci_packet[1], read_pos-1); 210 hci_transport_h4_reset_statemachine(); 211 break; 212 default: 213 break; 214 } 215 hci_transport_h4_trigger_next_read(); 216 } 217 218 static void hci_transport_h4_block_sent(void){ 219 tx_state = TX_IDLE; 220 switch (tx_state){ 221 case TX_W4_PACKET_SENT: 222 // packet fully sent, reset state 223 tx_len = 0; 224 225 #ifdef HAVE_EHCILL 226 // now, send pending ehcill command if neccessary 227 switch (ehcill_command_to_send){ 228 case EHCILL_GO_TO_SLEEP_ACK: 229 hci_transport_h4_ehcill_sleep_ack_timer_setup(); 230 break; 231 case EHCILL_WAKE_UP_IND: 232 hci_transport_h4_ehcill_send_ehcill_command(); 233 break; 234 default: 235 break; 236 } 237 #endif 238 // notify upper stack that it can send again 239 packet_handler(HCI_EVENT_PACKET, &packet_sent_event[0], sizeof(packet_sent_event)); 240 break; 241 242 #ifdef HAVE_EHCILL 243 case TX_W4_EHCILL_SENT: { 244 int command = ehcill_command_to_send; 245 ehcill_command_to_send = 0; 246 if (command == EHCILL_GO_TO_SLEEP_ACK) { 247 // UART not needed after EHCILL_GO_TO_SLEEP_ACK was sent 248 if (btstack_uart->get_supported_sleep_modes() & BTSTACK_UART_SLEEP_MASK_RTS_HIGH_WAKE_ON_CTS_PULSE){ 249 btstack_uart->set_sleep(BTSTACK_UART_SLEEP_RTS_HIGH_WAKE_ON_CTS_PULSE); 250 } else if (btstack_uart->get_supported_sleep_modes() & BTSTACK_UART_SLEEP_MASK_RTS_LOW_WAKE_ON_RX_EDGE){ 251 btstack_uart->set_sleep(BTSTACK_UART_SLEEP_RTS_LOW_WAKE_ON_RX_EDGE); 252 } 253 } 254 if (hci_transport_h4_ehcill_outgoing_packet_ready()){ 255 // already packet ready? then start wakeup 256 btstack_uart->set_sleep(BTSTACK_UART_SLEEP_OFF); 257 hci_transport_h4_ehcill_reactivate_rx(); 258 hci_transport_h4_echill_send_wakeup_ind(); 259 } 260 // TODO: trigger run loop 261 // btstack_run_loop_embedded_trigger(); 262 break; 263 } 264 #endif 265 266 default: 267 break; 268 } 269 } 270 271 static int hci_transport_h4_can_send_now(uint8_t packet_type){ 272 return tx_state == TX_IDLE; 273 } 274 275 static int hci_transport_h4_send_packet(uint8_t packet_type, uint8_t * packet, int size){ 276 // store packet type before actual data and increase size 277 size++; 278 packet--; 279 *packet = packet_type; 280 281 tx_state = TX_W4_PACKET_SENT; 282 283 btstack_uart->send_block(packet, size); 284 return 0; 285 } 286 287 static void hci_transport_h4_init(const void * transport_config){ 288 // check for hci_transport_config_uart_t 289 if (!transport_config) { 290 log_error("hci_transport_h4: no config!"); 291 return; 292 } 293 if (((hci_transport_config_t*)transport_config)->type != HCI_TRANSPORT_CONFIG_UART) { 294 log_error("hci_transport_h4: config not of type != HCI_TRANSPORT_CONFIG_UART!"); 295 return; 296 } 297 298 // extract UART config from transport config 299 hci_transport_config_uart_t * hci_transport_config_uart = (hci_transport_config_uart_t*) transport_config; 300 uart_config.baudrate = hci_transport_config_uart->baudrate_init; 301 uart_config.flowcontrol = hci_transport_config_uart->flowcontrol; 302 uart_config.device_name = hci_transport_config_uart->device_name; 303 304 // setup UART driver 305 btstack_uart->init(&uart_config); 306 btstack_uart->set_block_received(&hci_transport_h4_block_read); 307 btstack_uart->set_block_sent(&hci_transport_h4_block_sent); 308 } 309 310 static int hci_transport_h4_open(void){ 311 int res = btstack_uart->open(); 312 if (res){ 313 return res; 314 } 315 hci_transport_h4_reset_statemachine(); 316 hci_transport_h4_trigger_next_read(); 317 318 tx_state = TX_IDLE; 319 320 #ifdef HAVE_EHCILL 321 hci_transport_h4_ehcill_reset_statemachine(); 322 #endif 323 return 0; 324 } 325 326 static int hci_transport_h4_close(void){ 327 return btstack_uart->close(); 328 } 329 330 static void hci_transport_h4_register_packet_handler(void (*handler)(uint8_t packet_type, uint8_t *packet, uint16_t size)){ 331 packet_handler = handler; 332 } 333 334 static void dummy_handler(uint8_t packet_type, uint8_t *packet, uint16_t size){ 335 } 336 337 // --- main part of eHCILL implementation --- 338 339 #ifdef HAVE_EHCILL 340 341 static void hci_transport_h4_ehcill_reactivate_rx(void){ 342 if (!ehcill_defer_rx_size){ 343 log_error("EHCILL: NO RX REQUEST PENDING"); 344 return; 345 } 346 log_info ("EHCILL: Re-activate rx"); 347 // receive request, clears RTS 348 int rx_size = ehcill_defer_rx_size; 349 ehcill_defer_rx_size = 0; 350 btstack_uart->receive_block(ehcill_defer_rx_buffer, rx_size); 351 } 352 353 static void hci_transport_h4_echill_send_wakeup_ind(void){ 354 // update state 355 tx_state = TX_W4_WAKEUP; 356 ehcill_state = EHCILL_STATE_W4_ACK; 357 ehcill_command_to_send = EHCILL_WAKE_UP_IND; 358 btstack_uart->send_block(&ehcill_command_to_send, 1); 359 } 360 361 static int hci_transport_h4_ehcill_outgoing_packet_ready(void){ 362 return tx_len != 0; 363 } 364 365 // static int ehcill_sleep_mode_active(void){ 366 // return ehcill_state == EHCILL_STATE_SLEEP; 367 // } 368 369 static void hci_transport_h4_ehcill_reset_statemachine(void){ 370 ehcill_state = EHCILL_STATE_AWAKE; 371 } 372 373 static void hci_transport_h4_ehcill_send_ehcill_command(void){ 374 tx_state = TX_W4_EHCILL_SENT; 375 btstack_uart->send_block(&ehcill_command_to_send, 1); 376 } 377 378 static void hci_transport_h4_ehcill_sleep_ack_timer_handler(btstack_timer_source_t * timer){ 379 hci_transport_h4_ehcill_send_ehcill_command(); 380 } 381 382 static void hci_transport_h4_ehcill_sleep_ack_timer_setup(void){ 383 // setup timer 384 ehcill_sleep_ack_timer.process = &hci_transport_h4_ehcill_sleep_ack_timer_handler; 385 btstack_run_loop_set_timer(&ehcill_sleep_ack_timer, 50); 386 btstack_run_loop_add_timer(&ehcill_sleep_ack_timer); 387 // TODO: trigger run loop 388 // btstack_run_loop_embedded_trigger(); 389 } 390 391 static void hci_transport_h4_ehcill_schedule_ecill_command(uint8_t command){ 392 ehcill_command_to_send = command; 393 switch (tx_state){ 394 case TX_IDLE: 395 if (ehcill_command_to_send == EHCILL_WAKE_UP_ACK){ 396 // send right away 397 hci_transport_h4_ehcill_send_ehcill_command(); 398 } else { 399 // change state so BTstack cannot send and setup timer 400 tx_state = TX_W2_EHCILL_SEND; 401 hci_transport_h4_ehcill_sleep_ack_timer_setup(); 402 } 403 break; 404 default: 405 break; 406 } 407 } 408 409 static void hci_transport_h4_ehcill_handle(uint8_t action){ 410 // log_info("hci_transport_h4_ehcill_handle: %x, state %u, defer_rx %u", action, ehcill_state, ehcill_defer_rx_size); 411 switch(ehcill_state){ 412 case EHCILL_STATE_AWAKE: 413 switch(action){ 414 case EHCILL_GO_TO_SLEEP_IND: 415 // 1. set RTS high - already done by BT RX ISR 416 // 2. enable CTS IRQ - CTS always enabled 417 ehcill_state = EHCILL_STATE_SLEEP; 418 log_info("EHCILL: GO_TO_SLEEP_IND RX"); 419 hci_transport_h4_ehcill_schedule_ecill_command(EHCILL_GO_TO_SLEEP_ACK); 420 break; 421 default: 422 break; 423 } 424 break; 425 426 case EHCILL_STATE_SLEEP: 427 switch(action){ 428 case EHCILL_WAKE_UP_IND: 429 ehcill_state = EHCILL_STATE_AWAKE; 430 log_info("EHCILL: WAKE_UP_IND RX"); 431 hci_transport_h4_ehcill_schedule_ecill_command(EHCILL_WAKE_UP_ACK); 432 break; 433 434 default: 435 break; 436 } 437 break; 438 439 case EHCILL_STATE_W4_ACK: 440 switch(action){ 441 case EHCILL_WAKE_UP_IND: 442 case EHCILL_WAKE_UP_ACK: 443 log_info("EHCILL: WAKE_UP_IND or ACK"); 444 tx_state = TX_W4_PACKET_SENT; 445 ehcill_state = EHCILL_STATE_AWAKE; 446 btstack_uart->send_block(tx_data, tx_len); 447 break; 448 default: 449 break; 450 } 451 break; 452 } 453 } 454 #endif 455 // --- end of eHCILL implementation --------- 456 457 static const hci_transport_t hci_transport_h4 = { 458 /* const char * name; */ "H4", 459 /* void (*init) (const void *transport_config); */ &hci_transport_h4_init, 460 /* int (*open)(void); */ &hci_transport_h4_open, 461 /* int (*close)(void); */ &hci_transport_h4_close, 462 /* void (*register_packet_handler)(void (*handler)(...); */ &hci_transport_h4_register_packet_handler, 463 /* int (*can_send_packet_now)(uint8_t packet_type); */ &hci_transport_h4_can_send_now, 464 /* int (*send_packet)(...); */ &hci_transport_h4_send_packet, 465 /* int (*set_baudrate)(uint32_t baudrate); */ &hci_transport_h4_set_baudrate, 466 /* void (*reset_link)(void); */ NULL, 467 }; 468 469 // configure and return h4 singleton 470 const hci_transport_t * hci_transport_h4_instance(const btstack_uart_block_t * uart_driver) { 471 btstack_uart = uart_driver; 472 return &hci_transport_h4; 473 } 474