1 /* 2 * Copyright (C) 2014 BlueKitchen GmbH 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. Neither the name of the copyright holders nor the names of 14 * contributors may be used to endorse or promote products derived 15 * from this software without specific prior written permission. 16 * 4. Any redistribution, use, or modification is done solely for 17 * personal benefit and not for any commercial purpose or for 18 * monetary gain. 19 * 20 * THIS SOFTWARE IS PROVIDED BY BLUEKITCHEN GMBH AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 23 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL MATTHIAS 24 * RINGWALD OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 26 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 27 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 28 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 29 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 30 * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * Please inquire about commercial licensing options at 34 * [email protected] 35 * 36 */ 37 38 #define __BTSTACK_FILE__ "hci_transport_em9304_spi.c" 39 40 #include "btstack_config.h" 41 #include "btstack_em9304_spi.h" 42 43 // EM9304 SPI Driver 44 static const btstack_em9304_spi_t * btstack_em9304_spi; 45 46 ///////////////////////// 47 // em9304 engine 48 #include "btstack_ring_buffer.h" 49 #include "btstack_debug.h" 50 #include "btstack_util.h" 51 #include "hci.h" 52 #include "hci_transport.h" 53 54 static void em9304_spi_engine_run(void); 55 56 #define STS_SLAVE_READY 0xc0 57 58 #define EM9304_SPI_HEADER_TX 0x42 59 #define EM9304_SPI_HEADER_RX 0x81 60 61 #define SPI_EM9304_RX_BUFFER_SIZE 64 62 #define SPI_EM9304_TX_BUFFER_SIZE 64 63 #define SPI_EM9304_RING_BUFFER_SIZE 128 64 65 // state 66 static volatile enum { 67 SPI_EM9304_READY_FOR_TX, 68 SPI_EM9304_READY_FOR_TX_AND_RX, 69 SPI_EM9304_RX_W4_READ_COMMAND_SENT, 70 SPI_EM9304_RX_READ_COMMAND_SENT, 71 SPI_EM9304_RX_W4_STS2_RECEIVED, 72 SPI_EM9304_RX_STS2_RECEIVED, 73 SPI_EM9304_RX_W4_DATA_RECEIVED, 74 SPI_EM9304_RX_DATA_RECEIVED, 75 SPI_EM9304_TX_W4_RDY, 76 SPI_EM9304_TX_W4_WRITE_COMMAND_SENT, 77 SPI_EM9304_TX_WRITE_COMMAND_SENT, 78 SPI_EM9304_TX_W4_STS2_RECEIVED, 79 SPI_EM9304_TX_STS2_RECEIVED, 80 SPI_EM9304_TX_W4_DATA_SENT, 81 SPI_EM9304_TX_DATA_SENT, 82 SPI_EM9304_DONE, 83 } em9304_spi_engine_state; 84 85 static uint16_t em9304_spi_engine_rx_request_len; 86 static uint16_t em9304_spi_engine_tx_request_len; 87 88 static btstack_ring_buffer_t em9304_spi_engine_rx_ring_buffer; 89 static uint8_t em9304_spi_engine_rx_ring_buffer_storage[SPI_EM9304_RING_BUFFER_SIZE]; 90 91 static const uint8_t * em9304_spi_engine_tx_data; 92 static uint16_t em9304_spi_engine_tx_size; 93 94 // handlers 95 static void (*em9304_spi_engine_rx_available_handler)(void); 96 static void (*em9304_spi_engine_tx_done_handler)(void); 97 98 // TODO: get rid of alignment requirement 99 union { 100 uint32_t words[1]; 101 uint8_t bytes[1]; 102 } sCommand; 103 104 union { 105 uint32_t words[1]; 106 uint8_t bytes[1]; 107 } sStas; 108 109 union { 110 uint32_t words[SPI_EM9304_RX_BUFFER_SIZE/4]; 111 uint8_t bytes[SPI_EM9304_RX_BUFFER_SIZE]; 112 } em9304_spi_engine_spi_rx_buffer; 113 114 static void em9304_spi_engine_ready_callback(void){ 115 // TODO: collect states 116 em9304_spi_engine_run(); 117 } 118 119 static void em9304_spi_engine_transfer_done(void){ 120 switch (em9304_spi_engine_state){ 121 case SPI_EM9304_RX_W4_READ_COMMAND_SENT: 122 em9304_spi_engine_state = SPI_EM9304_RX_READ_COMMAND_SENT; 123 break; 124 case SPI_EM9304_RX_W4_STS2_RECEIVED: 125 em9304_spi_engine_state = SPI_EM9304_RX_STS2_RECEIVED; 126 break; 127 case SPI_EM9304_RX_W4_DATA_RECEIVED: 128 em9304_spi_engine_state = SPI_EM9304_RX_DATA_RECEIVED; 129 break; 130 case SPI_EM9304_TX_W4_WRITE_COMMAND_SENT: 131 em9304_spi_engine_state = SPI_EM9304_TX_WRITE_COMMAND_SENT; 132 break; 133 case SPI_EM9304_TX_W4_STS2_RECEIVED: 134 em9304_spi_engine_state = SPI_EM9304_TX_STS2_RECEIVED; 135 break; 136 case SPI_EM9304_TX_W4_DATA_SENT: 137 em9304_spi_engine_state = SPI_EM9304_TX_DATA_SENT; 138 break; 139 default: 140 return; 141 } 142 em9304_spi_engine_run(); 143 } 144 145 static void em9304_spi_engine_start_tx_transaction(void){ 146 // state = wait for RDY 147 em9304_spi_engine_state = SPI_EM9304_TX_W4_RDY; 148 149 // chip select 150 btstack_em9304_spi->set_chip_select(1); 151 152 // enable IRQ 153 btstack_em9304_spi->set_ready_callback(&em9304_spi_engine_ready_callback); 154 } 155 156 static inline int em9304_engine_space_in_rx_buffer(void){ 157 return btstack_ring_buffer_bytes_free(&em9304_spi_engine_rx_ring_buffer) >= SPI_EM9304_RX_BUFFER_SIZE; 158 } 159 160 static void em9304_engine_receive_buffer_ready(void){ 161 // no data ready for receive or transmit, but space in rx ringbuffer -> enable READY IRQ 162 em9304_spi_engine_state = SPI_EM9304_READY_FOR_TX_AND_RX; 163 btstack_em9304_spi->set_ready_callback(&em9304_spi_engine_ready_callback); 164 } 165 166 static void em9304_engine_start_next_transaction(void){ 167 168 if (em9304_spi_engine_state != SPI_EM9304_DONE) return; 169 170 if (btstack_em9304_spi->get_ready()){ 171 // RDY -> data available 172 if (em9304_engine_space_in_rx_buffer()) { 173 // disable interrupt again 174 btstack_em9304_spi->set_ready_callback(NULL); 175 176 // enable chip select 177 btstack_em9304_spi->set_chip_select(1); 178 179 // send read command 180 em9304_spi_engine_state = SPI_EM9304_RX_W4_READ_COMMAND_SENT; 181 sCommand.bytes[0] = EM9304_SPI_HEADER_RX; 182 btstack_em9304_spi->transmit(sCommand.bytes, 1); 183 } 184 } else if (em9304_spi_engine_tx_size){ 185 em9304_spi_engine_start_tx_transaction(); 186 } else if (em9304_engine_space_in_rx_buffer()){ 187 em9304_engine_receive_buffer_ready(); 188 } 189 } 190 191 static void em9304_engine_action_done(void){ 192 // chip deselect & done 193 btstack_em9304_spi->set_chip_select(0); 194 em9304_spi_engine_state = SPI_EM9304_DONE; 195 } 196 197 static void em9304_spi_engine_run(void){ 198 uint16_t max_bytes_to_send; 199 switch (em9304_spi_engine_state){ 200 201 case SPI_EM9304_RX_READ_COMMAND_SENT: 202 em9304_spi_engine_state = SPI_EM9304_RX_W4_STS2_RECEIVED; 203 btstack_em9304_spi->receive(sStas.bytes, 1); 204 break; 205 206 case SPI_EM9304_RX_STS2_RECEIVED: 207 // check slave status 208 log_debug("RX: STS2 0x%02X", sStas.bytes[0]); 209 210 // read data 211 em9304_spi_engine_state = SPI_EM9304_RX_W4_DATA_RECEIVED; 212 em9304_spi_engine_rx_request_len = sStas.bytes[0]; 213 btstack_em9304_spi->receive(em9304_spi_engine_spi_rx_buffer.bytes, em9304_spi_engine_rx_request_len); 214 break; 215 216 case SPI_EM9304_RX_DATA_RECEIVED: 217 // done 218 em9304_engine_action_done(); 219 220 // move data into ring buffer 221 btstack_ring_buffer_write(&em9304_spi_engine_rx_ring_buffer, em9304_spi_engine_spi_rx_buffer.bytes, em9304_spi_engine_rx_request_len); 222 em9304_spi_engine_rx_request_len = 0; 223 224 // notify about new data available -- assume empty 225 (*em9304_spi_engine_rx_available_handler)(); 226 227 // next 228 em9304_engine_start_next_transaction(); 229 break; 230 231 case SPI_EM9304_TX_W4_RDY: 232 // check if ready 233 if (!btstack_em9304_spi->get_ready()) break; 234 235 // disable interrupt again 236 btstack_em9304_spi->set_ready_callback(NULL); 237 238 // send write command 239 em9304_spi_engine_state = SPI_EM9304_TX_W4_WRITE_COMMAND_SENT; 240 sCommand.bytes[0] = EM9304_SPI_HEADER_TX; 241 btstack_em9304_spi->transmit(sCommand.bytes, 1); 242 break; 243 244 case SPI_EM9304_TX_WRITE_COMMAND_SENT: 245 em9304_spi_engine_state = SPI_EM9304_TX_W4_STS2_RECEIVED; 246 btstack_em9304_spi->receive(sStas.bytes, 1); 247 break; 248 249 case SPI_EM9304_TX_STS2_RECEIVED: 250 // check slave status and em9304 rx buffer space 251 log_debug("TX: STS2 0x%02X", sStas.bytes[0]); 252 max_bytes_to_send = sStas.bytes[0]; 253 if (max_bytes_to_send == 0){ 254 // done 255 em9304_engine_action_done(); 256 // next 257 em9304_engine_start_next_transaction(); 258 break; 259 } 260 261 // number bytes to send 262 em9304_spi_engine_tx_request_len = btstack_min(em9304_spi_engine_tx_size, max_bytes_to_send); 263 264 // send command 265 em9304_spi_engine_state = SPI_EM9304_TX_W4_DATA_SENT; 266 btstack_em9304_spi->transmit( (uint8_t*) em9304_spi_engine_tx_data, em9304_spi_engine_tx_request_len); 267 break; 268 269 case SPI_EM9304_TX_DATA_SENT: 270 // done 271 em9304_engine_action_done(); 272 273 // chunk sent 274 em9304_spi_engine_tx_size -= em9304_spi_engine_tx_request_len; 275 em9304_spi_engine_tx_data += em9304_spi_engine_tx_request_len; 276 em9304_spi_engine_tx_request_len = 0; 277 278 // notify higher layer when complete 279 if (em9304_spi_engine_tx_size == 0){ 280 (*em9304_spi_engine_tx_done_handler)(); 281 } 282 283 // next 284 em9304_engine_start_next_transaction(); 285 break; 286 287 default: 288 break; 289 } 290 } 291 292 static void em9304_spi_engine_init(void){ 293 btstack_em9304_spi->open(); 294 btstack_em9304_spi->set_transfer_done_callback(&em9304_spi_engine_transfer_done); 295 btstack_ring_buffer_init(&em9304_spi_engine_rx_ring_buffer, &em9304_spi_engine_rx_ring_buffer_storage[0], SPI_EM9304_RING_BUFFER_SIZE); 296 em9304_spi_engine_state = SPI_EM9304_DONE; 297 em9304_engine_start_next_transaction(); 298 } 299 300 static void em9304_spi_engine_close(void){ 301 btstack_em9304_spi->close(); 302 } 303 304 static void em9304_spi_engine_set_data_available( void (*the_block_handler)(void)){ 305 em9304_spi_engine_rx_available_handler = the_block_handler; 306 } 307 308 static void em9304_spi_engine_set_block_sent( void (*the_block_handler)(void)){ 309 em9304_spi_engine_tx_done_handler = the_block_handler; 310 } 311 312 static void em9304_spi_engine_send_block(const uint8_t *buffer, uint16_t length){ 313 em9304_spi_engine_tx_data = buffer; 314 em9304_spi_engine_tx_size = length; 315 em9304_engine_start_next_transaction(); 316 } 317 318 static uint16_t em9304_engine_num_bytes_available(void){ 319 return btstack_ring_buffer_bytes_available(&em9304_spi_engine_rx_ring_buffer); 320 } 321 322 static void em9304_engine_get_bytes(uint8_t * buffer, uint16_t num_bytes){ 323 uint32_t bytes_read; 324 btstack_ring_buffer_read(&em9304_spi_engine_rx_ring_buffer, buffer, num_bytes, &bytes_read); 325 } 326 327 ////////////////////////////////////////////////////////////////////////////// 328 329 // assert pre-buffer for packet type is available 330 #if !defined(HCI_OUTGOING_PRE_BUFFER_SIZE) || (HCI_OUTGOING_PRE_BUFFER_SIZE == 0) 331 #error HCI_OUTGOING_PRE_BUFFER_SIZE not defined. Please update hci.h 332 #endif 333 334 static void dummy_handler(uint8_t packet_type, uint8_t *packet, uint16_t size); 335 336 typedef enum { 337 H4_W4_PACKET_TYPE, 338 H4_W4_EVENT_HEADER, 339 H4_W4_ACL_HEADER, 340 H4_W4_PAYLOAD, 341 } H4_STATE; 342 343 typedef enum { 344 TX_IDLE = 1, 345 TX_W4_PACKET_SENT, 346 } TX_STATE; 347 348 // write state 349 static TX_STATE tx_state; 350 351 static uint8_t packet_sent_event[] = { HCI_EVENT_TRANSPORT_PACKET_SENT, 0}; 352 353 static void (*packet_handler)(uint8_t packet_type, uint8_t *packet, uint16_t size) = dummy_handler; 354 355 // packet reader state machine 356 static H4_STATE hci_transport_em9304_h4_state; 357 static uint16_t hci_transport_em9304_spi_bytes_to_read; 358 static uint16_t hci_transport_em9304_spi_read_pos; 359 360 // incoming packet buffer 361 static uint8_t hci_packet_with_pre_buffer[HCI_INCOMING_PRE_BUFFER_SIZE + 1 + HCI_PACKET_BUFFER_SIZE]; // packet type + max(acl header + acl payload, event header + event data) 362 static uint8_t * hci_packet = &hci_packet_with_pre_buffer[HCI_INCOMING_PRE_BUFFER_SIZE]; 363 364 static void hci_transport_em9304_spi_block_read(void); 365 366 static void hci_transport_em9304_spi_reset_statemachine(void){ 367 hci_transport_em9304_h4_state = H4_W4_PACKET_TYPE; 368 hci_transport_em9304_spi_read_pos = 0; 369 hci_transport_em9304_spi_bytes_to_read = 1; 370 } 371 372 static void hci_transport_em9304_spi_process_data(void){ 373 while (1){ 374 375 uint16_t bytes_available = em9304_engine_num_bytes_available(); 376 log_debug("transfer_rx_data: ring buffer has %u -> hci wants %u", bytes_available, hci_transport_em9304_spi_bytes_to_read); 377 378 if (!bytes_available) break; 379 if (!hci_transport_em9304_spi_bytes_to_read) break; 380 381 uint16_t bytes_to_copy = btstack_min(bytes_available, hci_transport_em9304_spi_bytes_to_read); 382 em9304_engine_get_bytes(&hci_packet[hci_transport_em9304_spi_read_pos], bytes_to_copy); 383 384 hci_transport_em9304_spi_read_pos += bytes_to_copy; 385 hci_transport_em9304_spi_bytes_to_read -= bytes_to_copy; 386 387 if (hci_transport_em9304_spi_bytes_to_read == 0){ 388 hci_transport_em9304_spi_block_read(); 389 } 390 } 391 } 392 393 static void hci_transport_em9304_spi_block_read(void){ 394 switch (hci_transport_em9304_h4_state) { 395 case H4_W4_PACKET_TYPE: 396 switch (hci_packet[0]){ 397 case HCI_EVENT_PACKET: 398 hci_transport_em9304_spi_bytes_to_read = HCI_EVENT_HEADER_SIZE; 399 hci_transport_em9304_h4_state = H4_W4_EVENT_HEADER; 400 break; 401 case HCI_ACL_DATA_PACKET: 402 hci_transport_em9304_spi_bytes_to_read = HCI_ACL_HEADER_SIZE; 403 hci_transport_em9304_h4_state = H4_W4_ACL_HEADER; 404 break; 405 default: 406 log_error("invalid packet type 0x%02x", hci_packet[0]); 407 hci_transport_em9304_spi_reset_statemachine(); 408 break; 409 } 410 break; 411 412 case H4_W4_EVENT_HEADER: 413 hci_transport_em9304_spi_bytes_to_read = hci_packet[2]; 414 hci_transport_em9304_h4_state = H4_W4_PAYLOAD; 415 break; 416 417 case H4_W4_ACL_HEADER: 418 hci_transport_em9304_spi_bytes_to_read = little_endian_read_16( hci_packet, 3); 419 // check ACL length 420 if (HCI_ACL_HEADER_SIZE + hci_transport_em9304_spi_bytes_to_read > HCI_PACKET_BUFFER_SIZE){ 421 log_error("invalid ACL payload len %d - only space for %u", hci_transport_em9304_spi_bytes_to_read, HCI_PACKET_BUFFER_SIZE - HCI_ACL_HEADER_SIZE); 422 hci_transport_em9304_spi_reset_statemachine(); 423 break; 424 } 425 hci_transport_em9304_h4_state = H4_W4_PAYLOAD; 426 break; 427 428 case H4_W4_PAYLOAD: 429 packet_handler(hci_packet[0], &hci_packet[1], hci_transport_em9304_spi_read_pos-1); 430 hci_transport_em9304_spi_reset_statemachine(); 431 break; 432 default: 433 break; 434 } 435 } 436 437 static void hci_transport_em9304_spi_block_sent(void){ 438 switch (tx_state){ 439 case TX_W4_PACKET_SENT: 440 // packet fully sent, reset state 441 tx_state = TX_IDLE; 442 // notify upper stack that it can send again 443 packet_handler(HCI_EVENT_PACKET, &packet_sent_event[0], sizeof(packet_sent_event)); 444 break; 445 default: 446 break; 447 } 448 } 449 450 static int hci_transport_em9304_spi_can_send_now(uint8_t packet_type){ 451 return tx_state == TX_IDLE; 452 } 453 454 static int hci_transport_em9304_spi_send_packet(uint8_t packet_type, uint8_t * packet, int size){ 455 456 // store packet type before actual data and increase size 457 size++; 458 packet--; 459 *packet = packet_type; 460 461 // start sending 462 tx_state = TX_W4_PACKET_SENT; 463 em9304_spi_engine_send_block(packet, size); 464 return 0; 465 } 466 467 static void hci_transport_em9304_spi_init(const void * transport_config){ 468 } 469 470 static int hci_transport_em9304_spi_open(void){ 471 472 // setup UART driver 473 em9304_spi_engine_init(); 474 em9304_spi_engine_set_data_available(&hci_transport_em9304_spi_process_data); 475 em9304_spi_engine_set_block_sent(&hci_transport_em9304_spi_block_sent); 476 // setup H4 RX 477 hci_transport_em9304_spi_reset_statemachine(); 478 // setup H4 TX 479 tx_state = TX_IDLE; 480 return 0; 481 } 482 483 static int hci_transport_em9304_spi_close(void){ 484 em9304_spi_engine_close(); 485 return 0; 486 } 487 488 static void hci_transport_em9304_spi_register_packet_handler(void (*handler)(uint8_t packet_type, uint8_t *packet, uint16_t size)){ 489 packet_handler = handler; 490 } 491 492 static void dummy_handler(uint8_t packet_type, uint8_t *packet, uint16_t size){ 493 } 494 495 // --- end of eHCILL implementation --------- 496 497 static const hci_transport_t hci_transport_em9304_spi = { 498 /* const char * name; */ "H4", 499 /* void (*init) (const void *transport_config); */ &hci_transport_em9304_spi_init, 500 /* int (*open)(void); */ &hci_transport_em9304_spi_open, 501 /* int (*close)(void); */ &hci_transport_em9304_spi_close, 502 /* void (*register_packet_handler)(void (*handler)(...); */ &hci_transport_em9304_spi_register_packet_handler, 503 /* int (*can_send_packet_now)(uint8_t packet_type); */ &hci_transport_em9304_spi_can_send_now, 504 /* int (*send_packet)(...); */ &hci_transport_em9304_spi_send_packet, 505 /* int (*set_baudrate)(uint32_t baudrate); */ NULL, 506 /* void (*reset_link)(void); */ NULL, 507 /* void (*set_sco_config)(uint16_t voice_setting, int num_connections); */ NULL, 508 }; 509 510 // configure and return h4 singleton 511 const hci_transport_t * hci_transport_em9304_spi_instance(const btstack_em9304_spi_t * em9304_spi_driver) { 512 btstack_em9304_spi = em9304_spi_driver; 513 return &hci_transport_em9304_spi; 514 } 515