1 /* 2 * Copyright (C) 2014 BlueKitchen GmbH 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. Neither the name of the copyright holders nor the names of 14 * contributors may be used to endorse or promote products derived 15 * from this software without specific prior written permission. 16 * 4. Any redistribution, use, or modification is done solely for 17 * personal benefit and not for any commercial purpose or for 18 * monetary gain. 19 * 20 * THIS SOFTWARE IS PROVIDED BY BLUEKITCHEN GMBH AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 23 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL MATTHIAS 24 * RINGWALD OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 26 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 27 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 28 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 29 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 30 * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * Please inquire about commercial licensing options at 34 * [email protected] 35 * 36 */ 37 38 #define __BTSTACK_FILE__ "hci_transport_em9304_spi.c" 39 40 #include "btstack_config.h" 41 #include "btstack_em9304_spi.h" 42 43 // EM9304 SPI Driver 44 static const btstack_em9304_spi_t * btstack_em9304_spi; 45 46 ///////////////////////// 47 // em9304 engine 48 #include "btstack_ring_buffer.h" 49 #include "btstack_debug.h" 50 #include "btstack_util.h" 51 #include "hci.h" 52 #include "hci_transport.h" 53 54 static void em9304_spi_engine_run(void); 55 56 #define STS_SLAVE_READY 0xc0 57 58 #define EM9304_SPI_HEADER_TX 0x42 59 #define EM9304_SPI_HEADER_RX 0x81 60 61 #define SPI_EM9304_BUFFER_SIZE 64 62 #define SPI_EM9304_RING_BUFFER_SIZE 128 63 64 // state 65 static volatile enum { 66 SPI_EM9304_READY_FOR_TX, 67 SPI_EM9304_READY_FOR_TX_AND_RX, 68 SPI_EM9304_RX_W4_READ_COMMAND_SENT, 69 SPI_EM9304_RX_READ_COMMAND_SENT, 70 SPI_EM9304_RX_W4_STS2_RECEIVED, 71 SPI_EM9304_RX_STS2_RECEIVED, 72 SPI_EM9304_RX_W4_DATA_RECEIVED, 73 SPI_EM9304_RX_DATA_RECEIVED, 74 SPI_EM9304_TX_W4_RDY, 75 SPI_EM9304_TX_W4_WRITE_COMMAND_SENT, 76 SPI_EM9304_TX_WRITE_COMMAND_SENT, 77 SPI_EM9304_TX_W4_STS2_RECEIVED, 78 SPI_EM9304_TX_STS2_RECEIVED, 79 SPI_EM9304_TX_W4_DATA_SENT, 80 SPI_EM9304_TX_DATA_SENT, 81 SPI_EM9304_DONE, 82 } em9304_spi_engine_state; 83 84 static uint16_t em9304_spi_engine_rx_request_len; 85 static uint16_t em9304_spi_engine_tx_request_len; 86 87 static btstack_ring_buffer_t em9304_spi_engine_rx_ring_buffer; 88 89 // note: needs to be aligned 90 static uint8_t em9304_spi_engine_rx_ring_buffer_storage[SPI_EM9304_RING_BUFFER_SIZE]; 91 92 static const uint8_t * em9304_spi_engine_tx_data; 93 static uint16_t em9304_spi_engine_tx_size; 94 95 // handlers 96 static void (*em9304_spi_engine_rx_available_handler)(void); 97 static void (*em9304_spi_engine_tx_done_handler)(void); 98 99 // TODO: get rid of alignment requirement 100 union { 101 uint32_t words[1]; 102 uint8_t bytes[1]; 103 } sCommand; 104 105 union { 106 uint32_t words[1]; 107 uint8_t bytes[1]; 108 } sStas; 109 110 union { 111 uint32_t words[SPI_EM9304_BUFFER_SIZE/4]; 112 uint8_t bytes[SPI_EM9304_BUFFER_SIZE]; 113 } em9304_spi_engine_spi_buffer; 114 115 static void em9304_spi_engine_ready_callback(void){ 116 // TODO: collect states 117 em9304_spi_engine_run(); 118 } 119 120 static void em9304_spi_engine_transfer_done(void){ 121 switch (em9304_spi_engine_state){ 122 case SPI_EM9304_RX_W4_READ_COMMAND_SENT: 123 em9304_spi_engine_state = SPI_EM9304_RX_READ_COMMAND_SENT; 124 break; 125 case SPI_EM9304_RX_W4_STS2_RECEIVED: 126 em9304_spi_engine_state = SPI_EM9304_RX_STS2_RECEIVED; 127 break; 128 case SPI_EM9304_RX_W4_DATA_RECEIVED: 129 em9304_spi_engine_state = SPI_EM9304_RX_DATA_RECEIVED; 130 break; 131 case SPI_EM9304_TX_W4_WRITE_COMMAND_SENT: 132 em9304_spi_engine_state = SPI_EM9304_TX_WRITE_COMMAND_SENT; 133 break; 134 case SPI_EM9304_TX_W4_STS2_RECEIVED: 135 em9304_spi_engine_state = SPI_EM9304_TX_STS2_RECEIVED; 136 break; 137 case SPI_EM9304_TX_W4_DATA_SENT: 138 em9304_spi_engine_state = SPI_EM9304_TX_DATA_SENT; 139 break; 140 default: 141 return; 142 } 143 em9304_spi_engine_run(); 144 } 145 146 static void em9304_spi_engine_start_tx_transaction(void){ 147 // state = wait for RDY 148 em9304_spi_engine_state = SPI_EM9304_TX_W4_RDY; 149 150 // chip select 151 btstack_em9304_spi->set_chip_select(1); 152 153 // enable IRQ 154 btstack_em9304_spi->set_ready_callback(&em9304_spi_engine_ready_callback); 155 } 156 157 static inline int em9304_engine_space_in_rx_buffer(void){ 158 return btstack_ring_buffer_bytes_free(&em9304_spi_engine_rx_ring_buffer) >= SPI_EM9304_BUFFER_SIZE; 159 } 160 161 static void em9304_engine_receive_buffer_ready(void){ 162 // no data ready for receive or transmit, but space in rx ringbuffer -> enable READY IRQ 163 em9304_spi_engine_state = SPI_EM9304_READY_FOR_TX_AND_RX; 164 btstack_em9304_spi->set_ready_callback(&em9304_spi_engine_ready_callback); 165 } 166 167 static void em9304_engine_start_next_transaction(void){ 168 169 if (em9304_spi_engine_state != SPI_EM9304_DONE) return; 170 171 if (btstack_em9304_spi->get_ready()){ 172 // RDY -> data available 173 if (em9304_engine_space_in_rx_buffer()) { 174 // disable interrupt again 175 btstack_em9304_spi->set_ready_callback(NULL); 176 177 // enable chip select 178 btstack_em9304_spi->set_chip_select(1); 179 180 // send read command 181 em9304_spi_engine_state = SPI_EM9304_RX_W4_READ_COMMAND_SENT; 182 sCommand.bytes[0] = EM9304_SPI_HEADER_RX; 183 btstack_em9304_spi->transmit(sCommand.bytes, 1); 184 } 185 } else if (em9304_spi_engine_tx_size){ 186 em9304_spi_engine_start_tx_transaction(); 187 } else if (em9304_engine_space_in_rx_buffer()){ 188 em9304_engine_receive_buffer_ready(); 189 } 190 } 191 192 static void em9304_engine_action_done(void){ 193 // chip deselect & done 194 btstack_em9304_spi->set_chip_select(0); 195 em9304_spi_engine_state = SPI_EM9304_DONE; 196 } 197 198 static void em9304_spi_engine_run(void){ 199 uint16_t max_bytes_to_send; 200 switch (em9304_spi_engine_state){ 201 202 case SPI_EM9304_RX_READ_COMMAND_SENT: 203 em9304_spi_engine_state = SPI_EM9304_RX_W4_STS2_RECEIVED; 204 btstack_em9304_spi->receive(sStas.bytes, 1); 205 break; 206 207 case SPI_EM9304_RX_STS2_RECEIVED: 208 // check slave status 209 log_debug("RX: STS2 0x%02X", sStas.bytes[0]); 210 211 // read data 212 em9304_spi_engine_state = SPI_EM9304_RX_W4_DATA_RECEIVED; 213 em9304_spi_engine_rx_request_len = sStas.bytes[0]; 214 btstack_em9304_spi->receive(em9304_spi_engine_spi_buffer.bytes, em9304_spi_engine_rx_request_len); 215 break; 216 217 case SPI_EM9304_RX_DATA_RECEIVED: 218 // done 219 em9304_engine_action_done(); 220 221 // move data into ring buffer 222 btstack_ring_buffer_write(&em9304_spi_engine_rx_ring_buffer, em9304_spi_engine_spi_buffer.bytes, em9304_spi_engine_rx_request_len); 223 em9304_spi_engine_rx_request_len = 0; 224 225 // notify about new data available -- assume empty 226 (*em9304_spi_engine_rx_available_handler)(); 227 228 // next 229 em9304_engine_start_next_transaction(); 230 break; 231 232 case SPI_EM9304_TX_W4_RDY: 233 // check if ready 234 if (!btstack_em9304_spi->get_ready()) break; 235 236 // disable interrupt again 237 btstack_em9304_spi->set_ready_callback(NULL); 238 239 // send write command 240 em9304_spi_engine_state = SPI_EM9304_TX_W4_WRITE_COMMAND_SENT; 241 sCommand.bytes[0] = EM9304_SPI_HEADER_TX; 242 btstack_em9304_spi->transmit(sCommand.bytes, 1); 243 break; 244 245 case SPI_EM9304_TX_WRITE_COMMAND_SENT: 246 em9304_spi_engine_state = SPI_EM9304_TX_W4_STS2_RECEIVED; 247 btstack_em9304_spi->receive(sStas.bytes, 1); 248 break; 249 250 case SPI_EM9304_TX_STS2_RECEIVED: 251 // check slave status and em9304 rx buffer space 252 log_debug("TX: STS2 0x%02X", sStas.bytes[0]); 253 max_bytes_to_send = sStas.bytes[0]; 254 if (max_bytes_to_send == 0){ 255 // done 256 em9304_engine_action_done(); 257 // next 258 em9304_engine_start_next_transaction(); 259 break; 260 } 261 262 // number bytes to send 263 em9304_spi_engine_tx_request_len = btstack_min(em9304_spi_engine_tx_size, max_bytes_to_send); 264 265 // send command 266 em9304_spi_engine_state = SPI_EM9304_TX_W4_DATA_SENT; 267 if ( (((uintptr_t) em9304_spi_engine_tx_data) & 0x03) == 0){ 268 // 4-byte aligned 269 btstack_em9304_spi->transmit( (uint8_t*) em9304_spi_engine_tx_data, em9304_spi_engine_tx_request_len); 270 } else { 271 // TODO: get rid of alignment requirement 272 // enforce alignment by copying to spi buffer first 273 memcpy(em9304_spi_engine_spi_buffer.bytes, em9304_spi_engine_tx_data, em9304_spi_engine_tx_request_len); 274 btstack_em9304_spi->transmit( (uint8_t*) em9304_spi_engine_spi_buffer.bytes, em9304_spi_engine_tx_request_len); 275 } 276 break; 277 278 case SPI_EM9304_TX_DATA_SENT: 279 // done 280 em9304_engine_action_done(); 281 282 // chunk sent 283 em9304_spi_engine_tx_size -= em9304_spi_engine_tx_request_len; 284 em9304_spi_engine_tx_data += em9304_spi_engine_tx_request_len; 285 em9304_spi_engine_tx_request_len = 0; 286 287 // notify higher layer when complete 288 if (em9304_spi_engine_tx_size == 0){ 289 (*em9304_spi_engine_tx_done_handler)(); 290 } 291 292 // next 293 em9304_engine_start_next_transaction(); 294 break; 295 296 default: 297 break; 298 } 299 } 300 301 static void em9304_spi_engine_init(void){ 302 btstack_em9304_spi->open(); 303 btstack_em9304_spi->set_transfer_done_callback(&em9304_spi_engine_transfer_done); 304 btstack_ring_buffer_init(&em9304_spi_engine_rx_ring_buffer, &em9304_spi_engine_rx_ring_buffer_storage[0], SPI_EM9304_RING_BUFFER_SIZE); 305 em9304_spi_engine_state = SPI_EM9304_DONE; 306 em9304_engine_start_next_transaction(); 307 } 308 309 static void em9304_spi_engine_close(void){ 310 btstack_em9304_spi->close(); 311 } 312 313 static void em9304_spi_engine_set_data_available( void (*the_block_handler)(void)){ 314 em9304_spi_engine_rx_available_handler = the_block_handler; 315 } 316 317 static void em9304_spi_engine_set_block_sent( void (*the_block_handler)(void)){ 318 em9304_spi_engine_tx_done_handler = the_block_handler; 319 } 320 321 static void em9304_spi_engine_send_block(const uint8_t *buffer, uint16_t length){ 322 em9304_spi_engine_tx_data = buffer; 323 em9304_spi_engine_tx_size = length; 324 em9304_engine_start_next_transaction(); 325 } 326 327 static uint16_t em9304_engine_num_bytes_available(void){ 328 return btstack_ring_buffer_bytes_available(&em9304_spi_engine_rx_ring_buffer); 329 } 330 331 static void em9304_engine_get_bytes(uint8_t * buffer, uint16_t num_bytes){ 332 uint32_t bytes_read; 333 btstack_ring_buffer_read(&em9304_spi_engine_rx_ring_buffer, buffer, num_bytes, &bytes_read); 334 } 335 336 ////////////////////////////////////////////////////////////////////////////// 337 338 // assert pre-buffer for packet type is available 339 #if !defined(HCI_OUTGOING_PRE_BUFFER_SIZE) || (HCI_OUTGOING_PRE_BUFFER_SIZE == 0) 340 #error HCI_OUTGOING_PRE_BUFFER_SIZE not defined. Please update hci.h 341 #endif 342 343 static void dummy_handler(uint8_t packet_type, uint8_t *packet, uint16_t size); 344 345 typedef enum { 346 H4_W4_PACKET_TYPE, 347 H4_W4_EVENT_HEADER, 348 H4_W4_ACL_HEADER, 349 H4_W4_PAYLOAD, 350 } H4_STATE; 351 352 typedef enum { 353 TX_IDLE = 1, 354 TX_W4_PACKET_SENT, 355 } TX_STATE; 356 357 // write state 358 static TX_STATE tx_state; 359 360 static uint8_t packet_sent_event[] = { HCI_EVENT_TRANSPORT_PACKET_SENT, 0}; 361 362 static void (*packet_handler)(uint8_t packet_type, uint8_t *packet, uint16_t size) = dummy_handler; 363 364 // packet reader state machine 365 static H4_STATE hci_transport_em9304_h4_state; 366 static uint16_t hci_transport_em9304_spi_bytes_to_read; 367 static uint16_t hci_transport_em9304_spi_read_pos; 368 369 // incoming packet buffer 370 static uint8_t hci_packet_with_pre_buffer[HCI_INCOMING_PRE_BUFFER_SIZE + 1 + HCI_PACKET_BUFFER_SIZE]; // packet type + max(acl header + acl payload, event header + event data) 371 static uint8_t * hci_packet = &hci_packet_with_pre_buffer[HCI_INCOMING_PRE_BUFFER_SIZE]; 372 373 static void hci_transport_em9304_spi_block_read(void); 374 375 static void hci_transport_em9304_spi_reset_statemachine(void){ 376 hci_transport_em9304_h4_state = H4_W4_PACKET_TYPE; 377 hci_transport_em9304_spi_read_pos = 0; 378 hci_transport_em9304_spi_bytes_to_read = 1; 379 } 380 381 static void hci_transport_em9304_spi_process_data(void){ 382 while (1){ 383 384 uint16_t bytes_available = em9304_engine_num_bytes_available(); 385 log_debug("transfer_rx_data: ring buffer has %u -> hci wants %u", bytes_available, hci_transport_em9304_spi_bytes_to_read); 386 387 if (!bytes_available) break; 388 if (!hci_transport_em9304_spi_bytes_to_read) break; 389 390 uint16_t bytes_to_copy = btstack_min(bytes_available, hci_transport_em9304_spi_bytes_to_read); 391 em9304_engine_get_bytes(&hci_packet[hci_transport_em9304_spi_read_pos], bytes_to_copy); 392 393 hci_transport_em9304_spi_read_pos += bytes_to_copy; 394 hci_transport_em9304_spi_bytes_to_read -= bytes_to_copy; 395 396 if (hci_transport_em9304_spi_bytes_to_read == 0){ 397 hci_transport_em9304_spi_block_read(); 398 } 399 } 400 } 401 402 static void hci_transport_em9304_spi_block_read(void){ 403 switch (hci_transport_em9304_h4_state) { 404 case H4_W4_PACKET_TYPE: 405 switch (hci_packet[0]){ 406 case HCI_EVENT_PACKET: 407 hci_transport_em9304_spi_bytes_to_read = HCI_EVENT_HEADER_SIZE; 408 hci_transport_em9304_h4_state = H4_W4_EVENT_HEADER; 409 break; 410 case HCI_ACL_DATA_PACKET: 411 hci_transport_em9304_spi_bytes_to_read = HCI_ACL_HEADER_SIZE; 412 hci_transport_em9304_h4_state = H4_W4_ACL_HEADER; 413 break; 414 default: 415 log_error("invalid packet type 0x%02x", hci_packet[0]); 416 hci_transport_em9304_spi_reset_statemachine(); 417 break; 418 } 419 break; 420 421 case H4_W4_EVENT_HEADER: 422 hci_transport_em9304_spi_bytes_to_read = hci_packet[2]; 423 hci_transport_em9304_h4_state = H4_W4_PAYLOAD; 424 break; 425 426 case H4_W4_ACL_HEADER: 427 hci_transport_em9304_spi_bytes_to_read = little_endian_read_16( hci_packet, 3); 428 // check ACL length 429 if (HCI_ACL_HEADER_SIZE + hci_transport_em9304_spi_bytes_to_read > HCI_PACKET_BUFFER_SIZE){ 430 log_error("invalid ACL payload len %d - only space for %u", hci_transport_em9304_spi_bytes_to_read, HCI_PACKET_BUFFER_SIZE - HCI_ACL_HEADER_SIZE); 431 hci_transport_em9304_spi_reset_statemachine(); 432 break; 433 } 434 hci_transport_em9304_h4_state = H4_W4_PAYLOAD; 435 break; 436 437 case H4_W4_PAYLOAD: 438 packet_handler(hci_packet[0], &hci_packet[1], hci_transport_em9304_spi_read_pos-1); 439 hci_transport_em9304_spi_reset_statemachine(); 440 break; 441 default: 442 break; 443 } 444 } 445 446 static void hci_transport_em9304_spi_block_sent(void){ 447 switch (tx_state){ 448 case TX_W4_PACKET_SENT: 449 // packet fully sent, reset state 450 tx_state = TX_IDLE; 451 // notify upper stack that it can send again 452 packet_handler(HCI_EVENT_PACKET, &packet_sent_event[0], sizeof(packet_sent_event)); 453 break; 454 default: 455 break; 456 } 457 } 458 459 static int hci_transport_em9304_spi_can_send_now(uint8_t packet_type){ 460 return tx_state == TX_IDLE; 461 } 462 463 static int hci_transport_em9304_spi_send_packet(uint8_t packet_type, uint8_t * packet, int size){ 464 465 // store packet type before actual data and increase size 466 size++; 467 packet--; 468 *packet = packet_type; 469 470 // start sending 471 tx_state = TX_W4_PACKET_SENT; 472 em9304_spi_engine_send_block(packet, size); 473 return 0; 474 } 475 476 static void hci_transport_em9304_spi_init(const void * transport_config){ 477 } 478 479 static int hci_transport_em9304_spi_open(void){ 480 481 // setup UART driver 482 em9304_spi_engine_init(); 483 em9304_spi_engine_set_data_available(&hci_transport_em9304_spi_process_data); 484 em9304_spi_engine_set_block_sent(&hci_transport_em9304_spi_block_sent); 485 // setup H4 RX 486 hci_transport_em9304_spi_reset_statemachine(); 487 // setup H4 TX 488 tx_state = TX_IDLE; 489 return 0; 490 } 491 492 static int hci_transport_em9304_spi_close(void){ 493 em9304_spi_engine_close(); 494 return 0; 495 } 496 497 static void hci_transport_em9304_spi_register_packet_handler(void (*handler)(uint8_t packet_type, uint8_t *packet, uint16_t size)){ 498 packet_handler = handler; 499 } 500 501 static void dummy_handler(uint8_t packet_type, uint8_t *packet, uint16_t size){ 502 } 503 504 // --- end of eHCILL implementation --------- 505 506 static const hci_transport_t hci_transport_em9304_spi = { 507 /* const char * name; */ "H4", 508 /* void (*init) (const void *transport_config); */ &hci_transport_em9304_spi_init, 509 /* int (*open)(void); */ &hci_transport_em9304_spi_open, 510 /* int (*close)(void); */ &hci_transport_em9304_spi_close, 511 /* void (*register_packet_handler)(void (*handler)(...); */ &hci_transport_em9304_spi_register_packet_handler, 512 /* int (*can_send_packet_now)(uint8_t packet_type); */ &hci_transport_em9304_spi_can_send_now, 513 /* int (*send_packet)(...); */ &hci_transport_em9304_spi_send_packet, 514 /* int (*set_baudrate)(uint32_t baudrate); */ NULL, 515 /* void (*reset_link)(void); */ NULL, 516 /* void (*set_sco_config)(uint16_t voice_setting, int num_connections); */ NULL, 517 }; 518 519 // configure and return h4 singleton 520 const hci_transport_t * hci_transport_em9304_spi_instance(const btstack_em9304_spi_t * em9304_spi_driver) { 521 btstack_em9304_spi = em9304_spi_driver; 522 return &hci_transport_em9304_spi; 523 } 524