xref: /btstack/port/stm32-wb55xx-nucleo-freertos/startup_stm32wb55xx_cm4.s (revision 0561b2d8d5dba972c7daa57d5e677f7a1327edfd)
1*0561b2d8STREFOU Felix/**
2*0561b2d8STREFOU Felix  ******************************************************************************
3*0561b2d8STREFOU Felix  * @file      startup_stm32wb55xx_cm4.s
4*0561b2d8STREFOU Felix  * @author    MCD Application Team
5*0561b2d8STREFOU Felix  * @brief     STM32WB55xx devices vector table GCC toolchain.
6*0561b2d8STREFOU Felix  *            This module performs:
7*0561b2d8STREFOU Felix  *                - Set the initial SP
8*0561b2d8STREFOU Felix  *                - Set the initial PC == Reset_Handler,
9*0561b2d8STREFOU Felix  *                - Set the vector table entries with the exceptions ISR address
10*0561b2d8STREFOU Felix  *                - Branches to main in the C library (which eventually
11*0561b2d8STREFOU Felix  *                  calls main()).
12*0561b2d8STREFOU Felix  *            After Reset the Cortex-M4 processor is in Thread mode,
13*0561b2d8STREFOU Felix  *            priority is Privileged, and the Stack is set to Main.
14*0561b2d8STREFOU Felix  ******************************************************************************
15*0561b2d8STREFOU Felix  * @attention
16*0561b2d8STREFOU Felix  *
17*0561b2d8STREFOU Felix  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
18*0561b2d8STREFOU Felix  * All rights reserved.</center></h2>
19*0561b2d8STREFOU Felix  *
20*0561b2d8STREFOU Felix  * This software component is licensed by ST under BSD 3-Clause license,
21*0561b2d8STREFOU Felix  * the "License"; You may not use this file except in compliance with the
22*0561b2d8STREFOU Felix  * License. You may obtain a copy of the License at:
23*0561b2d8STREFOU Felix  *                        opensource.org/licenses/BSD-3-Clause
24*0561b2d8STREFOU Felix  *
25*0561b2d8STREFOU Felix  ******************************************************************************
26*0561b2d8STREFOU Felix  */
27*0561b2d8STREFOU Felix
28*0561b2d8STREFOU Felix  .syntax unified
29*0561b2d8STREFOU Felix	.cpu cortex-m4
30*0561b2d8STREFOU Felix	.fpu softvfp
31*0561b2d8STREFOU Felix	.thumb
32*0561b2d8STREFOU Felix
33*0561b2d8STREFOU Felix.global	g_pfnVectors
34*0561b2d8STREFOU Felix.global	Default_Handler
35*0561b2d8STREFOU Felix
36*0561b2d8STREFOU Felix/* start address for the initialization values of the .data section.
37*0561b2d8STREFOU Felixdefined in linker script */
38*0561b2d8STREFOU Felix.word	_sidata
39*0561b2d8STREFOU Felix/* start address for the .data section. defined in linker script */
40*0561b2d8STREFOU Felix.word	_sdata
41*0561b2d8STREFOU Felix/* end address for the .data section. defined in linker script */
42*0561b2d8STREFOU Felix.word	_edata
43*0561b2d8STREFOU Felix/* start address for the .bss section. defined in linker script */
44*0561b2d8STREFOU Felix.word	_sbss
45*0561b2d8STREFOU Felix/* end address for the .bss section. defined in linker script */
46*0561b2d8STREFOU Felix.word	_ebss
47*0561b2d8STREFOU Felix
48*0561b2d8STREFOU Felix  .section .text.Reset_Handler
49*0561b2d8STREFOU Felix  .weak Reset_Handler
50*0561b2d8STREFOU Felix  .type Reset_Handler, %function
51*0561b2d8STREFOU FelixReset_Handler:
52*0561b2d8STREFOU Felix  ldr   r0, =_estack
53*0561b2d8STREFOU Felix  mov   sp, r0          /* set stack pointer */
54*0561b2d8STREFOU Felix
55*0561b2d8STREFOU Felix/* Copy the data segment initializers from flash to SRAM */
56*0561b2d8STREFOU Felix  ldr r0, =_sdata
57*0561b2d8STREFOU Felix  ldr r1, =_edata
58*0561b2d8STREFOU Felix  ldr r2, =_sidata
59*0561b2d8STREFOU Felix  movs r3, #0
60*0561b2d8STREFOU Felix  b	LoopCopyDataInit
61*0561b2d8STREFOU Felix
62*0561b2d8STREFOU FelixCopyDataInit:
63*0561b2d8STREFOU Felix  ldr r4, [r2, r3]
64*0561b2d8STREFOU Felix  str r4, [r0, r3]
65*0561b2d8STREFOU Felix  adds r3, r3, #4
66*0561b2d8STREFOU Felix
67*0561b2d8STREFOU FelixLoopCopyDataInit:
68*0561b2d8STREFOU Felix  adds r4, r0, r3
69*0561b2d8STREFOU Felix  cmp r4, r1
70*0561b2d8STREFOU Felix  bcc CopyDataInit
71*0561b2d8STREFOU Felix
72*0561b2d8STREFOU Felix/* Zero fill the bss segment. */
73*0561b2d8STREFOU Felix  ldr r2, =_sbss
74*0561b2d8STREFOU Felix  ldr r4, =_ebss
75*0561b2d8STREFOU Felix  movs r3, #0
76*0561b2d8STREFOU Felix  b LoopFillZerobss
77*0561b2d8STREFOU Felix
78*0561b2d8STREFOU FelixFillZerobss:
79*0561b2d8STREFOU Felix  str  r3, [r2]
80*0561b2d8STREFOU Felix  adds r2, r2, #4
81*0561b2d8STREFOU Felix
82*0561b2d8STREFOU FelixLoopFillZerobss:
83*0561b2d8STREFOU Felix  cmp r2, r4
84*0561b2d8STREFOU Felix  bcc FillZerobss
85*0561b2d8STREFOU Felix
86*0561b2d8STREFOU Felix/* Call the clock system intitialization function.*/
87*0561b2d8STREFOU Felix  bl  SystemInit
88*0561b2d8STREFOU Felix/* Call static constructors */
89*0561b2d8STREFOU Felix  bl __libc_init_array
90*0561b2d8STREFOU Felix/* Call the application s entry point.*/
91*0561b2d8STREFOU Felix	bl	main
92*0561b2d8STREFOU Felix
93*0561b2d8STREFOU FelixLoopForever:
94*0561b2d8STREFOU Felix  b LoopForever
95*0561b2d8STREFOU Felix
96*0561b2d8STREFOU Felix.size	Reset_Handler, .-Reset_Handler
97*0561b2d8STREFOU Felix
98*0561b2d8STREFOU Felix/**
99*0561b2d8STREFOU Felix * @brief  This is the code that gets called when the processor receives an
100*0561b2d8STREFOU Felix *         unexpected interrupt.  This simply enters an infinite loop, preserving
101*0561b2d8STREFOU Felix *         the system state for examination by a debugger.
102*0561b2d8STREFOU Felix *
103*0561b2d8STREFOU Felix * @param  None
104*0561b2d8STREFOU Felix * @retval None
105*0561b2d8STREFOU Felix*/
106*0561b2d8STREFOU Felix  .section .text.Default_Handler,"ax",%progbits
107*0561b2d8STREFOU FelixDefault_Handler:
108*0561b2d8STREFOU FelixInfinite_Loop:
109*0561b2d8STREFOU Felix	b	Infinite_Loop
110*0561b2d8STREFOU Felix	.size	Default_Handler, .-Default_Handler
111*0561b2d8STREFOU Felix/******************************************************************************
112*0561b2d8STREFOU Felix*
113*0561b2d8STREFOU Felix* The minimal vector table for a Cortex-M4.  Note that the proper constructs
114*0561b2d8STREFOU Felix* must be placed on this to ensure that it ends up at physical address
115*0561b2d8STREFOU Felix* 0x0000.0000.
116*0561b2d8STREFOU Felix*
117*0561b2d8STREFOU Felix******************************************************************************/
118*0561b2d8STREFOU Felix 	.section	.isr_vector,"a",%progbits
119*0561b2d8STREFOU Felix	.type	g_pfnVectors, %object
120*0561b2d8STREFOU Felix	.size	g_pfnVectors, .-g_pfnVectors
121*0561b2d8STREFOU Felix
122*0561b2d8STREFOU Felix
123*0561b2d8STREFOU Felixg_pfnVectors:
124*0561b2d8STREFOU Felix  .word _estack
125*0561b2d8STREFOU Felix  .word Reset_Handler
126*0561b2d8STREFOU Felix	.word	NMI_Handler
127*0561b2d8STREFOU Felix  .word HardFault_Handler
128*0561b2d8STREFOU Felix  .word MemManage_Handler
129*0561b2d8STREFOU Felix  .word BusFault_Handler
130*0561b2d8STREFOU Felix  .word UsageFault_Handler
131*0561b2d8STREFOU Felix  .word 0
132*0561b2d8STREFOU Felix  .word 0
133*0561b2d8STREFOU Felix  .word 0
134*0561b2d8STREFOU Felix  .word 0
135*0561b2d8STREFOU Felix  .word SVC_Handler
136*0561b2d8STREFOU Felix  .word DebugMon_Handler
137*0561b2d8STREFOU Felix  .word 0
138*0561b2d8STREFOU Felix  .word PendSV_Handler
139*0561b2d8STREFOU Felix  .word SysTick_Handler
140*0561b2d8STREFOU Felix  .word WWDG_IRQHandler
141*0561b2d8STREFOU Felix  .word PVD_PVM_IRQHandler
142*0561b2d8STREFOU Felix  .word TAMP_STAMP_LSECSS_IRQHandler
143*0561b2d8STREFOU Felix  .word RTC_WKUP_IRQHandler
144*0561b2d8STREFOU Felix  .word FLASH_IRQHandler
145*0561b2d8STREFOU Felix  .word RCC_IRQHandler
146*0561b2d8STREFOU Felix  .word EXTI0_IRQHandler
147*0561b2d8STREFOU Felix  .word EXTI1_IRQHandler
148*0561b2d8STREFOU Felix  .word EXTI2_IRQHandler
149*0561b2d8STREFOU Felix  .word EXTI3_IRQHandler
150*0561b2d8STREFOU Felix  .word EXTI4_IRQHandler
151*0561b2d8STREFOU Felix  .word DMA1_Channel1_IRQHandler
152*0561b2d8STREFOU Felix  .word DMA1_Channel2_IRQHandler
153*0561b2d8STREFOU Felix  .word DMA1_Channel3_IRQHandler
154*0561b2d8STREFOU Felix  .word DMA1_Channel4_IRQHandler
155*0561b2d8STREFOU Felix  .word DMA1_Channel5_IRQHandler
156*0561b2d8STREFOU Felix  .word DMA1_Channel6_IRQHandler
157*0561b2d8STREFOU Felix  .word DMA1_Channel7_IRQHandler
158*0561b2d8STREFOU Felix  .word ADC1_IRQHandler
159*0561b2d8STREFOU Felix  .word USB_HP_IRQHandler
160*0561b2d8STREFOU Felix  .word USB_LP_IRQHandler
161*0561b2d8STREFOU Felix  .word C2SEV_PWR_C2H_IRQHandler
162*0561b2d8STREFOU Felix  .word COMP_IRQHandler
163*0561b2d8STREFOU Felix  .word EXTI9_5_IRQHandler
164*0561b2d8STREFOU Felix  .word TIM1_BRK_IRQHandler
165*0561b2d8STREFOU Felix  .word TIM1_UP_TIM16_IRQHandler
166*0561b2d8STREFOU Felix  .word TIM1_TRG_COM_TIM17_IRQHandler
167*0561b2d8STREFOU Felix  .word TIM1_CC_IRQHandler
168*0561b2d8STREFOU Felix  .word TIM2_IRQHandler
169*0561b2d8STREFOU Felix  .word PKA_IRQHandler
170*0561b2d8STREFOU Felix  .word I2C1_EV_IRQHandler
171*0561b2d8STREFOU Felix  .word I2C1_ER_IRQHandler
172*0561b2d8STREFOU Felix  .word I2C3_EV_IRQHandler
173*0561b2d8STREFOU Felix  .word I2C3_ER_IRQHandler
174*0561b2d8STREFOU Felix  .word SPI1_IRQHandler
175*0561b2d8STREFOU Felix  .word SPI2_IRQHandler
176*0561b2d8STREFOU Felix  .word USART1_IRQHandler
177*0561b2d8STREFOU Felix  .word LPUART1_IRQHandler
178*0561b2d8STREFOU Felix  .word SAI1_IRQHandler
179*0561b2d8STREFOU Felix  .word TSC_IRQHandler
180*0561b2d8STREFOU Felix  .word EXTI15_10_IRQHandler
181*0561b2d8STREFOU Felix  .word RTC_Alarm_IRQHandler
182*0561b2d8STREFOU Felix  .word CRS_IRQHandler
183*0561b2d8STREFOU Felix  .word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
184*0561b2d8STREFOU Felix  .word IPCC_C1_RX_IRQHandler
185*0561b2d8STREFOU Felix  .word IPCC_C1_TX_IRQHandler
186*0561b2d8STREFOU Felix  .word HSEM_IRQHandler
187*0561b2d8STREFOU Felix  .word LPTIM1_IRQHandler
188*0561b2d8STREFOU Felix  .word LPTIM2_IRQHandler
189*0561b2d8STREFOU Felix  .word LCD_IRQHandler
190*0561b2d8STREFOU Felix  .word QUADSPI_IRQHandler
191*0561b2d8STREFOU Felix  .word AES1_IRQHandler
192*0561b2d8STREFOU Felix  .word AES2_IRQHandler
193*0561b2d8STREFOU Felix  .word RNG_IRQHandler
194*0561b2d8STREFOU Felix  .word FPU_IRQHandler
195*0561b2d8STREFOU Felix  .word DMA2_Channel1_IRQHandler
196*0561b2d8STREFOU Felix  .word DMA2_Channel2_IRQHandler
197*0561b2d8STREFOU Felix  .word DMA2_Channel3_IRQHandler
198*0561b2d8STREFOU Felix  .word DMA2_Channel4_IRQHandler
199*0561b2d8STREFOU Felix  .word DMA2_Channel5_IRQHandler
200*0561b2d8STREFOU Felix  .word DMA2_Channel6_IRQHandler
201*0561b2d8STREFOU Felix  .word DMA2_Channel7_IRQHandler
202*0561b2d8STREFOU Felix  .word DMAMUX1_OVR_IRQHandler
203*0561b2d8STREFOU Felix
204*0561b2d8STREFOU Felix/*******************************************************************************
205*0561b2d8STREFOU Felix*
206*0561b2d8STREFOU Felix* Provide weak aliases for each Exception handler to the Default_Handler.
207*0561b2d8STREFOU Felix* As they are weak aliases, any function with the same name will override
208*0561b2d8STREFOU Felix* this definition.
209*0561b2d8STREFOU Felix*
210*0561b2d8STREFOU Felix*******************************************************************************/
211*0561b2d8STREFOU Felix  .weak	NMI_Handler
212*0561b2d8STREFOU Felix  .thumb_set NMI_Handler,Default_Handler
213*0561b2d8STREFOU Felix
214*0561b2d8STREFOU Felix  .weak  HardFault_Handler
215*0561b2d8STREFOU Felix  .thumb_set HardFault_Handler,Default_Handler
216*0561b2d8STREFOU Felix
217*0561b2d8STREFOU Felix  .weak  MemManage_Handler
218*0561b2d8STREFOU Felix  .thumb_set MemManage_Handler,Default_Handler
219*0561b2d8STREFOU Felix
220*0561b2d8STREFOU Felix  .weak  BusFault_Handler
221*0561b2d8STREFOU Felix  .thumb_set BusFault_Handler,Default_Handler
222*0561b2d8STREFOU Felix
223*0561b2d8STREFOU Felix  .weak  UsageFault_Handler
224*0561b2d8STREFOU Felix  .thumb_set UsageFault_Handler,Default_Handler
225*0561b2d8STREFOU Felix
226*0561b2d8STREFOU Felix  .weak  SVC_Handler
227*0561b2d8STREFOU Felix  .thumb_set SVC_Handler,Default_Handler
228*0561b2d8STREFOU Felix
229*0561b2d8STREFOU Felix  .weak  DebugMon_Handler
230*0561b2d8STREFOU Felix  .thumb_set DebugMon_Handler,Default_Handler
231*0561b2d8STREFOU Felix
232*0561b2d8STREFOU Felix  .weak  PendSV_Handler
233*0561b2d8STREFOU Felix  .thumb_set PendSV_Handler,Default_Handler
234*0561b2d8STREFOU Felix
235*0561b2d8STREFOU Felix  .weak  SysTick_Handler
236*0561b2d8STREFOU Felix  .thumb_set SysTick_Handler,Default_Handler
237*0561b2d8STREFOU Felix
238*0561b2d8STREFOU Felix  .weak  WWDG_IRQHandler
239*0561b2d8STREFOU Felix  .thumb_set WWDG_IRQHandler,Default_Handler
240*0561b2d8STREFOU Felix
241*0561b2d8STREFOU Felix  .weak  PVD_PVM_IRQHandler
242*0561b2d8STREFOU Felix  .thumb_set PVD_PVM_IRQHandler,Default_Handler
243*0561b2d8STREFOU Felix
244*0561b2d8STREFOU Felix  .weak  TAMP_STAMP_LSECSS_IRQHandler
245*0561b2d8STREFOU Felix  .thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
246*0561b2d8STREFOU Felix
247*0561b2d8STREFOU Felix  .weak  RTC_WKUP_IRQHandler
248*0561b2d8STREFOU Felix  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
249*0561b2d8STREFOU Felix
250*0561b2d8STREFOU Felix  .weak  FLASH_IRQHandler
251*0561b2d8STREFOU Felix  .thumb_set FLASH_IRQHandler,Default_Handler
252*0561b2d8STREFOU Felix
253*0561b2d8STREFOU Felix  .weak  RCC_IRQHandler
254*0561b2d8STREFOU Felix  .thumb_set RCC_IRQHandler,Default_Handler
255*0561b2d8STREFOU Felix
256*0561b2d8STREFOU Felix  .weak  EXTI0_IRQHandler
257*0561b2d8STREFOU Felix  .thumb_set EXTI0_IRQHandler,Default_Handler
258*0561b2d8STREFOU Felix
259*0561b2d8STREFOU Felix  .weak  EXTI1_IRQHandler
260*0561b2d8STREFOU Felix  .thumb_set EXTI1_IRQHandler,Default_Handler
261*0561b2d8STREFOU Felix
262*0561b2d8STREFOU Felix  .weak  EXTI2_IRQHandler
263*0561b2d8STREFOU Felix  .thumb_set EXTI2_IRQHandler,Default_Handler
264*0561b2d8STREFOU Felix
265*0561b2d8STREFOU Felix  .weak  EXTI3_IRQHandler
266*0561b2d8STREFOU Felix  .thumb_set EXTI3_IRQHandler,Default_Handler
267*0561b2d8STREFOU Felix
268*0561b2d8STREFOU Felix  .weak  EXTI4_IRQHandler
269*0561b2d8STREFOU Felix  .thumb_set EXTI4_IRQHandler,Default_Handler
270*0561b2d8STREFOU Felix
271*0561b2d8STREFOU Felix  .weak  DMA1_Channel1_IRQHandler
272*0561b2d8STREFOU Felix  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
273*0561b2d8STREFOU Felix
274*0561b2d8STREFOU Felix  .weak  DMA1_Channel2_IRQHandler
275*0561b2d8STREFOU Felix  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
276*0561b2d8STREFOU Felix
277*0561b2d8STREFOU Felix  .weak  DMA1_Channel3_IRQHandler
278*0561b2d8STREFOU Felix  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
279*0561b2d8STREFOU Felix
280*0561b2d8STREFOU Felix  .weak  DMA1_Channel4_IRQHandler
281*0561b2d8STREFOU Felix  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
282*0561b2d8STREFOU Felix
283*0561b2d8STREFOU Felix  .weak  DMA1_Channel5_IRQHandler
284*0561b2d8STREFOU Felix  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
285*0561b2d8STREFOU Felix
286*0561b2d8STREFOU Felix  .weak  DMA1_Channel6_IRQHandler
287*0561b2d8STREFOU Felix  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
288*0561b2d8STREFOU Felix
289*0561b2d8STREFOU Felix  .weak  DMA1_Channel7_IRQHandler
290*0561b2d8STREFOU Felix  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
291*0561b2d8STREFOU Felix
292*0561b2d8STREFOU Felix  .weak  ADC1_IRQHandler
293*0561b2d8STREFOU Felix  .thumb_set ADC1_IRQHandler,Default_Handler
294*0561b2d8STREFOU Felix
295*0561b2d8STREFOU Felix  .weak  USB_HP_IRQHandler
296*0561b2d8STREFOU Felix  .thumb_set USB_HP_IRQHandler,Default_Handler
297*0561b2d8STREFOU Felix
298*0561b2d8STREFOU Felix  .weak  USB_LP_IRQHandler
299*0561b2d8STREFOU Felix  .thumb_set USB_LP_IRQHandler,Default_Handler
300*0561b2d8STREFOU Felix
301*0561b2d8STREFOU Felix  .weak  C2SEV_PWR_C2H_IRQHandler
302*0561b2d8STREFOU Felix  .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
303*0561b2d8STREFOU Felix
304*0561b2d8STREFOU Felix  .weak  COMP_IRQHandler
305*0561b2d8STREFOU Felix  .thumb_set COMP_IRQHandler,Default_Handler
306*0561b2d8STREFOU Felix
307*0561b2d8STREFOU Felix  .weak  EXTI9_5_IRQHandler
308*0561b2d8STREFOU Felix  .thumb_set EXTI9_5_IRQHandler,Default_Handler
309*0561b2d8STREFOU Felix
310*0561b2d8STREFOU Felix  .weak  TIM1_BRK_IRQHandler
311*0561b2d8STREFOU Felix  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
312*0561b2d8STREFOU Felix
313*0561b2d8STREFOU Felix  .weak  TIM1_UP_TIM16_IRQHandler
314*0561b2d8STREFOU Felix  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
315*0561b2d8STREFOU Felix
316*0561b2d8STREFOU Felix  .weak  TIM1_TRG_COM_TIM17_IRQHandler
317*0561b2d8STREFOU Felix  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
318*0561b2d8STREFOU Felix
319*0561b2d8STREFOU Felix  .weak  TIM1_CC_IRQHandler
320*0561b2d8STREFOU Felix  .thumb_set TIM1_CC_IRQHandler,Default_Handler
321*0561b2d8STREFOU Felix
322*0561b2d8STREFOU Felix  .weak  TIM2_IRQHandler
323*0561b2d8STREFOU Felix  .thumb_set TIM2_IRQHandler,Default_Handler
324*0561b2d8STREFOU Felix
325*0561b2d8STREFOU Felix  .weak  PKA_IRQHandler
326*0561b2d8STREFOU Felix  .thumb_set PKA_IRQHandler,Default_Handler
327*0561b2d8STREFOU Felix
328*0561b2d8STREFOU Felix  .weak  I2C1_EV_IRQHandler
329*0561b2d8STREFOU Felix  .thumb_set I2C1_EV_IRQHandler,Default_Handler
330*0561b2d8STREFOU Felix
331*0561b2d8STREFOU Felix  .weak  I2C1_ER_IRQHandler
332*0561b2d8STREFOU Felix  .thumb_set I2C1_ER_IRQHandler,Default_Handler
333*0561b2d8STREFOU Felix
334*0561b2d8STREFOU Felix  .weak  I2C3_EV_IRQHandler
335*0561b2d8STREFOU Felix  .thumb_set I2C3_EV_IRQHandler,Default_Handler
336*0561b2d8STREFOU Felix
337*0561b2d8STREFOU Felix  .weak  I2C3_ER_IRQHandler
338*0561b2d8STREFOU Felix  .thumb_set I2C3_ER_IRQHandler,Default_Handler
339*0561b2d8STREFOU Felix
340*0561b2d8STREFOU Felix  .weak  SPI1_IRQHandler
341*0561b2d8STREFOU Felix  .thumb_set SPI1_IRQHandler,Default_Handler
342*0561b2d8STREFOU Felix
343*0561b2d8STREFOU Felix  .weak  SPI2_IRQHandler
344*0561b2d8STREFOU Felix  .thumb_set SPI2_IRQHandler,Default_Handler
345*0561b2d8STREFOU Felix
346*0561b2d8STREFOU Felix  .weak  USART1_IRQHandler
347*0561b2d8STREFOU Felix  .thumb_set USART1_IRQHandler,Default_Handler
348*0561b2d8STREFOU Felix
349*0561b2d8STREFOU Felix  .weak  LPUART1_IRQHandler
350*0561b2d8STREFOU Felix  .thumb_set LPUART1_IRQHandler,Default_Handler
351*0561b2d8STREFOU Felix
352*0561b2d8STREFOU Felix  .weak  SAI1_IRQHandler
353*0561b2d8STREFOU Felix  .thumb_set SAI1_IRQHandler,Default_Handler
354*0561b2d8STREFOU Felix
355*0561b2d8STREFOU Felix  .weak  TSC_IRQHandler
356*0561b2d8STREFOU Felix  .thumb_set TSC_IRQHandler,Default_Handler
357*0561b2d8STREFOU Felix
358*0561b2d8STREFOU Felix  .weak  EXTI15_10_IRQHandler
359*0561b2d8STREFOU Felix  .thumb_set EXTI15_10_IRQHandler,Default_Handler
360*0561b2d8STREFOU Felix
361*0561b2d8STREFOU Felix  .weak  RTC_Alarm_IRQHandler
362*0561b2d8STREFOU Felix  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
363*0561b2d8STREFOU Felix
364*0561b2d8STREFOU Felix  .weak  CRS_IRQHandler
365*0561b2d8STREFOU Felix  .thumb_set CRS_IRQHandler,Default_Handler
366*0561b2d8STREFOU Felix
367*0561b2d8STREFOU Felix  .weak  PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
368*0561b2d8STREFOU Felix  .thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
369*0561b2d8STREFOU Felix
370*0561b2d8STREFOU Felix  .weak  IPCC_C1_RX_IRQHandler
371*0561b2d8STREFOU Felix  .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
372*0561b2d8STREFOU Felix
373*0561b2d8STREFOU Felix  .weak  IPCC_C1_TX_IRQHandler
374*0561b2d8STREFOU Felix  .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
375*0561b2d8STREFOU Felix
376*0561b2d8STREFOU Felix  .weak  HSEM_IRQHandler
377*0561b2d8STREFOU Felix  .thumb_set HSEM_IRQHandler,Default_Handler
378*0561b2d8STREFOU Felix
379*0561b2d8STREFOU Felix  .weak  LPTIM1_IRQHandler
380*0561b2d8STREFOU Felix  .thumb_set LPTIM1_IRQHandler,Default_Handler
381*0561b2d8STREFOU Felix
382*0561b2d8STREFOU Felix  .weak  LPTIM2_IRQHandler
383*0561b2d8STREFOU Felix  .thumb_set LPTIM2_IRQHandler,Default_Handler
384*0561b2d8STREFOU Felix
385*0561b2d8STREFOU Felix  .weak  LCD_IRQHandler
386*0561b2d8STREFOU Felix  .thumb_set LCD_IRQHandler,Default_Handler
387*0561b2d8STREFOU Felix
388*0561b2d8STREFOU Felix  .weak  QUADSPI_IRQHandler
389*0561b2d8STREFOU Felix  .thumb_set QUADSPI_IRQHandler,Default_Handler
390*0561b2d8STREFOU Felix
391*0561b2d8STREFOU Felix  .weak  AES1_IRQHandler
392*0561b2d8STREFOU Felix  .thumb_set AES1_IRQHandler,Default_Handler
393*0561b2d8STREFOU Felix
394*0561b2d8STREFOU Felix  .weak  AES2_IRQHandler
395*0561b2d8STREFOU Felix  .thumb_set AES2_IRQHandler,Default_Handler
396*0561b2d8STREFOU Felix
397*0561b2d8STREFOU Felix  .weak  RNG_IRQHandler
398*0561b2d8STREFOU Felix  .thumb_set RNG_IRQHandler,Default_Handler
399*0561b2d8STREFOU Felix
400*0561b2d8STREFOU Felix  .weak  FPU_IRQHandler
401*0561b2d8STREFOU Felix  .thumb_set FPU_IRQHandler,Default_Handler
402*0561b2d8STREFOU Felix
403*0561b2d8STREFOU Felix  .weak  DMA2_Channel1_IRQHandler
404*0561b2d8STREFOU Felix  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
405*0561b2d8STREFOU Felix
406*0561b2d8STREFOU Felix  .weak  DMA2_Channel2_IRQHandler
407*0561b2d8STREFOU Felix  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
408*0561b2d8STREFOU Felix
409*0561b2d8STREFOU Felix  .weak  DMA2_Channel3_IRQHandler
410*0561b2d8STREFOU Felix  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
411*0561b2d8STREFOU Felix
412*0561b2d8STREFOU Felix  .weak  DMA2_Channel4_IRQHandler
413*0561b2d8STREFOU Felix  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
414*0561b2d8STREFOU Felix
415*0561b2d8STREFOU Felix  .weak  DMA2_Channel5_IRQHandler
416*0561b2d8STREFOU Felix  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
417*0561b2d8STREFOU Felix
418*0561b2d8STREFOU Felix  .weak  DMA2_Channel6_IRQHandler
419*0561b2d8STREFOU Felix  .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
420*0561b2d8STREFOU Felix
421*0561b2d8STREFOU Felix  .weak  DMA2_Channel7_IRQHandler
422*0561b2d8STREFOU Felix  .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
423*0561b2d8STREFOU Felix
424*0561b2d8STREFOU Felix  .weak  DMAMUX1_OVR_IRQHandler
425*0561b2d8STREFOU Felix  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
426*0561b2d8STREFOU Felix
427*0561b2d8STREFOU Felix/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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