xref: /btstack/port/stm32-l476rg-nucleo-sx1280/startup_stm32l476xx.s (revision 6b8177c56d8d42c688f52897394f8b5eac7ee972)
1*6b8177c5SMatthias Ringwald/**
2*6b8177c5SMatthias Ringwald  ******************************************************************************
3*6b8177c5SMatthias Ringwald  * @file      startup_stm32l476xx.s
4*6b8177c5SMatthias Ringwald  * @author    MCD Application Team
5*6b8177c5SMatthias Ringwald  * @brief     STM32L476xx devices vector table GCC toolchain.
6*6b8177c5SMatthias Ringwald  *            This module performs:
7*6b8177c5SMatthias Ringwald  *                - Set the initial SP
8*6b8177c5SMatthias Ringwald  *                - Set the initial PC == Reset_Handler,
9*6b8177c5SMatthias Ringwald  *                - Set the vector table entries with the exceptions ISR address,
10*6b8177c5SMatthias Ringwald  *                - Configure the clock system
11*6b8177c5SMatthias Ringwald  *                - Branches to main in the C library (which eventually
12*6b8177c5SMatthias Ringwald  *                  calls main()).
13*6b8177c5SMatthias Ringwald  *            After Reset the Cortex-M4 processor is in Thread mode,
14*6b8177c5SMatthias Ringwald  *            priority is Privileged, and the Stack is set to Main.
15*6b8177c5SMatthias Ringwald  ******************************************************************************
16*6b8177c5SMatthias Ringwald  * @attention
17*6b8177c5SMatthias Ringwald  *
18*6b8177c5SMatthias Ringwald  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
19*6b8177c5SMatthias Ringwald  * All rights reserved.</center></h2>
20*6b8177c5SMatthias Ringwald  *
21*6b8177c5SMatthias Ringwald  * This software component is licensed by ST under BSD 3-Clause license,
22*6b8177c5SMatthias Ringwald  * the "License"; You may not use this file except in compliance with the
23*6b8177c5SMatthias Ringwald  * License. You may obtain a copy of the License at:
24*6b8177c5SMatthias Ringwald  *                        opensource.org/licenses/BSD-3-Clause
25*6b8177c5SMatthias Ringwald  *
26*6b8177c5SMatthias Ringwald  ******************************************************************************
27*6b8177c5SMatthias Ringwald  */
28*6b8177c5SMatthias Ringwald
29*6b8177c5SMatthias Ringwald  .syntax unified
30*6b8177c5SMatthias Ringwald	.cpu cortex-m4
31*6b8177c5SMatthias Ringwald	.fpu softvfp
32*6b8177c5SMatthias Ringwald	.thumb
33*6b8177c5SMatthias Ringwald
34*6b8177c5SMatthias Ringwald.global	g_pfnVectors
35*6b8177c5SMatthias Ringwald.global	Default_Handler
36*6b8177c5SMatthias Ringwald
37*6b8177c5SMatthias Ringwald/* start address for the initialization values of the .data section.
38*6b8177c5SMatthias Ringwalddefined in linker script */
39*6b8177c5SMatthias Ringwald.word	_sidata
40*6b8177c5SMatthias Ringwald/* start address for the .data section. defined in linker script */
41*6b8177c5SMatthias Ringwald.word	_sdata
42*6b8177c5SMatthias Ringwald/* end address for the .data section. defined in linker script */
43*6b8177c5SMatthias Ringwald.word	_edata
44*6b8177c5SMatthias Ringwald/* start address for the .bss section. defined in linker script */
45*6b8177c5SMatthias Ringwald.word	_sbss
46*6b8177c5SMatthias Ringwald/* end address for the .bss section. defined in linker script */
47*6b8177c5SMatthias Ringwald.word	_ebss
48*6b8177c5SMatthias Ringwald
49*6b8177c5SMatthias Ringwald.equ  BootRAM,        0xF1E0F85F
50*6b8177c5SMatthias Ringwald/**
51*6b8177c5SMatthias Ringwald * @brief  This is the code that gets called when the processor first
52*6b8177c5SMatthias Ringwald *          starts execution following a reset event. Only the absolutely
53*6b8177c5SMatthias Ringwald *          necessary set is performed, after which the application
54*6b8177c5SMatthias Ringwald *          supplied main() routine is called.
55*6b8177c5SMatthias Ringwald * @param  None
56*6b8177c5SMatthias Ringwald * @retval : None
57*6b8177c5SMatthias Ringwald*/
58*6b8177c5SMatthias Ringwald
59*6b8177c5SMatthias Ringwald    .section	.text.Reset_Handler
60*6b8177c5SMatthias Ringwald	.weak	Reset_Handler
61*6b8177c5SMatthias Ringwald	.type	Reset_Handler, %function
62*6b8177c5SMatthias RingwaldReset_Handler:
63*6b8177c5SMatthias Ringwald  ldr   sp, =_estack    /* Set stack pointer */
64*6b8177c5SMatthias Ringwald
65*6b8177c5SMatthias Ringwald/* Copy the data segment initializers from flash to SRAM */
66*6b8177c5SMatthias Ringwald  movs	r1, #0
67*6b8177c5SMatthias Ringwald  b	LoopCopyDataInit
68*6b8177c5SMatthias Ringwald
69*6b8177c5SMatthias RingwaldCopyDataInit:
70*6b8177c5SMatthias Ringwald	ldr	r3, =_sidata
71*6b8177c5SMatthias Ringwald	ldr	r3, [r3, r1]
72*6b8177c5SMatthias Ringwald	str	r3, [r0, r1]
73*6b8177c5SMatthias Ringwald	adds	r1, r1, #4
74*6b8177c5SMatthias Ringwald
75*6b8177c5SMatthias RingwaldLoopCopyDataInit:
76*6b8177c5SMatthias Ringwald	ldr	r0, =_sdata
77*6b8177c5SMatthias Ringwald	ldr	r3, =_edata
78*6b8177c5SMatthias Ringwald	adds	r2, r0, r1
79*6b8177c5SMatthias Ringwald	cmp	r2, r3
80*6b8177c5SMatthias Ringwald	bcc	CopyDataInit
81*6b8177c5SMatthias Ringwald	ldr	r2, =_sbss
82*6b8177c5SMatthias Ringwald	b	LoopFillZerobss
83*6b8177c5SMatthias Ringwald/* Zero fill the bss segment. */
84*6b8177c5SMatthias RingwaldFillZerobss:
85*6b8177c5SMatthias Ringwald	movs	r3, #0
86*6b8177c5SMatthias Ringwald	str	r3, [r2], #4
87*6b8177c5SMatthias Ringwald
88*6b8177c5SMatthias RingwaldLoopFillZerobss:
89*6b8177c5SMatthias Ringwald	ldr	r3, = _ebss
90*6b8177c5SMatthias Ringwald	cmp	r2, r3
91*6b8177c5SMatthias Ringwald	bcc	FillZerobss
92*6b8177c5SMatthias Ringwald
93*6b8177c5SMatthias Ringwald/* Call the clock system intitialization function.*/
94*6b8177c5SMatthias Ringwald    bl  SystemInit
95*6b8177c5SMatthias Ringwald/* Call static constructors */
96*6b8177c5SMatthias Ringwald    bl __libc_init_array
97*6b8177c5SMatthias Ringwald/* Call the application's entry point.*/
98*6b8177c5SMatthias Ringwald	bl	main
99*6b8177c5SMatthias Ringwald
100*6b8177c5SMatthias RingwaldLoopForever:
101*6b8177c5SMatthias Ringwald    b LoopForever
102*6b8177c5SMatthias Ringwald
103*6b8177c5SMatthias Ringwald.size	Reset_Handler, .-Reset_Handler
104*6b8177c5SMatthias Ringwald
105*6b8177c5SMatthias Ringwald/**
106*6b8177c5SMatthias Ringwald * @brief  This is the code that gets called when the processor receives an
107*6b8177c5SMatthias Ringwald *         unexpected interrupt.  This simply enters an infinite loop, preserving
108*6b8177c5SMatthias Ringwald *         the system state for examination by a debugger.
109*6b8177c5SMatthias Ringwald *
110*6b8177c5SMatthias Ringwald * @param  None
111*6b8177c5SMatthias Ringwald * @retval : None
112*6b8177c5SMatthias Ringwald*/
113*6b8177c5SMatthias Ringwald    .section	.text.Default_Handler,"ax",%progbits
114*6b8177c5SMatthias RingwaldDefault_Handler:
115*6b8177c5SMatthias RingwaldInfinite_Loop:
116*6b8177c5SMatthias Ringwald	b	Infinite_Loop
117*6b8177c5SMatthias Ringwald	.size	Default_Handler, .-Default_Handler
118*6b8177c5SMatthias Ringwald/******************************************************************************
119*6b8177c5SMatthias Ringwald*
120*6b8177c5SMatthias Ringwald* The minimal vector table for a Cortex-M4.  Note that the proper constructs
121*6b8177c5SMatthias Ringwald* must be placed on this to ensure that it ends up at physical address
122*6b8177c5SMatthias Ringwald* 0x0000.0000.
123*6b8177c5SMatthias Ringwald*
124*6b8177c5SMatthias Ringwald******************************************************************************/
125*6b8177c5SMatthias Ringwald 	.section	.isr_vector,"a",%progbits
126*6b8177c5SMatthias Ringwald	.type	g_pfnVectors, %object
127*6b8177c5SMatthias Ringwald	.size	g_pfnVectors, .-g_pfnVectors
128*6b8177c5SMatthias Ringwald
129*6b8177c5SMatthias Ringwald
130*6b8177c5SMatthias Ringwaldg_pfnVectors:
131*6b8177c5SMatthias Ringwald	.word	_estack
132*6b8177c5SMatthias Ringwald	.word	Reset_Handler
133*6b8177c5SMatthias Ringwald	.word	NMI_Handler
134*6b8177c5SMatthias Ringwald	.word	HardFault_Handler
135*6b8177c5SMatthias Ringwald	.word	MemManage_Handler
136*6b8177c5SMatthias Ringwald	.word	BusFault_Handler
137*6b8177c5SMatthias Ringwald	.word	UsageFault_Handler
138*6b8177c5SMatthias Ringwald	.word	0
139*6b8177c5SMatthias Ringwald	.word	0
140*6b8177c5SMatthias Ringwald	.word	0
141*6b8177c5SMatthias Ringwald	.word	0
142*6b8177c5SMatthias Ringwald	.word	SVC_Handler
143*6b8177c5SMatthias Ringwald	.word	DebugMon_Handler
144*6b8177c5SMatthias Ringwald	.word	0
145*6b8177c5SMatthias Ringwald	.word	PendSV_Handler
146*6b8177c5SMatthias Ringwald	.word	SysTick_Handler
147*6b8177c5SMatthias Ringwald	.word	WWDG_IRQHandler
148*6b8177c5SMatthias Ringwald	.word	PVD_PVM_IRQHandler
149*6b8177c5SMatthias Ringwald	.word	TAMP_STAMP_IRQHandler
150*6b8177c5SMatthias Ringwald	.word	RTC_WKUP_IRQHandler
151*6b8177c5SMatthias Ringwald	.word	FLASH_IRQHandler
152*6b8177c5SMatthias Ringwald	.word	RCC_IRQHandler
153*6b8177c5SMatthias Ringwald	.word	EXTI0_IRQHandler
154*6b8177c5SMatthias Ringwald	.word	EXTI1_IRQHandler
155*6b8177c5SMatthias Ringwald	.word	EXTI2_IRQHandler
156*6b8177c5SMatthias Ringwald	.word	EXTI3_IRQHandler
157*6b8177c5SMatthias Ringwald	.word	EXTI4_IRQHandler
158*6b8177c5SMatthias Ringwald	.word	DMA1_Channel1_IRQHandler
159*6b8177c5SMatthias Ringwald	.word	DMA1_Channel2_IRQHandler
160*6b8177c5SMatthias Ringwald	.word	DMA1_Channel3_IRQHandler
161*6b8177c5SMatthias Ringwald	.word	DMA1_Channel4_IRQHandler
162*6b8177c5SMatthias Ringwald	.word	DMA1_Channel5_IRQHandler
163*6b8177c5SMatthias Ringwald	.word	DMA1_Channel6_IRQHandler
164*6b8177c5SMatthias Ringwald	.word	DMA1_Channel7_IRQHandler
165*6b8177c5SMatthias Ringwald	.word	ADC1_2_IRQHandler
166*6b8177c5SMatthias Ringwald	.word	CAN1_TX_IRQHandler
167*6b8177c5SMatthias Ringwald	.word	CAN1_RX0_IRQHandler
168*6b8177c5SMatthias Ringwald	.word	CAN1_RX1_IRQHandler
169*6b8177c5SMatthias Ringwald	.word	CAN1_SCE_IRQHandler
170*6b8177c5SMatthias Ringwald	.word	EXTI9_5_IRQHandler
171*6b8177c5SMatthias Ringwald	.word	TIM1_BRK_TIM15_IRQHandler
172*6b8177c5SMatthias Ringwald	.word	TIM1_UP_TIM16_IRQHandler
173*6b8177c5SMatthias Ringwald	.word	TIM1_TRG_COM_TIM17_IRQHandler
174*6b8177c5SMatthias Ringwald	.word	TIM1_CC_IRQHandler
175*6b8177c5SMatthias Ringwald	.word	TIM2_IRQHandler
176*6b8177c5SMatthias Ringwald	.word	TIM3_IRQHandler
177*6b8177c5SMatthias Ringwald	.word	TIM4_IRQHandler
178*6b8177c5SMatthias Ringwald	.word	I2C1_EV_IRQHandler
179*6b8177c5SMatthias Ringwald	.word	I2C1_ER_IRQHandler
180*6b8177c5SMatthias Ringwald	.word	I2C2_EV_IRQHandler
181*6b8177c5SMatthias Ringwald	.word	I2C2_ER_IRQHandler
182*6b8177c5SMatthias Ringwald	.word	SPI1_IRQHandler
183*6b8177c5SMatthias Ringwald	.word	SPI2_IRQHandler
184*6b8177c5SMatthias Ringwald	.word	USART1_IRQHandler
185*6b8177c5SMatthias Ringwald	.word	USART2_IRQHandler
186*6b8177c5SMatthias Ringwald	.word	USART3_IRQHandler
187*6b8177c5SMatthias Ringwald	.word	EXTI15_10_IRQHandler
188*6b8177c5SMatthias Ringwald	.word	RTC_Alarm_IRQHandler
189*6b8177c5SMatthias Ringwald	.word	DFSDM1_FLT3_IRQHandler
190*6b8177c5SMatthias Ringwald	.word	TIM8_BRK_IRQHandler
191*6b8177c5SMatthias Ringwald	.word	TIM8_UP_IRQHandler
192*6b8177c5SMatthias Ringwald	.word	TIM8_TRG_COM_IRQHandler
193*6b8177c5SMatthias Ringwald	.word	TIM8_CC_IRQHandler
194*6b8177c5SMatthias Ringwald	.word	ADC3_IRQHandler
195*6b8177c5SMatthias Ringwald	.word	FMC_IRQHandler
196*6b8177c5SMatthias Ringwald	.word	SDMMC1_IRQHandler
197*6b8177c5SMatthias Ringwald	.word	TIM5_IRQHandler
198*6b8177c5SMatthias Ringwald	.word	SPI3_IRQHandler
199*6b8177c5SMatthias Ringwald	.word	UART4_IRQHandler
200*6b8177c5SMatthias Ringwald	.word	UART5_IRQHandler
201*6b8177c5SMatthias Ringwald	.word	TIM6_DAC_IRQHandler
202*6b8177c5SMatthias Ringwald	.word	TIM7_IRQHandler
203*6b8177c5SMatthias Ringwald	.word	DMA2_Channel1_IRQHandler
204*6b8177c5SMatthias Ringwald	.word	DMA2_Channel2_IRQHandler
205*6b8177c5SMatthias Ringwald	.word	DMA2_Channel3_IRQHandler
206*6b8177c5SMatthias Ringwald	.word	DMA2_Channel4_IRQHandler
207*6b8177c5SMatthias Ringwald	.word	DMA2_Channel5_IRQHandler
208*6b8177c5SMatthias Ringwald	.word	DFSDM1_FLT0_IRQHandler
209*6b8177c5SMatthias Ringwald	.word	DFSDM1_FLT1_IRQHandler
210*6b8177c5SMatthias Ringwald	.word	DFSDM1_FLT2_IRQHandler
211*6b8177c5SMatthias Ringwald	.word	COMP_IRQHandler
212*6b8177c5SMatthias Ringwald	.word	LPTIM1_IRQHandler
213*6b8177c5SMatthias Ringwald	.word	LPTIM2_IRQHandler
214*6b8177c5SMatthias Ringwald	.word	OTG_FS_IRQHandler
215*6b8177c5SMatthias Ringwald	.word	DMA2_Channel6_IRQHandler
216*6b8177c5SMatthias Ringwald	.word	DMA2_Channel7_IRQHandler
217*6b8177c5SMatthias Ringwald	.word	LPUART1_IRQHandler
218*6b8177c5SMatthias Ringwald	.word	QUADSPI_IRQHandler
219*6b8177c5SMatthias Ringwald	.word	I2C3_EV_IRQHandler
220*6b8177c5SMatthias Ringwald	.word	I2C3_ER_IRQHandler
221*6b8177c5SMatthias Ringwald	.word	SAI1_IRQHandler
222*6b8177c5SMatthias Ringwald	.word	SAI2_IRQHandler
223*6b8177c5SMatthias Ringwald	.word	SWPMI1_IRQHandler
224*6b8177c5SMatthias Ringwald	.word	TSC_IRQHandler
225*6b8177c5SMatthias Ringwald	.word	LCD_IRQHandler
226*6b8177c5SMatthias Ringwald	.word 0
227*6b8177c5SMatthias Ringwald	.word	RNG_IRQHandler
228*6b8177c5SMatthias Ringwald	.word	FPU_IRQHandler
229*6b8177c5SMatthias Ringwald
230*6b8177c5SMatthias Ringwald
231*6b8177c5SMatthias Ringwald/*******************************************************************************
232*6b8177c5SMatthias Ringwald*
233*6b8177c5SMatthias Ringwald* Provide weak aliases for each Exception handler to the Default_Handler.
234*6b8177c5SMatthias Ringwald* As they are weak aliases, any function with the same name will override
235*6b8177c5SMatthias Ringwald* this definition.
236*6b8177c5SMatthias Ringwald*
237*6b8177c5SMatthias Ringwald*******************************************************************************/
238*6b8177c5SMatthias Ringwald
239*6b8177c5SMatthias Ringwald  .weak	NMI_Handler
240*6b8177c5SMatthias Ringwald	.thumb_set NMI_Handler,Default_Handler
241*6b8177c5SMatthias Ringwald
242*6b8177c5SMatthias Ringwald  .weak	HardFault_Handler
243*6b8177c5SMatthias Ringwald	.thumb_set HardFault_Handler,Default_Handler
244*6b8177c5SMatthias Ringwald
245*6b8177c5SMatthias Ringwald  .weak	MemManage_Handler
246*6b8177c5SMatthias Ringwald	.thumb_set MemManage_Handler,Default_Handler
247*6b8177c5SMatthias Ringwald
248*6b8177c5SMatthias Ringwald  .weak	BusFault_Handler
249*6b8177c5SMatthias Ringwald	.thumb_set BusFault_Handler,Default_Handler
250*6b8177c5SMatthias Ringwald
251*6b8177c5SMatthias Ringwald	.weak	UsageFault_Handler
252*6b8177c5SMatthias Ringwald	.thumb_set UsageFault_Handler,Default_Handler
253*6b8177c5SMatthias Ringwald
254*6b8177c5SMatthias Ringwald	.weak	SVC_Handler
255*6b8177c5SMatthias Ringwald	.thumb_set SVC_Handler,Default_Handler
256*6b8177c5SMatthias Ringwald
257*6b8177c5SMatthias Ringwald	.weak	DebugMon_Handler
258*6b8177c5SMatthias Ringwald	.thumb_set DebugMon_Handler,Default_Handler
259*6b8177c5SMatthias Ringwald
260*6b8177c5SMatthias Ringwald	.weak	PendSV_Handler
261*6b8177c5SMatthias Ringwald	.thumb_set PendSV_Handler,Default_Handler
262*6b8177c5SMatthias Ringwald
263*6b8177c5SMatthias Ringwald	.weak	SysTick_Handler
264*6b8177c5SMatthias Ringwald	.thumb_set SysTick_Handler,Default_Handler
265*6b8177c5SMatthias Ringwald
266*6b8177c5SMatthias Ringwald	.weak	WWDG_IRQHandler
267*6b8177c5SMatthias Ringwald	.thumb_set WWDG_IRQHandler,Default_Handler
268*6b8177c5SMatthias Ringwald
269*6b8177c5SMatthias Ringwald	.weak	PVD_PVM_IRQHandler
270*6b8177c5SMatthias Ringwald	.thumb_set PVD_PVM_IRQHandler,Default_Handler
271*6b8177c5SMatthias Ringwald
272*6b8177c5SMatthias Ringwald	.weak	TAMP_STAMP_IRQHandler
273*6b8177c5SMatthias Ringwald	.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
274*6b8177c5SMatthias Ringwald
275*6b8177c5SMatthias Ringwald	.weak	RTC_WKUP_IRQHandler
276*6b8177c5SMatthias Ringwald	.thumb_set RTC_WKUP_IRQHandler,Default_Handler
277*6b8177c5SMatthias Ringwald
278*6b8177c5SMatthias Ringwald	.weak	FLASH_IRQHandler
279*6b8177c5SMatthias Ringwald	.thumb_set FLASH_IRQHandler,Default_Handler
280*6b8177c5SMatthias Ringwald
281*6b8177c5SMatthias Ringwald	.weak	RCC_IRQHandler
282*6b8177c5SMatthias Ringwald	.thumb_set RCC_IRQHandler,Default_Handler
283*6b8177c5SMatthias Ringwald
284*6b8177c5SMatthias Ringwald	.weak	EXTI0_IRQHandler
285*6b8177c5SMatthias Ringwald	.thumb_set EXTI0_IRQHandler,Default_Handler
286*6b8177c5SMatthias Ringwald
287*6b8177c5SMatthias Ringwald	.weak	EXTI1_IRQHandler
288*6b8177c5SMatthias Ringwald	.thumb_set EXTI1_IRQHandler,Default_Handler
289*6b8177c5SMatthias Ringwald
290*6b8177c5SMatthias Ringwald	.weak	EXTI2_IRQHandler
291*6b8177c5SMatthias Ringwald	.thumb_set EXTI2_IRQHandler,Default_Handler
292*6b8177c5SMatthias Ringwald
293*6b8177c5SMatthias Ringwald	.weak	EXTI3_IRQHandler
294*6b8177c5SMatthias Ringwald	.thumb_set EXTI3_IRQHandler,Default_Handler
295*6b8177c5SMatthias Ringwald
296*6b8177c5SMatthias Ringwald	.weak	EXTI4_IRQHandler
297*6b8177c5SMatthias Ringwald	.thumb_set EXTI4_IRQHandler,Default_Handler
298*6b8177c5SMatthias Ringwald
299*6b8177c5SMatthias Ringwald	.weak	DMA1_Channel1_IRQHandler
300*6b8177c5SMatthias Ringwald	.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
301*6b8177c5SMatthias Ringwald
302*6b8177c5SMatthias Ringwald	.weak	DMA1_Channel2_IRQHandler
303*6b8177c5SMatthias Ringwald	.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
304*6b8177c5SMatthias Ringwald
305*6b8177c5SMatthias Ringwald	.weak	DMA1_Channel3_IRQHandler
306*6b8177c5SMatthias Ringwald	.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
307*6b8177c5SMatthias Ringwald
308*6b8177c5SMatthias Ringwald	.weak	DMA1_Channel4_IRQHandler
309*6b8177c5SMatthias Ringwald	.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
310*6b8177c5SMatthias Ringwald
311*6b8177c5SMatthias Ringwald	.weak	DMA1_Channel5_IRQHandler
312*6b8177c5SMatthias Ringwald	.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
313*6b8177c5SMatthias Ringwald
314*6b8177c5SMatthias Ringwald	.weak	DMA1_Channel6_IRQHandler
315*6b8177c5SMatthias Ringwald	.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
316*6b8177c5SMatthias Ringwald
317*6b8177c5SMatthias Ringwald	.weak	DMA1_Channel7_IRQHandler
318*6b8177c5SMatthias Ringwald	.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
319*6b8177c5SMatthias Ringwald
320*6b8177c5SMatthias Ringwald	.weak	ADC1_2_IRQHandler
321*6b8177c5SMatthias Ringwald	.thumb_set ADC1_2_IRQHandler,Default_Handler
322*6b8177c5SMatthias Ringwald
323*6b8177c5SMatthias Ringwald	.weak	CAN1_TX_IRQHandler
324*6b8177c5SMatthias Ringwald	.thumb_set CAN1_TX_IRQHandler,Default_Handler
325*6b8177c5SMatthias Ringwald
326*6b8177c5SMatthias Ringwald	.weak	CAN1_RX0_IRQHandler
327*6b8177c5SMatthias Ringwald	.thumb_set CAN1_RX0_IRQHandler,Default_Handler
328*6b8177c5SMatthias Ringwald
329*6b8177c5SMatthias Ringwald	.weak	CAN1_RX1_IRQHandler
330*6b8177c5SMatthias Ringwald	.thumb_set CAN1_RX1_IRQHandler,Default_Handler
331*6b8177c5SMatthias Ringwald
332*6b8177c5SMatthias Ringwald	.weak	CAN1_SCE_IRQHandler
333*6b8177c5SMatthias Ringwald	.thumb_set CAN1_SCE_IRQHandler,Default_Handler
334*6b8177c5SMatthias Ringwald
335*6b8177c5SMatthias Ringwald	.weak	EXTI9_5_IRQHandler
336*6b8177c5SMatthias Ringwald	.thumb_set EXTI9_5_IRQHandler,Default_Handler
337*6b8177c5SMatthias Ringwald
338*6b8177c5SMatthias Ringwald	.weak	TIM1_BRK_TIM15_IRQHandler
339*6b8177c5SMatthias Ringwald	.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
340*6b8177c5SMatthias Ringwald
341*6b8177c5SMatthias Ringwald	.weak	TIM1_UP_TIM16_IRQHandler
342*6b8177c5SMatthias Ringwald	.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
343*6b8177c5SMatthias Ringwald
344*6b8177c5SMatthias Ringwald	.weak	TIM1_TRG_COM_TIM17_IRQHandler
345*6b8177c5SMatthias Ringwald	.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
346*6b8177c5SMatthias Ringwald
347*6b8177c5SMatthias Ringwald	.weak	TIM1_CC_IRQHandler
348*6b8177c5SMatthias Ringwald	.thumb_set TIM1_CC_IRQHandler,Default_Handler
349*6b8177c5SMatthias Ringwald
350*6b8177c5SMatthias Ringwald	.weak	TIM2_IRQHandler
351*6b8177c5SMatthias Ringwald	.thumb_set TIM2_IRQHandler,Default_Handler
352*6b8177c5SMatthias Ringwald
353*6b8177c5SMatthias Ringwald	.weak	TIM3_IRQHandler
354*6b8177c5SMatthias Ringwald	.thumb_set TIM3_IRQHandler,Default_Handler
355*6b8177c5SMatthias Ringwald
356*6b8177c5SMatthias Ringwald	.weak	TIM4_IRQHandler
357*6b8177c5SMatthias Ringwald	.thumb_set TIM4_IRQHandler,Default_Handler
358*6b8177c5SMatthias Ringwald
359*6b8177c5SMatthias Ringwald	.weak	I2C1_EV_IRQHandler
360*6b8177c5SMatthias Ringwald	.thumb_set I2C1_EV_IRQHandler,Default_Handler
361*6b8177c5SMatthias Ringwald
362*6b8177c5SMatthias Ringwald	.weak	I2C1_ER_IRQHandler
363*6b8177c5SMatthias Ringwald	.thumb_set I2C1_ER_IRQHandler,Default_Handler
364*6b8177c5SMatthias Ringwald
365*6b8177c5SMatthias Ringwald	.weak	I2C2_EV_IRQHandler
366*6b8177c5SMatthias Ringwald	.thumb_set I2C2_EV_IRQHandler,Default_Handler
367*6b8177c5SMatthias Ringwald
368*6b8177c5SMatthias Ringwald	.weak	I2C2_ER_IRQHandler
369*6b8177c5SMatthias Ringwald	.thumb_set I2C2_ER_IRQHandler,Default_Handler
370*6b8177c5SMatthias Ringwald
371*6b8177c5SMatthias Ringwald	.weak	SPI1_IRQHandler
372*6b8177c5SMatthias Ringwald	.thumb_set SPI1_IRQHandler,Default_Handler
373*6b8177c5SMatthias Ringwald
374*6b8177c5SMatthias Ringwald	.weak	SPI2_IRQHandler
375*6b8177c5SMatthias Ringwald	.thumb_set SPI2_IRQHandler,Default_Handler
376*6b8177c5SMatthias Ringwald
377*6b8177c5SMatthias Ringwald	.weak	USART1_IRQHandler
378*6b8177c5SMatthias Ringwald	.thumb_set USART1_IRQHandler,Default_Handler
379*6b8177c5SMatthias Ringwald
380*6b8177c5SMatthias Ringwald	.weak	USART2_IRQHandler
381*6b8177c5SMatthias Ringwald	.thumb_set USART2_IRQHandler,Default_Handler
382*6b8177c5SMatthias Ringwald
383*6b8177c5SMatthias Ringwald	.weak	USART3_IRQHandler
384*6b8177c5SMatthias Ringwald	.thumb_set USART3_IRQHandler,Default_Handler
385*6b8177c5SMatthias Ringwald
386*6b8177c5SMatthias Ringwald	.weak	EXTI15_10_IRQHandler
387*6b8177c5SMatthias Ringwald	.thumb_set EXTI15_10_IRQHandler,Default_Handler
388*6b8177c5SMatthias Ringwald
389*6b8177c5SMatthias Ringwald	.weak	RTC_Alarm_IRQHandler
390*6b8177c5SMatthias Ringwald	.thumb_set RTC_Alarm_IRQHandler,Default_Handler
391*6b8177c5SMatthias Ringwald
392*6b8177c5SMatthias Ringwald	.weak	DFSDM1_FLT3_IRQHandler
393*6b8177c5SMatthias Ringwald	.thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
394*6b8177c5SMatthias Ringwald
395*6b8177c5SMatthias Ringwald	.weak	TIM8_BRK_IRQHandler
396*6b8177c5SMatthias Ringwald	.thumb_set TIM8_BRK_IRQHandler,Default_Handler
397*6b8177c5SMatthias Ringwald
398*6b8177c5SMatthias Ringwald	.weak	TIM8_UP_IRQHandler
399*6b8177c5SMatthias Ringwald	.thumb_set TIM8_UP_IRQHandler,Default_Handler
400*6b8177c5SMatthias Ringwald
401*6b8177c5SMatthias Ringwald	.weak	TIM8_TRG_COM_IRQHandler
402*6b8177c5SMatthias Ringwald	.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
403*6b8177c5SMatthias Ringwald
404*6b8177c5SMatthias Ringwald	.weak	TIM8_CC_IRQHandler
405*6b8177c5SMatthias Ringwald	.thumb_set TIM8_CC_IRQHandler,Default_Handler
406*6b8177c5SMatthias Ringwald
407*6b8177c5SMatthias Ringwald	.weak	ADC3_IRQHandler
408*6b8177c5SMatthias Ringwald	.thumb_set ADC3_IRQHandler,Default_Handler
409*6b8177c5SMatthias Ringwald
410*6b8177c5SMatthias Ringwald	.weak	FMC_IRQHandler
411*6b8177c5SMatthias Ringwald	.thumb_set FMC_IRQHandler,Default_Handler
412*6b8177c5SMatthias Ringwald
413*6b8177c5SMatthias Ringwald	.weak	SDMMC1_IRQHandler
414*6b8177c5SMatthias Ringwald	.thumb_set SDMMC1_IRQHandler,Default_Handler
415*6b8177c5SMatthias Ringwald
416*6b8177c5SMatthias Ringwald	.weak	TIM5_IRQHandler
417*6b8177c5SMatthias Ringwald	.thumb_set TIM5_IRQHandler,Default_Handler
418*6b8177c5SMatthias Ringwald
419*6b8177c5SMatthias Ringwald	.weak	SPI3_IRQHandler
420*6b8177c5SMatthias Ringwald	.thumb_set SPI3_IRQHandler,Default_Handler
421*6b8177c5SMatthias Ringwald
422*6b8177c5SMatthias Ringwald	.weak	UART4_IRQHandler
423*6b8177c5SMatthias Ringwald	.thumb_set UART4_IRQHandler,Default_Handler
424*6b8177c5SMatthias Ringwald
425*6b8177c5SMatthias Ringwald	.weak	UART5_IRQHandler
426*6b8177c5SMatthias Ringwald	.thumb_set UART5_IRQHandler,Default_Handler
427*6b8177c5SMatthias Ringwald
428*6b8177c5SMatthias Ringwald	.weak	TIM6_DAC_IRQHandler
429*6b8177c5SMatthias Ringwald	.thumb_set TIM6_DAC_IRQHandler,Default_Handler
430*6b8177c5SMatthias Ringwald
431*6b8177c5SMatthias Ringwald	.weak	TIM7_IRQHandler
432*6b8177c5SMatthias Ringwald	.thumb_set TIM7_IRQHandler,Default_Handler
433*6b8177c5SMatthias Ringwald
434*6b8177c5SMatthias Ringwald	.weak	DMA2_Channel1_IRQHandler
435*6b8177c5SMatthias Ringwald	.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
436*6b8177c5SMatthias Ringwald
437*6b8177c5SMatthias Ringwald	.weak	DMA2_Channel2_IRQHandler
438*6b8177c5SMatthias Ringwald	.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
439*6b8177c5SMatthias Ringwald
440*6b8177c5SMatthias Ringwald	.weak	DMA2_Channel3_IRQHandler
441*6b8177c5SMatthias Ringwald	.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
442*6b8177c5SMatthias Ringwald
443*6b8177c5SMatthias Ringwald	.weak	DMA2_Channel4_IRQHandler
444*6b8177c5SMatthias Ringwald	.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
445*6b8177c5SMatthias Ringwald
446*6b8177c5SMatthias Ringwald	.weak	DMA2_Channel5_IRQHandler
447*6b8177c5SMatthias Ringwald	.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
448*6b8177c5SMatthias Ringwald
449*6b8177c5SMatthias Ringwald	.weak	DFSDM1_FLT0_IRQHandler
450*6b8177c5SMatthias Ringwald	.thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
451*6b8177c5SMatthias Ringwald
452*6b8177c5SMatthias Ringwald	.weak	DFSDM1_FLT1_IRQHandler
453*6b8177c5SMatthias Ringwald	.thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
454*6b8177c5SMatthias Ringwald
455*6b8177c5SMatthias Ringwald	.weak	DFSDM1_FLT2_IRQHandler
456*6b8177c5SMatthias Ringwald	.thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
457*6b8177c5SMatthias Ringwald
458*6b8177c5SMatthias Ringwald	.weak	COMP_IRQHandler
459*6b8177c5SMatthias Ringwald	.thumb_set COMP_IRQHandler,Default_Handler
460*6b8177c5SMatthias Ringwald
461*6b8177c5SMatthias Ringwald	.weak	LPTIM1_IRQHandler
462*6b8177c5SMatthias Ringwald	.thumb_set LPTIM1_IRQHandler,Default_Handler
463*6b8177c5SMatthias Ringwald
464*6b8177c5SMatthias Ringwald	.weak	LPTIM2_IRQHandler
465*6b8177c5SMatthias Ringwald	.thumb_set LPTIM2_IRQHandler,Default_Handler
466*6b8177c5SMatthias Ringwald
467*6b8177c5SMatthias Ringwald	.weak	OTG_FS_IRQHandler
468*6b8177c5SMatthias Ringwald	.thumb_set OTG_FS_IRQHandler,Default_Handler
469*6b8177c5SMatthias Ringwald
470*6b8177c5SMatthias Ringwald	.weak	DMA2_Channel6_IRQHandler
471*6b8177c5SMatthias Ringwald	.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
472*6b8177c5SMatthias Ringwald
473*6b8177c5SMatthias Ringwald	.weak	DMA2_Channel7_IRQHandler
474*6b8177c5SMatthias Ringwald	.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
475*6b8177c5SMatthias Ringwald
476*6b8177c5SMatthias Ringwald	.weak	LPUART1_IRQHandler
477*6b8177c5SMatthias Ringwald	.thumb_set LPUART1_IRQHandler,Default_Handler
478*6b8177c5SMatthias Ringwald
479*6b8177c5SMatthias Ringwald	.weak	QUADSPI_IRQHandler
480*6b8177c5SMatthias Ringwald	.thumb_set QUADSPI_IRQHandler,Default_Handler
481*6b8177c5SMatthias Ringwald
482*6b8177c5SMatthias Ringwald	.weak	I2C3_EV_IRQHandler
483*6b8177c5SMatthias Ringwald	.thumb_set I2C3_EV_IRQHandler,Default_Handler
484*6b8177c5SMatthias Ringwald
485*6b8177c5SMatthias Ringwald	.weak	I2C3_ER_IRQHandler
486*6b8177c5SMatthias Ringwald	.thumb_set I2C3_ER_IRQHandler,Default_Handler
487*6b8177c5SMatthias Ringwald
488*6b8177c5SMatthias Ringwald	.weak	SAI1_IRQHandler
489*6b8177c5SMatthias Ringwald	.thumb_set SAI1_IRQHandler,Default_Handler
490*6b8177c5SMatthias Ringwald
491*6b8177c5SMatthias Ringwald	.weak	SAI2_IRQHandler
492*6b8177c5SMatthias Ringwald	.thumb_set SAI2_IRQHandler,Default_Handler
493*6b8177c5SMatthias Ringwald
494*6b8177c5SMatthias Ringwald	.weak	SWPMI1_IRQHandler
495*6b8177c5SMatthias Ringwald	.thumb_set SWPMI1_IRQHandler,Default_Handler
496*6b8177c5SMatthias Ringwald
497*6b8177c5SMatthias Ringwald	.weak	TSC_IRQHandler
498*6b8177c5SMatthias Ringwald	.thumb_set TSC_IRQHandler,Default_Handler
499*6b8177c5SMatthias Ringwald
500*6b8177c5SMatthias Ringwald	.weak	LCD_IRQHandler
501*6b8177c5SMatthias Ringwald	.thumb_set LCD_IRQHandler,Default_Handler
502*6b8177c5SMatthias Ringwald
503*6b8177c5SMatthias Ringwald	.weak	RNG_IRQHandler
504*6b8177c5SMatthias Ringwald	.thumb_set RNG_IRQHandler,Default_Handler
505*6b8177c5SMatthias Ringwald
506*6b8177c5SMatthias Ringwald	.weak	FPU_IRQHandler
507*6b8177c5SMatthias Ringwald	.thumb_set FPU_IRQHandler,Default_Handler
508*6b8177c5SMatthias Ringwald/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
509