1 /****************************************************************************** 2 * @file mpu_armv8.h 3 * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU 4 * @version V5.1.0 5 * @date 08. March 2019 6 ******************************************************************************/ 7 /* 8 * Copyright (c) 2017-2019 Arm Limited. All rights reserved. 9 * 10 * SPDX-License-Identifier: Apache-2.0 11 * 12 * Licensed under the Apache License, Version 2.0 (the License); you may 13 * not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 */ 24 25 #if defined ( __ICCARM__ ) 26 #pragma system_include /* treat file as system include file for MISRA check */ 27 #elif defined (__clang__) 28 #pragma clang system_header /* treat file as system include file */ 29 #endif 30 31 #ifndef ARM_MPU_ARMV8_H 32 #define ARM_MPU_ARMV8_H 33 34 /** \brief Attribute for device memory (outer only) */ 35 #define ARM_MPU_ATTR_DEVICE ( 0U ) 36 37 /** \brief Attribute for non-cacheable, normal memory */ 38 #define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) 39 40 /** \brief Attribute for normal memory (outer and inner) 41 * \param NT Non-Transient: Set to 1 for non-transient data. 42 * \param WB Write-Back: Set to 1 to use write-back update policy. 43 * \param RA Read Allocation: Set to 1 to use cache allocation on read miss. 44 * \param WA Write Allocation: Set to 1 to use cache allocation on write miss. 45 */ 46 #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ 47 (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) 48 49 /** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ 50 #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) 51 52 /** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ 53 #define ARM_MPU_ATTR_DEVICE_nGnRE (1U) 54 55 /** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ 56 #define ARM_MPU_ATTR_DEVICE_nGRE (2U) 57 58 /** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ 59 #define ARM_MPU_ATTR_DEVICE_GRE (3U) 60 61 /** \brief Memory Attribute 62 * \param O Outer memory attributes 63 * \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes 64 */ 65 #define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) 66 67 /** \brief Normal memory non-shareable */ 68 #define ARM_MPU_SH_NON (0U) 69 70 /** \brief Normal memory outer shareable */ 71 #define ARM_MPU_SH_OUTER (2U) 72 73 /** \brief Normal memory inner shareable */ 74 #define ARM_MPU_SH_INNER (3U) 75 76 /** \brief Memory access permissions 77 * \param RO Read-Only: Set to 1 for read-only memory. 78 * \param NP Non-Privileged: Set to 1 for non-privileged memory. 79 */ 80 #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) 81 82 /** \brief Region Base Address Register value 83 * \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. 84 * \param SH Defines the Shareability domain for this memory region. 85 * \param RO Read-Only: Set to 1 for a read-only memory region. 86 * \param NP Non-Privileged: Set to 1 for a non-privileged memory region. 87 * \oaram XN eXecute Never: Set to 1 for a non-executable memory region. 88 */ 89 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ 90 ((BASE & MPU_RBAR_BASE_Msk) | \ 91 ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ 92 ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ 93 ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) 94 95 /** \brief Region Limit Address Register value 96 * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. 97 * \param IDX The attribute index to be associated with this memory region. 98 */ 99 #define ARM_MPU_RLAR(LIMIT, IDX) \ 100 ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ 101 ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ 102 (MPU_RLAR_EN_Msk)) 103 104 #if defined(MPU_RLAR_PXN_Pos) 105 106 /** \brief Region Limit Address Register with PXN value 107 * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. 108 * \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. 109 * \param IDX The attribute index to be associated with this memory region. 110 */ 111 #define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ 112 ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ 113 ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ 114 ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ 115 (MPU_RLAR_EN_Msk)) 116 117 #endif 118 119 /** 120 * Struct for a single MPU Region 121 */ 122 typedef struct { 123 uint32_t RBAR; /*!< Region Base Address Register value */ 124 uint32_t RLAR; /*!< Region Limit Address Register value */ 125 } ARM_MPU_Region_t; 126 127 /** Enable the MPU. 128 * \param MPU_Control Default access permissions for unconfigured regions. 129 */ 130 __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) 131 { 132 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 133 #ifdef SCB_SHCSR_MEMFAULTENA_Msk 134 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 135 #endif 136 __DSB(); 137 __ISB(); 138 } 139 140 /** Disable the MPU. 141 */ 142 __STATIC_INLINE void ARM_MPU_Disable(void) 143 { 144 __DMB(); 145 #ifdef SCB_SHCSR_MEMFAULTENA_Msk 146 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 147 #endif 148 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; 149 } 150 151 #ifdef MPU_NS 152 /** Enable the Non-secure MPU. 153 * \param MPU_Control Default access permissions for unconfigured regions. 154 */ 155 __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) 156 { 157 MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 158 #ifdef SCB_SHCSR_MEMFAULTENA_Msk 159 SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 160 #endif 161 __DSB(); 162 __ISB(); 163 } 164 165 /** Disable the Non-secure MPU. 166 */ 167 __STATIC_INLINE void ARM_MPU_Disable_NS(void) 168 { 169 __DMB(); 170 #ifdef SCB_SHCSR_MEMFAULTENA_Msk 171 SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 172 #endif 173 MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; 174 } 175 #endif 176 177 /** Set the memory attribute encoding to the given MPU. 178 * \param mpu Pointer to the MPU to be configured. 179 * \param idx The attribute index to be set [0-7] 180 * \param attr The attribute value to be set. 181 */ 182 __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) 183 { 184 const uint8_t reg = idx / 4U; 185 const uint32_t pos = ((idx % 4U) * 8U); 186 const uint32_t mask = 0xFFU << pos; 187 188 if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { 189 return; // invalid index 190 } 191 192 mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); 193 } 194 195 /** Set the memory attribute encoding. 196 * \param idx The attribute index to be set [0-7] 197 * \param attr The attribute value to be set. 198 */ 199 __STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) 200 { 201 ARM_MPU_SetMemAttrEx(MPU, idx, attr); 202 } 203 204 #ifdef MPU_NS 205 /** Set the memory attribute encoding to the Non-secure MPU. 206 * \param idx The attribute index to be set [0-7] 207 * \param attr The attribute value to be set. 208 */ 209 __STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) 210 { 211 ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); 212 } 213 #endif 214 215 /** Clear and disable the given MPU region of the given MPU. 216 * \param mpu Pointer to MPU to be used. 217 * \param rnr Region number to be cleared. 218 */ 219 __STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) 220 { 221 mpu->RNR = rnr; 222 mpu->RLAR = 0U; 223 } 224 225 /** Clear and disable the given MPU region. 226 * \param rnr Region number to be cleared. 227 */ 228 __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) 229 { 230 ARM_MPU_ClrRegionEx(MPU, rnr); 231 } 232 233 #ifdef MPU_NS 234 /** Clear and disable the given Non-secure MPU region. 235 * \param rnr Region number to be cleared. 236 */ 237 __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) 238 { 239 ARM_MPU_ClrRegionEx(MPU_NS, rnr); 240 } 241 #endif 242 243 /** Configure the given MPU region of the given MPU. 244 * \param mpu Pointer to MPU to be used. 245 * \param rnr Region number to be configured. 246 * \param rbar Value for RBAR register. 247 * \param rlar Value for RLAR register. 248 */ 249 __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) 250 { 251 mpu->RNR = rnr; 252 mpu->RBAR = rbar; 253 mpu->RLAR = rlar; 254 } 255 256 /** Configure the given MPU region. 257 * \param rnr Region number to be configured. 258 * \param rbar Value for RBAR register. 259 * \param rlar Value for RLAR register. 260 */ 261 __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) 262 { 263 ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); 264 } 265 266 #ifdef MPU_NS 267 /** Configure the given Non-secure MPU region. 268 * \param rnr Region number to be configured. 269 * \param rbar Value for RBAR register. 270 * \param rlar Value for RLAR register. 271 */ 272 __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) 273 { 274 ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); 275 } 276 #endif 277 278 /** Memcopy with strictly ordered memory access, e.g. for register targets. 279 * \param dst Destination data is copied to. 280 * \param src Source data is copied from. 281 * \param len Amount of data words to be copied. 282 */ 283 __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) 284 { 285 uint32_t i; 286 for (i = 0U; i < len; ++i) 287 { 288 dst[i] = src[i]; 289 } 290 } 291 292 /** Load the given number of MPU regions from a table to the given MPU. 293 * \param mpu Pointer to the MPU registers to be used. 294 * \param rnr First region number to be configured. 295 * \param table Pointer to the MPU configuration table. 296 * \param cnt Amount of regions to be configured. 297 */ 298 __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 299 { 300 const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; 301 if (cnt == 1U) { 302 mpu->RNR = rnr; 303 ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); 304 } else { 305 uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); 306 uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; 307 308 mpu->RNR = rnrBase; 309 while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { 310 uint32_t c = MPU_TYPE_RALIASES - rnrOffset; 311 ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); 312 table += c; 313 cnt -= c; 314 rnrOffset = 0U; 315 rnrBase += MPU_TYPE_RALIASES; 316 mpu->RNR = rnrBase; 317 } 318 319 ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); 320 } 321 } 322 323 /** Load the given number of MPU regions from a table. 324 * \param rnr First region number to be configured. 325 * \param table Pointer to the MPU configuration table. 326 * \param cnt Amount of regions to be configured. 327 */ 328 __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 329 { 330 ARM_MPU_LoadEx(MPU, rnr, table, cnt); 331 } 332 333 #ifdef MPU_NS 334 /** Load the given number of MPU regions from a table to the Non-secure MPU. 335 * \param rnr First region number to be configured. 336 * \param table Pointer to the MPU configuration table. 337 * \param cnt Amount of regions to be configured. 338 */ 339 __STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 340 { 341 ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); 342 } 343 #endif 344 345 #endif 346 347