xref: /btstack/port/stm32-l451-miromico-sx1280/startup/startup_stm32l451xx.s (revision 2fd737d36a1de5d778cacc671d4b4d8c4f3fed82)
1*2fd737d3SMatthias Ringwald/**
2*2fd737d3SMatthias Ringwald  ******************************************************************************
3*2fd737d3SMatthias Ringwald  * @file      startup_stm32l451xx.s
4*2fd737d3SMatthias Ringwald  * @author    MCD Application Team
5*2fd737d3SMatthias Ringwald  * @brief     STM32L451xx devices vector table for GCC toolchain.
6*2fd737d3SMatthias Ringwald  *            This module performs:
7*2fd737d3SMatthias Ringwald  *                - Set the initial SP
8*2fd737d3SMatthias Ringwald  *                - Set the initial PC == Reset_Handler,
9*2fd737d3SMatthias Ringwald  *                - Set the vector table entries with the exceptions ISR address,
10*2fd737d3SMatthias Ringwald  *                - Configure the clock system
11*2fd737d3SMatthias Ringwald  *                - Branches to main in the C library (which eventually
12*2fd737d3SMatthias Ringwald  *                  calls main()).
13*2fd737d3SMatthias Ringwald  *            After Reset the Cortex-M4 processor is in Thread mode,
14*2fd737d3SMatthias Ringwald  *            priority is Privileged, and the Stack is set to Main.
15*2fd737d3SMatthias Ringwald  ******************************************************************************
16*2fd737d3SMatthias Ringwald  * @attention
17*2fd737d3SMatthias Ringwald  *
18*2fd737d3SMatthias Ringwald  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
19*2fd737d3SMatthias Ringwald  * All rights reserved.</center></h2>
20*2fd737d3SMatthias Ringwald  *
21*2fd737d3SMatthias Ringwald  * This software component is licensed by ST under BSD 3-Clause license,
22*2fd737d3SMatthias Ringwald  * the "License"; You may not use this file except in compliance with the
23*2fd737d3SMatthias Ringwald  * License. You may obtain a copy of the License at:
24*2fd737d3SMatthias Ringwald  *                        opensource.org/licenses/BSD-3-Clause
25*2fd737d3SMatthias Ringwald  *
26*2fd737d3SMatthias Ringwald  ******************************************************************************
27*2fd737d3SMatthias Ringwald  */
28*2fd737d3SMatthias Ringwald
29*2fd737d3SMatthias Ringwald  .syntax unified
30*2fd737d3SMatthias Ringwald	.cpu cortex-m4
31*2fd737d3SMatthias Ringwald	.fpu softvfp
32*2fd737d3SMatthias Ringwald	.thumb
33*2fd737d3SMatthias Ringwald
34*2fd737d3SMatthias Ringwald.global	g_pfnVectors
35*2fd737d3SMatthias Ringwald.global	Default_Handler
36*2fd737d3SMatthias Ringwald
37*2fd737d3SMatthias Ringwald/* start address for the initialization values of the .data section.
38*2fd737d3SMatthias Ringwalddefined in linker script */
39*2fd737d3SMatthias Ringwald.word	_sidata
40*2fd737d3SMatthias Ringwald/* start address for the .data section. defined in linker script */
41*2fd737d3SMatthias Ringwald.word	_sdata
42*2fd737d3SMatthias Ringwald/* end address for the .data section. defined in linker script */
43*2fd737d3SMatthias Ringwald.word	_edata
44*2fd737d3SMatthias Ringwald/* start address for the .bss section. defined in linker script */
45*2fd737d3SMatthias Ringwald.word	_sbss
46*2fd737d3SMatthias Ringwald/* end address for the .bss section. defined in linker script */
47*2fd737d3SMatthias Ringwald.word	_ebss
48*2fd737d3SMatthias Ringwald
49*2fd737d3SMatthias Ringwald.equ  BootRAM,        0xF1E0F85F
50*2fd737d3SMatthias Ringwald/**
51*2fd737d3SMatthias Ringwald * @brief  This is the code that gets called when the processor first
52*2fd737d3SMatthias Ringwald *          starts execution following a reset event. Only the absolutely
53*2fd737d3SMatthias Ringwald *          necessary set is performed, after which the application
54*2fd737d3SMatthias Ringwald *          supplied main() routine is called.
55*2fd737d3SMatthias Ringwald * @param  None
56*2fd737d3SMatthias Ringwald * @retval : None
57*2fd737d3SMatthias Ringwald*/
58*2fd737d3SMatthias Ringwald
59*2fd737d3SMatthias Ringwald    .section	.text.Reset_Handler
60*2fd737d3SMatthias Ringwald	.weak	Reset_Handler
61*2fd737d3SMatthias Ringwald	.type	Reset_Handler, %function
62*2fd737d3SMatthias RingwaldReset_Handler:
63*2fd737d3SMatthias Ringwald  ldr   sp, =_estack    /* Set stack pointer */
64*2fd737d3SMatthias Ringwald
65*2fd737d3SMatthias Ringwald/* Copy the data segment initializers from flash to SRAM */
66*2fd737d3SMatthias Ringwald  movs	r1, #0
67*2fd737d3SMatthias Ringwald  b	LoopCopyDataInit
68*2fd737d3SMatthias Ringwald
69*2fd737d3SMatthias RingwaldCopyDataInit:
70*2fd737d3SMatthias Ringwald	ldr	r3, =_sidata
71*2fd737d3SMatthias Ringwald	ldr	r3, [r3, r1]
72*2fd737d3SMatthias Ringwald	str	r3, [r0, r1]
73*2fd737d3SMatthias Ringwald	adds	r1, r1, #4
74*2fd737d3SMatthias Ringwald
75*2fd737d3SMatthias RingwaldLoopCopyDataInit:
76*2fd737d3SMatthias Ringwald	ldr	r0, =_sdata
77*2fd737d3SMatthias Ringwald	ldr	r3, =_edata
78*2fd737d3SMatthias Ringwald	adds	r2, r0, r1
79*2fd737d3SMatthias Ringwald	cmp	r2, r3
80*2fd737d3SMatthias Ringwald	bcc	CopyDataInit
81*2fd737d3SMatthias Ringwald	ldr	r2, =_sbss
82*2fd737d3SMatthias Ringwald	b	LoopFillZerobss
83*2fd737d3SMatthias Ringwald/* Zero fill the bss segment. */
84*2fd737d3SMatthias RingwaldFillZerobss:
85*2fd737d3SMatthias Ringwald	movs	r3, #0
86*2fd737d3SMatthias Ringwald	str	r3, [r2], #4
87*2fd737d3SMatthias Ringwald
88*2fd737d3SMatthias RingwaldLoopFillZerobss:
89*2fd737d3SMatthias Ringwald	ldr	r3, = _ebss
90*2fd737d3SMatthias Ringwald	cmp	r2, r3
91*2fd737d3SMatthias Ringwald	bcc	FillZerobss
92*2fd737d3SMatthias Ringwald
93*2fd737d3SMatthias Ringwald/* Call the clock system intitialization function.*/
94*2fd737d3SMatthias Ringwald    bl  SystemInit
95*2fd737d3SMatthias Ringwald/* Call static constructors */
96*2fd737d3SMatthias Ringwald    bl __libc_init_array
97*2fd737d3SMatthias Ringwald/* Call the application's entry point.*/
98*2fd737d3SMatthias Ringwald	bl	main
99*2fd737d3SMatthias Ringwald
100*2fd737d3SMatthias RingwaldLoopForever:
101*2fd737d3SMatthias Ringwald    b LoopForever
102*2fd737d3SMatthias Ringwald
103*2fd737d3SMatthias Ringwald.size	Reset_Handler, .-Reset_Handler
104*2fd737d3SMatthias Ringwald
105*2fd737d3SMatthias Ringwald/**
106*2fd737d3SMatthias Ringwald * @brief  This is the code that gets called when the processor receives an
107*2fd737d3SMatthias Ringwald *         unexpected interrupt.  This simply enters an infinite loop, preserving
108*2fd737d3SMatthias Ringwald *         the system state for examination by a debugger.
109*2fd737d3SMatthias Ringwald *
110*2fd737d3SMatthias Ringwald * @param  None
111*2fd737d3SMatthias Ringwald * @retval : None
112*2fd737d3SMatthias Ringwald*/
113*2fd737d3SMatthias Ringwald    .section	.text.Default_Handler,"ax",%progbits
114*2fd737d3SMatthias RingwaldDefault_Handler:
115*2fd737d3SMatthias RingwaldInfinite_Loop:
116*2fd737d3SMatthias Ringwald	b	Infinite_Loop
117*2fd737d3SMatthias Ringwald	.size	Default_Handler, .-Default_Handler
118*2fd737d3SMatthias Ringwald/******************************************************************************
119*2fd737d3SMatthias Ringwald*
120*2fd737d3SMatthias Ringwald* The minimal vector table for a Cortex-M4.  Note that the proper constructs
121*2fd737d3SMatthias Ringwald* must be placed on this to ensure that it ends up at physical address
122*2fd737d3SMatthias Ringwald* 0x0000.0000.
123*2fd737d3SMatthias Ringwald*
124*2fd737d3SMatthias Ringwald******************************************************************************/
125*2fd737d3SMatthias Ringwald 	.section	.isr_vector,"a",%progbits
126*2fd737d3SMatthias Ringwald	.type	g_pfnVectors, %object
127*2fd737d3SMatthias Ringwald	.size	g_pfnVectors, .-g_pfnVectors
128*2fd737d3SMatthias Ringwald
129*2fd737d3SMatthias Ringwald
130*2fd737d3SMatthias Ringwaldg_pfnVectors:
131*2fd737d3SMatthias Ringwald	.word	_estack
132*2fd737d3SMatthias Ringwald	.word	Reset_Handler
133*2fd737d3SMatthias Ringwald	.word	NMI_Handler
134*2fd737d3SMatthias Ringwald	.word	HardFault_Handler
135*2fd737d3SMatthias Ringwald	.word	MemManage_Handler
136*2fd737d3SMatthias Ringwald	.word	BusFault_Handler
137*2fd737d3SMatthias Ringwald	.word	UsageFault_Handler
138*2fd737d3SMatthias Ringwald	.word	0
139*2fd737d3SMatthias Ringwald	.word	0
140*2fd737d3SMatthias Ringwald	.word	0
141*2fd737d3SMatthias Ringwald	.word	0
142*2fd737d3SMatthias Ringwald	.word	SVC_Handler
143*2fd737d3SMatthias Ringwald	.word	DebugMon_Handler
144*2fd737d3SMatthias Ringwald	.word	0
145*2fd737d3SMatthias Ringwald	.word	PendSV_Handler
146*2fd737d3SMatthias Ringwald	.word	SysTick_Handler
147*2fd737d3SMatthias Ringwald	.word	WWDG_IRQHandler
148*2fd737d3SMatthias Ringwald	.word	PVD_PVM_IRQHandler
149*2fd737d3SMatthias Ringwald	.word	TAMP_STAMP_IRQHandler
150*2fd737d3SMatthias Ringwald	.word	RTC_WKUP_IRQHandler
151*2fd737d3SMatthias Ringwald	.word	FLASH_IRQHandler
152*2fd737d3SMatthias Ringwald	.word	RCC_IRQHandler
153*2fd737d3SMatthias Ringwald	.word	EXTI0_IRQHandler
154*2fd737d3SMatthias Ringwald	.word	EXTI1_IRQHandler
155*2fd737d3SMatthias Ringwald	.word	EXTI2_IRQHandler
156*2fd737d3SMatthias Ringwald	.word	EXTI3_IRQHandler
157*2fd737d3SMatthias Ringwald	.word	EXTI4_IRQHandler
158*2fd737d3SMatthias Ringwald	.word	DMA1_Channel1_IRQHandler
159*2fd737d3SMatthias Ringwald	.word	DMA1_Channel2_IRQHandler
160*2fd737d3SMatthias Ringwald	.word	DMA1_Channel3_IRQHandler
161*2fd737d3SMatthias Ringwald	.word	DMA1_Channel4_IRQHandler
162*2fd737d3SMatthias Ringwald	.word	DMA1_Channel5_IRQHandler
163*2fd737d3SMatthias Ringwald	.word	DMA1_Channel6_IRQHandler
164*2fd737d3SMatthias Ringwald	.word	DMA1_Channel7_IRQHandler
165*2fd737d3SMatthias Ringwald	.word	ADC1_IRQHandler
166*2fd737d3SMatthias Ringwald	.word	CAN1_TX_IRQHandler
167*2fd737d3SMatthias Ringwald	.word	CAN1_RX0_IRQHandler
168*2fd737d3SMatthias Ringwald	.word	CAN1_RX1_IRQHandler
169*2fd737d3SMatthias Ringwald	.word	CAN1_SCE_IRQHandler
170*2fd737d3SMatthias Ringwald	.word	EXTI9_5_IRQHandler
171*2fd737d3SMatthias Ringwald	.word	TIM1_BRK_TIM15_IRQHandler
172*2fd737d3SMatthias Ringwald	.word	TIM1_UP_TIM16_IRQHandler
173*2fd737d3SMatthias Ringwald	.word	TIM1_TRG_COM_IRQHandler
174*2fd737d3SMatthias Ringwald	.word	TIM1_CC_IRQHandler
175*2fd737d3SMatthias Ringwald	.word	TIM2_IRQHandler
176*2fd737d3SMatthias Ringwald	.word	TIM3_IRQHandler
177*2fd737d3SMatthias Ringwald	.word	0
178*2fd737d3SMatthias Ringwald	.word	I2C1_EV_IRQHandler
179*2fd737d3SMatthias Ringwald	.word	I2C1_ER_IRQHandler
180*2fd737d3SMatthias Ringwald	.word	I2C2_EV_IRQHandler
181*2fd737d3SMatthias Ringwald	.word	I2C2_ER_IRQHandler
182*2fd737d3SMatthias Ringwald	.word	SPI1_IRQHandler
183*2fd737d3SMatthias Ringwald	.word	SPI2_IRQHandler
184*2fd737d3SMatthias Ringwald	.word	USART1_IRQHandler
185*2fd737d3SMatthias Ringwald	.word	USART2_IRQHandler
186*2fd737d3SMatthias Ringwald	.word	USART3_IRQHandler
187*2fd737d3SMatthias Ringwald	.word	EXTI15_10_IRQHandler
188*2fd737d3SMatthias Ringwald	.word	RTC_Alarm_IRQHandler
189*2fd737d3SMatthias Ringwald	.word	0
190*2fd737d3SMatthias Ringwald	.word	0
191*2fd737d3SMatthias Ringwald	.word	0
192*2fd737d3SMatthias Ringwald	.word	0
193*2fd737d3SMatthias Ringwald	.word	0
194*2fd737d3SMatthias Ringwald	.word	0
195*2fd737d3SMatthias Ringwald	.word	0
196*2fd737d3SMatthias Ringwald	.word	SDMMC1_IRQHandler
197*2fd737d3SMatthias Ringwald	.word	0
198*2fd737d3SMatthias Ringwald	.word	SPI3_IRQHandler
199*2fd737d3SMatthias Ringwald	.word	UART4_IRQHandler
200*2fd737d3SMatthias Ringwald	.word	0
201*2fd737d3SMatthias Ringwald	.word	TIM6_DAC_IRQHandler
202*2fd737d3SMatthias Ringwald	.word	0
203*2fd737d3SMatthias Ringwald	.word	DMA2_Channel1_IRQHandler
204*2fd737d3SMatthias Ringwald	.word	DMA2_Channel2_IRQHandler
205*2fd737d3SMatthias Ringwald	.word	DMA2_Channel3_IRQHandler
206*2fd737d3SMatthias Ringwald	.word	DMA2_Channel4_IRQHandler
207*2fd737d3SMatthias Ringwald	.word	DMA2_Channel5_IRQHandler
208*2fd737d3SMatthias Ringwald	.word	DFSDM1_FLT0_IRQHandler
209*2fd737d3SMatthias Ringwald	.word	DFSDM1_FLT1_IRQHandler
210*2fd737d3SMatthias Ringwald	.word	0
211*2fd737d3SMatthias Ringwald	.word	COMP_IRQHandler
212*2fd737d3SMatthias Ringwald	.word	LPTIM1_IRQHandler
213*2fd737d3SMatthias Ringwald	.word	LPTIM2_IRQHandler
214*2fd737d3SMatthias Ringwald	.word	0
215*2fd737d3SMatthias Ringwald	.word	DMA2_Channel6_IRQHandler
216*2fd737d3SMatthias Ringwald	.word	DMA2_Channel7_IRQHandler
217*2fd737d3SMatthias Ringwald	.word	LPUART1_IRQHandler
218*2fd737d3SMatthias Ringwald	.word	QUADSPI_IRQHandler
219*2fd737d3SMatthias Ringwald	.word	I2C3_EV_IRQHandler
220*2fd737d3SMatthias Ringwald	.word	I2C3_ER_IRQHandler
221*2fd737d3SMatthias Ringwald	.word	SAI1_IRQHandler
222*2fd737d3SMatthias Ringwald	.word	0
223*2fd737d3SMatthias Ringwald	.word	0
224*2fd737d3SMatthias Ringwald	.word	TSC_IRQHandler
225*2fd737d3SMatthias Ringwald	.word	0
226*2fd737d3SMatthias Ringwald	.word	0
227*2fd737d3SMatthias Ringwald	.word	RNG_IRQHandler
228*2fd737d3SMatthias Ringwald	.word	FPU_IRQHandler
229*2fd737d3SMatthias Ringwald	.word	CRS_IRQHandler
230*2fd737d3SMatthias Ringwald	.word	I2C4_EV_IRQHandler
231*2fd737d3SMatthias Ringwald	.word	I2C4_ER_IRQHandler
232*2fd737d3SMatthias Ringwald
233*2fd737d3SMatthias Ringwald
234*2fd737d3SMatthias Ringwald/*******************************************************************************
235*2fd737d3SMatthias Ringwald*
236*2fd737d3SMatthias Ringwald* Provide weak aliases for each Exception handler to the Default_Handler.
237*2fd737d3SMatthias Ringwald* As they are weak aliases, any function with the same name will override
238*2fd737d3SMatthias Ringwald* this definition.
239*2fd737d3SMatthias Ringwald*
240*2fd737d3SMatthias Ringwald*******************************************************************************/
241*2fd737d3SMatthias Ringwald
242*2fd737d3SMatthias Ringwald  .weak	NMI_Handler
243*2fd737d3SMatthias Ringwald	.thumb_set NMI_Handler,Default_Handler
244*2fd737d3SMatthias Ringwald
245*2fd737d3SMatthias Ringwald  .weak	HardFault_Handler
246*2fd737d3SMatthias Ringwald	.thumb_set HardFault_Handler,Default_Handler
247*2fd737d3SMatthias Ringwald
248*2fd737d3SMatthias Ringwald  .weak	MemManage_Handler
249*2fd737d3SMatthias Ringwald	.thumb_set MemManage_Handler,Default_Handler
250*2fd737d3SMatthias Ringwald
251*2fd737d3SMatthias Ringwald  .weak	BusFault_Handler
252*2fd737d3SMatthias Ringwald	.thumb_set BusFault_Handler,Default_Handler
253*2fd737d3SMatthias Ringwald
254*2fd737d3SMatthias Ringwald	.weak	UsageFault_Handler
255*2fd737d3SMatthias Ringwald	.thumb_set UsageFault_Handler,Default_Handler
256*2fd737d3SMatthias Ringwald
257*2fd737d3SMatthias Ringwald	.weak	SVC_Handler
258*2fd737d3SMatthias Ringwald	.thumb_set SVC_Handler,Default_Handler
259*2fd737d3SMatthias Ringwald
260*2fd737d3SMatthias Ringwald	.weak	DebugMon_Handler
261*2fd737d3SMatthias Ringwald	.thumb_set DebugMon_Handler,Default_Handler
262*2fd737d3SMatthias Ringwald
263*2fd737d3SMatthias Ringwald	.weak	PendSV_Handler
264*2fd737d3SMatthias Ringwald	.thumb_set PendSV_Handler,Default_Handler
265*2fd737d3SMatthias Ringwald
266*2fd737d3SMatthias Ringwald	.weak	SysTick_Handler
267*2fd737d3SMatthias Ringwald	.thumb_set SysTick_Handler,Default_Handler
268*2fd737d3SMatthias Ringwald
269*2fd737d3SMatthias Ringwald	.weak	WWDG_IRQHandler
270*2fd737d3SMatthias Ringwald	.thumb_set WWDG_IRQHandler,Default_Handler
271*2fd737d3SMatthias Ringwald
272*2fd737d3SMatthias Ringwald	.weak	PVD_PVM_IRQHandler
273*2fd737d3SMatthias Ringwald	.thumb_set PVD_PVM_IRQHandler,Default_Handler
274*2fd737d3SMatthias Ringwald
275*2fd737d3SMatthias Ringwald	.weak	TAMP_STAMP_IRQHandler
276*2fd737d3SMatthias Ringwald	.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
277*2fd737d3SMatthias Ringwald
278*2fd737d3SMatthias Ringwald	.weak	RTC_WKUP_IRQHandler
279*2fd737d3SMatthias Ringwald	.thumb_set RTC_WKUP_IRQHandler,Default_Handler
280*2fd737d3SMatthias Ringwald
281*2fd737d3SMatthias Ringwald	.weak	FLASH_IRQHandler
282*2fd737d3SMatthias Ringwald	.thumb_set FLASH_IRQHandler,Default_Handler
283*2fd737d3SMatthias Ringwald
284*2fd737d3SMatthias Ringwald	.weak	RCC_IRQHandler
285*2fd737d3SMatthias Ringwald	.thumb_set RCC_IRQHandler,Default_Handler
286*2fd737d3SMatthias Ringwald
287*2fd737d3SMatthias Ringwald	.weak	EXTI0_IRQHandler
288*2fd737d3SMatthias Ringwald	.thumb_set EXTI0_IRQHandler,Default_Handler
289*2fd737d3SMatthias Ringwald
290*2fd737d3SMatthias Ringwald	.weak	EXTI1_IRQHandler
291*2fd737d3SMatthias Ringwald	.thumb_set EXTI1_IRQHandler,Default_Handler
292*2fd737d3SMatthias Ringwald
293*2fd737d3SMatthias Ringwald	.weak	EXTI2_IRQHandler
294*2fd737d3SMatthias Ringwald	.thumb_set EXTI2_IRQHandler,Default_Handler
295*2fd737d3SMatthias Ringwald
296*2fd737d3SMatthias Ringwald	.weak	EXTI3_IRQHandler
297*2fd737d3SMatthias Ringwald	.thumb_set EXTI3_IRQHandler,Default_Handler
298*2fd737d3SMatthias Ringwald
299*2fd737d3SMatthias Ringwald	.weak	EXTI4_IRQHandler
300*2fd737d3SMatthias Ringwald	.thumb_set EXTI4_IRQHandler,Default_Handler
301*2fd737d3SMatthias Ringwald
302*2fd737d3SMatthias Ringwald	.weak	DMA1_Channel1_IRQHandler
303*2fd737d3SMatthias Ringwald	.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
304*2fd737d3SMatthias Ringwald
305*2fd737d3SMatthias Ringwald	.weak	DMA1_Channel2_IRQHandler
306*2fd737d3SMatthias Ringwald	.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
307*2fd737d3SMatthias Ringwald
308*2fd737d3SMatthias Ringwald	.weak	DMA1_Channel3_IRQHandler
309*2fd737d3SMatthias Ringwald	.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
310*2fd737d3SMatthias Ringwald
311*2fd737d3SMatthias Ringwald	.weak	DMA1_Channel4_IRQHandler
312*2fd737d3SMatthias Ringwald	.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
313*2fd737d3SMatthias Ringwald
314*2fd737d3SMatthias Ringwald	.weak	DMA1_Channel5_IRQHandler
315*2fd737d3SMatthias Ringwald	.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
316*2fd737d3SMatthias Ringwald
317*2fd737d3SMatthias Ringwald	.weak	DMA1_Channel6_IRQHandler
318*2fd737d3SMatthias Ringwald	.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
319*2fd737d3SMatthias Ringwald
320*2fd737d3SMatthias Ringwald	.weak	DMA1_Channel7_IRQHandler
321*2fd737d3SMatthias Ringwald	.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
322*2fd737d3SMatthias Ringwald
323*2fd737d3SMatthias Ringwald	.weak	ADC1_IRQHandler
324*2fd737d3SMatthias Ringwald	.thumb_set ADC1_IRQHandler,Default_Handler
325*2fd737d3SMatthias Ringwald
326*2fd737d3SMatthias Ringwald	.weak	CAN1_TX_IRQHandler
327*2fd737d3SMatthias Ringwald	.thumb_set CAN1_TX_IRQHandler,Default_Handler
328*2fd737d3SMatthias Ringwald
329*2fd737d3SMatthias Ringwald	.weak	CAN1_RX0_IRQHandler
330*2fd737d3SMatthias Ringwald	.thumb_set CAN1_RX0_IRQHandler,Default_Handler
331*2fd737d3SMatthias Ringwald
332*2fd737d3SMatthias Ringwald	.weak	CAN1_RX1_IRQHandler
333*2fd737d3SMatthias Ringwald	.thumb_set CAN1_RX1_IRQHandler,Default_Handler
334*2fd737d3SMatthias Ringwald
335*2fd737d3SMatthias Ringwald	.weak	CAN1_SCE_IRQHandler
336*2fd737d3SMatthias Ringwald	.thumb_set CAN1_SCE_IRQHandler,Default_Handler
337*2fd737d3SMatthias Ringwald
338*2fd737d3SMatthias Ringwald	.weak	EXTI9_5_IRQHandler
339*2fd737d3SMatthias Ringwald	.thumb_set EXTI9_5_IRQHandler,Default_Handler
340*2fd737d3SMatthias Ringwald
341*2fd737d3SMatthias Ringwald	.weak	TIM1_BRK_TIM15_IRQHandler
342*2fd737d3SMatthias Ringwald	.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
343*2fd737d3SMatthias Ringwald
344*2fd737d3SMatthias Ringwald	.weak	TIM1_UP_TIM16_IRQHandler
345*2fd737d3SMatthias Ringwald	.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
346*2fd737d3SMatthias Ringwald
347*2fd737d3SMatthias Ringwald	.weak	TIM1_TRG_COM_IRQHandler
348*2fd737d3SMatthias Ringwald	.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
349*2fd737d3SMatthias Ringwald
350*2fd737d3SMatthias Ringwald	.weak	TIM1_CC_IRQHandler
351*2fd737d3SMatthias Ringwald	.thumb_set TIM1_CC_IRQHandler,Default_Handler
352*2fd737d3SMatthias Ringwald
353*2fd737d3SMatthias Ringwald	.weak	TIM2_IRQHandler
354*2fd737d3SMatthias Ringwald	.thumb_set TIM2_IRQHandler,Default_Handler
355*2fd737d3SMatthias Ringwald
356*2fd737d3SMatthias Ringwald	.weak	TIM3_IRQHandler
357*2fd737d3SMatthias Ringwald	.thumb_set TIM3_IRQHandler,Default_Handler
358*2fd737d3SMatthias Ringwald
359*2fd737d3SMatthias Ringwald	.weak	I2C1_EV_IRQHandler
360*2fd737d3SMatthias Ringwald	.thumb_set I2C1_EV_IRQHandler,Default_Handler
361*2fd737d3SMatthias Ringwald
362*2fd737d3SMatthias Ringwald	.weak	I2C1_ER_IRQHandler
363*2fd737d3SMatthias Ringwald	.thumb_set I2C1_ER_IRQHandler,Default_Handler
364*2fd737d3SMatthias Ringwald
365*2fd737d3SMatthias Ringwald	.weak	I2C2_EV_IRQHandler
366*2fd737d3SMatthias Ringwald	.thumb_set I2C2_EV_IRQHandler,Default_Handler
367*2fd737d3SMatthias Ringwald
368*2fd737d3SMatthias Ringwald	.weak	I2C2_ER_IRQHandler
369*2fd737d3SMatthias Ringwald	.thumb_set I2C2_ER_IRQHandler,Default_Handler
370*2fd737d3SMatthias Ringwald
371*2fd737d3SMatthias Ringwald	.weak	SPI1_IRQHandler
372*2fd737d3SMatthias Ringwald	.thumb_set SPI1_IRQHandler,Default_Handler
373*2fd737d3SMatthias Ringwald
374*2fd737d3SMatthias Ringwald	.weak	SPI2_IRQHandler
375*2fd737d3SMatthias Ringwald	.thumb_set SPI2_IRQHandler,Default_Handler
376*2fd737d3SMatthias Ringwald
377*2fd737d3SMatthias Ringwald	.weak	USART1_IRQHandler
378*2fd737d3SMatthias Ringwald	.thumb_set USART1_IRQHandler,Default_Handler
379*2fd737d3SMatthias Ringwald
380*2fd737d3SMatthias Ringwald	.weak	USART2_IRQHandler
381*2fd737d3SMatthias Ringwald	.thumb_set USART2_IRQHandler,Default_Handler
382*2fd737d3SMatthias Ringwald
383*2fd737d3SMatthias Ringwald	.weak	USART3_IRQHandler
384*2fd737d3SMatthias Ringwald	.thumb_set USART3_IRQHandler,Default_Handler
385*2fd737d3SMatthias Ringwald
386*2fd737d3SMatthias Ringwald	.weak	EXTI15_10_IRQHandler
387*2fd737d3SMatthias Ringwald	.thumb_set EXTI15_10_IRQHandler,Default_Handler
388*2fd737d3SMatthias Ringwald
389*2fd737d3SMatthias Ringwald	.weak	RTC_Alarm_IRQHandler
390*2fd737d3SMatthias Ringwald	.thumb_set RTC_Alarm_IRQHandler,Default_Handler
391*2fd737d3SMatthias Ringwald
392*2fd737d3SMatthias Ringwald	.weak	SDMMC1_IRQHandler
393*2fd737d3SMatthias Ringwald	.thumb_set SDMMC1_IRQHandler,Default_Handler
394*2fd737d3SMatthias Ringwald
395*2fd737d3SMatthias Ringwald	.weak	SPI3_IRQHandler
396*2fd737d3SMatthias Ringwald	.thumb_set SPI3_IRQHandler,Default_Handler
397*2fd737d3SMatthias Ringwald
398*2fd737d3SMatthias Ringwald	.weak	UART4_IRQHandler
399*2fd737d3SMatthias Ringwald	.thumb_set UART4_IRQHandler,Default_Handler
400*2fd737d3SMatthias Ringwald
401*2fd737d3SMatthias Ringwald	.weak	TIM6_DAC_IRQHandler
402*2fd737d3SMatthias Ringwald	.thumb_set TIM6_DAC_IRQHandler,Default_Handler
403*2fd737d3SMatthias Ringwald
404*2fd737d3SMatthias Ringwald	.weak	DMA2_Channel1_IRQHandler
405*2fd737d3SMatthias Ringwald	.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
406*2fd737d3SMatthias Ringwald
407*2fd737d3SMatthias Ringwald	.weak	DMA2_Channel2_IRQHandler
408*2fd737d3SMatthias Ringwald	.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
409*2fd737d3SMatthias Ringwald
410*2fd737d3SMatthias Ringwald	.weak	DMA2_Channel3_IRQHandler
411*2fd737d3SMatthias Ringwald	.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
412*2fd737d3SMatthias Ringwald
413*2fd737d3SMatthias Ringwald	.weak	DMA2_Channel4_IRQHandler
414*2fd737d3SMatthias Ringwald	.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
415*2fd737d3SMatthias Ringwald
416*2fd737d3SMatthias Ringwald	.weak	DMA2_Channel5_IRQHandler
417*2fd737d3SMatthias Ringwald	.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
418*2fd737d3SMatthias Ringwald
419*2fd737d3SMatthias Ringwald	.weak	DFSDM1_FLT0_IRQHandler
420*2fd737d3SMatthias Ringwald	.thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
421*2fd737d3SMatthias Ringwald
422*2fd737d3SMatthias Ringwald	.weak	DFSDM1_FLT1_IRQHandler
423*2fd737d3SMatthias Ringwald	.thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
424*2fd737d3SMatthias Ringwald
425*2fd737d3SMatthias Ringwald	.weak	COMP_IRQHandler
426*2fd737d3SMatthias Ringwald	.thumb_set COMP_IRQHandler,Default_Handler
427*2fd737d3SMatthias Ringwald
428*2fd737d3SMatthias Ringwald	.weak	LPTIM1_IRQHandler
429*2fd737d3SMatthias Ringwald	.thumb_set LPTIM1_IRQHandler,Default_Handler
430*2fd737d3SMatthias Ringwald
431*2fd737d3SMatthias Ringwald	.weak	LPTIM2_IRQHandler
432*2fd737d3SMatthias Ringwald	.thumb_set LPTIM2_IRQHandler,Default_Handler
433*2fd737d3SMatthias Ringwald
434*2fd737d3SMatthias Ringwald	.weak	DMA2_Channel6_IRQHandler
435*2fd737d3SMatthias Ringwald	.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
436*2fd737d3SMatthias Ringwald
437*2fd737d3SMatthias Ringwald	.weak	DMA2_Channel7_IRQHandler
438*2fd737d3SMatthias Ringwald	.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
439*2fd737d3SMatthias Ringwald
440*2fd737d3SMatthias Ringwald	.weak	LPUART1_IRQHandler
441*2fd737d3SMatthias Ringwald	.thumb_set LPUART1_IRQHandler,Default_Handler
442*2fd737d3SMatthias Ringwald
443*2fd737d3SMatthias Ringwald	.weak	QUADSPI_IRQHandler
444*2fd737d3SMatthias Ringwald	.thumb_set QUADSPI_IRQHandler,Default_Handler
445*2fd737d3SMatthias Ringwald
446*2fd737d3SMatthias Ringwald	.weak	I2C3_EV_IRQHandler
447*2fd737d3SMatthias Ringwald	.thumb_set I2C3_EV_IRQHandler,Default_Handler
448*2fd737d3SMatthias Ringwald
449*2fd737d3SMatthias Ringwald	.weak	I2C3_ER_IRQHandler
450*2fd737d3SMatthias Ringwald	.thumb_set I2C3_ER_IRQHandler,Default_Handler
451*2fd737d3SMatthias Ringwald
452*2fd737d3SMatthias Ringwald	.weak	SAI1_IRQHandler
453*2fd737d3SMatthias Ringwald	.thumb_set SAI1_IRQHandler,Default_Handler
454*2fd737d3SMatthias Ringwald
455*2fd737d3SMatthias Ringwald	.weak	TSC_IRQHandler
456*2fd737d3SMatthias Ringwald	.thumb_set TSC_IRQHandler,Default_Handler
457*2fd737d3SMatthias Ringwald
458*2fd737d3SMatthias Ringwald	.weak	RNG_IRQHandler
459*2fd737d3SMatthias Ringwald	.thumb_set RNG_IRQHandler,Default_Handler
460*2fd737d3SMatthias Ringwald
461*2fd737d3SMatthias Ringwald	.weak	FPU_IRQHandler
462*2fd737d3SMatthias Ringwald	.thumb_set FPU_IRQHandler,Default_Handler
463*2fd737d3SMatthias Ringwald
464*2fd737d3SMatthias Ringwald	.weak	CRS_IRQHandler
465*2fd737d3SMatthias Ringwald	.thumb_set CRS_IRQHandler,Default_Handler
466*2fd737d3SMatthias Ringwald
467*2fd737d3SMatthias Ringwald	.weak	I2C4_EV_IRQHandler
468*2fd737d3SMatthias Ringwald	.thumb_set I2C4_EV_IRQHandler,Default_Handler
469*2fd737d3SMatthias Ringwald
470*2fd737d3SMatthias Ringwald	.weak	I2C4_ER_IRQHandler
471*2fd737d3SMatthias Ringwald	.thumb_set I2C4_ER_IRQHandler,Default_Handler
472*2fd737d3SMatthias Ringwald/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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