xref: /btstack/port/stm32-f4discovery-usb/startup_stm32f407xx.s (revision a8f7f3fcbcd51f8d2e92aca076b6a9f812db358c)
1*a8f7f3fcSMatthias Ringwald/**
2*a8f7f3fcSMatthias Ringwald  ******************************************************************************
3*a8f7f3fcSMatthias Ringwald  * @file      startup_stm32f407xx.s
4*a8f7f3fcSMatthias Ringwald  * @author    MCD Application Team
5*a8f7f3fcSMatthias Ringwald  * @brief     STM32F407xx Devices vector table for GCC based toolchains.
6*a8f7f3fcSMatthias Ringwald  *            This module performs:
7*a8f7f3fcSMatthias Ringwald  *                - Set the initial SP
8*a8f7f3fcSMatthias Ringwald  *                - Set the initial PC == Reset_Handler,
9*a8f7f3fcSMatthias Ringwald  *                - Set the vector table entries with the exceptions ISR address
10*a8f7f3fcSMatthias Ringwald  *                - Branches to main in the C library (which eventually
11*a8f7f3fcSMatthias Ringwald  *                  calls main()).
12*a8f7f3fcSMatthias Ringwald  *            After Reset the Cortex-M4 processor is in Thread mode,
13*a8f7f3fcSMatthias Ringwald  *            priority is Privileged, and the Stack is set to Main.
14*a8f7f3fcSMatthias Ringwald  ******************************************************************************
15*a8f7f3fcSMatthias Ringwald  * @attention
16*a8f7f3fcSMatthias Ringwald  *
17*a8f7f3fcSMatthias Ringwald  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
18*a8f7f3fcSMatthias Ringwald  * All rights reserved.</center></h2>
19*a8f7f3fcSMatthias Ringwald  *
20*a8f7f3fcSMatthias Ringwald  * This software component is licensed by ST under BSD 3-Clause license,
21*a8f7f3fcSMatthias Ringwald  * the "License"; You may not use this file except in compliance with the
22*a8f7f3fcSMatthias Ringwald  * License. You may obtain a copy of the License at:
23*a8f7f3fcSMatthias Ringwald  *                        opensource.org/licenses/BSD-3-Clause
24*a8f7f3fcSMatthias Ringwald  *
25*a8f7f3fcSMatthias Ringwald  ******************************************************************************
26*a8f7f3fcSMatthias Ringwald  */
27*a8f7f3fcSMatthias Ringwald
28*a8f7f3fcSMatthias Ringwald  .syntax unified
29*a8f7f3fcSMatthias Ringwald  .cpu cortex-m4
30*a8f7f3fcSMatthias Ringwald  .fpu softvfp
31*a8f7f3fcSMatthias Ringwald  .thumb
32*a8f7f3fcSMatthias Ringwald
33*a8f7f3fcSMatthias Ringwald.global  g_pfnVectors
34*a8f7f3fcSMatthias Ringwald.global  Default_Handler
35*a8f7f3fcSMatthias Ringwald
36*a8f7f3fcSMatthias Ringwald/* start address for the initialization values of the .data section.
37*a8f7f3fcSMatthias Ringwalddefined in linker script */
38*a8f7f3fcSMatthias Ringwald.word  _sidata
39*a8f7f3fcSMatthias Ringwald/* start address for the .data section. defined in linker script */
40*a8f7f3fcSMatthias Ringwald.word  _sdata
41*a8f7f3fcSMatthias Ringwald/* end address for the .data section. defined in linker script */
42*a8f7f3fcSMatthias Ringwald.word  _edata
43*a8f7f3fcSMatthias Ringwald/* start address for the .bss section. defined in linker script */
44*a8f7f3fcSMatthias Ringwald.word  _sbss
45*a8f7f3fcSMatthias Ringwald/* end address for the .bss section. defined in linker script */
46*a8f7f3fcSMatthias Ringwald.word  _ebss
47*a8f7f3fcSMatthias Ringwald/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
48*a8f7f3fcSMatthias Ringwald
49*a8f7f3fcSMatthias Ringwald/**
50*a8f7f3fcSMatthias Ringwald * @brief  This is the code that gets called when the processor first
51*a8f7f3fcSMatthias Ringwald *          starts execution following a reset event. Only the absolutely
52*a8f7f3fcSMatthias Ringwald *          necessary set is performed, after which the application
53*a8f7f3fcSMatthias Ringwald *          supplied main() routine is called.
54*a8f7f3fcSMatthias Ringwald * @param  None
55*a8f7f3fcSMatthias Ringwald * @retval : None
56*a8f7f3fcSMatthias Ringwald*/
57*a8f7f3fcSMatthias Ringwald
58*a8f7f3fcSMatthias Ringwald    .section  .text.Reset_Handler
59*a8f7f3fcSMatthias Ringwald  .weak  Reset_Handler
60*a8f7f3fcSMatthias Ringwald  .type  Reset_Handler, %function
61*a8f7f3fcSMatthias RingwaldReset_Handler:
62*a8f7f3fcSMatthias Ringwald  ldr   sp, =_estack     /* set stack pointer */
63*a8f7f3fcSMatthias Ringwald
64*a8f7f3fcSMatthias Ringwald/* Copy the data segment initializers from flash to SRAM */
65*a8f7f3fcSMatthias Ringwald  movs  r1, #0
66*a8f7f3fcSMatthias Ringwald  b  LoopCopyDataInit
67*a8f7f3fcSMatthias Ringwald
68*a8f7f3fcSMatthias RingwaldCopyDataInit:
69*a8f7f3fcSMatthias Ringwald  ldr  r3, =_sidata
70*a8f7f3fcSMatthias Ringwald  ldr  r3, [r3, r1]
71*a8f7f3fcSMatthias Ringwald  str  r3, [r0, r1]
72*a8f7f3fcSMatthias Ringwald  adds  r1, r1, #4
73*a8f7f3fcSMatthias Ringwald
74*a8f7f3fcSMatthias RingwaldLoopCopyDataInit:
75*a8f7f3fcSMatthias Ringwald  ldr  r0, =_sdata
76*a8f7f3fcSMatthias Ringwald  ldr  r3, =_edata
77*a8f7f3fcSMatthias Ringwald  adds  r2, r0, r1
78*a8f7f3fcSMatthias Ringwald  cmp  r2, r3
79*a8f7f3fcSMatthias Ringwald  bcc  CopyDataInit
80*a8f7f3fcSMatthias Ringwald  ldr  r2, =_sbss
81*a8f7f3fcSMatthias Ringwald  b  LoopFillZerobss
82*a8f7f3fcSMatthias Ringwald/* Zero fill the bss segment. */
83*a8f7f3fcSMatthias RingwaldFillZerobss:
84*a8f7f3fcSMatthias Ringwald  movs  r3, #0
85*a8f7f3fcSMatthias Ringwald  str  r3, [r2], #4
86*a8f7f3fcSMatthias Ringwald
87*a8f7f3fcSMatthias RingwaldLoopFillZerobss:
88*a8f7f3fcSMatthias Ringwald  ldr  r3, = _ebss
89*a8f7f3fcSMatthias Ringwald  cmp  r2, r3
90*a8f7f3fcSMatthias Ringwald  bcc  FillZerobss
91*a8f7f3fcSMatthias Ringwald
92*a8f7f3fcSMatthias Ringwald/* Call the clock system intitialization function.*/
93*a8f7f3fcSMatthias Ringwald  bl  SystemInit
94*a8f7f3fcSMatthias Ringwald/* Call static constructors */
95*a8f7f3fcSMatthias Ringwald    bl __libc_init_array
96*a8f7f3fcSMatthias Ringwald/* Call the application's entry point.*/
97*a8f7f3fcSMatthias Ringwald  bl  main
98*a8f7f3fcSMatthias Ringwald  bx  lr
99*a8f7f3fcSMatthias Ringwald.size  Reset_Handler, .-Reset_Handler
100*a8f7f3fcSMatthias Ringwald
101*a8f7f3fcSMatthias Ringwald/**
102*a8f7f3fcSMatthias Ringwald * @brief  This is the code that gets called when the processor receives an
103*a8f7f3fcSMatthias Ringwald *         unexpected interrupt.  This simply enters an infinite loop, preserving
104*a8f7f3fcSMatthias Ringwald *         the system state for examination by a debugger.
105*a8f7f3fcSMatthias Ringwald * @param  None
106*a8f7f3fcSMatthias Ringwald * @retval None
107*a8f7f3fcSMatthias Ringwald*/
108*a8f7f3fcSMatthias Ringwald    .section  .text.Default_Handler,"ax",%progbits
109*a8f7f3fcSMatthias RingwaldDefault_Handler:
110*a8f7f3fcSMatthias RingwaldInfinite_Loop:
111*a8f7f3fcSMatthias Ringwald  b  Infinite_Loop
112*a8f7f3fcSMatthias Ringwald  .size  Default_Handler, .-Default_Handler
113*a8f7f3fcSMatthias Ringwald/******************************************************************************
114*a8f7f3fcSMatthias Ringwald*
115*a8f7f3fcSMatthias Ringwald* The minimal vector table for a Cortex M3. Note that the proper constructs
116*a8f7f3fcSMatthias Ringwald* must be placed on this to ensure that it ends up at physical address
117*a8f7f3fcSMatthias Ringwald* 0x0000.0000.
118*a8f7f3fcSMatthias Ringwald*
119*a8f7f3fcSMatthias Ringwald*******************************************************************************/
120*a8f7f3fcSMatthias Ringwald   .section  .isr_vector,"a",%progbits
121*a8f7f3fcSMatthias Ringwald  .type  g_pfnVectors, %object
122*a8f7f3fcSMatthias Ringwald  .size  g_pfnVectors, .-g_pfnVectors
123*a8f7f3fcSMatthias Ringwald
124*a8f7f3fcSMatthias Ringwald
125*a8f7f3fcSMatthias Ringwaldg_pfnVectors:
126*a8f7f3fcSMatthias Ringwald  .word  _estack
127*a8f7f3fcSMatthias Ringwald  .word  Reset_Handler
128*a8f7f3fcSMatthias Ringwald  .word  NMI_Handler
129*a8f7f3fcSMatthias Ringwald  .word  HardFault_Handler
130*a8f7f3fcSMatthias Ringwald  .word  MemManage_Handler
131*a8f7f3fcSMatthias Ringwald  .word  BusFault_Handler
132*a8f7f3fcSMatthias Ringwald  .word  UsageFault_Handler
133*a8f7f3fcSMatthias Ringwald  .word  0
134*a8f7f3fcSMatthias Ringwald  .word  0
135*a8f7f3fcSMatthias Ringwald  .word  0
136*a8f7f3fcSMatthias Ringwald  .word  0
137*a8f7f3fcSMatthias Ringwald  .word  SVC_Handler
138*a8f7f3fcSMatthias Ringwald  .word  DebugMon_Handler
139*a8f7f3fcSMatthias Ringwald  .word  0
140*a8f7f3fcSMatthias Ringwald  .word  PendSV_Handler
141*a8f7f3fcSMatthias Ringwald  .word  SysTick_Handler
142*a8f7f3fcSMatthias Ringwald
143*a8f7f3fcSMatthias Ringwald  /* External Interrupts */
144*a8f7f3fcSMatthias Ringwald  .word     WWDG_IRQHandler                   /* Window WatchDog              */
145*a8f7f3fcSMatthias Ringwald  .word     PVD_IRQHandler                    /* PVD through EXTI Line detection */
146*a8f7f3fcSMatthias Ringwald  .word     TAMP_STAMP_IRQHandler             /* Tamper and TimeStamps through the EXTI line */
147*a8f7f3fcSMatthias Ringwald  .word     RTC_WKUP_IRQHandler               /* RTC Wakeup through the EXTI line */
148*a8f7f3fcSMatthias Ringwald  .word     FLASH_IRQHandler                  /* FLASH                        */
149*a8f7f3fcSMatthias Ringwald  .word     RCC_IRQHandler                    /* RCC                          */
150*a8f7f3fcSMatthias Ringwald  .word     EXTI0_IRQHandler                  /* EXTI Line0                   */
151*a8f7f3fcSMatthias Ringwald  .word     EXTI1_IRQHandler                  /* EXTI Line1                   */
152*a8f7f3fcSMatthias Ringwald  .word     EXTI2_IRQHandler                  /* EXTI Line2                   */
153*a8f7f3fcSMatthias Ringwald  .word     EXTI3_IRQHandler                  /* EXTI Line3                   */
154*a8f7f3fcSMatthias Ringwald  .word     EXTI4_IRQHandler                  /* EXTI Line4                   */
155*a8f7f3fcSMatthias Ringwald  .word     DMA1_Stream0_IRQHandler           /* DMA1 Stream 0                */
156*a8f7f3fcSMatthias Ringwald  .word     DMA1_Stream1_IRQHandler           /* DMA1 Stream 1                */
157*a8f7f3fcSMatthias Ringwald  .word     DMA1_Stream2_IRQHandler           /* DMA1 Stream 2                */
158*a8f7f3fcSMatthias Ringwald  .word     DMA1_Stream3_IRQHandler           /* DMA1 Stream 3                */
159*a8f7f3fcSMatthias Ringwald  .word     DMA1_Stream4_IRQHandler           /* DMA1 Stream 4                */
160*a8f7f3fcSMatthias Ringwald  .word     DMA1_Stream5_IRQHandler           /* DMA1 Stream 5                */
161*a8f7f3fcSMatthias Ringwald  .word     DMA1_Stream6_IRQHandler           /* DMA1 Stream 6                */
162*a8f7f3fcSMatthias Ringwald  .word     ADC_IRQHandler                    /* ADC1, ADC2 and ADC3s         */
163*a8f7f3fcSMatthias Ringwald  .word     CAN1_TX_IRQHandler                /* CAN1 TX                      */
164*a8f7f3fcSMatthias Ringwald  .word     CAN1_RX0_IRQHandler               /* CAN1 RX0                     */
165*a8f7f3fcSMatthias Ringwald  .word     CAN1_RX1_IRQHandler               /* CAN1 RX1                     */
166*a8f7f3fcSMatthias Ringwald  .word     CAN1_SCE_IRQHandler               /* CAN1 SCE                     */
167*a8f7f3fcSMatthias Ringwald  .word     EXTI9_5_IRQHandler                /* External Line[9:5]s          */
168*a8f7f3fcSMatthias Ringwald  .word     TIM1_BRK_TIM9_IRQHandler          /* TIM1 Break and TIM9          */
169*a8f7f3fcSMatthias Ringwald  .word     TIM1_UP_TIM10_IRQHandler          /* TIM1 Update and TIM10        */
170*a8f7f3fcSMatthias Ringwald  .word     TIM1_TRG_COM_TIM11_IRQHandler     /* TIM1 Trigger and Commutation and TIM11 */
171*a8f7f3fcSMatthias Ringwald  .word     TIM1_CC_IRQHandler                /* TIM1 Capture Compare         */
172*a8f7f3fcSMatthias Ringwald  .word     TIM2_IRQHandler                   /* TIM2                         */
173*a8f7f3fcSMatthias Ringwald  .word     TIM3_IRQHandler                   /* TIM3                         */
174*a8f7f3fcSMatthias Ringwald  .word     TIM4_IRQHandler                   /* TIM4                         */
175*a8f7f3fcSMatthias Ringwald  .word     I2C1_EV_IRQHandler                /* I2C1 Event                   */
176*a8f7f3fcSMatthias Ringwald  .word     I2C1_ER_IRQHandler                /* I2C1 Error                   */
177*a8f7f3fcSMatthias Ringwald  .word     I2C2_EV_IRQHandler                /* I2C2 Event                   */
178*a8f7f3fcSMatthias Ringwald  .word     I2C2_ER_IRQHandler                /* I2C2 Error                   */
179*a8f7f3fcSMatthias Ringwald  .word     SPI1_IRQHandler                   /* SPI1                         */
180*a8f7f3fcSMatthias Ringwald  .word     SPI2_IRQHandler                   /* SPI2                         */
181*a8f7f3fcSMatthias Ringwald  .word     USART1_IRQHandler                 /* USART1                       */
182*a8f7f3fcSMatthias Ringwald  .word     USART2_IRQHandler                 /* USART2                       */
183*a8f7f3fcSMatthias Ringwald  .word     USART3_IRQHandler                 /* USART3                       */
184*a8f7f3fcSMatthias Ringwald  .word     EXTI15_10_IRQHandler              /* External Line[15:10]s        */
185*a8f7f3fcSMatthias Ringwald  .word     RTC_Alarm_IRQHandler              /* RTC Alarm (A and B) through EXTI Line */
186*a8f7f3fcSMatthias Ringwald  .word     OTG_FS_WKUP_IRQHandler            /* USB OTG FS Wakeup through EXTI line */
187*a8f7f3fcSMatthias Ringwald  .word     TIM8_BRK_TIM12_IRQHandler         /* TIM8 Break and TIM12         */
188*a8f7f3fcSMatthias Ringwald  .word     TIM8_UP_TIM13_IRQHandler          /* TIM8 Update and TIM13        */
189*a8f7f3fcSMatthias Ringwald  .word     TIM8_TRG_COM_TIM14_IRQHandler     /* TIM8 Trigger and Commutation and TIM14 */
190*a8f7f3fcSMatthias Ringwald  .word     TIM8_CC_IRQHandler                /* TIM8 Capture Compare         */
191*a8f7f3fcSMatthias Ringwald  .word     DMA1_Stream7_IRQHandler           /* DMA1 Stream7                 */
192*a8f7f3fcSMatthias Ringwald  .word     FSMC_IRQHandler                   /* FSMC                         */
193*a8f7f3fcSMatthias Ringwald  .word     SDIO_IRQHandler                   /* SDIO                         */
194*a8f7f3fcSMatthias Ringwald  .word     TIM5_IRQHandler                   /* TIM5                         */
195*a8f7f3fcSMatthias Ringwald  .word     SPI3_IRQHandler                   /* SPI3                         */
196*a8f7f3fcSMatthias Ringwald  .word     UART4_IRQHandler                  /* UART4                        */
197*a8f7f3fcSMatthias Ringwald  .word     UART5_IRQHandler                  /* UART5                        */
198*a8f7f3fcSMatthias Ringwald  .word     TIM6_DAC_IRQHandler               /* TIM6 and DAC1&2 underrun errors */
199*a8f7f3fcSMatthias Ringwald  .word     TIM7_IRQHandler                   /* TIM7                         */
200*a8f7f3fcSMatthias Ringwald  .word     DMA2_Stream0_IRQHandler           /* DMA2 Stream 0                */
201*a8f7f3fcSMatthias Ringwald  .word     DMA2_Stream1_IRQHandler           /* DMA2 Stream 1                */
202*a8f7f3fcSMatthias Ringwald  .word     DMA2_Stream2_IRQHandler           /* DMA2 Stream 2                */
203*a8f7f3fcSMatthias Ringwald  .word     DMA2_Stream3_IRQHandler           /* DMA2 Stream 3                */
204*a8f7f3fcSMatthias Ringwald  .word     DMA2_Stream4_IRQHandler           /* DMA2 Stream 4                */
205*a8f7f3fcSMatthias Ringwald  .word     ETH_IRQHandler                    /* Ethernet                     */
206*a8f7f3fcSMatthias Ringwald  .word     ETH_WKUP_IRQHandler               /* Ethernet Wakeup through EXTI line */
207*a8f7f3fcSMatthias Ringwald  .word     CAN2_TX_IRQHandler                /* CAN2 TX                      */
208*a8f7f3fcSMatthias Ringwald  .word     CAN2_RX0_IRQHandler               /* CAN2 RX0                     */
209*a8f7f3fcSMatthias Ringwald  .word     CAN2_RX1_IRQHandler               /* CAN2 RX1                     */
210*a8f7f3fcSMatthias Ringwald  .word     CAN2_SCE_IRQHandler               /* CAN2 SCE                     */
211*a8f7f3fcSMatthias Ringwald  .word     OTG_FS_IRQHandler                 /* USB OTG FS                   */
212*a8f7f3fcSMatthias Ringwald  .word     DMA2_Stream5_IRQHandler           /* DMA2 Stream 5                */
213*a8f7f3fcSMatthias Ringwald  .word     DMA2_Stream6_IRQHandler           /* DMA2 Stream 6                */
214*a8f7f3fcSMatthias Ringwald  .word     DMA2_Stream7_IRQHandler           /* DMA2 Stream 7                */
215*a8f7f3fcSMatthias Ringwald  .word     USART6_IRQHandler                 /* USART6                       */
216*a8f7f3fcSMatthias Ringwald  .word     I2C3_EV_IRQHandler                /* I2C3 event                   */
217*a8f7f3fcSMatthias Ringwald  .word     I2C3_ER_IRQHandler                /* I2C3 error                   */
218*a8f7f3fcSMatthias Ringwald  .word     OTG_HS_EP1_OUT_IRQHandler         /* USB OTG HS End Point 1 Out   */
219*a8f7f3fcSMatthias Ringwald  .word     OTG_HS_EP1_IN_IRQHandler          /* USB OTG HS End Point 1 In    */
220*a8f7f3fcSMatthias Ringwald  .word     OTG_HS_WKUP_IRQHandler            /* USB OTG HS Wakeup through EXTI */
221*a8f7f3fcSMatthias Ringwald  .word     OTG_HS_IRQHandler                 /* USB OTG HS                   */
222*a8f7f3fcSMatthias Ringwald  .word     DCMI_IRQHandler                   /* DCMI                         */
223*a8f7f3fcSMatthias Ringwald  .word     0                                 /* CRYP crypto                  */
224*a8f7f3fcSMatthias Ringwald  .word     HASH_RNG_IRQHandler               /* Hash and Rng                 */
225*a8f7f3fcSMatthias Ringwald  .word     FPU_IRQHandler                    /* FPU                          */
226*a8f7f3fcSMatthias Ringwald
227*a8f7f3fcSMatthias Ringwald
228*a8f7f3fcSMatthias Ringwald/*******************************************************************************
229*a8f7f3fcSMatthias Ringwald*
230*a8f7f3fcSMatthias Ringwald* Provide weak aliases for each Exception handler to the Default_Handler.
231*a8f7f3fcSMatthias Ringwald* As they are weak aliases, any function with the same name will override
232*a8f7f3fcSMatthias Ringwald* this definition.
233*a8f7f3fcSMatthias Ringwald*
234*a8f7f3fcSMatthias Ringwald*******************************************************************************/
235*a8f7f3fcSMatthias Ringwald   .weak      NMI_Handler
236*a8f7f3fcSMatthias Ringwald   .thumb_set NMI_Handler,Default_Handler
237*a8f7f3fcSMatthias Ringwald
238*a8f7f3fcSMatthias Ringwald   .weak      HardFault_Handler
239*a8f7f3fcSMatthias Ringwald   .thumb_set HardFault_Handler,Default_Handler
240*a8f7f3fcSMatthias Ringwald
241*a8f7f3fcSMatthias Ringwald   .weak      MemManage_Handler
242*a8f7f3fcSMatthias Ringwald   .thumb_set MemManage_Handler,Default_Handler
243*a8f7f3fcSMatthias Ringwald
244*a8f7f3fcSMatthias Ringwald   .weak      BusFault_Handler
245*a8f7f3fcSMatthias Ringwald   .thumb_set BusFault_Handler,Default_Handler
246*a8f7f3fcSMatthias Ringwald
247*a8f7f3fcSMatthias Ringwald   .weak      UsageFault_Handler
248*a8f7f3fcSMatthias Ringwald   .thumb_set UsageFault_Handler,Default_Handler
249*a8f7f3fcSMatthias Ringwald
250*a8f7f3fcSMatthias Ringwald   .weak      SVC_Handler
251*a8f7f3fcSMatthias Ringwald   .thumb_set SVC_Handler,Default_Handler
252*a8f7f3fcSMatthias Ringwald
253*a8f7f3fcSMatthias Ringwald   .weak      DebugMon_Handler
254*a8f7f3fcSMatthias Ringwald   .thumb_set DebugMon_Handler,Default_Handler
255*a8f7f3fcSMatthias Ringwald
256*a8f7f3fcSMatthias Ringwald   .weak      PendSV_Handler
257*a8f7f3fcSMatthias Ringwald   .thumb_set PendSV_Handler,Default_Handler
258*a8f7f3fcSMatthias Ringwald
259*a8f7f3fcSMatthias Ringwald   .weak      SysTick_Handler
260*a8f7f3fcSMatthias Ringwald   .thumb_set SysTick_Handler,Default_Handler
261*a8f7f3fcSMatthias Ringwald
262*a8f7f3fcSMatthias Ringwald   .weak      WWDG_IRQHandler
263*a8f7f3fcSMatthias Ringwald   .thumb_set WWDG_IRQHandler,Default_Handler
264*a8f7f3fcSMatthias Ringwald
265*a8f7f3fcSMatthias Ringwald   .weak      PVD_IRQHandler
266*a8f7f3fcSMatthias Ringwald   .thumb_set PVD_IRQHandler,Default_Handler
267*a8f7f3fcSMatthias Ringwald
268*a8f7f3fcSMatthias Ringwald   .weak      TAMP_STAMP_IRQHandler
269*a8f7f3fcSMatthias Ringwald   .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
270*a8f7f3fcSMatthias Ringwald
271*a8f7f3fcSMatthias Ringwald   .weak      RTC_WKUP_IRQHandler
272*a8f7f3fcSMatthias Ringwald   .thumb_set RTC_WKUP_IRQHandler,Default_Handler
273*a8f7f3fcSMatthias Ringwald
274*a8f7f3fcSMatthias Ringwald   .weak      FLASH_IRQHandler
275*a8f7f3fcSMatthias Ringwald   .thumb_set FLASH_IRQHandler,Default_Handler
276*a8f7f3fcSMatthias Ringwald
277*a8f7f3fcSMatthias Ringwald   .weak      RCC_IRQHandler
278*a8f7f3fcSMatthias Ringwald   .thumb_set RCC_IRQHandler,Default_Handler
279*a8f7f3fcSMatthias Ringwald
280*a8f7f3fcSMatthias Ringwald   .weak      EXTI0_IRQHandler
281*a8f7f3fcSMatthias Ringwald   .thumb_set EXTI0_IRQHandler,Default_Handler
282*a8f7f3fcSMatthias Ringwald
283*a8f7f3fcSMatthias Ringwald   .weak      EXTI1_IRQHandler
284*a8f7f3fcSMatthias Ringwald   .thumb_set EXTI1_IRQHandler,Default_Handler
285*a8f7f3fcSMatthias Ringwald
286*a8f7f3fcSMatthias Ringwald   .weak      EXTI2_IRQHandler
287*a8f7f3fcSMatthias Ringwald   .thumb_set EXTI2_IRQHandler,Default_Handler
288*a8f7f3fcSMatthias Ringwald
289*a8f7f3fcSMatthias Ringwald   .weak      EXTI3_IRQHandler
290*a8f7f3fcSMatthias Ringwald   .thumb_set EXTI3_IRQHandler,Default_Handler
291*a8f7f3fcSMatthias Ringwald
292*a8f7f3fcSMatthias Ringwald   .weak      EXTI4_IRQHandler
293*a8f7f3fcSMatthias Ringwald   .thumb_set EXTI4_IRQHandler,Default_Handler
294*a8f7f3fcSMatthias Ringwald
295*a8f7f3fcSMatthias Ringwald   .weak      DMA1_Stream0_IRQHandler
296*a8f7f3fcSMatthias Ringwald   .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
297*a8f7f3fcSMatthias Ringwald
298*a8f7f3fcSMatthias Ringwald   .weak      DMA1_Stream1_IRQHandler
299*a8f7f3fcSMatthias Ringwald   .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
300*a8f7f3fcSMatthias Ringwald
301*a8f7f3fcSMatthias Ringwald   .weak      DMA1_Stream2_IRQHandler
302*a8f7f3fcSMatthias Ringwald   .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
303*a8f7f3fcSMatthias Ringwald
304*a8f7f3fcSMatthias Ringwald   .weak      DMA1_Stream3_IRQHandler
305*a8f7f3fcSMatthias Ringwald   .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
306*a8f7f3fcSMatthias Ringwald
307*a8f7f3fcSMatthias Ringwald   .weak      DMA1_Stream4_IRQHandler
308*a8f7f3fcSMatthias Ringwald   .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
309*a8f7f3fcSMatthias Ringwald
310*a8f7f3fcSMatthias Ringwald   .weak      DMA1_Stream5_IRQHandler
311*a8f7f3fcSMatthias Ringwald   .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
312*a8f7f3fcSMatthias Ringwald
313*a8f7f3fcSMatthias Ringwald   .weak      DMA1_Stream6_IRQHandler
314*a8f7f3fcSMatthias Ringwald   .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
315*a8f7f3fcSMatthias Ringwald
316*a8f7f3fcSMatthias Ringwald   .weak      ADC_IRQHandler
317*a8f7f3fcSMatthias Ringwald   .thumb_set ADC_IRQHandler,Default_Handler
318*a8f7f3fcSMatthias Ringwald
319*a8f7f3fcSMatthias Ringwald   .weak      CAN1_TX_IRQHandler
320*a8f7f3fcSMatthias Ringwald   .thumb_set CAN1_TX_IRQHandler,Default_Handler
321*a8f7f3fcSMatthias Ringwald
322*a8f7f3fcSMatthias Ringwald   .weak      CAN1_RX0_IRQHandler
323*a8f7f3fcSMatthias Ringwald   .thumb_set CAN1_RX0_IRQHandler,Default_Handler
324*a8f7f3fcSMatthias Ringwald
325*a8f7f3fcSMatthias Ringwald   .weak      CAN1_RX1_IRQHandler
326*a8f7f3fcSMatthias Ringwald   .thumb_set CAN1_RX1_IRQHandler,Default_Handler
327*a8f7f3fcSMatthias Ringwald
328*a8f7f3fcSMatthias Ringwald   .weak      CAN1_SCE_IRQHandler
329*a8f7f3fcSMatthias Ringwald   .thumb_set CAN1_SCE_IRQHandler,Default_Handler
330*a8f7f3fcSMatthias Ringwald
331*a8f7f3fcSMatthias Ringwald   .weak      EXTI9_5_IRQHandler
332*a8f7f3fcSMatthias Ringwald   .thumb_set EXTI9_5_IRQHandler,Default_Handler
333*a8f7f3fcSMatthias Ringwald
334*a8f7f3fcSMatthias Ringwald   .weak      TIM1_BRK_TIM9_IRQHandler
335*a8f7f3fcSMatthias Ringwald   .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
336*a8f7f3fcSMatthias Ringwald
337*a8f7f3fcSMatthias Ringwald   .weak      TIM1_UP_TIM10_IRQHandler
338*a8f7f3fcSMatthias Ringwald   .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
339*a8f7f3fcSMatthias Ringwald
340*a8f7f3fcSMatthias Ringwald   .weak      TIM1_TRG_COM_TIM11_IRQHandler
341*a8f7f3fcSMatthias Ringwald   .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
342*a8f7f3fcSMatthias Ringwald
343*a8f7f3fcSMatthias Ringwald   .weak      TIM1_CC_IRQHandler
344*a8f7f3fcSMatthias Ringwald   .thumb_set TIM1_CC_IRQHandler,Default_Handler
345*a8f7f3fcSMatthias Ringwald
346*a8f7f3fcSMatthias Ringwald   .weak      TIM2_IRQHandler
347*a8f7f3fcSMatthias Ringwald   .thumb_set TIM2_IRQHandler,Default_Handler
348*a8f7f3fcSMatthias Ringwald
349*a8f7f3fcSMatthias Ringwald   .weak      TIM3_IRQHandler
350*a8f7f3fcSMatthias Ringwald   .thumb_set TIM3_IRQHandler,Default_Handler
351*a8f7f3fcSMatthias Ringwald
352*a8f7f3fcSMatthias Ringwald   .weak      TIM4_IRQHandler
353*a8f7f3fcSMatthias Ringwald   .thumb_set TIM4_IRQHandler,Default_Handler
354*a8f7f3fcSMatthias Ringwald
355*a8f7f3fcSMatthias Ringwald   .weak      I2C1_EV_IRQHandler
356*a8f7f3fcSMatthias Ringwald   .thumb_set I2C1_EV_IRQHandler,Default_Handler
357*a8f7f3fcSMatthias Ringwald
358*a8f7f3fcSMatthias Ringwald   .weak      I2C1_ER_IRQHandler
359*a8f7f3fcSMatthias Ringwald   .thumb_set I2C1_ER_IRQHandler,Default_Handler
360*a8f7f3fcSMatthias Ringwald
361*a8f7f3fcSMatthias Ringwald   .weak      I2C2_EV_IRQHandler
362*a8f7f3fcSMatthias Ringwald   .thumb_set I2C2_EV_IRQHandler,Default_Handler
363*a8f7f3fcSMatthias Ringwald
364*a8f7f3fcSMatthias Ringwald   .weak      I2C2_ER_IRQHandler
365*a8f7f3fcSMatthias Ringwald   .thumb_set I2C2_ER_IRQHandler,Default_Handler
366*a8f7f3fcSMatthias Ringwald
367*a8f7f3fcSMatthias Ringwald   .weak      SPI1_IRQHandler
368*a8f7f3fcSMatthias Ringwald   .thumb_set SPI1_IRQHandler,Default_Handler
369*a8f7f3fcSMatthias Ringwald
370*a8f7f3fcSMatthias Ringwald   .weak      SPI2_IRQHandler
371*a8f7f3fcSMatthias Ringwald   .thumb_set SPI2_IRQHandler,Default_Handler
372*a8f7f3fcSMatthias Ringwald
373*a8f7f3fcSMatthias Ringwald   .weak      USART1_IRQHandler
374*a8f7f3fcSMatthias Ringwald   .thumb_set USART1_IRQHandler,Default_Handler
375*a8f7f3fcSMatthias Ringwald
376*a8f7f3fcSMatthias Ringwald   .weak      USART2_IRQHandler
377*a8f7f3fcSMatthias Ringwald   .thumb_set USART2_IRQHandler,Default_Handler
378*a8f7f3fcSMatthias Ringwald
379*a8f7f3fcSMatthias Ringwald   .weak      USART3_IRQHandler
380*a8f7f3fcSMatthias Ringwald   .thumb_set USART3_IRQHandler,Default_Handler
381*a8f7f3fcSMatthias Ringwald
382*a8f7f3fcSMatthias Ringwald   .weak      EXTI15_10_IRQHandler
383*a8f7f3fcSMatthias Ringwald   .thumb_set EXTI15_10_IRQHandler,Default_Handler
384*a8f7f3fcSMatthias Ringwald
385*a8f7f3fcSMatthias Ringwald   .weak      RTC_Alarm_IRQHandler
386*a8f7f3fcSMatthias Ringwald   .thumb_set RTC_Alarm_IRQHandler,Default_Handler
387*a8f7f3fcSMatthias Ringwald
388*a8f7f3fcSMatthias Ringwald   .weak      OTG_FS_WKUP_IRQHandler
389*a8f7f3fcSMatthias Ringwald   .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
390*a8f7f3fcSMatthias Ringwald
391*a8f7f3fcSMatthias Ringwald   .weak      TIM8_BRK_TIM12_IRQHandler
392*a8f7f3fcSMatthias Ringwald   .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
393*a8f7f3fcSMatthias Ringwald
394*a8f7f3fcSMatthias Ringwald   .weak      TIM8_UP_TIM13_IRQHandler
395*a8f7f3fcSMatthias Ringwald   .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
396*a8f7f3fcSMatthias Ringwald
397*a8f7f3fcSMatthias Ringwald   .weak      TIM8_TRG_COM_TIM14_IRQHandler
398*a8f7f3fcSMatthias Ringwald   .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
399*a8f7f3fcSMatthias Ringwald
400*a8f7f3fcSMatthias Ringwald   .weak      TIM8_CC_IRQHandler
401*a8f7f3fcSMatthias Ringwald   .thumb_set TIM8_CC_IRQHandler,Default_Handler
402*a8f7f3fcSMatthias Ringwald
403*a8f7f3fcSMatthias Ringwald   .weak      DMA1_Stream7_IRQHandler
404*a8f7f3fcSMatthias Ringwald   .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
405*a8f7f3fcSMatthias Ringwald
406*a8f7f3fcSMatthias Ringwald   .weak      FSMC_IRQHandler
407*a8f7f3fcSMatthias Ringwald   .thumb_set FSMC_IRQHandler,Default_Handler
408*a8f7f3fcSMatthias Ringwald
409*a8f7f3fcSMatthias Ringwald   .weak      SDIO_IRQHandler
410*a8f7f3fcSMatthias Ringwald   .thumb_set SDIO_IRQHandler,Default_Handler
411*a8f7f3fcSMatthias Ringwald
412*a8f7f3fcSMatthias Ringwald   .weak      TIM5_IRQHandler
413*a8f7f3fcSMatthias Ringwald   .thumb_set TIM5_IRQHandler,Default_Handler
414*a8f7f3fcSMatthias Ringwald
415*a8f7f3fcSMatthias Ringwald   .weak      SPI3_IRQHandler
416*a8f7f3fcSMatthias Ringwald   .thumb_set SPI3_IRQHandler,Default_Handler
417*a8f7f3fcSMatthias Ringwald
418*a8f7f3fcSMatthias Ringwald   .weak      UART4_IRQHandler
419*a8f7f3fcSMatthias Ringwald   .thumb_set UART4_IRQHandler,Default_Handler
420*a8f7f3fcSMatthias Ringwald
421*a8f7f3fcSMatthias Ringwald   .weak      UART5_IRQHandler
422*a8f7f3fcSMatthias Ringwald   .thumb_set UART5_IRQHandler,Default_Handler
423*a8f7f3fcSMatthias Ringwald
424*a8f7f3fcSMatthias Ringwald   .weak      TIM6_DAC_IRQHandler
425*a8f7f3fcSMatthias Ringwald   .thumb_set TIM6_DAC_IRQHandler,Default_Handler
426*a8f7f3fcSMatthias Ringwald
427*a8f7f3fcSMatthias Ringwald   .weak      TIM7_IRQHandler
428*a8f7f3fcSMatthias Ringwald   .thumb_set TIM7_IRQHandler,Default_Handler
429*a8f7f3fcSMatthias Ringwald
430*a8f7f3fcSMatthias Ringwald   .weak      DMA2_Stream0_IRQHandler
431*a8f7f3fcSMatthias Ringwald   .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
432*a8f7f3fcSMatthias Ringwald
433*a8f7f3fcSMatthias Ringwald   .weak      DMA2_Stream1_IRQHandler
434*a8f7f3fcSMatthias Ringwald   .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
435*a8f7f3fcSMatthias Ringwald
436*a8f7f3fcSMatthias Ringwald   .weak      DMA2_Stream2_IRQHandler
437*a8f7f3fcSMatthias Ringwald   .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
438*a8f7f3fcSMatthias Ringwald
439*a8f7f3fcSMatthias Ringwald   .weak      DMA2_Stream3_IRQHandler
440*a8f7f3fcSMatthias Ringwald   .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
441*a8f7f3fcSMatthias Ringwald
442*a8f7f3fcSMatthias Ringwald   .weak      DMA2_Stream4_IRQHandler
443*a8f7f3fcSMatthias Ringwald   .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
444*a8f7f3fcSMatthias Ringwald
445*a8f7f3fcSMatthias Ringwald   .weak      ETH_IRQHandler
446*a8f7f3fcSMatthias Ringwald   .thumb_set ETH_IRQHandler,Default_Handler
447*a8f7f3fcSMatthias Ringwald
448*a8f7f3fcSMatthias Ringwald   .weak      ETH_WKUP_IRQHandler
449*a8f7f3fcSMatthias Ringwald   .thumb_set ETH_WKUP_IRQHandler,Default_Handler
450*a8f7f3fcSMatthias Ringwald
451*a8f7f3fcSMatthias Ringwald   .weak      CAN2_TX_IRQHandler
452*a8f7f3fcSMatthias Ringwald   .thumb_set CAN2_TX_IRQHandler,Default_Handler
453*a8f7f3fcSMatthias Ringwald
454*a8f7f3fcSMatthias Ringwald   .weak      CAN2_RX0_IRQHandler
455*a8f7f3fcSMatthias Ringwald   .thumb_set CAN2_RX0_IRQHandler,Default_Handler
456*a8f7f3fcSMatthias Ringwald
457*a8f7f3fcSMatthias Ringwald   .weak      CAN2_RX1_IRQHandler
458*a8f7f3fcSMatthias Ringwald   .thumb_set CAN2_RX1_IRQHandler,Default_Handler
459*a8f7f3fcSMatthias Ringwald
460*a8f7f3fcSMatthias Ringwald   .weak      CAN2_SCE_IRQHandler
461*a8f7f3fcSMatthias Ringwald   .thumb_set CAN2_SCE_IRQHandler,Default_Handler
462*a8f7f3fcSMatthias Ringwald
463*a8f7f3fcSMatthias Ringwald   .weak      OTG_FS_IRQHandler
464*a8f7f3fcSMatthias Ringwald   .thumb_set OTG_FS_IRQHandler,Default_Handler
465*a8f7f3fcSMatthias Ringwald
466*a8f7f3fcSMatthias Ringwald   .weak      DMA2_Stream5_IRQHandler
467*a8f7f3fcSMatthias Ringwald   .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
468*a8f7f3fcSMatthias Ringwald
469*a8f7f3fcSMatthias Ringwald   .weak      DMA2_Stream6_IRQHandler
470*a8f7f3fcSMatthias Ringwald   .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
471*a8f7f3fcSMatthias Ringwald
472*a8f7f3fcSMatthias Ringwald   .weak      DMA2_Stream7_IRQHandler
473*a8f7f3fcSMatthias Ringwald   .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
474*a8f7f3fcSMatthias Ringwald
475*a8f7f3fcSMatthias Ringwald   .weak      USART6_IRQHandler
476*a8f7f3fcSMatthias Ringwald   .thumb_set USART6_IRQHandler,Default_Handler
477*a8f7f3fcSMatthias Ringwald
478*a8f7f3fcSMatthias Ringwald   .weak      I2C3_EV_IRQHandler
479*a8f7f3fcSMatthias Ringwald   .thumb_set I2C3_EV_IRQHandler,Default_Handler
480*a8f7f3fcSMatthias Ringwald
481*a8f7f3fcSMatthias Ringwald   .weak      I2C3_ER_IRQHandler
482*a8f7f3fcSMatthias Ringwald   .thumb_set I2C3_ER_IRQHandler,Default_Handler
483*a8f7f3fcSMatthias Ringwald
484*a8f7f3fcSMatthias Ringwald   .weak      OTG_HS_EP1_OUT_IRQHandler
485*a8f7f3fcSMatthias Ringwald   .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
486*a8f7f3fcSMatthias Ringwald
487*a8f7f3fcSMatthias Ringwald   .weak      OTG_HS_EP1_IN_IRQHandler
488*a8f7f3fcSMatthias Ringwald   .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
489*a8f7f3fcSMatthias Ringwald
490*a8f7f3fcSMatthias Ringwald   .weak      OTG_HS_WKUP_IRQHandler
491*a8f7f3fcSMatthias Ringwald   .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
492*a8f7f3fcSMatthias Ringwald
493*a8f7f3fcSMatthias Ringwald   .weak      OTG_HS_IRQHandler
494*a8f7f3fcSMatthias Ringwald   .thumb_set OTG_HS_IRQHandler,Default_Handler
495*a8f7f3fcSMatthias Ringwald
496*a8f7f3fcSMatthias Ringwald   .weak      DCMI_IRQHandler
497*a8f7f3fcSMatthias Ringwald   .thumb_set DCMI_IRQHandler,Default_Handler
498*a8f7f3fcSMatthias Ringwald
499*a8f7f3fcSMatthias Ringwald   .weak      HASH_RNG_IRQHandler
500*a8f7f3fcSMatthias Ringwald   .thumb_set HASH_RNG_IRQHandler,Default_Handler
501*a8f7f3fcSMatthias Ringwald
502*a8f7f3fcSMatthias Ringwald   .weak      FPU_IRQHandler
503*a8f7f3fcSMatthias Ringwald   .thumb_set FPU_IRQHandler,Default_Handler
504*a8f7f3fcSMatthias Ringwald
505*a8f7f3fcSMatthias Ringwald/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
506