1 #include "asf.h" 2 #include "stdio_serial.h" 3 #include "conf_board.h" 4 #include "conf_clock.h" 5 6 // BTstack 7 #include "btstack_chipset_atwilc3000.h" 8 #include "btstack_debug.h" 9 #include "btstack_memory.h" 10 #include "btstack_run_loop.h" 11 #include "btstack_run_loop_embedded.h" 12 #include "classic/btstack_link_key_db.h" 13 #include "hal_uart_dma.h" 14 #include "hal_cpu.h" 15 #include "hal_tick.h" 16 #include "hci.h" 17 #include "hci_dump.h" 18 #include "wilc3000_bt_firmware.h" 19 20 // #define USE_XDMAC_FOR_USART 21 #define XDMA_CH_UART_TX 0 22 #define XDMA_CH_UART_RX 1 23 24 /** All interrupt mask. */ 25 #define ALL_INTERRUPT_MASK 0xffffffff 26 27 #ifdef __cplusplus 28 extern "C" { 29 #endif 30 31 extern int btstack_main(int argc, const char * argv[]); 32 33 static void dummy_handler(void){} 34 static void (*tick_handler)(void) = &dummy_handler; 35 36 static btstack_uart_config_t uart_config; 37 38 static hci_transport_config_uart_t transport_config = { 39 HCI_TRANSPORT_CONFIG_UART, 40 115200, 41 0, // use 0 to skip baud rate change from 115200 to X for debugging purposes 42 1, // flow control 43 NULL, 44 }; 45 46 /** 47 * \brief Handler for System Tick interrupt. 48 */ 49 void SysTick_Handler(void) 50 { 51 tick_handler(); 52 } 53 54 /** 55 * Configure UART console. 56 */ 57 // [main_console_configure] 58 static void configure_console(void) 59 { 60 const usart_serial_options_t uart_serial_options = { 61 .baudrate = CONF_UART_BAUDRATE, 62 #ifdef CONF_UART_CHAR_LENGTH 63 .charlength = CONF_UART_CHAR_LENGTH, 64 #endif 65 .paritytype = CONF_UART_PARITY, 66 #ifdef CONF_UART_STOP_BITS 67 .stopbits = CONF_UART_STOP_BITS, 68 #endif 69 }; 70 71 /* Configure console UART. */ 72 sysclk_enable_peripheral_clock(CONSOLE_UART_ID); 73 stdio_serial_init(CONF_UART, &uart_serial_options); 74 } 75 76 // [main_console_configure] 77 78 /** 79 * \brief Wait for the given number of milliseconds (ticks 80 * generated by the SAM's microcontrollers's system tick). 81 * 82 * \param ul_dly_ticks Delay to wait for, in milliseconds. 83 */ 84 // [main_ms_delay] 85 static void mdelay(uint32_t delay_in_ms) 86 { 87 // delay_ms(delay_in_ms); 88 uint32_t time_to_wait = btstack_run_loop_get_time_ms() + delay_in_ms; 89 while (btstack_run_loop_get_time_ms() < time_to_wait); 90 } 91 // [main_ms_delay] 92 93 //////////////////////////////////////////////////////////////////////////////// 94 // hal_cpu.h implementation 95 //////////////////////////////////////////////////////////////////////////////// 96 // hal_led.h implementation 97 #include "hal_led.h" 98 void hal_led_off(void); 99 void hal_led_on(void); 100 101 void hal_led_off(void){ 102 // gpio_set_pin_low(GPIOA, GPIO_LED2); 103 } 104 void hal_led_on(void){ 105 // gpio_set_pin_high(GPIOA, GPIO_LED2); 106 } 107 void hal_led_toggle(void){ 108 // gpio_toggle_pin(GPIOA, GPIO_LED2); 109 } 110 111 // hal_cpu.h implementation 112 #include "hal_cpu.h" 113 114 void hal_cpu_disable_irqs(void){ 115 //__disable_irq(); 116 } 117 118 void hal_cpu_enable_irqs(void){ 119 // __enable_irq(); 120 } 121 122 void hal_cpu_enable_irqs_and_sleep(void){ 123 hal_led_off(); 124 // __enable_irq(); 125 // __asm__("wfe"); // go to sleep if event flag isn't set. if set, just clear it. IRQs set event flag 126 127 // note: hal_uart_needed_during_sleep can be used to disable peripheral clock if it's not needed for a timer 128 hal_led_on(); 129 } 130 131 132 #ifndef USE_XDMAC_FOR_USART 133 // RX state 134 static volatile uint16_t bytes_to_read = 0; 135 static volatile uint8_t * rx_buffer_ptr = 0; 136 static volatile int rx_notify; 137 138 // TX state 139 static volatile uint16_t bytes_to_write = 0; 140 static volatile uint8_t * tx_buffer_ptr = 0; 141 static volatile int tx_notify; 142 #endif 143 144 static int simulate_flowcontrol; 145 146 // handlers 147 static void (*rx_done_handler)(void) = dummy_handler; 148 static void (*tx_done_handler)(void) = dummy_handler; 149 static void (*cts_irq_handler)(void) = dummy_handler; 150 151 // @note While the Atmel SAM S7x data sheet states 152 // "The hardware handshaking feature enables an out-of-band flow control by automatic management 153 // of the pins RTS and CTS.", 154 // I didn't see RTS going up automatically up, ever. So, at least for RTS, the automatic management 155 // is just a glorified GPIO pin control feature, which provides no benefit, but irritates a lot 156 157 // J505:6 158 #define DEBUG_PIN_1 PIO_PD16_IDX 159 // J505:5 160 #define DEBUG_PIN_2 PIO_PD15_IDX 161 162 static inline void hal_uart_rts_high(void){ 163 if (!simulate_flowcontrol) return; 164 ioport_set_pin_level(DEBUG_PIN_2, IOPORT_PIN_LEVEL_HIGH); 165 BOARD_USART->US_CR = US_CR_RTSEN; 166 } 167 static inline void hal_uart_rts_low(void){ 168 if (!simulate_flowcontrol) return; 169 ioport_set_pin_level(DEBUG_PIN_2, IOPORT_PIN_LEVEL_LOW); 170 BOARD_USART->US_CR = US_CR_RTSDIS; 171 } 172 173 /** 174 */ 175 static int hal_uart_dma_initialized = 0; 176 void hal_uart_dma_init(void) 177 { 178 if (hal_uart_dma_initialized){ 179 log_info("hal_uart_dma_init already initialized"); 180 return; 181 } 182 hal_uart_dma_initialized = 1; 183 184 // debug 185 #ifdef DEBUG_PIN_1 186 ioport_set_pin_dir(DEBUG_PIN_1, IOPORT_DIR_OUTPUT); 187 ioport_set_pin_level(DEBUG_PIN_1, IOPORT_PIN_LEVEL_LOW); 188 #endif 189 #ifdef DEBUG_PIN_2 190 ioport_set_pin_dir(DEBUG_PIN_2, IOPORT_DIR_OUTPUT); 191 ioport_set_pin_level(DEBUG_PIN_2, IOPORT_PIN_LEVEL_LOW); 192 #endif 193 // power on 194 ioport_set_pin_dir(BLUETOOTH_CHP_EN, IOPORT_DIR_OUTPUT); 195 ioport_set_pin_level(BLUETOOTH_CHP_EN, IOPORT_PIN_LEVEL_HIGH); 196 197 // reset 198 ioport_set_pin_dir(BLUETOOTH_RESET, IOPORT_DIR_OUTPUT); 199 ioport_set_pin_level(BLUETOOTH_RESET, IOPORT_PIN_LEVEL_LOW); 200 mdelay(250); 201 ioport_set_pin_level(BLUETOOTH_RESET, IOPORT_PIN_LEVEL_HIGH); 202 mdelay(250); 203 204 /* Enable the peripheral clock in the PMC. */ 205 sysclk_enable_peripheral_clock(BOARD_ID_USART); 206 207 // configure Bluetooth USART 208 const sam_usart_opt_t bluetooth_settings = { 209 115200, 210 US_MR_CHRL_8_BIT, 211 US_MR_PAR_NO, 212 US_MR_NBSTOP_1_BIT, 213 US_MR_CHMODE_NORMAL, 214 /* This field is only used in IrDA mode. */ 215 0 216 }; 217 218 /* Configure USART mode. */ 219 simulate_flowcontrol = 0; 220 usart_init_rs232(BOARD_USART, &bluetooth_settings, sysclk_get_peripheral_hz()); 221 // Set RTS = 0 (normal mode) 222 BOARD_USART->US_CR = US_CR_RTSEN; 223 224 /* Disable all the interrupts. */ 225 usart_disable_interrupt(BOARD_USART, ALL_INTERRUPT_MASK); 226 227 /* Enable TX & RX function. */ 228 usart_enable_tx(BOARD_USART); 229 usart_enable_rx(BOARD_USART); 230 231 /* Configure and enable interrupt of USART. */ 232 NVIC_EnableIRQ(USART_IRQn); 233 234 #ifdef USE_XDMAC_FOR_USART 235 236 // setup XDMAC 237 238 /* Initialize and enable DMA controller */ 239 pmc_enable_periph_clk(ID_XDMAC); 240 241 /* Enable XDMA interrupt */ 242 NVIC_ClearPendingIRQ(XDMAC_IRQn); 243 NVIC_SetPriority( XDMAC_IRQn ,1); 244 NVIC_EnableIRQ(XDMAC_IRQn); 245 246 // Setup XDMA Channel for USART TX 247 xdmac_channel_set_destination_addr(XDMAC, XDMA_CH_UART_TX, (uint32_t)&BOARD_USART->US_THR); 248 xdmac_channel_set_config(XDMAC, XDMA_CH_UART_TX, 249 XDMAC_CC_TYPE_PER_TRAN | 250 XDMAC_CC_DSYNC_MEM2PER | 251 XDMAC_CC_MEMSET_NORMAL_MODE | 252 XDMAC_CC_MBSIZE_SINGLE | 253 XDMAC_CC_DWIDTH_BYTE | 254 XDMAC_CC_SIF_AHB_IF0 | 255 XDMAC_CC_DIF_AHB_IF1 | 256 XDMAC_CC_SAM_INCREMENTED_AM | 257 XDMAC_CC_DAM_FIXED_AM | 258 XDMAC_CC_CSIZE_CHK_1 | 259 XDMAC_CC_PERID(XDAMC_CHANNEL_HWID_USART0_TX) 260 ); 261 xdmac_channel_set_descriptor_control(XDMAC, XDMA_CH_UART_TX, 0); 262 xdmac_channel_set_source_microblock_stride(XDMAC, XDMA_CH_UART_TX, 0); 263 xdmac_channel_set_destination_microblock_stride(XDMAC, XDMA_CH_UART_TX, 0); 264 xdmac_channel_set_datastride_mempattern(XDMAC, XDMA_CH_UART_TX, 0); 265 xdmac_channel_set_block_control(XDMAC, XDMA_CH_UART_TX, 0); 266 xdmac_enable_interrupt(XDMAC, XDMA_CH_UART_TX); 267 xdmac_channel_enable_interrupt(XDMAC, XDMA_CH_UART_TX, XDMAC_CIE_BIE); 268 269 // Setup XDMA Channel for USART RX 270 xdmac_channel_set_source_addr(XDMAC, XDMA_CH_UART_RX, (uint32_t)&BOARD_USART->US_RHR); 271 xdmac_channel_set_config(XDMAC, XDMA_CH_UART_RX, 272 XDMAC_CC_TYPE_PER_TRAN | 273 XDMAC_CC_DSYNC_PER2MEM | 274 XDMAC_CC_MEMSET_NORMAL_MODE | 275 XDMAC_CC_MBSIZE_SINGLE | 276 XDMAC_CC_DWIDTH_BYTE | 277 XDMAC_CC_SIF_AHB_IF1 | 278 XDMAC_CC_DIF_AHB_IF0 | 279 XDMAC_CC_SAM_FIXED_AM | 280 XDMAC_CC_DAM_INCREMENTED_AM | 281 XDMAC_CC_CSIZE_CHK_1 | 282 XDMAC_CC_PERID(XDAMC_CHANNEL_HWID_USART0_RX) 283 ); 284 xdmac_channel_set_descriptor_control(XDMAC, XDMA_CH_UART_RX, 0); 285 xdmac_channel_set_source_microblock_stride(XDMAC, XDMA_CH_UART_RX, 0); 286 xdmac_channel_set_destination_microblock_stride(XDMAC, XDMA_CH_UART_RX, 0); 287 xdmac_channel_set_datastride_mempattern(XDMAC, XDMA_CH_UART_RX, 0); 288 xdmac_channel_set_block_control(XDMAC, XDMA_CH_UART_RX, 0); 289 xdmac_enable_interrupt(XDMAC, XDMA_CH_UART_RX); 290 xdmac_channel_enable_interrupt(XDMAC, XDMA_CH_UART_RX, XDMAC_CIE_BIE); 291 #endif 292 } 293 294 void hal_uart_dma_set_sleep(uint8_t sleep){ 295 } 296 297 void hal_uart_dma_set_block_received( void (*the_block_handler)(void)){ 298 rx_done_handler = the_block_handler; 299 } 300 301 void hal_uart_dma_set_block_sent( void (*the_block_handler)(void)){ 302 tx_done_handler = the_block_handler; 303 } 304 305 void hal_uart_dma_set_csr_irq_handler( void (*the_irq_handler)(void)){ 306 cts_irq_handler = the_irq_handler; 307 } 308 309 int hal_uart_dma_set_baud(uint32_t baud){ 310 /* Disable TX & RX function. */ 311 usart_disable_tx(BOARD_USART); 312 usart_disable_rx(BOARD_USART); 313 uint32_t res = usart_set_async_baudrate(BOARD_USART, baud, sysclk_get_peripheral_hz()); 314 if (res){ 315 log_error("hal_uart_dma_set_baud library call failed"); 316 } 317 318 /* Enable TX & RX function. */ 319 usart_enable_tx(BOARD_USART); 320 usart_enable_rx(BOARD_USART); 321 322 log_info("set baud rate %u", (int) baud); 323 return 0; 324 } 325 326 int hal_uart_dma_set_flowcontrol(int flowcontrol){ 327 log_info("hal_uart_dma_set_flowcontrol %u", flowcontrol); 328 simulate_flowcontrol = flowcontrol; 329 if (flowcontrol){ 330 /* Set hardware handshaking mode. */ 331 BOARD_USART->US_MR = (BOARD_USART->US_MR & ~US_MR_USART_MODE_Msk) | US_MR_USART_MODE_HW_HANDSHAKING; 332 hal_uart_rts_high(); 333 } else { 334 /* Set nomal mode. */ 335 BOARD_USART->US_MR = (BOARD_USART->US_MR & ~US_MR_USART_MODE_Msk) | US_MR_USART_MODE_NORMAL; 336 // Set RTS = 0 (normal mode) 337 BOARD_USART->US_CR = US_CR_RTSEN; 338 } 339 return 0; 340 } 341 342 void hal_uart_dma_send_block(const uint8_t *data, uint16_t size){ 343 344 tx_notify = 1; 345 346 #ifdef USE_XDMAC_FOR_USART 347 xdmac_channel_get_interrupt_status( XDMAC, XDMA_CH_UART_TX); 348 xdmac_channel_set_source_addr(XDMAC, XDMA_CH_UART_TX, (uint32_t)data); 349 xdmac_channel_set_microblock_control(XDMAC, XDMA_CH_UART_TX, size); 350 xdmac_channel_enable(XDMAC, XDMA_CH_UART_TX); 351 #else 352 if (bytes_to_write){ 353 log_error("send block, bytes to write %u", bytes_to_write); 354 return; 355 } 356 tx_buffer_ptr = (uint8_t *) data; 357 bytes_to_write = size; 358 usart_enable_interrupt(BOARD_USART, US_IER_TXRDY); 359 #endif 360 } 361 362 void hal_uart_dma_receive_block(uint8_t *data, uint16_t size){ 363 364 #ifdef DEBUG_PIN_1 365 ioport_set_pin_level(DEBUG_PIN_1, IOPORT_PIN_LEVEL_HIGH); 366 #endif 367 368 hal_uart_rts_low(); 369 370 rx_notify = 1; 371 372 #ifdef USE_XDMAC_FOR_USART 373 xdmac_channel_get_interrupt_status( XDMAC, XDMA_CH_UART_RX); 374 xdmac_channel_set_destination_addr(XDMAC, XDMA_CH_UART_RX, (uint32_t)data); 375 xdmac_channel_set_microblock_control(XDMAC, XDMA_CH_UART_RX, size); 376 xdmac_channel_enable(XDMAC, XDMA_CH_UART_RX); 377 #else 378 rx_buffer_ptr = data; 379 bytes_to_read = size; 380 usart_enable_interrupt(BOARD_USART, US_IER_RXRDY); 381 #endif 382 } 383 384 #ifdef USE_XDMAC_FOR_USART 385 void XDMAC_Handler(void) 386 { 387 uint32_t dma_status; 388 dma_status = xdmac_channel_get_interrupt_status(XDMAC, XDMA_CH_UART_TX); 389 if (dma_status & XDMAC_CIS_BIS) { 390 if (tx_notify){ 391 tx_notify = 0; 392 tx_done_handler(); 393 } 394 } 395 dma_status = xdmac_channel_get_interrupt_status(XDMAC, XDMA_CH_UART_RX); 396 if (dma_status & XDMAC_CIS_BIS) { 397 hal_uart_rts_high(); 398 if (rx_notify){ 399 rx_notify = 0; 400 rx_done_handler(); 401 } 402 } 403 } 404 #else 405 void USART_Handler(void) 406 { 407 408 #ifdef DEBUG_PIN_2 409 // ioport_set_pin_level(DEBUG_PIN_2, IOPORT_PIN_LEVEL_HIGH); 410 #endif 411 412 /* Read USART status. */ 413 uint32_t ul_status = usart_get_status(BOARD_USART); 414 415 // handle ready to send 416 if(ul_status & US_IER_TXRDY) { 417 if (bytes_to_write){ 418 // send next byte 419 usart_write(BOARD_USART, *tx_buffer_ptr); 420 tx_buffer_ptr++; 421 bytes_to_write--; 422 } else { 423 424 // done. disable tx ready interrupt to avoid starvation here 425 usart_disable_interrupt(BOARD_USART, US_IER_TXRDY); 426 if (tx_notify){ 427 tx_notify = 0; 428 tx_done_handler(); 429 } 430 } 431 } 432 433 // handle byte available for read 434 if (ul_status & US_IER_RXRDY) { 435 if (bytes_to_read){ 436 uint32_t ch; 437 usart_read(BOARD_USART, (uint32_t *)&ch); 438 *rx_buffer_ptr++ = ch; 439 bytes_to_read--; 440 if (bytes_to_read == 0){ 441 442 #ifdef DEBUG_PIN_1 443 ioport_set_pin_level(DEBUG_PIN_1, IOPORT_PIN_LEVEL_LOW); 444 #endif 445 446 // done. disable rx ready interrupt, raise RTS 447 hal_uart_rts_high(); 448 usart_disable_interrupt(BOARD_USART, US_IER_RXRDY); 449 if (rx_notify){ 450 rx_notify = 0; 451 rx_done_handler(); 452 } 453 } 454 } else { 455 // shoult not happen, disable irq anyway 456 usart_disable_interrupt(BOARD_USART, US_IER_RXRDY); 457 } 458 } 459 #ifdef DEBUG_PIN_2 460 // ioport_set_pin_level(DEBUG_PIN_2, IOPORT_PIN_LEVEL_LOW); 461 #endif 462 463 } 464 #endif 465 466 void hal_tick_init() 467 { 468 /* Configure systick for 1 ms */ 469 puts("Configure system tick to get 1ms tick period.\r"); 470 if (SysTick_Config(sysclk_get_cpu_hz() / 1000)) { 471 puts("-F- Systick configuration error\r"); 472 while (1); 473 } 474 } 475 476 void hal_tick_set_handler(void (*handler)(void)){ 477 if (handler == NULL){ 478 tick_handler = &dummy_handler; 479 return; 480 } 481 tick_handler = handler; 482 } 483 484 int hal_tick_get_tick_period_in_ms(void){ 485 return 1; 486 } 487 488 static const btstack_uart_block_t * uart_driver; 489 490 static void phase2(int status){ 491 492 if (status){ 493 printf("Download firmware failed\n"); 494 return; 495 } 496 497 printf("Phase 2: Main app\n"); 498 499 // init HCI 500 const hci_transport_t * transport = hci_transport_h4_instance(uart_driver); 501 // const btstack_link_key_db_t * link_key_db = btstack_link_key_db_fs_instance(); 502 hci_init(transport, (void*) &transport_config); 503 hci_set_chipset(btstack_chipset_atwilc3000_instance()); 504 // hci_set_link_key_db(link_key_db); 505 506 // setup app 507 btstack_main(0, NULL); 508 } 509 510 /** 511 * \brief getting-started Application entry point. 512 * 513 * \return Unused (ANSI-C compatibility). 514 */ 515 // [main] 516 int main(void) 517 { 518 /* Initialize the SAM system */ 519 sysclk_init(); 520 board_init(); 521 522 /* Initialize the console uart */ 523 configure_console(); 524 525 /* Output boot info */ 526 printf("BTstack on SAMV71 Xplained Ultra with ATWILC3000\n"); 527 printf("CPU %lu hz, peripheral clock %lu hz\n", sysclk_get_cpu_hz(), sysclk_get_peripheral_hz()); 528 #ifdef USE_XDMAC_FOR_USART 529 printf("Using XDMA for Bluetooth UART\n"); 530 #else 531 printf("Using IRQ driver for Bluetooth UART\n"); 532 #endif 533 printf("--\n"); 534 535 // start with BTstack init - especially configure HCI Transport 536 btstack_memory_init(); 537 btstack_run_loop_init(btstack_run_loop_embedded_get_instance()); 538 539 // enable full log output while porting 540 hci_dump_open(NULL, HCI_DUMP_STDOUT); 541 542 // setup UART HAL + Run Loop integration 543 uart_driver = btstack_uart_block_embedded_instance(); 544 545 // extract UART config from transport config, but disable flow control 546 uart_config.baudrate = transport_config.baudrate_init; 547 uart_config.flowcontrol = 0; 548 uart_config.device_name = transport_config.device_name; 549 uart_driver->init(&uart_config); 550 551 // phase #1 download firmware 552 printf("Phase 1: Download firmware\n"); 553 554 // phase #2 start main app 555 btstack_chipset_atwilc3000_download_firmware(uart_driver,921600, transport_config.flowcontrol, atwilc3000_fw_data, atwilc3000_fw_size, &phase2); 556 557 // go 558 btstack_run_loop_execute(); 559 560 // compiler happy 561 while(1); 562 } 563 #ifdef __cplusplus 564 } 565 #endif 566