1 #include "asf.h" 2 #include "stdio_serial.h" 3 #include "conf_board.h" 4 #include "conf_clock.h" 5 6 // BTstack 7 #include "btstack_chipset_atwilc3000.h" 8 #include "btstack_debug.h" 9 #include "btstack_memory.h" 10 #include "btstack_run_loop.h" 11 #include "btstack_run_loop_embedded.h" 12 #include "classic/btstack_link_key_db.h" 13 #include "hal_uart_dma.h" 14 #include "hal_cpu.h" 15 #include "hal_tick.h" 16 #include "hci.h" 17 #include "hci_dump.h" 18 #include "wilc3000_bt_firmware.h" 19 20 // #define USE_XDMAC_FOR_USART 21 #define XDMA_CH_UART_TX 0 22 #define XDMA_CH_UART_RX 1 23 24 /** All interrupt mask. */ 25 #define ALL_INTERRUPT_MASK 0xffffffff 26 27 #ifdef __cplusplus 28 extern "C" { 29 #endif 30 31 extern int btstack_main(int argc, const char * argv[]); 32 33 static void dummy_handler(void){} 34 static void (*tick_handler)(void) = &dummy_handler; 35 36 static btstack_uart_config_t uart_config; 37 38 static hci_transport_config_uart_t transport_config = { 39 HCI_TRANSPORT_CONFIG_UART, 40 115200, 41 921600, // use 0 to skip baud rate change from 115200 to X for debugging purposes 42 1, // flow control 43 NULL, 44 }; 45 46 /** 47 * \brief Handler for System Tick interrupt. 48 */ 49 void SysTick_Handler(void) 50 { 51 tick_handler(); 52 } 53 54 /** 55 * Configure UART console. 56 */ 57 // [main_console_configure] 58 static void configure_console(void) 59 { 60 const usart_serial_options_t uart_serial_options = { 61 .baudrate = CONF_UART_BAUDRATE, 62 #ifdef CONF_UART_CHAR_LENGTH 63 .charlength = CONF_UART_CHAR_LENGTH, 64 #endif 65 .paritytype = CONF_UART_PARITY, 66 #ifdef CONF_UART_STOP_BITS 67 .stopbits = CONF_UART_STOP_BITS, 68 #endif 69 }; 70 71 /* Configure console UART. */ 72 sysclk_enable_peripheral_clock(CONSOLE_UART_ID); 73 stdio_serial_init(CONF_UART, &uart_serial_options); 74 } 75 76 // [main_console_configure] 77 78 /** 79 * \brief Wait for the given number of milliseconds (ticks 80 * generated by the SAM's microcontrollers's system tick). 81 * 82 * \param ul_dly_ticks Delay to wait for, in milliseconds. 83 */ 84 // [main_ms_delay] 85 static void mdelay(uint32_t delay_in_ms) 86 { 87 // delay_ms(delay_in_ms); 88 uint32_t time_to_wait = btstack_run_loop_get_time_ms() + delay_in_ms; 89 while (btstack_run_loop_get_time_ms() < time_to_wait); 90 } 91 // [main_ms_delay] 92 93 //////////////////////////////////////////////////////////////////////////////// 94 // hal_cpu.h implementation 95 //////////////////////////////////////////////////////////////////////////////// 96 // hal_led.h implementation 97 #include "hal_led.h" 98 void hal_led_off(void); 99 void hal_led_on(void); 100 101 void hal_led_off(void){ 102 // gpio_set_pin_low(GPIOA, GPIO_LED2); 103 } 104 void hal_led_on(void){ 105 // gpio_set_pin_high(GPIOA, GPIO_LED2); 106 } 107 void hal_led_toggle(void){ 108 // gpio_toggle_pin(GPIOA, GPIO_LED2); 109 } 110 111 // hal_cpu.h implementation 112 #include "hal_cpu.h" 113 114 void hal_cpu_disable_irqs(void){ 115 //__disable_irq(); 116 } 117 118 void hal_cpu_enable_irqs(void){ 119 // __enable_irq(); 120 } 121 122 void hal_cpu_enable_irqs_and_sleep(void){ 123 hal_led_off(); 124 // __enable_irq(); 125 // __asm__("wfe"); // go to sleep if event flag isn't set. if set, just clear it. IRQs set event flag 126 127 // note: hal_uart_needed_during_sleep can be used to disable peripheral clock if it's not needed for a timer 128 hal_led_on(); 129 } 130 131 132 #ifndef USE_XDMAC_FOR_USART 133 // RX state 134 static volatile uint16_t bytes_to_read = 0; 135 static volatile uint8_t * rx_buffer_ptr = 0; 136 137 // TX state 138 static volatile uint16_t bytes_to_write = 0; 139 static volatile uint8_t * tx_buffer_ptr = 0; 140 static volatile int tx_notify; 141 #endif 142 143 static int simulate_flowcontrol; 144 145 // handlers 146 static void (*rx_done_handler)(void) = dummy_handler; 147 static void (*tx_done_handler)(void) = dummy_handler; 148 static void (*cts_irq_handler)(void) = dummy_handler; 149 150 // @note While the Atmel SAM S7x data sheet states 151 // "The hardware handshaking feature enables an out-of-band flow control by automatic management 152 // of the pins RTS and CTS.", 153 // I didn't see RTS going up automatically up, ever. So, at least for RTS, the automatic management 154 // is just a glorified GPIO pin control feature, which provides no benefit, but irritates a lot 155 156 static inline void hal_uart_rts_high(void){ 157 if (!simulate_flowcontrol) return; 158 BOARD_USART->US_CR = US_CR_RTSEN; 159 } 160 static inline void hal_uart_rts_low(void){ 161 if (!simulate_flowcontrol) return; 162 BOARD_USART->US_CR = US_CR_RTSDIS; 163 } 164 165 // J505:6 166 // #define DEBUG_PIN_1 PIO_PD16_IDX 167 // J505:5 168 // #define DEBUG_PIN_2 PIO_PD15_IDX 169 170 /** 171 */ 172 void hal_uart_dma_init(void) 173 { 174 175 // debug 176 #ifdef DEBUG_PIN_1 177 ioport_set_pin_dir(DEBUG_PIN_1, IOPORT_DIR_OUTPUT); 178 ioport_set_pin_level(DEBUG_PIN_1, IOPORT_PIN_LEVEL_LOW); 179 #endif 180 #ifdef DEBUG_PIN_2 181 ioport_set_pin_dir(DEBUG_PIN_2, IOPORT_DIR_OUTPUT); 182 ioport_set_pin_level(DEBUG_PIN_2, IOPORT_PIN_LEVEL_LOW); 183 #endif 184 // power on 185 ioport_set_pin_dir(BLUETOOTH_CHP_EN, IOPORT_DIR_OUTPUT); 186 ioport_set_pin_level(BLUETOOTH_CHP_EN, IOPORT_PIN_LEVEL_HIGH); 187 188 // reset 189 ioport_set_pin_dir(BLUETOOTH_RESET, IOPORT_DIR_OUTPUT); 190 ioport_set_pin_level(BLUETOOTH_RESET, IOPORT_PIN_LEVEL_LOW); 191 mdelay(250); 192 ioport_set_pin_level(BLUETOOTH_RESET, IOPORT_PIN_LEVEL_HIGH); 193 mdelay(250); 194 195 /* Enable the peripheral clock in the PMC. */ 196 sysclk_enable_peripheral_clock(BOARD_ID_USART); 197 198 // configure Bluetooth USART 199 const sam_usart_opt_t bluetooth_settings = { 200 115200, 201 US_MR_CHRL_8_BIT, 202 US_MR_PAR_NO, 203 US_MR_NBSTOP_1_BIT, 204 US_MR_CHMODE_NORMAL, 205 /* This field is only used in IrDA mode. */ 206 0 207 }; 208 209 /* Configure USART mode. */ 210 simulate_flowcontrol = 0; 211 usart_init_rs232(BOARD_USART, &bluetooth_settings, sysclk_get_peripheral_hz()); 212 // Set RTS = 0 (normal mode) 213 BOARD_USART->US_CR = US_CR_RTSEN; 214 215 /* Disable all the interrupts. */ 216 usart_disable_interrupt(BOARD_USART, ALL_INTERRUPT_MASK); 217 218 /* Enable TX & RX function. */ 219 usart_enable_tx(BOARD_USART); 220 usart_enable_rx(BOARD_USART); 221 222 /* Configure and enable interrupt of USART. */ 223 NVIC_EnableIRQ(USART_IRQn); 224 225 #ifdef USE_XDMAC_FOR_USART 226 227 // setup XDMAC 228 229 /* Initialize and enable DMA controller */ 230 pmc_enable_periph_clk(ID_XDMAC); 231 232 /* Enable XDMA interrupt */ 233 NVIC_ClearPendingIRQ(XDMAC_IRQn); 234 NVIC_SetPriority( XDMAC_IRQn ,1); 235 NVIC_EnableIRQ(XDMAC_IRQn); 236 237 // Setup XDMA Channel for USART TX 238 xdmac_channel_set_destination_addr(XDMAC, XDMA_CH_UART_TX, (uint32_t)&BOARD_USART->US_THR); 239 xdmac_channel_set_config(XDMAC, XDMA_CH_UART_TX, 240 XDMAC_CC_TYPE_PER_TRAN | 241 XDMAC_CC_DSYNC_MEM2PER | 242 XDMAC_CC_MEMSET_NORMAL_MODE | 243 XDMAC_CC_MBSIZE_SINGLE | 244 XDMAC_CC_DWIDTH_BYTE | 245 XDMAC_CC_SIF_AHB_IF0 | 246 XDMAC_CC_DIF_AHB_IF1 | 247 XDMAC_CC_SAM_INCREMENTED_AM | 248 XDMAC_CC_DAM_FIXED_AM | 249 XDMAC_CC_CSIZE_CHK_1 | 250 XDMAC_CC_PERID(XDAMC_CHANNEL_HWID_USART0_TX) 251 ); 252 xdmac_channel_set_descriptor_control(XDMAC, XDMA_CH_UART_TX, 0); 253 xdmac_channel_set_source_microblock_stride(XDMAC, XDMA_CH_UART_TX, 0); 254 xdmac_channel_set_destination_microblock_stride(XDMAC, XDMA_CH_UART_TX, 0); 255 xdmac_channel_set_datastride_mempattern(XDMAC, XDMA_CH_UART_TX, 0); 256 xdmac_channel_set_block_control(XDMAC, XDMA_CH_UART_TX, 0); 257 xdmac_enable_interrupt(XDMAC, XDMA_CH_UART_TX); 258 xdmac_channel_enable_interrupt(XDMAC, XDMA_CH_UART_TX, XDMAC_CIE_BIE); 259 260 // Setup XDMA Channel for USART RX 261 xdmac_channel_set_source_addr(XDMAC, XDMA_CH_UART_RX, (uint32_t)&BOARD_USART->US_RHR); 262 xdmac_channel_set_config(XDMAC, XDMA_CH_UART_RX, 263 XDMAC_CC_TYPE_PER_TRAN | 264 XDMAC_CC_DSYNC_PER2MEM | 265 XDMAC_CC_MEMSET_NORMAL_MODE | 266 XDMAC_CC_MBSIZE_SINGLE | 267 XDMAC_CC_DWIDTH_BYTE | 268 XDMAC_CC_SIF_AHB_IF1 | 269 XDMAC_CC_DIF_AHB_IF0 | 270 XDMAC_CC_SAM_FIXED_AM | 271 XDMAC_CC_DAM_INCREMENTED_AM | 272 XDMAC_CC_CSIZE_CHK_1 | 273 XDMAC_CC_PERID(XDAMC_CHANNEL_HWID_USART0_RX) 274 ); 275 xdmac_channel_set_descriptor_control(XDMAC, XDMA_CH_UART_RX, 0); 276 xdmac_channel_set_source_microblock_stride(XDMAC, XDMA_CH_UART_RX, 0); 277 xdmac_channel_set_destination_microblock_stride(XDMAC, XDMA_CH_UART_RX, 0); 278 xdmac_channel_set_datastride_mempattern(XDMAC, XDMA_CH_UART_RX, 0); 279 xdmac_channel_set_block_control(XDMAC, XDMA_CH_UART_RX, 0); 280 xdmac_enable_interrupt(XDMAC, XDMA_CH_UART_RX); 281 xdmac_channel_enable_interrupt(XDMAC, XDMA_CH_UART_RX, XDMAC_CIE_BIE); 282 #endif 283 } 284 285 void hal_uart_dma_set_sleep(uint8_t sleep){ 286 } 287 288 void hal_uart_dma_set_block_received( void (*the_block_handler)(void)){ 289 rx_done_handler = the_block_handler; 290 } 291 292 void hal_uart_dma_set_block_sent( void (*the_block_handler)(void)){ 293 tx_done_handler = the_block_handler; 294 } 295 296 void hal_uart_dma_set_csr_irq_handler( void (*the_irq_handler)(void)){ 297 cts_irq_handler = the_irq_handler; 298 } 299 300 int hal_uart_dma_set_baud(uint32_t baud){ 301 /* Disable TX & RX function. */ 302 usart_disable_tx(BOARD_USART); 303 usart_disable_rx(BOARD_USART); 304 uint32_t res = usart_set_async_baudrate(BOARD_USART, baud, sysclk_get_peripheral_hz()); 305 if (res){ 306 log_error("hal_uart_dma_set_baud library call failed"); 307 } 308 309 /* Enable TX & RX function. */ 310 usart_enable_tx(BOARD_USART); 311 usart_enable_rx(BOARD_USART); 312 313 log_info("set baud rate %u", (int) baud); 314 return 0; 315 } 316 317 int hal_uart_dma_set_flowcontrol(int flowcontrol){ 318 simulate_flowcontrol = flowcontrol; 319 if (flowcontrol){ 320 /* Set hardware handshaking mode. */ 321 BOARD_USART->US_MR = (BOARD_USART->US_MR & ~US_MR_USART_MODE_Msk) | US_MR_USART_MODE_HW_HANDSHAKING; 322 hal_uart_rts_low(); 323 } else { 324 /* Set nomal mode. */ 325 BOARD_USART->US_MR = (BOARD_USART->US_MR & ~US_MR_USART_MODE_Msk) | US_MR_USART_MODE_NORMAL; 326 // Set RTS = 0 (normal mode) 327 BOARD_USART->US_CR = US_CR_RTSEN; 328 } 329 return 0; 330 } 331 332 void hal_uart_dma_send_block(const uint8_t *data, uint16_t size){ 333 334 #ifdef DEBUG_PIN_1 335 ioport_set_pin_level(DEBUG_PIN_1, IOPORT_PIN_LEVEL_HIGH); 336 #endif 337 338 tx_notify = 1; 339 340 #ifdef USE_XDMAC_FOR_USART 341 xdmac_channel_get_interrupt_status( XDMAC, XDMA_CH_UART_TX); 342 xdmac_channel_set_source_addr(XDMAC, XDMA_CH_UART_TX, (uint32_t)data); 343 xdmac_channel_set_microblock_control(XDMAC, XDMA_CH_UART_TX, size); 344 xdmac_channel_enable(XDMAC, XDMA_CH_UART_TX); 345 #else 346 if (bytes_to_write){ 347 log_error("send block, bytes to write %u", bytes_to_write); 348 return; 349 } 350 tx_buffer_ptr = (uint8_t *) data; 351 bytes_to_write = size; 352 usart_enable_interrupt(BOARD_USART, US_IER_TXRDY); 353 #endif 354 } 355 356 void hal_uart_dma_receive_block(uint8_t *data, uint16_t size){ 357 358 hal_uart_rts_low(); 359 360 #ifdef USE_XDMAC_FOR_USART 361 xdmac_channel_get_interrupt_status( XDMAC, XDMA_CH_UART_RX); 362 xdmac_channel_set_destination_addr(XDMAC, XDMA_CH_UART_RX, (uint32_t)data); 363 xdmac_channel_set_microblock_control(XDMAC, XDMA_CH_UART_RX, size); 364 xdmac_channel_enable(XDMAC, XDMA_CH_UART_RX); 365 #else 366 rx_buffer_ptr = data; 367 bytes_to_read = size; 368 usart_enable_interrupt(BOARD_USART, US_IER_RXRDY); 369 #endif 370 } 371 372 #ifdef USE_XDMAC_FOR_USART 373 void XDMAC_Handler(void) 374 { 375 uint32_t dma_status; 376 dma_status = xdmac_channel_get_interrupt_status(XDMAC, XDMA_CH_UART_TX); 377 if (dma_status & XDMAC_CIS_BIS) { 378 if (tx_notify){ 379 tx_notify = 0; 380 tx_done_handler(); 381 } 382 } 383 dma_status = xdmac_channel_get_interrupt_status(XDMAC, XDMA_CH_UART_RX); 384 if (dma_status & XDMAC_CIS_BIS) { 385 hal_uart_rts_high(); 386 rx_done_handler(); 387 } 388 } 389 #else 390 void USART_Handler(void) 391 { 392 393 #ifdef DEBUG_PIN_2 394 ioport_set_pin_level(DEBUG_PIN_2, IOPORT_PIN_LEVEL_HIGH); 395 #endif 396 397 /* Read USART status. */ 398 uint32_t ul_status = usart_get_status(BOARD_USART); 399 400 // handle ready to send 401 if(ul_status & US_IER_TXRDY) { 402 if (bytes_to_write){ 403 // send next byte 404 usart_write(BOARD_USART, *tx_buffer_ptr); 405 tx_buffer_ptr++; 406 bytes_to_write--; 407 } else { 408 409 #ifdef DEBUG_PIN_1 410 ioport_set_pin_level(DEBUG_PIN_1, IOPORT_PIN_LEVEL_LOW); 411 #endif 412 // done. disable tx ready interrupt to avoid starvation here 413 usart_disable_interrupt(BOARD_USART, US_IER_TXRDY); 414 if (tx_notify){ 415 tx_notify = 0; 416 tx_done_handler(); 417 } 418 } 419 } 420 421 // handle byte available for read 422 if (ul_status & US_IER_RXRDY) { 423 if (bytes_to_read){ 424 uint32_t ch; 425 usart_read(BOARD_USART, (uint32_t *)&ch); 426 *rx_buffer_ptr++ = ch; 427 bytes_to_read--; 428 if (bytes_to_read == 0){ 429 // done. disable rx ready interrupt, raise RTS 430 hal_uart_rts_high(); 431 usart_disable_interrupt(BOARD_USART, US_IER_RXRDY); 432 rx_done_handler(); 433 } 434 } else { 435 // shoult not happen, disable irq anyway 436 usart_disable_interrupt(BOARD_USART, US_IER_RXRDY); 437 } 438 } 439 #ifdef DEBUG_PIN_2 440 ioport_set_pin_level(DEBUG_PIN_2, IOPORT_PIN_LEVEL_LOW); 441 #endif 442 443 } 444 #endif 445 446 void hal_tick_init() 447 { 448 /* Configure systick for 1 ms */ 449 puts("Configure system tick to get 1ms tick period.\r"); 450 if (SysTick_Config(sysclk_get_cpu_hz() / 1000)) { 451 puts("-F- Systick configuration error\r"); 452 while (1); 453 } 454 } 455 456 void hal_tick_set_handler(void (*handler)(void)){ 457 if (handler == NULL){ 458 tick_handler = &dummy_handler; 459 return; 460 } 461 tick_handler = handler; 462 } 463 464 int hal_tick_get_tick_period_in_ms(void){ 465 return 1; 466 } 467 468 static const btstack_uart_block_t * uart_driver; 469 470 static void phase2(int status){ 471 472 if (status){ 473 printf("Download firmware failed\n"); 474 return; 475 } 476 477 printf("Phase 2: Main app\n"); 478 479 // init HCI 480 const hci_transport_t * transport = hci_transport_h4_instance(uart_driver); 481 // const btstack_link_key_db_t * link_key_db = btstack_link_key_db_fs_instance(); 482 hci_init(transport, (void*) &transport_config); 483 hci_set_chipset(btstack_chipset_atwilc3000_instance()); 484 // hci_set_link_key_db(link_key_db); 485 486 // setup app 487 btstack_main(0, NULL); 488 } 489 490 /** 491 * \brief getting-started Application entry point. 492 * 493 * \return Unused (ANSI-C compatibility). 494 */ 495 // [main] 496 int main(void) 497 { 498 /* Initialize the SAM system */ 499 sysclk_init(); 500 board_init(); 501 502 /* Initialize the console uart */ 503 configure_console(); 504 505 /* Output boot info */ 506 printf("BTstack on SAMV71 Xplained Ultra with ATWILC3000\n"); 507 printf("CPU %lu hz, peripheral clock %lu hz\n", sysclk_get_cpu_hz(), sysclk_get_peripheral_hz()); 508 #ifdef USE_XDMAC_FOR_USART 509 printf("Using XDMA for Bluetooth UART\n"); 510 #else 511 printf("Using IRQ driver for Bluetooth UART\n"); 512 #endif 513 printf("--\n"); 514 515 // start with BTstack init - especially configure HCI Transport 516 btstack_memory_init(); 517 btstack_run_loop_init(btstack_run_loop_embedded_get_instance()); 518 519 // enable full log output while porting 520 hci_dump_open(NULL, HCI_DUMP_STDOUT); 521 522 // setup UART HAL + Run Loop integration 523 uart_driver = btstack_uart_block_embedded_instance(); 524 525 // extract UART config from transport config, but disable flow control 526 uart_config.baudrate = transport_config.baudrate_init; 527 uart_config.flowcontrol = 0; 528 uart_config.device_name = transport_config.device_name; 529 uart_driver->init(&uart_config); 530 531 // phase #1 download firmware 532 printf("Phase 1: Download firmware\n"); 533 534 // phase #2 start main app 535 btstack_chipset_atwilc3000_download_firmware(uart_driver, transport_config.baudrate_main, transport_config.flowcontrol, atwilc3000_fw_data, atwilc3000_fw_size, &phase2); 536 537 // go 538 btstack_run_loop_execute(); 539 540 // compiler happy 541 while(1); 542 } 543 #ifdef __cplusplus 544 } 545 #endif 546