1 #include "asf.h" 2 #include "stdio_serial.h" 3 #include "conf_board.h" 4 #include "conf_clock.h" 5 6 // BTstack 7 #include "btstack_chipset_atwilc3000.h" 8 #include "btstack_debug.h" 9 #include "btstack_memory.h" 10 #include "btstack_run_loop.h" 11 #include "btstack_run_loop_embedded.h" 12 #include "classic/btstack_link_key_db.h" 13 #include "hal_uart_dma.h" 14 #include "hal_cpu.h" 15 #include "hal_tick.h" 16 #include "hci.h" 17 #include "hci_dump.h" 18 #include "wilc3000_bt_firmware.h" 19 20 // #define USE_XDMAC_FOR_USART 21 #define XDMA_CH_UART_TX 0 22 #define XDMA_CH_UART_RX 1 23 24 /** All interrupt mask. */ 25 #define ALL_INTERRUPT_MASK 0xffffffff 26 27 #ifdef __cplusplus 28 extern "C" { 29 #endif 30 31 extern int btstack_main(int argc, const char * argv[]); 32 33 static void dummy_handler(void){} 34 static void (*tick_handler)(void) = &dummy_handler; 35 36 static btstack_uart_config_t uart_config; 37 38 static hci_transport_config_uart_t transport_config = { 39 HCI_TRANSPORT_CONFIG_UART, 40 115200, 41 921600, // use 0 to skip baud rate change from 115200 to X for debugging purposes 42 1, // flow control 43 NULL, 44 }; 45 46 /** 47 * \brief Handler for System Tick interrupt. 48 */ 49 void SysTick_Handler(void) 50 { 51 tick_handler(); 52 } 53 54 /** 55 * Configure UART console. 56 */ 57 // [main_console_configure] 58 static void configure_console(void) 59 { 60 const usart_serial_options_t uart_serial_options = { 61 .baudrate = CONF_UART_BAUDRATE, 62 #ifdef CONF_UART_CHAR_LENGTH 63 .charlength = CONF_UART_CHAR_LENGTH, 64 #endif 65 .paritytype = CONF_UART_PARITY, 66 #ifdef CONF_UART_STOP_BITS 67 .stopbits = CONF_UART_STOP_BITS, 68 #endif 69 }; 70 71 /* Configure console UART. */ 72 sysclk_enable_peripheral_clock(CONSOLE_UART_ID); 73 stdio_serial_init(CONF_UART, &uart_serial_options); 74 } 75 76 // [main_console_configure] 77 78 /** 79 * \brief Wait for the given number of milliseconds (ticks 80 * generated by the SAM's microcontrollers's system tick). 81 * 82 * \param ul_dly_ticks Delay to wait for, in milliseconds. 83 */ 84 // [main_ms_delay] 85 static void mdelay(uint32_t delay_in_ms) 86 { 87 // delay_ms(delay_in_ms); 88 uint32_t time_to_wait = btstack_run_loop_get_time_ms() + delay_in_ms; 89 while (btstack_run_loop_get_time_ms() < time_to_wait); 90 } 91 // [main_ms_delay] 92 93 //////////////////////////////////////////////////////////////////////////////// 94 // hal_cpu.h implementation 95 //////////////////////////////////////////////////////////////////////////////// 96 // hal_led.h implementation 97 #include "hal_led.h" 98 void hal_led_off(void); 99 void hal_led_on(void); 100 101 void hal_led_off(void){ 102 // gpio_set_pin_low(GPIOA, GPIO_LED2); 103 } 104 void hal_led_on(void){ 105 // gpio_set_pin_high(GPIOA, GPIO_LED2); 106 } 107 void hal_led_toggle(void){ 108 // gpio_toggle_pin(GPIOA, GPIO_LED2); 109 } 110 111 // hal_cpu.h implementation 112 #include "hal_cpu.h" 113 114 void hal_cpu_disable_irqs(void){ 115 //__disable_irq(); 116 } 117 118 void hal_cpu_enable_irqs(void){ 119 // __enable_irq(); 120 } 121 122 void hal_cpu_enable_irqs_and_sleep(void){ 123 hal_led_off(); 124 // __enable_irq(); 125 // __asm__("wfe"); // go to sleep if event flag isn't set. if set, just clear it. IRQs set event flag 126 127 // note: hal_uart_needed_during_sleep can be used to disable peripheral clock if it's not needed for a timer 128 hal_led_on(); 129 } 130 131 132 #ifndef USE_XDMAC_FOR_USART 133 // RX state 134 static volatile uint16_t bytes_to_read = 0; 135 static volatile uint8_t * rx_buffer_ptr = 0; 136 137 // TX state 138 static volatile uint16_t bytes_to_write = 0; 139 static volatile uint8_t * tx_buffer_ptr = 0; 140 #endif 141 142 // handlers 143 static void (*rx_done_handler)(void) = dummy_handler; 144 static void (*tx_done_handler)(void) = dummy_handler; 145 static void (*cts_irq_handler)(void) = dummy_handler; 146 147 // @note While the Atmel SAM S7x data sheet states 148 // "The hardware handshaking feature enables an out-of-band flow control by automatic management 149 // of the pins RTS and CTS.", 150 // I didn't see RTS going up automatically up, ever. So, at least for RTS, the automatic management 151 // is just a glorified GPIO pin control feature, which provides no benefit, but irritates a lot 152 153 static void hal_uart_rts_high(void){ 154 BOARD_USART->US_CR = US_CR_RTSEN; 155 } 156 static void hal_uart_rts_low(void){ 157 BOARD_USART->US_CR = US_CR_RTSDIS; 158 } 159 160 /** 161 */ 162 void hal_uart_dma_init(void) 163 { 164 // power on 165 ioport_set_pin_dir(BLUETOOTH_CHP_EN, IOPORT_DIR_OUTPUT); 166 ioport_set_pin_level(BLUETOOTH_CHP_EN, IOPORT_PIN_LEVEL_HIGH); 167 168 // reset 169 ioport_set_pin_dir(BLUETOOTH_RESET, IOPORT_DIR_OUTPUT); 170 ioport_set_pin_level(BLUETOOTH_RESET, IOPORT_PIN_LEVEL_LOW); 171 mdelay(250); 172 ioport_set_pin_level(BLUETOOTH_RESET, IOPORT_PIN_LEVEL_HIGH); 173 mdelay(250); 174 175 /* Enable the peripheral clock in the PMC. */ 176 sysclk_enable_peripheral_clock(BOARD_ID_USART); 177 178 // configure Bluetooth USART 179 const sam_usart_opt_t bluetooth_settings = { 180 115200, 181 US_MR_CHRL_8_BIT, 182 US_MR_PAR_NO, 183 US_MR_NBSTOP_1_BIT, 184 US_MR_CHMODE_NORMAL, 185 /* This field is only used in IrDA mode. */ 186 0 187 }; 188 189 /* Configure USART mode. */ 190 #if 0 191 usart_init_hw_handshaking(BOARD_USART, &bluetooth_settings, sysclk_get_peripheral_hz()); 192 hal_uart_rts_low(); 193 #else 194 usart_init_rs232(BOARD_USART, &bluetooth_settings, sysclk_get_peripheral_hz()); 195 #endif 196 197 /* Disable all the interrupts. */ 198 usart_disable_interrupt(BOARD_USART, ALL_INTERRUPT_MASK); 199 200 /* Enable TX & RX function. */ 201 usart_enable_tx(BOARD_USART); 202 usart_enable_rx(BOARD_USART); 203 204 /* Configure and enable interrupt of USART. */ 205 NVIC_EnableIRQ(USART_IRQn); 206 207 #ifdef USE_XDMAC_FOR_USART 208 209 // setup XDMAC 210 211 /* Initialize and enable DMA controller */ 212 pmc_enable_periph_clk(ID_XDMAC); 213 214 /* Enable XDMA interrupt */ 215 NVIC_ClearPendingIRQ(XDMAC_IRQn); 216 NVIC_SetPriority( XDMAC_IRQn ,1); 217 NVIC_EnableIRQ(XDMAC_IRQn); 218 219 // Setup XDMA Channel for USART TX 220 xdmac_channel_set_destination_addr(XDMAC, XDMA_CH_UART_TX, (uint32_t)&BOARD_USART->US_THR); 221 xdmac_channel_set_config(XDMAC, XDMA_CH_UART_TX, 222 XDMAC_CC_TYPE_PER_TRAN | 223 XDMAC_CC_DSYNC_MEM2PER | 224 XDMAC_CC_MEMSET_NORMAL_MODE | 225 XDMAC_CC_MBSIZE_SINGLE | 226 XDMAC_CC_DWIDTH_BYTE | 227 XDMAC_CC_SIF_AHB_IF0 | 228 XDMAC_CC_DIF_AHB_IF1 | 229 XDMAC_CC_SAM_INCREMENTED_AM | 230 XDMAC_CC_DAM_FIXED_AM | 231 XDMAC_CC_CSIZE_CHK_1 | 232 XDMAC_CC_PERID(XDAMC_CHANNEL_HWID_USART0_TX) 233 ); 234 xdmac_channel_set_descriptor_control(XDMAC, XDMA_CH_UART_TX, 0); 235 xdmac_channel_set_source_microblock_stride(XDMAC, XDMA_CH_UART_TX, 0); 236 xdmac_channel_set_destination_microblock_stride(XDMAC, XDMA_CH_UART_TX, 0); 237 xdmac_channel_set_datastride_mempattern(XDMAC, XDMA_CH_UART_TX, 0); 238 xdmac_channel_set_block_control(XDMAC, XDMA_CH_UART_TX, 0); 239 xdmac_enable_interrupt(XDMAC, XDMA_CH_UART_TX); 240 xdmac_channel_enable_interrupt(XDMAC, XDMA_CH_UART_TX, XDMAC_CIE_BIE); 241 242 // Setup XDMA Channel for USART RX 243 xdmac_channel_set_source_addr(XDMAC, XDMA_CH_UART_RX, (uint32_t)&BOARD_USART->US_RHR); 244 xdmac_channel_set_config(XDMAC, XDMA_CH_UART_RX, 245 XDMAC_CC_TYPE_PER_TRAN | 246 XDMAC_CC_DSYNC_PER2MEM | 247 XDMAC_CC_MEMSET_NORMAL_MODE | 248 XDMAC_CC_MBSIZE_SINGLE | 249 XDMAC_CC_DWIDTH_BYTE | 250 XDMAC_CC_SIF_AHB_IF1 | 251 XDMAC_CC_DIF_AHB_IF0 | 252 XDMAC_CC_SAM_FIXED_AM | 253 XDMAC_CC_DAM_INCREMENTED_AM | 254 XDMAC_CC_CSIZE_CHK_1 | 255 XDMAC_CC_PERID(XDAMC_CHANNEL_HWID_USART0_RX) 256 ); 257 xdmac_channel_set_descriptor_control(XDMAC, XDMA_CH_UART_RX, 0); 258 xdmac_channel_set_source_microblock_stride(XDMAC, XDMA_CH_UART_RX, 0); 259 xdmac_channel_set_destination_microblock_stride(XDMAC, XDMA_CH_UART_RX, 0); 260 xdmac_channel_set_datastride_mempattern(XDMAC, XDMA_CH_UART_RX, 0); 261 xdmac_channel_set_block_control(XDMAC, XDMA_CH_UART_RX, 0); 262 xdmac_enable_interrupt(XDMAC, XDMA_CH_UART_RX); 263 xdmac_channel_enable_interrupt(XDMAC, XDMA_CH_UART_RX, XDMAC_CIE_BIE); 264 #endif 265 } 266 267 void hal_uart_dma_set_sleep(uint8_t sleep){ 268 } 269 270 void hal_uart_dma_set_block_received( void (*the_block_handler)(void)){ 271 rx_done_handler = the_block_handler; 272 } 273 274 void hal_uart_dma_set_block_sent( void (*the_block_handler)(void)){ 275 tx_done_handler = the_block_handler; 276 } 277 278 void hal_uart_dma_set_csr_irq_handler( void (*the_irq_handler)(void)){ 279 cts_irq_handler = the_irq_handler; 280 } 281 282 int hal_uart_dma_set_baud(uint32_t baud){ 283 /* Disable TX & RX function. */ 284 usart_disable_tx(BOARD_USART); 285 usart_disable_rx(BOARD_USART); 286 uint32_t res = usart_set_async_baudrate(BOARD_USART, baud, sysclk_get_peripheral_hz()); 287 if (res){ 288 log_error("hal_uart_dma_set_baud library call failed"); 289 } 290 291 /* Enable TX & RX function. */ 292 usart_enable_tx(BOARD_USART); 293 usart_enable_rx(BOARD_USART); 294 295 log_info("set baud rate %u", (int) baud); 296 return 0; 297 } 298 299 int hal_uart_dma_set_flowcontrol(uint32_t flowcontrol){ 300 UNUSED(flowcontrol); 301 return 0; 302 } 303 304 void hal_uart_dma_send_block(const uint8_t *data, uint16_t size){ 305 // log_info("send %u", size); 306 // log_info_hexdump(data, size); 307 #ifdef USE_XDMAC_FOR_USART 308 xdmac_channel_get_interrupt_status( XDMAC, XDMA_CH_UART_TX); 309 xdmac_channel_set_source_addr(XDMAC, XDMA_CH_UART_TX, (uint32_t)data); 310 xdmac_channel_set_microblock_control(XDMAC, XDMA_CH_UART_TX, size); 311 xdmac_channel_enable(XDMAC, XDMA_CH_UART_TX); 312 #else 313 tx_buffer_ptr = (uint8_t *) data; 314 bytes_to_write = size; 315 usart_enable_interrupt(BOARD_USART, US_IER_TXRDY); 316 #endif 317 } 318 319 void hal_uart_dma_receive_block(uint8_t *data, uint16_t size){ 320 321 hal_uart_rts_low(); 322 323 #ifdef USE_XDMAC_FOR_USART 324 xdmac_channel_get_interrupt_status( XDMAC, XDMA_CH_UART_RX); 325 xdmac_channel_set_destination_addr(XDMAC, XDMA_CH_UART_RX, (uint32_t)data); 326 xdmac_channel_set_microblock_control(XDMAC, XDMA_CH_UART_RX, size); 327 xdmac_channel_enable(XDMAC, XDMA_CH_UART_RX); 328 #else 329 rx_buffer_ptr = data; 330 bytes_to_read = size; 331 usart_enable_interrupt(BOARD_USART, US_IER_RXRDY); 332 #endif 333 } 334 335 #ifdef USE_XDMAC_FOR_USART 336 void XDMAC_Handler(void) 337 { 338 uint32_t dma_status; 339 dma_status = xdmac_channel_get_interrupt_status(XDMAC, XDMA_CH_UART_TX); 340 if (dma_status & XDMAC_CIS_BIS) { 341 tx_done_handler(); 342 } 343 dma_status = xdmac_channel_get_interrupt_status(XDMAC, XDMA_CH_UART_RX); 344 if (dma_status & XDMAC_CIS_BIS) { 345 hal_uart_rts_high(); 346 rx_done_handler(); 347 } 348 } 349 #else 350 void USART_Handler(void) 351 { 352 uint32_t ul_status; 353 354 /* Read USART status. */ 355 ul_status = usart_get_status(BOARD_USART); 356 357 // handle ready to send 358 if(ul_status & US_IER_TXRDY) { 359 if (bytes_to_write){ 360 // send next byte 361 usart_write(BOARD_USART, *tx_buffer_ptr); 362 tx_buffer_ptr++; 363 bytes_to_write--; 364 } else { 365 // done. disable tx ready interrupt to avoid starvation here 366 usart_disable_interrupt(BOARD_USART, US_IER_TXRDY); 367 tx_done_handler(); 368 } 369 } 370 371 // handle byte available for read 372 if (ul_status & US_IER_RXRDY) { 373 uint32_t ch; 374 usart_read(BOARD_USART, (uint32_t *)&ch); 375 *rx_buffer_ptr++ = ch; 376 bytes_to_read--; 377 if (bytes_to_read == 0){ 378 // done. disable rx ready interrupt, raise RTS 379 hal_uart_rts_high(); 380 usart_disable_interrupt(BOARD_USART, US_IER_RXRDY); 381 rx_done_handler(); 382 } 383 } 384 } 385 #endif 386 387 void hal_tick_init() 388 { 389 /* Configure systick for 1 ms */ 390 puts("Configure system tick to get 1ms tick period.\r"); 391 if (SysTick_Config(sysclk_get_cpu_hz() / 1000)) { 392 puts("-F- Systick configuration error\r"); 393 while (1); 394 } 395 } 396 397 void hal_tick_set_handler(void (*handler)(void)){ 398 if (handler == NULL){ 399 tick_handler = &dummy_handler; 400 return; 401 } 402 tick_handler = handler; 403 } 404 405 int hal_tick_get_tick_period_in_ms(void){ 406 return 1; 407 } 408 409 static const btstack_uart_block_t * uart_driver; 410 411 static void phase2(int status){ 412 413 if (status){ 414 printf("Download firmware failed\n"); 415 return; 416 } 417 418 printf("Phase 2: Main app\n"); 419 420 // init HCI 421 const hci_transport_t * transport = hci_transport_h4_instance(uart_driver); 422 // const btstack_link_key_db_t * link_key_db = btstack_link_key_db_fs_instance(); 423 hci_init(transport, (void*) &transport_config); 424 hci_set_chipset(btstack_chipset_atwilc3000_instance()); 425 // hci_set_link_key_db(link_key_db); 426 427 // setup app 428 btstack_main(0, NULL); 429 } 430 431 /** 432 * \brief getting-started Application entry point. 433 * 434 * \return Unused (ANSI-C compatibility). 435 */ 436 // [main] 437 int main(void) 438 { 439 /* Initialize the SAM system */ 440 sysclk_init(); 441 board_init(); 442 443 /* Initialize the console uart */ 444 configure_console(); 445 446 /* Output boot info */ 447 printf("BTstack on SAMV71 Xplained Ultra with ATWILC3000\n"); 448 printf("CPU %lu hz, peripheral clock %lu hz\n", sysclk_get_cpu_hz(), sysclk_get_peripheral_hz()); 449 #ifdef USE_XDMAC_FOR_USART 450 printf("Using XDMA for Bluetooth UART\n"); 451 #else 452 printf("Using IRQ driver for Bluetooth UART\n"); 453 #endif 454 printf("--\n"); 455 456 // start with BTstack init - especially configure HCI Transport 457 btstack_memory_init(); 458 btstack_run_loop_init(btstack_run_loop_embedded_get_instance()); 459 460 // enable full log output while porting 461 hci_dump_open(NULL, HCI_DUMP_STDOUT); 462 463 // setup UART HAL + Run Loop integration 464 uart_driver = btstack_uart_block_embedded_instance(); 465 466 // extract UART config from transport config, but disable flow control 467 uart_config.baudrate = transport_config.baudrate_init; 468 uart_config.flowcontrol = 0; 469 uart_config.device_name = transport_config.device_name; 470 uart_driver->init(&uart_config); 471 472 // phase #1 download firmware 473 printf("Phase 1: Download firmware\n"); 474 475 // phase #2 start main app 476 btstack_chipset_atwilc3000_download_firmware(uart_driver, transport_config.baudrate_main, transport_config.flowcontrol, atwilc3000_fw_data, atwilc3000_fw_size, &phase2); 477 478 // go 479 btstack_run_loop_execute(); 480 481 // compiler happy 482 while(1); 483 } 484 #ifdef __cplusplus 485 } 486 #endif 487