11b2596b5SMatthias Ringwald #include "asf.h" 21b2596b5SMatthias Ringwald #include "stdio_serial.h" 31b2596b5SMatthias Ringwald #include "conf_board.h" 41b2596b5SMatthias Ringwald #include "conf_clock.h" 51b2596b5SMatthias Ringwald 658a1b1bbSMatthias Ringwald // BTstack 713b8e9b1SMatthias Ringwald #include "btstack_chipset_atwilc3000.h" 813b8e9b1SMatthias Ringwald #include "btstack_debug.h" 913b8e9b1SMatthias Ringwald #include "btstack_memory.h" 1058a1b1bbSMatthias Ringwald #include "btstack_run_loop.h" 1158a1b1bbSMatthias Ringwald #include "btstack_run_loop_embedded.h" 1258a1b1bbSMatthias Ringwald #include "classic/btstack_link_key_db.h" 1358a1b1bbSMatthias Ringwald #include "hal_uart_dma.h" 1458a1b1bbSMatthias Ringwald #include "hal_cpu.h" 1558a1b1bbSMatthias Ringwald #include "hal_tick.h" 1613b8e9b1SMatthias Ringwald #include "hci.h" 1713b8e9b1SMatthias Ringwald #include "hci_dump.h" 1813b8e9b1SMatthias Ringwald #include "wilc3000_bt_firmware.h" 1958a1b1bbSMatthias Ringwald 2013b8e9b1SMatthias Ringwald // #define USE_XDMAC_FOR_USART 2158a1b1bbSMatthias Ringwald #define XDMA_CH_UART_TX 0 2258a1b1bbSMatthias Ringwald #define XDMA_CH_UART_RX 1 231b2596b5SMatthias Ringwald 2458a1b1bbSMatthias Ringwald /** All interrupt mask. */ 2558a1b1bbSMatthias Ringwald #define ALL_INTERRUPT_MASK 0xffffffff 261b2596b5SMatthias Ringwald 271b2596b5SMatthias Ringwald #ifdef __cplusplus 281b2596b5SMatthias Ringwald extern "C" { 291b2596b5SMatthias Ringwald #endif 3013b8e9b1SMatthias Ringwald 3113b8e9b1SMatthias Ringwald extern int btstack_main(int argc, const char * argv[]); 3213b8e9b1SMatthias Ringwald 3313b8e9b1SMatthias Ringwald static void dummy_handler(void){} 3413b8e9b1SMatthias Ringwald static void (*tick_handler)(void) = &dummy_handler; 3513b8e9b1SMatthias Ringwald 3613b8e9b1SMatthias Ringwald static btstack_uart_config_t uart_config; 3713b8e9b1SMatthias Ringwald 3813b8e9b1SMatthias Ringwald static hci_transport_config_uart_t transport_config = { 3913b8e9b1SMatthias Ringwald HCI_TRANSPORT_CONFIG_UART, 4013b8e9b1SMatthias Ringwald 115200, 4113b8e9b1SMatthias Ringwald 921600, // use 0 to skip baud rate change from 115200 to X for debugging purposes 4213b8e9b1SMatthias Ringwald 1, // flow control 4313b8e9b1SMatthias Ringwald NULL, 4413b8e9b1SMatthias Ringwald }; 451b2596b5SMatthias Ringwald 461b2596b5SMatthias Ringwald /** 471b2596b5SMatthias Ringwald * \brief Handler for System Tick interrupt. 481b2596b5SMatthias Ringwald */ 491b2596b5SMatthias Ringwald void SysTick_Handler(void) 501b2596b5SMatthias Ringwald { 5158a1b1bbSMatthias Ringwald tick_handler(); 521b2596b5SMatthias Ringwald } 531b2596b5SMatthias Ringwald 541b2596b5SMatthias Ringwald /** 551b2596b5SMatthias Ringwald * Configure UART console. 561b2596b5SMatthias Ringwald */ 571b2596b5SMatthias Ringwald // [main_console_configure] 581b2596b5SMatthias Ringwald static void configure_console(void) 591b2596b5SMatthias Ringwald { 601b2596b5SMatthias Ringwald const usart_serial_options_t uart_serial_options = { 611b2596b5SMatthias Ringwald .baudrate = CONF_UART_BAUDRATE, 621b2596b5SMatthias Ringwald #ifdef CONF_UART_CHAR_LENGTH 631b2596b5SMatthias Ringwald .charlength = CONF_UART_CHAR_LENGTH, 641b2596b5SMatthias Ringwald #endif 651b2596b5SMatthias Ringwald .paritytype = CONF_UART_PARITY, 661b2596b5SMatthias Ringwald #ifdef CONF_UART_STOP_BITS 671b2596b5SMatthias Ringwald .stopbits = CONF_UART_STOP_BITS, 681b2596b5SMatthias Ringwald #endif 691b2596b5SMatthias Ringwald }; 701b2596b5SMatthias Ringwald 711b2596b5SMatthias Ringwald /* Configure console UART. */ 721b2596b5SMatthias Ringwald sysclk_enable_peripheral_clock(CONSOLE_UART_ID); 731b2596b5SMatthias Ringwald stdio_serial_init(CONF_UART, &uart_serial_options); 741b2596b5SMatthias Ringwald } 751b2596b5SMatthias Ringwald 761b2596b5SMatthias Ringwald // [main_console_configure] 771b2596b5SMatthias Ringwald 781b2596b5SMatthias Ringwald /** 7958a1b1bbSMatthias Ringwald * \brief Wait for the given number of milliseconds (ticks 801b2596b5SMatthias Ringwald * generated by the SAM's microcontrollers's system tick). 811b2596b5SMatthias Ringwald * 821b2596b5SMatthias Ringwald * \param ul_dly_ticks Delay to wait for, in milliseconds. 831b2596b5SMatthias Ringwald */ 841b2596b5SMatthias Ringwald // [main_ms_delay] 8558a1b1bbSMatthias Ringwald static void mdelay(uint32_t delay_in_ms) 861b2596b5SMatthias Ringwald { 8758a1b1bbSMatthias Ringwald // delay_ms(delay_in_ms); 8858a1b1bbSMatthias Ringwald uint32_t time_to_wait = btstack_run_loop_get_time_ms() + delay_in_ms; 8958a1b1bbSMatthias Ringwald while (btstack_run_loop_get_time_ms() < time_to_wait); 901b2596b5SMatthias Ringwald } 911b2596b5SMatthias Ringwald // [main_ms_delay] 921b2596b5SMatthias Ringwald 9358a1b1bbSMatthias Ringwald //////////////////////////////////////////////////////////////////////////////// 9458a1b1bbSMatthias Ringwald // hal_cpu.h implementation 9558a1b1bbSMatthias Ringwald //////////////////////////////////////////////////////////////////////////////// 9658a1b1bbSMatthias Ringwald // hal_led.h implementation 9758a1b1bbSMatthias Ringwald #include "hal_led.h" 9858a1b1bbSMatthias Ringwald void hal_led_off(void); 9958a1b1bbSMatthias Ringwald void hal_led_on(void); 10058a1b1bbSMatthias Ringwald 10158a1b1bbSMatthias Ringwald void hal_led_off(void){ 10258a1b1bbSMatthias Ringwald // gpio_set_pin_low(GPIOA, GPIO_LED2); 10358a1b1bbSMatthias Ringwald } 10458a1b1bbSMatthias Ringwald void hal_led_on(void){ 10558a1b1bbSMatthias Ringwald // gpio_set_pin_high(GPIOA, GPIO_LED2); 10658a1b1bbSMatthias Ringwald } 10758a1b1bbSMatthias Ringwald void hal_led_toggle(void){ 10858a1b1bbSMatthias Ringwald // gpio_toggle_pin(GPIOA, GPIO_LED2); 10958a1b1bbSMatthias Ringwald } 11058a1b1bbSMatthias Ringwald 11158a1b1bbSMatthias Ringwald // hal_cpu.h implementation 11258a1b1bbSMatthias Ringwald #include "hal_cpu.h" 11358a1b1bbSMatthias Ringwald 11458a1b1bbSMatthias Ringwald void hal_cpu_disable_irqs(void){ 11558a1b1bbSMatthias Ringwald //__disable_irq(); 11658a1b1bbSMatthias Ringwald } 11758a1b1bbSMatthias Ringwald 11858a1b1bbSMatthias Ringwald void hal_cpu_enable_irqs(void){ 11958a1b1bbSMatthias Ringwald // __enable_irq(); 12058a1b1bbSMatthias Ringwald } 12158a1b1bbSMatthias Ringwald 12258a1b1bbSMatthias Ringwald void hal_cpu_enable_irqs_and_sleep(void){ 12358a1b1bbSMatthias Ringwald hal_led_off(); 12458a1b1bbSMatthias Ringwald // __enable_irq(); 12558a1b1bbSMatthias Ringwald // __asm__("wfe"); // go to sleep if event flag isn't set. if set, just clear it. IRQs set event flag 12658a1b1bbSMatthias Ringwald 12758a1b1bbSMatthias Ringwald // note: hal_uart_needed_during_sleep can be used to disable peripheral clock if it's not needed for a timer 12858a1b1bbSMatthias Ringwald hal_led_on(); 12958a1b1bbSMatthias Ringwald } 13058a1b1bbSMatthias Ringwald 13158a1b1bbSMatthias Ringwald 13258a1b1bbSMatthias Ringwald #ifndef USE_XDMAC_FOR_USART 13358a1b1bbSMatthias Ringwald // RX state 13458a1b1bbSMatthias Ringwald static volatile uint16_t bytes_to_read = 0; 13558a1b1bbSMatthias Ringwald static volatile uint8_t * rx_buffer_ptr = 0; 13658a1b1bbSMatthias Ringwald 13758a1b1bbSMatthias Ringwald // TX state 13858a1b1bbSMatthias Ringwald static volatile uint16_t bytes_to_write = 0; 13958a1b1bbSMatthias Ringwald static volatile uint8_t * tx_buffer_ptr = 0; 140*67422dbdSMatthias Ringwald static volatile int tx_notify; 14158a1b1bbSMatthias Ringwald #endif 14258a1b1bbSMatthias Ringwald 143c267d18bSMatthias Ringwald static int simulate_flowcontrol; 144c267d18bSMatthias Ringwald 14558a1b1bbSMatthias Ringwald // handlers 14658a1b1bbSMatthias Ringwald static void (*rx_done_handler)(void) = dummy_handler; 14758a1b1bbSMatthias Ringwald static void (*tx_done_handler)(void) = dummy_handler; 14858a1b1bbSMatthias Ringwald static void (*cts_irq_handler)(void) = dummy_handler; 14958a1b1bbSMatthias Ringwald 15058a1b1bbSMatthias Ringwald // @note While the Atmel SAM S7x data sheet states 15158a1b1bbSMatthias Ringwald // "The hardware handshaking feature enables an out-of-band flow control by automatic management 15258a1b1bbSMatthias Ringwald // of the pins RTS and CTS.", 15358a1b1bbSMatthias Ringwald // I didn't see RTS going up automatically up, ever. So, at least for RTS, the automatic management 15458a1b1bbSMatthias Ringwald // is just a glorified GPIO pin control feature, which provides no benefit, but irritates a lot 15558a1b1bbSMatthias Ringwald 156c267d18bSMatthias Ringwald static inline void hal_uart_rts_high(void){ 157c267d18bSMatthias Ringwald if (!simulate_flowcontrol) return; 15858a1b1bbSMatthias Ringwald BOARD_USART->US_CR = US_CR_RTSEN; 15958a1b1bbSMatthias Ringwald } 160c267d18bSMatthias Ringwald static inline void hal_uart_rts_low(void){ 161c267d18bSMatthias Ringwald if (!simulate_flowcontrol) return; 16258a1b1bbSMatthias Ringwald BOARD_USART->US_CR = US_CR_RTSDIS; 16358a1b1bbSMatthias Ringwald } 16458a1b1bbSMatthias Ringwald 165*67422dbdSMatthias Ringwald // J505:6 166*67422dbdSMatthias Ringwald // #define DEBUG_PIN_1 PIO_PD16_IDX 167*67422dbdSMatthias Ringwald // J505:5 168*67422dbdSMatthias Ringwald // #define DEBUG_PIN_2 PIO_PD15_IDX 169*67422dbdSMatthias Ringwald 17058a1b1bbSMatthias Ringwald /** 17158a1b1bbSMatthias Ringwald */ 17258a1b1bbSMatthias Ringwald void hal_uart_dma_init(void) 17358a1b1bbSMatthias Ringwald { 174*67422dbdSMatthias Ringwald 175*67422dbdSMatthias Ringwald // debug 176*67422dbdSMatthias Ringwald #ifdef DEBUG_PIN_1 177*67422dbdSMatthias Ringwald ioport_set_pin_dir(DEBUG_PIN_1, IOPORT_DIR_OUTPUT); 178*67422dbdSMatthias Ringwald ioport_set_pin_level(DEBUG_PIN_1, IOPORT_PIN_LEVEL_LOW); 179*67422dbdSMatthias Ringwald #endif 180*67422dbdSMatthias Ringwald #ifdef DEBUG_PIN_2 181*67422dbdSMatthias Ringwald ioport_set_pin_dir(DEBUG_PIN_2, IOPORT_DIR_OUTPUT); 182*67422dbdSMatthias Ringwald ioport_set_pin_level(DEBUG_PIN_2, IOPORT_PIN_LEVEL_LOW); 183*67422dbdSMatthias Ringwald #endif 18413b8e9b1SMatthias Ringwald // power on 18513b8e9b1SMatthias Ringwald ioport_set_pin_dir(BLUETOOTH_CHP_EN, IOPORT_DIR_OUTPUT); 18613b8e9b1SMatthias Ringwald ioport_set_pin_level(BLUETOOTH_CHP_EN, IOPORT_PIN_LEVEL_HIGH); 18713b8e9b1SMatthias Ringwald 18813b8e9b1SMatthias Ringwald // reset 18913b8e9b1SMatthias Ringwald ioport_set_pin_dir(BLUETOOTH_RESET, IOPORT_DIR_OUTPUT); 19013b8e9b1SMatthias Ringwald ioport_set_pin_level(BLUETOOTH_RESET, IOPORT_PIN_LEVEL_LOW); 19113b8e9b1SMatthias Ringwald mdelay(250); 19213b8e9b1SMatthias Ringwald ioport_set_pin_level(BLUETOOTH_RESET, IOPORT_PIN_LEVEL_HIGH); 19313b8e9b1SMatthias Ringwald mdelay(250); 19413b8e9b1SMatthias Ringwald 19513b8e9b1SMatthias Ringwald /* Enable the peripheral clock in the PMC. */ 19613b8e9b1SMatthias Ringwald sysclk_enable_peripheral_clock(BOARD_ID_USART); 19758a1b1bbSMatthias Ringwald 19858a1b1bbSMatthias Ringwald // configure Bluetooth USART 19958a1b1bbSMatthias Ringwald const sam_usart_opt_t bluetooth_settings = { 20058a1b1bbSMatthias Ringwald 115200, 20158a1b1bbSMatthias Ringwald US_MR_CHRL_8_BIT, 20258a1b1bbSMatthias Ringwald US_MR_PAR_NO, 20358a1b1bbSMatthias Ringwald US_MR_NBSTOP_1_BIT, 20458a1b1bbSMatthias Ringwald US_MR_CHMODE_NORMAL, 20558a1b1bbSMatthias Ringwald /* This field is only used in IrDA mode. */ 20658a1b1bbSMatthias Ringwald 0 20758a1b1bbSMatthias Ringwald }; 20858a1b1bbSMatthias Ringwald 20958a1b1bbSMatthias Ringwald /* Configure USART mode. */ 210c267d18bSMatthias Ringwald simulate_flowcontrol = 0; 21113b8e9b1SMatthias Ringwald usart_init_rs232(BOARD_USART, &bluetooth_settings, sysclk_get_peripheral_hz()); 212c267d18bSMatthias Ringwald // Set RTS = 0 (normal mode) 213c267d18bSMatthias Ringwald BOARD_USART->US_CR = US_CR_RTSEN; 21458a1b1bbSMatthias Ringwald 21558a1b1bbSMatthias Ringwald /* Disable all the interrupts. */ 21658a1b1bbSMatthias Ringwald usart_disable_interrupt(BOARD_USART, ALL_INTERRUPT_MASK); 21758a1b1bbSMatthias Ringwald 21858a1b1bbSMatthias Ringwald /* Enable TX & RX function. */ 21958a1b1bbSMatthias Ringwald usart_enable_tx(BOARD_USART); 22058a1b1bbSMatthias Ringwald usart_enable_rx(BOARD_USART); 22158a1b1bbSMatthias Ringwald 22258a1b1bbSMatthias Ringwald /* Configure and enable interrupt of USART. */ 22358a1b1bbSMatthias Ringwald NVIC_EnableIRQ(USART_IRQn); 22458a1b1bbSMatthias Ringwald 22558a1b1bbSMatthias Ringwald #ifdef USE_XDMAC_FOR_USART 22658a1b1bbSMatthias Ringwald 22758a1b1bbSMatthias Ringwald // setup XDMAC 22858a1b1bbSMatthias Ringwald 22958a1b1bbSMatthias Ringwald /* Initialize and enable DMA controller */ 23058a1b1bbSMatthias Ringwald pmc_enable_periph_clk(ID_XDMAC); 23158a1b1bbSMatthias Ringwald 23258a1b1bbSMatthias Ringwald /* Enable XDMA interrupt */ 23358a1b1bbSMatthias Ringwald NVIC_ClearPendingIRQ(XDMAC_IRQn); 23458a1b1bbSMatthias Ringwald NVIC_SetPriority( XDMAC_IRQn ,1); 23558a1b1bbSMatthias Ringwald NVIC_EnableIRQ(XDMAC_IRQn); 23658a1b1bbSMatthias Ringwald 23758a1b1bbSMatthias Ringwald // Setup XDMA Channel for USART TX 23858a1b1bbSMatthias Ringwald xdmac_channel_set_destination_addr(XDMAC, XDMA_CH_UART_TX, (uint32_t)&BOARD_USART->US_THR); 23958a1b1bbSMatthias Ringwald xdmac_channel_set_config(XDMAC, XDMA_CH_UART_TX, 24058a1b1bbSMatthias Ringwald XDMAC_CC_TYPE_PER_TRAN | 24158a1b1bbSMatthias Ringwald XDMAC_CC_DSYNC_MEM2PER | 24258a1b1bbSMatthias Ringwald XDMAC_CC_MEMSET_NORMAL_MODE | 24358a1b1bbSMatthias Ringwald XDMAC_CC_MBSIZE_SINGLE | 24458a1b1bbSMatthias Ringwald XDMAC_CC_DWIDTH_BYTE | 24558a1b1bbSMatthias Ringwald XDMAC_CC_SIF_AHB_IF0 | 24658a1b1bbSMatthias Ringwald XDMAC_CC_DIF_AHB_IF1 | 24758a1b1bbSMatthias Ringwald XDMAC_CC_SAM_INCREMENTED_AM | 24858a1b1bbSMatthias Ringwald XDMAC_CC_DAM_FIXED_AM | 24958a1b1bbSMatthias Ringwald XDMAC_CC_CSIZE_CHK_1 | 25058a1b1bbSMatthias Ringwald XDMAC_CC_PERID(XDAMC_CHANNEL_HWID_USART0_TX) 25158a1b1bbSMatthias Ringwald ); 25258a1b1bbSMatthias Ringwald xdmac_channel_set_descriptor_control(XDMAC, XDMA_CH_UART_TX, 0); 25358a1b1bbSMatthias Ringwald xdmac_channel_set_source_microblock_stride(XDMAC, XDMA_CH_UART_TX, 0); 25458a1b1bbSMatthias Ringwald xdmac_channel_set_destination_microblock_stride(XDMAC, XDMA_CH_UART_TX, 0); 25558a1b1bbSMatthias Ringwald xdmac_channel_set_datastride_mempattern(XDMAC, XDMA_CH_UART_TX, 0); 25658a1b1bbSMatthias Ringwald xdmac_channel_set_block_control(XDMAC, XDMA_CH_UART_TX, 0); 25758a1b1bbSMatthias Ringwald xdmac_enable_interrupt(XDMAC, XDMA_CH_UART_TX); 25858a1b1bbSMatthias Ringwald xdmac_channel_enable_interrupt(XDMAC, XDMA_CH_UART_TX, XDMAC_CIE_BIE); 25958a1b1bbSMatthias Ringwald 26058a1b1bbSMatthias Ringwald // Setup XDMA Channel for USART RX 26158a1b1bbSMatthias Ringwald xdmac_channel_set_source_addr(XDMAC, XDMA_CH_UART_RX, (uint32_t)&BOARD_USART->US_RHR); 26258a1b1bbSMatthias Ringwald xdmac_channel_set_config(XDMAC, XDMA_CH_UART_RX, 26358a1b1bbSMatthias Ringwald XDMAC_CC_TYPE_PER_TRAN | 26458a1b1bbSMatthias Ringwald XDMAC_CC_DSYNC_PER2MEM | 26558a1b1bbSMatthias Ringwald XDMAC_CC_MEMSET_NORMAL_MODE | 26658a1b1bbSMatthias Ringwald XDMAC_CC_MBSIZE_SINGLE | 26758a1b1bbSMatthias Ringwald XDMAC_CC_DWIDTH_BYTE | 26858a1b1bbSMatthias Ringwald XDMAC_CC_SIF_AHB_IF1 | 26958a1b1bbSMatthias Ringwald XDMAC_CC_DIF_AHB_IF0 | 27058a1b1bbSMatthias Ringwald XDMAC_CC_SAM_FIXED_AM | 27158a1b1bbSMatthias Ringwald XDMAC_CC_DAM_INCREMENTED_AM | 27258a1b1bbSMatthias Ringwald XDMAC_CC_CSIZE_CHK_1 | 27358a1b1bbSMatthias Ringwald XDMAC_CC_PERID(XDAMC_CHANNEL_HWID_USART0_RX) 27458a1b1bbSMatthias Ringwald ); 27558a1b1bbSMatthias Ringwald xdmac_channel_set_descriptor_control(XDMAC, XDMA_CH_UART_RX, 0); 27658a1b1bbSMatthias Ringwald xdmac_channel_set_source_microblock_stride(XDMAC, XDMA_CH_UART_RX, 0); 27758a1b1bbSMatthias Ringwald xdmac_channel_set_destination_microblock_stride(XDMAC, XDMA_CH_UART_RX, 0); 27858a1b1bbSMatthias Ringwald xdmac_channel_set_datastride_mempattern(XDMAC, XDMA_CH_UART_RX, 0); 27958a1b1bbSMatthias Ringwald xdmac_channel_set_block_control(XDMAC, XDMA_CH_UART_RX, 0); 28058a1b1bbSMatthias Ringwald xdmac_enable_interrupt(XDMAC, XDMA_CH_UART_RX); 28158a1b1bbSMatthias Ringwald xdmac_channel_enable_interrupt(XDMAC, XDMA_CH_UART_RX, XDMAC_CIE_BIE); 28258a1b1bbSMatthias Ringwald #endif 28358a1b1bbSMatthias Ringwald } 28458a1b1bbSMatthias Ringwald 28558a1b1bbSMatthias Ringwald void hal_uart_dma_set_sleep(uint8_t sleep){ 28658a1b1bbSMatthias Ringwald } 28758a1b1bbSMatthias Ringwald 28858a1b1bbSMatthias Ringwald void hal_uart_dma_set_block_received( void (*the_block_handler)(void)){ 28958a1b1bbSMatthias Ringwald rx_done_handler = the_block_handler; 29058a1b1bbSMatthias Ringwald } 29158a1b1bbSMatthias Ringwald 29258a1b1bbSMatthias Ringwald void hal_uart_dma_set_block_sent( void (*the_block_handler)(void)){ 29358a1b1bbSMatthias Ringwald tx_done_handler = the_block_handler; 29458a1b1bbSMatthias Ringwald } 29558a1b1bbSMatthias Ringwald 29658a1b1bbSMatthias Ringwald void hal_uart_dma_set_csr_irq_handler( void (*the_irq_handler)(void)){ 29758a1b1bbSMatthias Ringwald cts_irq_handler = the_irq_handler; 29858a1b1bbSMatthias Ringwald } 29958a1b1bbSMatthias Ringwald 30058a1b1bbSMatthias Ringwald int hal_uart_dma_set_baud(uint32_t baud){ 30158a1b1bbSMatthias Ringwald /* Disable TX & RX function. */ 30258a1b1bbSMatthias Ringwald usart_disable_tx(BOARD_USART); 30358a1b1bbSMatthias Ringwald usart_disable_rx(BOARD_USART); 30458a1b1bbSMatthias Ringwald uint32_t res = usart_set_async_baudrate(BOARD_USART, baud, sysclk_get_peripheral_hz()); 30558a1b1bbSMatthias Ringwald if (res){ 30658a1b1bbSMatthias Ringwald log_error("hal_uart_dma_set_baud library call failed"); 30758a1b1bbSMatthias Ringwald } 30858a1b1bbSMatthias Ringwald 30958a1b1bbSMatthias Ringwald /* Enable TX & RX function. */ 31058a1b1bbSMatthias Ringwald usart_enable_tx(BOARD_USART); 31158a1b1bbSMatthias Ringwald usart_enable_rx(BOARD_USART); 31258a1b1bbSMatthias Ringwald 31313b8e9b1SMatthias Ringwald log_info("set baud rate %u", (int) baud); 31413b8e9b1SMatthias Ringwald return 0; 31513b8e9b1SMatthias Ringwald } 31658a1b1bbSMatthias Ringwald 317c267d18bSMatthias Ringwald int hal_uart_dma_set_flowcontrol(int flowcontrol){ 318c267d18bSMatthias Ringwald simulate_flowcontrol = flowcontrol; 319c267d18bSMatthias Ringwald if (flowcontrol){ 320c267d18bSMatthias Ringwald /* Set hardware handshaking mode. */ 321c267d18bSMatthias Ringwald BOARD_USART->US_MR = (BOARD_USART->US_MR & ~US_MR_USART_MODE_Msk) | US_MR_USART_MODE_HW_HANDSHAKING; 322c267d18bSMatthias Ringwald hal_uart_rts_low(); 323c267d18bSMatthias Ringwald } else { 324c267d18bSMatthias Ringwald /* Set nomal mode. */ 325c267d18bSMatthias Ringwald BOARD_USART->US_MR = (BOARD_USART->US_MR & ~US_MR_USART_MODE_Msk) | US_MR_USART_MODE_NORMAL; 326c267d18bSMatthias Ringwald // Set RTS = 0 (normal mode) 327c267d18bSMatthias Ringwald BOARD_USART->US_CR = US_CR_RTSEN; 328c267d18bSMatthias Ringwald } 32958a1b1bbSMatthias Ringwald return 0; 33058a1b1bbSMatthias Ringwald } 33158a1b1bbSMatthias Ringwald 33258a1b1bbSMatthias Ringwald void hal_uart_dma_send_block(const uint8_t *data, uint16_t size){ 333*67422dbdSMatthias Ringwald 334*67422dbdSMatthias Ringwald #ifdef DEBUG_PIN_1 335*67422dbdSMatthias Ringwald ioport_set_pin_level(DEBUG_PIN_1, IOPORT_PIN_LEVEL_HIGH); 336*67422dbdSMatthias Ringwald #endif 337*67422dbdSMatthias Ringwald 338*67422dbdSMatthias Ringwald tx_notify = 1; 339*67422dbdSMatthias Ringwald 34058a1b1bbSMatthias Ringwald #ifdef USE_XDMAC_FOR_USART 34158a1b1bbSMatthias Ringwald xdmac_channel_get_interrupt_status( XDMAC, XDMA_CH_UART_TX); 34258a1b1bbSMatthias Ringwald xdmac_channel_set_source_addr(XDMAC, XDMA_CH_UART_TX, (uint32_t)data); 34358a1b1bbSMatthias Ringwald xdmac_channel_set_microblock_control(XDMAC, XDMA_CH_UART_TX, size); 34458a1b1bbSMatthias Ringwald xdmac_channel_enable(XDMAC, XDMA_CH_UART_TX); 34558a1b1bbSMatthias Ringwald #else 346*67422dbdSMatthias Ringwald if (bytes_to_write){ 347*67422dbdSMatthias Ringwald log_error("send block, bytes to write %u", bytes_to_write); 348*67422dbdSMatthias Ringwald return; 349*67422dbdSMatthias Ringwald } 35058a1b1bbSMatthias Ringwald tx_buffer_ptr = (uint8_t *) data; 35158a1b1bbSMatthias Ringwald bytes_to_write = size; 35258a1b1bbSMatthias Ringwald usart_enable_interrupt(BOARD_USART, US_IER_TXRDY); 35358a1b1bbSMatthias Ringwald #endif 35458a1b1bbSMatthias Ringwald } 35558a1b1bbSMatthias Ringwald 35658a1b1bbSMatthias Ringwald void hal_uart_dma_receive_block(uint8_t *data, uint16_t size){ 35758a1b1bbSMatthias Ringwald 35858a1b1bbSMatthias Ringwald hal_uart_rts_low(); 35958a1b1bbSMatthias Ringwald 36058a1b1bbSMatthias Ringwald #ifdef USE_XDMAC_FOR_USART 36158a1b1bbSMatthias Ringwald xdmac_channel_get_interrupt_status( XDMAC, XDMA_CH_UART_RX); 36258a1b1bbSMatthias Ringwald xdmac_channel_set_destination_addr(XDMAC, XDMA_CH_UART_RX, (uint32_t)data); 36358a1b1bbSMatthias Ringwald xdmac_channel_set_microblock_control(XDMAC, XDMA_CH_UART_RX, size); 36458a1b1bbSMatthias Ringwald xdmac_channel_enable(XDMAC, XDMA_CH_UART_RX); 36558a1b1bbSMatthias Ringwald #else 36658a1b1bbSMatthias Ringwald rx_buffer_ptr = data; 36758a1b1bbSMatthias Ringwald bytes_to_read = size; 36858a1b1bbSMatthias Ringwald usart_enable_interrupt(BOARD_USART, US_IER_RXRDY); 36958a1b1bbSMatthias Ringwald #endif 37058a1b1bbSMatthias Ringwald } 37158a1b1bbSMatthias Ringwald 37258a1b1bbSMatthias Ringwald #ifdef USE_XDMAC_FOR_USART 37358a1b1bbSMatthias Ringwald void XDMAC_Handler(void) 37458a1b1bbSMatthias Ringwald { 37558a1b1bbSMatthias Ringwald uint32_t dma_status; 37658a1b1bbSMatthias Ringwald dma_status = xdmac_channel_get_interrupt_status(XDMAC, XDMA_CH_UART_TX); 37758a1b1bbSMatthias Ringwald if (dma_status & XDMAC_CIS_BIS) { 378*67422dbdSMatthias Ringwald if (tx_notify){ 379*67422dbdSMatthias Ringwald tx_notify = 0; 38058a1b1bbSMatthias Ringwald tx_done_handler(); 38158a1b1bbSMatthias Ringwald } 382*67422dbdSMatthias Ringwald } 38358a1b1bbSMatthias Ringwald dma_status = xdmac_channel_get_interrupt_status(XDMAC, XDMA_CH_UART_RX); 38458a1b1bbSMatthias Ringwald if (dma_status & XDMAC_CIS_BIS) { 38558a1b1bbSMatthias Ringwald hal_uart_rts_high(); 38658a1b1bbSMatthias Ringwald rx_done_handler(); 38758a1b1bbSMatthias Ringwald } 38858a1b1bbSMatthias Ringwald } 38958a1b1bbSMatthias Ringwald #else 39058a1b1bbSMatthias Ringwald void USART_Handler(void) 39158a1b1bbSMatthias Ringwald { 392*67422dbdSMatthias Ringwald 393*67422dbdSMatthias Ringwald #ifdef DEBUG_PIN_2 394*67422dbdSMatthias Ringwald ioport_set_pin_level(DEBUG_PIN_2, IOPORT_PIN_LEVEL_HIGH); 395*67422dbdSMatthias Ringwald #endif 39658a1b1bbSMatthias Ringwald 39758a1b1bbSMatthias Ringwald /* Read USART status. */ 398*67422dbdSMatthias Ringwald uint32_t ul_status = usart_get_status(BOARD_USART); 39958a1b1bbSMatthias Ringwald 40058a1b1bbSMatthias Ringwald // handle ready to send 40158a1b1bbSMatthias Ringwald if(ul_status & US_IER_TXRDY) { 40258a1b1bbSMatthias Ringwald if (bytes_to_write){ 40358a1b1bbSMatthias Ringwald // send next byte 40458a1b1bbSMatthias Ringwald usart_write(BOARD_USART, *tx_buffer_ptr); 40558a1b1bbSMatthias Ringwald tx_buffer_ptr++; 40658a1b1bbSMatthias Ringwald bytes_to_write--; 40758a1b1bbSMatthias Ringwald } else { 408*67422dbdSMatthias Ringwald 409*67422dbdSMatthias Ringwald #ifdef DEBUG_PIN_1 410*67422dbdSMatthias Ringwald ioport_set_pin_level(DEBUG_PIN_1, IOPORT_PIN_LEVEL_LOW); 411*67422dbdSMatthias Ringwald #endif 41258a1b1bbSMatthias Ringwald // done. disable tx ready interrupt to avoid starvation here 41358a1b1bbSMatthias Ringwald usart_disable_interrupt(BOARD_USART, US_IER_TXRDY); 414*67422dbdSMatthias Ringwald if (tx_notify){ 415*67422dbdSMatthias Ringwald tx_notify = 0; 41658a1b1bbSMatthias Ringwald tx_done_handler(); 41758a1b1bbSMatthias Ringwald } 41858a1b1bbSMatthias Ringwald } 419*67422dbdSMatthias Ringwald } 42058a1b1bbSMatthias Ringwald 42158a1b1bbSMatthias Ringwald // handle byte available for read 42258a1b1bbSMatthias Ringwald if (ul_status & US_IER_RXRDY) { 4235c5e4857SMatthias Ringwald if (bytes_to_read){ 42458a1b1bbSMatthias Ringwald uint32_t ch; 42558a1b1bbSMatthias Ringwald usart_read(BOARD_USART, (uint32_t *)&ch); 42658a1b1bbSMatthias Ringwald *rx_buffer_ptr++ = ch; 42758a1b1bbSMatthias Ringwald bytes_to_read--; 42858a1b1bbSMatthias Ringwald if (bytes_to_read == 0){ 42958a1b1bbSMatthias Ringwald // done. disable rx ready interrupt, raise RTS 43058a1b1bbSMatthias Ringwald hal_uart_rts_high(); 43158a1b1bbSMatthias Ringwald usart_disable_interrupt(BOARD_USART, US_IER_RXRDY); 43258a1b1bbSMatthias Ringwald rx_done_handler(); 43358a1b1bbSMatthias Ringwald } 4345c5e4857SMatthias Ringwald } else { 4355c5e4857SMatthias Ringwald // shoult not happen, disable irq anyway 4365c5e4857SMatthias Ringwald usart_disable_interrupt(BOARD_USART, US_IER_RXRDY); 4375c5e4857SMatthias Ringwald } 43858a1b1bbSMatthias Ringwald } 439*67422dbdSMatthias Ringwald #ifdef DEBUG_PIN_2 440*67422dbdSMatthias Ringwald ioport_set_pin_level(DEBUG_PIN_2, IOPORT_PIN_LEVEL_LOW); 441*67422dbdSMatthias Ringwald #endif 442*67422dbdSMatthias Ringwald 44358a1b1bbSMatthias Ringwald } 44458a1b1bbSMatthias Ringwald #endif 44558a1b1bbSMatthias Ringwald 44658a1b1bbSMatthias Ringwald void hal_tick_init() 44758a1b1bbSMatthias Ringwald { 44858a1b1bbSMatthias Ringwald /* Configure systick for 1 ms */ 44958a1b1bbSMatthias Ringwald puts("Configure system tick to get 1ms tick period.\r"); 45058a1b1bbSMatthias Ringwald if (SysTick_Config(sysclk_get_cpu_hz() / 1000)) { 45158a1b1bbSMatthias Ringwald puts("-F- Systick configuration error\r"); 45258a1b1bbSMatthias Ringwald while (1); 45358a1b1bbSMatthias Ringwald } 45458a1b1bbSMatthias Ringwald } 45558a1b1bbSMatthias Ringwald 45658a1b1bbSMatthias Ringwald void hal_tick_set_handler(void (*handler)(void)){ 45758a1b1bbSMatthias Ringwald if (handler == NULL){ 45858a1b1bbSMatthias Ringwald tick_handler = &dummy_handler; 45958a1b1bbSMatthias Ringwald return; 46058a1b1bbSMatthias Ringwald } 46158a1b1bbSMatthias Ringwald tick_handler = handler; 46258a1b1bbSMatthias Ringwald } 46358a1b1bbSMatthias Ringwald 46458a1b1bbSMatthias Ringwald int hal_tick_get_tick_period_in_ms(void){ 46558a1b1bbSMatthias Ringwald return 1; 46658a1b1bbSMatthias Ringwald } 46758a1b1bbSMatthias Ringwald 46813b8e9b1SMatthias Ringwald static const btstack_uart_block_t * uart_driver; 46913b8e9b1SMatthias Ringwald 47013b8e9b1SMatthias Ringwald static void phase2(int status){ 47113b8e9b1SMatthias Ringwald 47213b8e9b1SMatthias Ringwald if (status){ 47313b8e9b1SMatthias Ringwald printf("Download firmware failed\n"); 47413b8e9b1SMatthias Ringwald return; 47513b8e9b1SMatthias Ringwald } 47613b8e9b1SMatthias Ringwald 47713b8e9b1SMatthias Ringwald printf("Phase 2: Main app\n"); 47813b8e9b1SMatthias Ringwald 47913b8e9b1SMatthias Ringwald // init HCI 48013b8e9b1SMatthias Ringwald const hci_transport_t * transport = hci_transport_h4_instance(uart_driver); 48113b8e9b1SMatthias Ringwald // const btstack_link_key_db_t * link_key_db = btstack_link_key_db_fs_instance(); 48213b8e9b1SMatthias Ringwald hci_init(transport, (void*) &transport_config); 48313b8e9b1SMatthias Ringwald hci_set_chipset(btstack_chipset_atwilc3000_instance()); 48413b8e9b1SMatthias Ringwald // hci_set_link_key_db(link_key_db); 48513b8e9b1SMatthias Ringwald 48613b8e9b1SMatthias Ringwald // setup app 48713b8e9b1SMatthias Ringwald btstack_main(0, NULL); 48813b8e9b1SMatthias Ringwald } 48958a1b1bbSMatthias Ringwald 4901b2596b5SMatthias Ringwald /** 4911b2596b5SMatthias Ringwald * \brief getting-started Application entry point. 4921b2596b5SMatthias Ringwald * 4931b2596b5SMatthias Ringwald * \return Unused (ANSI-C compatibility). 4941b2596b5SMatthias Ringwald */ 4951b2596b5SMatthias Ringwald // [main] 4961b2596b5SMatthias Ringwald int main(void) 4971b2596b5SMatthias Ringwald { 4981b2596b5SMatthias Ringwald /* Initialize the SAM system */ 4991b2596b5SMatthias Ringwald sysclk_init(); 5001b2596b5SMatthias Ringwald board_init(); 5011b2596b5SMatthias Ringwald 5021b2596b5SMatthias Ringwald /* Initialize the console uart */ 5031b2596b5SMatthias Ringwald configure_console(); 5041b2596b5SMatthias Ringwald 50513b8e9b1SMatthias Ringwald /* Output boot info */ 50613b8e9b1SMatthias Ringwald printf("BTstack on SAMV71 Xplained Ultra with ATWILC3000\n"); 50758a1b1bbSMatthias Ringwald printf("CPU %lu hz, peripheral clock %lu hz\n", sysclk_get_cpu_hz(), sysclk_get_peripheral_hz()); 50813b8e9b1SMatthias Ringwald #ifdef USE_XDMAC_FOR_USART 50913b8e9b1SMatthias Ringwald printf("Using XDMA for Bluetooth UART\n"); 51013b8e9b1SMatthias Ringwald #else 51113b8e9b1SMatthias Ringwald printf("Using IRQ driver for Bluetooth UART\n"); 51213b8e9b1SMatthias Ringwald #endif 51313b8e9b1SMatthias Ringwald printf("--\n"); 51458a1b1bbSMatthias Ringwald 51558a1b1bbSMatthias Ringwald // start with BTstack init - especially configure HCI Transport 51658a1b1bbSMatthias Ringwald btstack_memory_init(); 51758a1b1bbSMatthias Ringwald btstack_run_loop_init(btstack_run_loop_embedded_get_instance()); 51858a1b1bbSMatthias Ringwald 51958a1b1bbSMatthias Ringwald // enable full log output while porting 52013b8e9b1SMatthias Ringwald hci_dump_open(NULL, HCI_DUMP_STDOUT); 52158a1b1bbSMatthias Ringwald 52213b8e9b1SMatthias Ringwald // setup UART HAL + Run Loop integration 52313b8e9b1SMatthias Ringwald uart_driver = btstack_uart_block_embedded_instance(); 52458a1b1bbSMatthias Ringwald 52513b8e9b1SMatthias Ringwald // extract UART config from transport config, but disable flow control 52613b8e9b1SMatthias Ringwald uart_config.baudrate = transport_config.baudrate_init; 52713b8e9b1SMatthias Ringwald uart_config.flowcontrol = 0; 52813b8e9b1SMatthias Ringwald uart_config.device_name = transport_config.device_name; 52913b8e9b1SMatthias Ringwald uart_driver->init(&uart_config); 53058a1b1bbSMatthias Ringwald 53113b8e9b1SMatthias Ringwald // phase #1 download firmware 53213b8e9b1SMatthias Ringwald printf("Phase 1: Download firmware\n"); 53313b8e9b1SMatthias Ringwald 53413b8e9b1SMatthias Ringwald // phase #2 start main app 53513b8e9b1SMatthias Ringwald btstack_chipset_atwilc3000_download_firmware(uart_driver, transport_config.baudrate_main, transport_config.flowcontrol, atwilc3000_fw_data, atwilc3000_fw_size, &phase2); 53658a1b1bbSMatthias Ringwald 53758a1b1bbSMatthias Ringwald // go 53858a1b1bbSMatthias Ringwald btstack_run_loop_execute(); 53958a1b1bbSMatthias Ringwald 54058a1b1bbSMatthias Ringwald // compiler happy 5411b2596b5SMatthias Ringwald while(1); 5421b2596b5SMatthias Ringwald } 5431b2596b5SMatthias Ringwald #ifdef __cplusplus 5441b2596b5SMatthias Ringwald } 5451b2596b5SMatthias Ringwald #endif 546