1 /** 2 * \file 3 * 4 * \brief Universal Synchronous Asynchronous Receiver Transmitter (USART) driver 5 * for SAM. 6 * 7 * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions are met: 15 * 16 * 1. Redistributions of source code must retain the above copyright notice, 17 * this list of conditions and the following disclaimer. 18 * 19 * 2. Redistributions in binary form must reproduce the above copyright notice, 20 * this list of conditions and the following disclaimer in the documentation 21 * and/or other materials provided with the distribution. 22 * 23 * 3. The name of Atmel may not be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * 4. This software may only be redistributed and used in connection with an 27 * Atmel microcontroller product. 28 * 29 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED 30 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 31 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 32 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR 33 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 37 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 38 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 * POSSIBILITY OF SUCH DAMAGE. 40 * 41 * \asf_license_stop 42 * 43 */ 44 /* 45 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> 46 */ 47 48 #include "usart.h" 49 50 /// @cond 0 51 /**INDENT-OFF**/ 52 #ifdef __cplusplus 53 extern "C" { 54 #endif 55 /**INDENT-ON**/ 56 /// @endcond 57 58 /** 59 * \defgroup sam_drivers_usart_group Universal Synchronous Asynchronous 60 * Receiver Transmitter (USART) 61 * 62 * The Universal Synchronous Asynchronous Receiver Transceiver (USART) 63 * provides one full duplex universal synchronous asynchronous serial link. 64 * Data frame format is widely programmable (data length, parity, number of 65 * stop bits) to support a maximum of standards. The receiver implements 66 * parity error, framing error and overrun error detection. The receiver 67 * time-out enables handling variable-length frames and the transmitter 68 * timeguard facilitates communications with slow remote devices. Multidrop 69 * communications are also supported through address bit handling in reception 70 * and transmission. The driver supports the following modes: 71 * RS232, RS485, SPI, IrDA, ISO7816, MODEM, Hardware handshaking and LIN. 72 * 73 * @{ 74 */ 75 76 /* The write protect key value. */ 77 #ifndef US_WPMR_WPKEY_PASSWD 78 #define US_WPMR_WPKEY_PASSWD US_WPMR_WPKEY(0x555341U) 79 #endif 80 81 #ifndef US_WPMR_WPKEY_PASSWD 82 # define US_WPMR_WPKEY_PASSWD US_WPMR_WPKEY(US_WPKEY_VALUE) 83 #endif 84 85 /* The CD value scope programmed in MR register. */ 86 #define MIN_CD_VALUE 0x01 87 #define MIN_CD_VALUE_SPI 0x04 88 #define MAX_CD_VALUE US_BRGR_CD_Msk 89 90 /* The receiver sampling divide of baudrate clock. */ 91 #define HIGH_FRQ_SAMPLE_DIV 16 92 #define LOW_FRQ_SAMPLE_DIV 8 93 94 /* Max transmitter timeguard. */ 95 #define MAX_TRAN_GUARD_TIME US_TTGR_TG_Msk 96 97 /* The non-existent parity error number. */ 98 #define USART_PARITY_ERROR 5 99 100 /* ISO7816 protocol type. */ 101 #define ISO7816_T_0 0 102 #define ISO7816_T_1 1 103 104 /** 105 * \brief Calculate a clock divider(CD) and a fractional part (FP) for the 106 * USART asynchronous modes to generate a baudrate as close as possible to 107 * the baudrate set point. 108 * 109 * \note Baud rate calculation: Baudrate = ul_mck/(Over * (CD + FP/8)) 110 * (Over being 16 or 8). The maximal oversampling is selected if it allows to 111 * generate a baudrate close to the set point. 112 * 113 * \param p_usart Pointer to a USART instance. 114 * \param baudrate Baud rate set point. 115 * \param ul_mck USART module input clock frequency. 116 * 117 * \retval 0 Baud rate is successfully initialized. 118 * \retval 1 Baud rate set point is out of range for the given input clock 119 * frequency. 120 */ 121 uint32_t usart_set_async_baudrate(Usart *p_usart, 122 uint32_t baudrate, uint32_t ul_mck) 123 { 124 uint32_t over; 125 uint32_t cd_fp; 126 uint32_t cd; 127 uint32_t fp; 128 129 /* Calculate the receiver sampling divide of baudrate clock. */ 130 if (ul_mck >= HIGH_FRQ_SAMPLE_DIV * baudrate) { 131 over = HIGH_FRQ_SAMPLE_DIV; 132 } else { 133 over = LOW_FRQ_SAMPLE_DIV; 134 } 135 136 /* Calculate clock divider according to the fraction calculated formula. */ 137 cd_fp = (8 * ul_mck + (over * baudrate) / 2) / (over * baudrate); 138 cd = cd_fp >> 3; 139 fp = cd_fp & 0x07; 140 if (cd < MIN_CD_VALUE || cd > MAX_CD_VALUE) { 141 return 1; 142 } 143 144 /* Configure the OVER bit in MR register. */ 145 if (over == 8) { 146 p_usart->US_MR |= US_MR_OVER; 147 } 148 149 /* Configure the baudrate generate register. */ 150 p_usart->US_BRGR = (cd << US_BRGR_CD_Pos) | (fp << US_BRGR_FP_Pos); 151 152 return 0; 153 } 154 155 /** 156 * \brief Calculate a clock divider for the USART synchronous master modes 157 * to generate a baudrate as close as possible to the baudrate set point. 158 * 159 * \note Synchronous baudrate calculation: baudrate = ul_mck / cd 160 * 161 * \param p_usart Pointer to a USART instance. 162 * \param baudrate Baud rate set point. 163 * \param ul_mck USART module input clock frequency. 164 * 165 * \retval 0 Baud rate is successfully initialized. 166 * \retval 1 Baud rate set point is out of range for the given input clock 167 * frequency. 168 */ 169 static uint32_t usart_set_sync_master_baudrate(Usart *p_usart, 170 uint32_t baudrate, uint32_t ul_mck) 171 { 172 uint32_t cd; 173 174 /* Calculate clock divider according to the formula in synchronous mode. */ 175 cd = (ul_mck + baudrate / 2) / baudrate; 176 177 if (cd < MIN_CD_VALUE || cd > MAX_CD_VALUE) { 178 return 1; 179 } 180 181 /* Configure the baudrate generate register. */ 182 p_usart->US_BRGR = cd << US_BRGR_CD_Pos; 183 184 p_usart->US_MR = (p_usart->US_MR & ~US_MR_USCLKS_Msk) | 185 US_MR_USCLKS_MCK | US_MR_SYNC; 186 return 0; 187 } 188 189 /** 190 * \brief Select the SCK pin as the source of baud rate for the USART 191 * synchronous slave modes. 192 * 193 * \param p_usart Pointer to a USART instance. 194 */ 195 static void usart_set_sync_slave_baudrate(Usart *p_usart) 196 { 197 p_usart->US_MR = (p_usart->US_MR & ~US_MR_USCLKS_Msk) | 198 US_MR_USCLKS_SCK | US_MR_SYNC; 199 } 200 201 /** 202 * \brief Calculate a clock divider (\e CD) for the USART SPI master mode to 203 * generate a baud rate as close as possible to the baud rate set point. 204 * 205 * \note Baud rate calculation: 206 * \f$ Baudrate = \frac{SelectedClock}{CD} \f$. 207 * 208 * \param p_usart Pointer to a USART instance. 209 * \param baudrate Baud rate set point. 210 * \param ul_mck USART module input clock frequency. 211 * 212 * \retval 0 Baud rate is successfully initialized. 213 * \retval 1 Baud rate set point is out of range for the given input clock 214 * frequency. 215 */ 216 static uint32_t usart_set_spi_master_baudrate(Usart *p_usart, 217 uint32_t baudrate, uint32_t ul_mck) 218 { 219 uint32_t cd; 220 221 /* Calculate the clock divider according to the formula in SPI mode. */ 222 cd = (ul_mck + baudrate / 2) / baudrate; 223 224 if (cd < MIN_CD_VALUE_SPI || cd > MAX_CD_VALUE) { 225 return 1; 226 } 227 228 p_usart->US_BRGR = cd << US_BRGR_CD_Pos; 229 230 return 0; 231 } 232 233 /** 234 * \brief Select the SCK pin as the source of baudrate for the USART SPI slave 235 * mode. 236 * 237 * \param p_usart Pointer to a USART instance. 238 */ 239 static void usart_set_spi_slave_baudrate(Usart *p_usart) 240 { 241 p_usart->US_MR &= ~US_MR_USCLKS_Msk; 242 p_usart->US_MR |= US_MR_USCLKS_SCK; 243 } 244 245 /** 246 * \brief Reset the USART and disable TX and RX. 247 * 248 * \param p_usart Pointer to a USART instance. 249 */ 250 void usart_reset(Usart *p_usart) 251 { 252 /* Disable the Write Protect. */ 253 usart_disable_writeprotect(p_usart); 254 255 /* Reset registers that could cause unpredictable behavior after reset. */ 256 p_usart->US_MR = 0; 257 p_usart->US_RTOR = 0; 258 p_usart->US_TTGR = 0; 259 260 /* Disable TX and RX. */ 261 usart_reset_tx(p_usart); 262 usart_reset_rx(p_usart); 263 /* Reset status bits. */ 264 usart_reset_status(p_usart); 265 /* Turn off RTS and DTR if exist. */ 266 usart_drive_RTS_pin_high(p_usart); 267 #if (SAM3S || SAM4S || SAM3U || SAM4L || SAM4E) 268 usart_drive_DTR_pin_high(p_usart); 269 #endif 270 } 271 272 /** 273 * \brief Configure USART to work in RS232 mode. 274 * 275 * \note By default, the transmitter and receiver aren't enabled. 276 * 277 * \param p_usart Pointer to a USART instance. 278 * \param p_usart_opt Pointer to sam_usart_opt_t instance. 279 * \param ul_mck USART module input clock frequency. 280 * 281 * \retval 0 on success. 282 * \retval 1 on failure. 283 */ 284 uint32_t usart_init_rs232(Usart *p_usart, 285 const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck) 286 { 287 static uint32_t ul_reg_val; 288 289 /* Reset the USART and shut down TX and RX. */ 290 usart_reset(p_usart); 291 292 ul_reg_val = 0; 293 /* Check whether the input values are legal. */ 294 if (!p_usart_opt || usart_set_async_baudrate(p_usart, 295 p_usart_opt->baudrate, ul_mck)) { 296 return 1; 297 } 298 299 /* Configure the USART option. */ 300 ul_reg_val |= p_usart_opt->char_length | p_usart_opt->parity_type | 301 p_usart_opt->channel_mode | p_usart_opt->stop_bits; 302 303 /* Configure the USART mode as normal mode. */ 304 ul_reg_val |= US_MR_USART_MODE_NORMAL; 305 306 p_usart->US_MR |= ul_reg_val; 307 308 return 0; 309 } 310 311 /** 312 * \brief Configure USART to work in hardware handshaking mode. 313 * 314 * \note By default, the transmitter and receiver aren't enabled. 315 * 316 * \param p_usart Pointer to a USART instance. 317 * \param p_usart_opt Pointer to sam_usart_opt_t instance. 318 * \param ul_mck USART module input clock frequency. 319 * 320 * \retval 0 on success. 321 * \retval 1 on failure. 322 */ 323 uint32_t usart_init_hw_handshaking(Usart *p_usart, 324 const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck) 325 { 326 /* Initialize the USART as standard RS232. */ 327 if (usart_init_rs232(p_usart, p_usart_opt, ul_mck)) { 328 return 1; 329 } 330 331 /* Set hardware handshaking mode. */ 332 p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) | 333 US_MR_USART_MODE_HW_HANDSHAKING; 334 335 return 0; 336 } 337 338 #if (SAM3S || SAM4S || SAM3U || SAM4L || SAM4E) 339 340 /** 341 * \brief Configure USART to work in modem mode. 342 * 343 * \note By default, the transmitter and receiver aren't enabled. 344 * 345 * \param p_usart Pointer to a USART instance. 346 * \param p_usart_opt Pointer to sam_usart_opt_t instance. 347 * \param ul_mck USART module input clock frequency. 348 * 349 * \retval 0 on success. 350 * \retval 1 on failure. 351 */ 352 uint32_t usart_init_modem(Usart *p_usart, 353 const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck) 354 { 355 /* 356 * SAM3S, SAM4S and SAM4E series support MODEM mode only on USART1, 357 * SAM3U and SAM4L series support MODEM mode only on USART0. 358 */ 359 #if (SAM3S || SAM4S || SAM4E) 360 #ifdef USART1 361 if (p_usart != USART1) { 362 return 1; 363 } 364 #endif 365 #elif (SAM3U || SAM4L) 366 if (p_usart != USART0) { 367 return 1; 368 } 369 #endif 370 371 /* Initialize the USART as standard RS232. */ 372 if (usart_init_rs232(p_usart, p_usart_opt, ul_mck)) { 373 return 1; 374 } 375 376 /* Set MODEM mode. */ 377 p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) | 378 US_MR_USART_MODE_MODEM; 379 380 return 0; 381 } 382 #endif 383 384 /** 385 * \brief Configure USART to work in SYNC mode and act as a master. 386 * 387 * \note By default, the transmitter and receiver aren't enabled. 388 * 389 * \param p_usart Pointer to a USART instance. 390 * \param p_usart_opt Pointer to sam_usart_opt_t instance. 391 * \param ul_mck USART module input clock frequency. 392 * 393 * \retval 0 on success. 394 * \retval 1 on failure. 395 */ 396 uint32_t usart_init_sync_master(Usart *p_usart, 397 const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck) 398 { 399 static uint32_t ul_reg_val; 400 401 /* Reset the USART and shut down TX and RX. */ 402 usart_reset(p_usart); 403 404 ul_reg_val = 0; 405 /* Check whether the input values are legal. */ 406 if (!p_usart_opt || usart_set_sync_master_baudrate(p_usart, 407 p_usart_opt->baudrate, ul_mck)) { 408 return 1; 409 } 410 411 /* Configure the USART option. */ 412 ul_reg_val |= p_usart_opt->char_length | p_usart_opt->parity_type | 413 p_usart_opt->channel_mode | p_usart_opt->stop_bits; 414 415 /* Set normal mode and output clock as synchronous master. */ 416 ul_reg_val |= US_MR_USART_MODE_NORMAL | US_MR_CLKO; 417 p_usart->US_MR |= ul_reg_val; 418 419 return 0; 420 } 421 422 /** 423 * \brief Configure USART to work in SYNC mode and act as a slave. 424 * 425 * \note By default, the transmitter and receiver aren't enabled. 426 * 427 * \param p_usart Pointer to a USART instance. 428 * \param p_usart_opt Pointer to sam_usart_opt_t instance. 429 * 430 * \retval 0 on success. 431 * \retval 1 on failure. 432 */ 433 uint32_t usart_init_sync_slave(Usart *p_usart, 434 const sam_usart_opt_t *p_usart_opt) 435 { 436 static uint32_t ul_reg_val; 437 438 /* Reset the USART and shut down TX and RX. */ 439 usart_reset(p_usart); 440 441 ul_reg_val = 0; 442 usart_set_sync_slave_baudrate(p_usart); 443 444 /* Check whether the input values are legal. */ 445 if (!p_usart_opt) { 446 return 1; 447 } 448 449 /* Configure the USART option. */ 450 ul_reg_val |= p_usart_opt->char_length | p_usart_opt->parity_type | 451 p_usart_opt->channel_mode | p_usart_opt->stop_bits; 452 453 /* Set normal mode. */ 454 ul_reg_val |= US_MR_USART_MODE_NORMAL; 455 p_usart->US_MR |= ul_reg_val; 456 457 return 0; 458 } 459 460 /** 461 * \brief Configure USART to work in RS485 mode. 462 * 463 * \note By default, the transmitter and receiver aren't enabled. 464 * 465 * \param p_usart Pointer to a USART instance. 466 * \param p_usart_opt Pointer to sam_usart_opt_t instance. 467 * \param ul_mck USART module input clock frequency. 468 * 469 * \retval 0 on success. 470 * \retval 1 on failure. 471 */ 472 uint32_t usart_init_rs485(Usart *p_usart, 473 const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck) 474 { 475 /* Initialize the USART as standard RS232. */ 476 if (usart_init_rs232(p_usart, p_usart_opt, ul_mck)) { 477 return 1; 478 } 479 480 /* Set RS485 mode. */ 481 p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) | 482 US_MR_USART_MODE_RS485; 483 484 return 0; 485 } 486 487 #if (!SAMG55 && !SAMV71 && !SAMV70 && !SAME70 && !SAMS70) 488 /** 489 * \brief Configure USART to work in IrDA mode. 490 * 491 * \note By default, the transmitter and receiver aren't enabled. 492 * 493 * \param p_usart Pointer to a USART instance. 494 * \param p_usart_opt Pointer to sam_usart_opt_t instance. 495 * \param ul_mck USART module input clock frequency. 496 * 497 * \retval 0 on success. 498 * \retval 1 on failure. 499 */ 500 uint32_t usart_init_irda(Usart *p_usart, 501 const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck) 502 { 503 /* Initialize the USART as standard RS232. */ 504 if (usart_init_rs232(p_usart, p_usart_opt, ul_mck)) { 505 return 1; 506 } 507 508 /* Set IrDA filter. */ 509 p_usart->US_IF = p_usart_opt->irda_filter; 510 511 /* Set IrDA mode. */ 512 p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) | 513 US_MR_USART_MODE_IRDA; 514 515 return 0; 516 } 517 #endif 518 519 #if (!SAMV71 && !SAMV70 && !SAME70 && !SAMS70) 520 /** 521 * \brief Calculate a clock divider (\e CD) for the USART ISO7816 mode to 522 * generate an ISO7816 clock as close as possible to the clock set point. 523 * 524 * \note ISO7816 clock calculation: Clock = ul_mck / cd 525 * 526 * \param p_usart Pointer to a USART instance. 527 * \param clock ISO7816 clock set point. 528 * \param ul_mck USART module input clock frequency. 529 * 530 * \retval 0 ISO7816 clock is successfully initialized. 531 * \retval 1 ISO7816 clock set point is out of range for the given input clock 532 * frequency. 533 */ 534 static uint32_t usart_set_iso7816_clock(Usart *p_usart, 535 uint32_t clock, uint32_t ul_mck) 536 { 537 uint32_t cd; 538 539 /* Calculate clock divider according to the formula in ISO7816 mode. */ 540 cd = (ul_mck + clock / 2) / clock; 541 542 if (cd < MIN_CD_VALUE || cd > MAX_CD_VALUE) { 543 return 1; 544 } 545 546 p_usart->US_MR = (p_usart->US_MR & ~(US_MR_USCLKS_Msk | US_MR_SYNC | 547 US_MR_OVER)) | US_MR_USCLKS_MCK | US_MR_CLKO; 548 549 /* Configure the baudrate generate register. */ 550 p_usart->US_BRGR = cd << US_BRGR_CD_Pos; 551 552 return 0; 553 } 554 555 /** 556 * \brief Configure USART to work in ISO7816 mode. 557 * 558 * \note By default, the transmitter and receiver aren't enabled. 559 * 560 * \param p_usart Pointer to a USART instance. 561 * \param p_usart_opt Pointer to sam_usart_opt_t instance. 562 * \param ul_mck USART module input clock frequency. 563 * 564 * \retval 0 on success. 565 * \retval 1 on failure. 566 */ 567 uint32_t usart_init_iso7816(Usart *p_usart, 568 const usart_iso7816_opt_t *p_usart_opt, uint32_t ul_mck) 569 { 570 static uint32_t ul_reg_val; 571 572 /* Reset the USART and shut down TX and RX. */ 573 usart_reset(p_usart); 574 575 ul_reg_val = 0; 576 577 /* Check whether the input values are legal. */ 578 if (!p_usart_opt || ((p_usart_opt->parity_type != US_MR_PAR_EVEN) && 579 (p_usart_opt->parity_type != US_MR_PAR_ODD))) { 580 return 1; 581 } 582 583 if (p_usart_opt->protocol_type == ISO7816_T_0) { 584 ul_reg_val |= US_MR_USART_MODE_IS07816_T_0 | US_MR_NBSTOP_2_BIT | 585 (p_usart_opt->max_iterations << US_MR_MAX_ITERATION_Pos); 586 587 if (p_usart_opt->bit_order) { 588 ul_reg_val |= US_MR_MSBF; 589 } 590 } else if (p_usart_opt->protocol_type == ISO7816_T_1) { 591 /* 592 * Only LSBF is used in the T=1 protocol, and max_iterations field 593 * is only used in T=0 mode. 594 */ 595 if (p_usart_opt->bit_order || p_usart_opt->max_iterations) { 596 return 1; 597 } 598 599 /* Set USART mode to ISO7816, T=1, and always uses 1 stop bit. */ 600 ul_reg_val |= US_MR_USART_MODE_IS07816_T_1 | US_MR_NBSTOP_1_BIT; 601 } else { 602 return 1; 603 } 604 605 /* Set up the baudrate. */ 606 if (usart_set_iso7816_clock(p_usart, p_usart_opt->iso7816_hz, ul_mck)) { 607 return 1; 608 } 609 610 /* Set FIDI register: bit rate = iso7816_hz / fidi_ratio. */ 611 p_usart->US_FIDI = p_usart_opt->fidi_ratio; 612 613 /* Set ISO7816 parity type in the MODE register. */ 614 ul_reg_val |= p_usart_opt->parity_type; 615 616 if (p_usart_opt->inhibit_nack) { 617 ul_reg_val |= US_MR_INACK; 618 } 619 if (p_usart_opt->dis_suc_nack) { 620 ul_reg_val |= US_MR_DSNACK; 621 } 622 623 p_usart->US_MR |= ul_reg_val; 624 625 return 0; 626 } 627 628 /** 629 * \brief Reset the ITERATION in US_CSR when the ISO7816 mode is enabled. 630 * 631 * \param p_usart Pointer to a USART instance. 632 */ 633 void usart_reset_iterations(Usart *p_usart) 634 { 635 p_usart->US_CR = US_CR_RSTIT; 636 } 637 638 /** 639 * \brief Reset NACK in US_CSR. 640 * 641 * \param p_usart Pointer to a USART instance. 642 */ 643 void usart_reset_nack(Usart *p_usart) 644 { 645 p_usart->US_CR = US_CR_RSTNACK; 646 } 647 648 /** 649 * \brief Check if one receive buffer is filled. 650 * 651 * \param p_usart Pointer to a USART instance. 652 * 653 * \retval 1 Receive is complete. 654 * \retval 0 Receive is still pending. 655 */ 656 uint32_t usart_is_rx_buf_end(Usart *p_usart) 657 { 658 return (p_usart->US_CSR & US_CSR_ENDRX) > 0; 659 } 660 661 /** 662 * \brief Check if one transmit buffer is empty. 663 * 664 * \param p_usart Pointer to a USART instance. 665 * 666 * \retval 1 Transmit is complete. 667 * \retval 0 Transmit is still pending. 668 */ 669 uint32_t usart_is_tx_buf_end(Usart *p_usart) 670 { 671 return (p_usart->US_CSR & US_CSR_ENDTX) > 0; 672 } 673 674 /** 675 * \brief Check if both receive buffers are full. 676 * 677 * \param p_usart Pointer to a USART instance. 678 * 679 * \retval 1 Receive buffers are full. 680 * \retval 0 Receive buffers are not full. 681 */ 682 uint32_t usart_is_rx_buf_full(Usart *p_usart) 683 { 684 return (p_usart->US_CSR & US_CSR_RXBUFF) > 0; 685 } 686 687 /** 688 * \brief Check if both transmit buffers are empty. 689 * 690 * \param p_usart Pointer to a USART instance. 691 * 692 * \retval 1 Transmit buffers are empty. 693 * \retval 0 Transmit buffers are not empty. 694 */ 695 uint32_t usart_is_tx_buf_empty(Usart *p_usart) 696 { 697 return (p_usart->US_CSR & US_CSR_TXBUFE) > 0; 698 } 699 700 /** 701 * \brief Get the total number of errors that occur during an ISO7816 transfer. 702 * 703 * \param p_usart Pointer to a USART instance. 704 * 705 * \return The number of errors that occurred. 706 */ 707 uint8_t usart_get_error_number(Usart *p_usart) 708 { 709 return (p_usart->US_NER & US_NER_NB_ERRORS_Msk); 710 } 711 712 #endif 713 714 /** 715 * \brief Configure USART to work in SPI mode and act as a master. 716 * 717 * \note By default, the transmitter and receiver aren't enabled. 718 * 719 * \param p_usart Pointer to a USART instance. 720 * \param p_usart_opt Pointer to sam_usart_opt_t instance. 721 * \param ul_mck USART module input clock frequency. 722 * 723 * \retval 0 on success. 724 * \retval 1 on failure. 725 */ 726 uint32_t usart_init_spi_master(Usart *p_usart, 727 const usart_spi_opt_t *p_usart_opt, uint32_t ul_mck) 728 { 729 static uint32_t ul_reg_val; 730 731 /* Reset the USART and shut down TX and RX. */ 732 usart_reset(p_usart); 733 734 ul_reg_val = 0; 735 /* Check whether the input values are legal. */ 736 if (!p_usart_opt || (p_usart_opt->spi_mode > SPI_MODE_3) || 737 usart_set_spi_master_baudrate(p_usart, p_usart_opt->baudrate, 738 ul_mck)) { 739 return 1; 740 } 741 742 /* Configure the character length bit in MR register. */ 743 ul_reg_val |= p_usart_opt->char_length; 744 745 /* Set SPI master mode and channel mode. */ 746 ul_reg_val |= US_MR_USART_MODE_SPI_MASTER | US_MR_CLKO | 747 p_usart_opt->channel_mode; 748 749 switch (p_usart_opt->spi_mode) { 750 case SPI_MODE_0: 751 ul_reg_val |= US_MR_CPHA; 752 ul_reg_val &= ~US_MR_CPOL; 753 break; 754 755 case SPI_MODE_1: 756 ul_reg_val &= ~US_MR_CPHA; 757 ul_reg_val &= ~US_MR_CPOL; 758 break; 759 760 case SPI_MODE_2: 761 ul_reg_val |= US_MR_CPHA; 762 ul_reg_val |= US_MR_CPOL; 763 break; 764 765 case SPI_MODE_3: 766 ul_reg_val &= ~US_MR_CPHA; 767 ul_reg_val |= US_MR_CPOL; 768 break; 769 770 default: 771 break; 772 } 773 774 p_usart->US_MR |= ul_reg_val; 775 776 return 0; 777 } 778 779 /** 780 * \brief Configure USART to work in SPI mode and act as a slave. 781 * 782 * \note By default, the transmitter and receiver aren't enabled. 783 * 784 * \param p_usart Pointer to a USART instance. 785 * \param p_usart_opt Pointer to sam_usart_opt_t instance. 786 * 787 * \retval 0 on success. 788 * \retval 1 on failure. 789 */ 790 uint32_t usart_init_spi_slave(Usart *p_usart, 791 const usart_spi_opt_t *p_usart_opt) 792 { 793 static uint32_t ul_reg_val; 794 795 /* Reset the USART and shut down TX and RX. */ 796 usart_reset(p_usart); 797 798 ul_reg_val = 0; 799 usart_set_spi_slave_baudrate(p_usart); 800 801 /* Check whether the input values are legal. */ 802 if (!p_usart_opt || p_usart_opt->spi_mode > SPI_MODE_3) { 803 return 1; 804 } 805 806 /* Configure the character length bit in MR register. */ 807 ul_reg_val |= p_usart_opt->char_length; 808 809 /* Set SPI slave mode and channel mode. */ 810 ul_reg_val |= US_MR_USART_MODE_SPI_SLAVE | p_usart_opt->channel_mode; 811 812 switch (p_usart_opt->spi_mode) { 813 case SPI_MODE_0: 814 ul_reg_val |= US_MR_CPHA; 815 ul_reg_val &= ~US_MR_CPOL; 816 break; 817 818 case SPI_MODE_1: 819 ul_reg_val &= ~US_MR_CPHA; 820 ul_reg_val &= ~US_MR_CPOL; 821 break; 822 823 case SPI_MODE_2: 824 ul_reg_val |= US_MR_CPHA; 825 ul_reg_val |= US_MR_CPOL; 826 break; 827 828 case SPI_MODE_3: 829 ul_reg_val |= US_MR_CPOL; 830 ul_reg_val &= ~US_MR_CPHA; 831 break; 832 833 default: 834 break; 835 } 836 837 p_usart->US_MR |= ul_reg_val; 838 839 return 0; 840 } 841 842 #if (SAM3XA || SAM4L || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) 843 844 /** 845 * \brief Configure USART to work in LIN mode and act as a LIN master. 846 * 847 * \note By default, the transmitter and receiver aren't enabled. 848 * 849 * \param p_usart Pointer to a USART instance. 850 * \param ul_baudrate Baudrate to be used. 851 * \param ul_mck USART module input clock frequency. 852 * 853 * \retval 0 on success. 854 * \retval 1 on failure. 855 */ 856 uint32_t usart_init_lin_master(Usart *p_usart,uint32_t ul_baudrate, 857 uint32_t ul_mck) 858 { 859 /* Reset the USART and shut down TX and RX. */ 860 usart_reset(p_usart); 861 862 /* Set up the baudrate. */ 863 if (usart_set_async_baudrate(p_usart, ul_baudrate, ul_mck)) { 864 return 1; 865 } 866 867 /* Set LIN master mode. */ 868 p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) | 869 US_MR_USART_MODE_LIN_MASTER; 870 871 usart_enable_rx(p_usart); 872 usart_enable_tx(p_usart); 873 874 return 0; 875 } 876 877 /** 878 * \brief Configure USART to work in LIN mode and act as a LIN slave. 879 * 880 * \note By default, the transmitter and receiver aren't enabled. 881 * 882 * \param p_usart Pointer to a USART instance. 883 * \param ul_baudrate Baudrate to be used. 884 * \param ul_mck USART module input clock frequency. 885 * 886 * \retval 0 on success. 887 * \retval 1 on failure. 888 */ 889 uint32_t usart_init_lin_slave(Usart *p_usart, uint32_t ul_baudrate, 890 uint32_t ul_mck) 891 { 892 /* Reset the USART and shut down TX and RX. */ 893 usart_reset(p_usart); 894 895 usart_enable_rx(p_usart); 896 usart_enable_tx(p_usart); 897 898 /* Set LIN slave mode. */ 899 p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) | 900 US_MR_USART_MODE_LIN_SLAVE; 901 902 /* Set up the baudrate. */ 903 if (usart_set_async_baudrate(p_usart, ul_baudrate, ul_mck)) { 904 return 1; 905 } 906 907 return 0; 908 } 909 910 /** 911 * \brief Abort the current LIN transmission. 912 * 913 * \param p_usart Pointer to a USART instance. 914 */ 915 void usart_lin_abort_tx(Usart *p_usart) 916 { 917 p_usart->US_CR = US_CR_LINABT; 918 } 919 920 /** 921 * \brief Send a wakeup signal on the LIN bus. 922 * 923 * \param p_usart Pointer to a USART instance. 924 */ 925 void usart_lin_send_wakeup_signal(Usart *p_usart) 926 { 927 p_usart->US_CR = US_CR_LINWKUP; 928 } 929 930 /** 931 * \brief Configure the LIN node action, which should be one of PUBLISH, 932 * SUBSCRIBE or IGNORE. 933 * 934 * \param p_usart Pointer to a USART instance. 935 * \param uc_action 0 for PUBLISH, 1 for SUBSCRIBE, 2 for IGNORE. 936 */ 937 void usart_lin_set_node_action(Usart *p_usart, uint8_t uc_action) 938 { 939 p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_NACT_Msk) | 940 (uc_action << US_LINMR_NACT_Pos); 941 } 942 943 /** 944 * \brief Disable the parity check during the LIN communication. 945 * 946 * \param p_usart Pointer to a USART instance. 947 */ 948 void usart_lin_disable_parity(Usart *p_usart) 949 { 950 p_usart->US_LINMR |= US_LINMR_PARDIS; 951 } 952 953 /** 954 * \brief Enable the parity check during the LIN communication. 955 * 956 * \param p_usart Pointer to a USART instance. 957 */ 958 void usart_lin_enable_parity(Usart *p_usart) 959 { 960 p_usart->US_LINMR &= ~US_LINMR_PARDIS; 961 } 962 963 /** 964 * \brief Disable the checksum during the LIN communication. 965 * 966 * \param p_usart Pointer to a USART instance. 967 */ 968 void usart_lin_disable_checksum(Usart *p_usart) 969 { 970 p_usart->US_LINMR |= US_LINMR_CHKDIS; 971 } 972 973 /** 974 * \brief Enable the checksum during the LIN communication. 975 * 976 * \param p_usart Pointer to a USART instance. 977 */ 978 void usart_lin_enable_checksum(Usart *p_usart) 979 { 980 p_usart->US_LINMR &= ~US_LINMR_CHKDIS; 981 } 982 983 /** 984 * \brief Configure the checksum type during the LIN communication. 985 * 986 * \param p_usart Pointer to a USART instance. 987 * \param uc_type 0 for LIN 2.0 Enhanced checksum or 1 for LIN 1.3 Classic 988 * checksum. 989 */ 990 void usart_lin_set_checksum_type(Usart *p_usart, uint8_t uc_type) 991 { 992 p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_CHKTYP) | 993 (uc_type << 4); 994 } 995 996 /** 997 * \brief Configure the data length mode during the LIN communication. 998 * 999 * \param p_usart Pointer to a USART instance. 1000 * \param uc_mode Indicate the data length type: 0 if the data length is 1001 * defined by the DLC of LIN mode register or 1 if the data length is defined 1002 * by the bit 5 and 6 of the identifier. 1003 */ 1004 void usart_lin_set_data_len_mode(Usart *p_usart, uint8_t uc_mode) 1005 { 1006 p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_DLM) | 1007 (uc_mode << 5); 1008 } 1009 1010 /** 1011 * \brief Disable the frame slot mode during the LIN communication. 1012 * 1013 * \param p_usart Pointer to a USART instance. 1014 */ 1015 void usart_lin_disable_frame_slot(Usart *p_usart) 1016 { 1017 p_usart->US_LINMR |= US_LINMR_FSDIS; 1018 } 1019 1020 /** 1021 * \brief Enable the frame slot mode during the LIN communication. 1022 * 1023 * \param p_usart Pointer to a USART instance. 1024 */ 1025 void usart_lin_enable_frame_slot(Usart *p_usart) 1026 { 1027 p_usart->US_LINMR &= ~US_LINMR_FSDIS; 1028 } 1029 1030 /** 1031 * \brief Configure the wakeup signal type during the LIN communication. 1032 * 1033 * \param p_usart Pointer to a USART instance. 1034 * \param uc_type Indicate the checksum type: 0 if the wakeup signal is a 1035 * LIN 2.0 wakeup signal; 1 if the wakeup signal is a LIN 1.3 wakeup signal. 1036 */ 1037 void usart_lin_set_wakeup_signal_type(Usart *p_usart, uint8_t uc_type) 1038 { 1039 p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_WKUPTYP) | 1040 (uc_type << 7); 1041 } 1042 1043 /** 1044 * \brief Configure the response data length if the data length is defined by 1045 * the DLC field during the LIN communication. 1046 * 1047 * \param p_usart Pointer to a USART instance. 1048 * \param uc_len Indicate the response data length. 1049 */ 1050 void usart_lin_set_response_data_len(Usart *p_usart, uint8_t uc_len) 1051 { 1052 p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_DLC_Msk) | 1053 ((uc_len - 1) << US_LINMR_DLC_Pos); 1054 } 1055 1056 /** 1057 * \brief The LIN mode register is not written by the PDC. 1058 * 1059 * \param p_usart Pointer to a USART instance. 1060 */ 1061 void usart_lin_disable_pdc_mode(Usart *p_usart) 1062 { 1063 p_usart->US_LINMR &= ~US_LINMR_PDCM; 1064 } 1065 1066 /** 1067 * \brief The LIN mode register (except this flag) is written by the PDC. 1068 * 1069 * \param p_usart Pointer to a USART instance. 1070 */ 1071 void usart_lin_enable_pdc_mode(Usart *p_usart) 1072 { 1073 p_usart->US_LINMR |= US_LINMR_PDCM; 1074 } 1075 1076 /** 1077 * \brief Configure the LIN identifier when USART works in LIN master mode. 1078 * 1079 * \param p_usart Pointer to a USART instance. 1080 * \param uc_id The identifier to be transmitted. 1081 */ 1082 void usart_lin_set_tx_identifier(Usart *p_usart, uint8_t uc_id) 1083 { 1084 p_usart->US_LINIR = (p_usart->US_LINIR & ~US_LINIR_IDCHR_Msk) | 1085 US_LINIR_IDCHR(uc_id); 1086 } 1087 1088 /** 1089 * \brief Read the identifier when USART works in LIN mode. 1090 * 1091 * \param p_usart Pointer to a USART instance. 1092 * 1093 * \return The last identifier received in LIN slave mode or the last 1094 * identifier transmitted in LIN master mode. 1095 */ 1096 uint8_t usart_lin_read_identifier(Usart *p_usart) 1097 { 1098 return (p_usart->US_LINIR & US_LINIR_IDCHR_Msk); 1099 } 1100 1101 /** 1102 * \brief Get data length. 1103 * 1104 * \param p_usart Pointer to a USART instance. 1105 * 1106 * \return Data length. 1107 */ 1108 uint8_t usart_lin_get_data_length(Usart *usart) 1109 { 1110 if (usart->US_LINMR & US_LINMR_DLM) { 1111 uint8_t data_length = 1 << ((usart->US_LINIR >> 1112 (US_LINIR_IDCHR_Pos + 4)) & 0x03); 1113 return data_length; 1114 } else { 1115 return ((usart->US_LINMR & US_LINMR_DLC_Msk) >> US_LINMR_DLC_Pos) + 1; 1116 } 1117 } 1118 1119 #endif 1120 1121 #if (SAMV71 || SAMV70 || SAME70 || SAMS70) 1122 /** 1123 * \brief Get identifier send status. 1124 * 1125 * \param p_usart Pointer to a USART instance. 1126 * 1127 * \return 1128 * 0: No LIN identifier has been sent since the last RSTSTA. 1129 * 1: :At least one LIN identifier has been sent since the last RSTSTA. 1130 */ 1131 uint8_t usart_lin_identifier_send_complete(Usart *usart) 1132 { 1133 return (usart->US_CSR & US_CSR_LINID) > 0; 1134 } 1135 1136 /** 1137 * \brief Get identifier received status. 1138 * 1139 * \param p_usart Pointer to a USART instance. 1140 * 1141 * \return 1142 * 0: No LIN identifier has been reveived since the last RSTSTA. 1143 * 1: At least one LIN identifier has been received since the last RSTSTA. 1144 */ 1145 uint8_t usart_lin_identifier_reception_complete(Usart *usart) 1146 { 1147 return (usart->US_CSR & US_CSR_LINID) > 0; 1148 } 1149 1150 /** 1151 * \brief Get transmission status. 1152 * 1153 * \param p_usart Pointer to a USART instance. 1154 * 1155 * \return 1156 * 0: The USART is idle or a LIN transfer is ongoing. 1157 * 1: A LIN transfer has been completed since the last RSTSTA. 1158 */ 1159 uint8_t usart_lin_tx_complete(Usart *usart) 1160 { 1161 return (usart->US_CSR & US_CSR_LINTC) > 0; 1162 } 1163 1164 /** 1165 * \brief Configure USART to work in LON mode. 1166 * 1167 * \note By default, the transmitter and receiver aren't enabled. 1168 * 1169 * \param p_usart Pointer to a USART instance. 1170 * \param ul_baudrate Baudrate to be used. 1171 * \param ul_mck USART module input clock frequency. 1172 * 1173 * \retval 0 on success. 1174 * \retval 1 on failure. 1175 */ 1176 uint32_t usart_init_lon(Usart *p_usart,uint32_t ul_baudrate, 1177 uint32_t ul_mck) 1178 { 1179 /* Reset the USART and shut down TX and RX. */ 1180 usart_reset(p_usart); 1181 1182 /* Set up the baudrate. */ 1183 if (usart_set_async_baudrate(p_usart, ul_baudrate, ul_mck)) { 1184 return 1; 1185 } 1186 1187 /* Set LIN master mode. */ 1188 p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) | 1189 US_MR_USART_MODE_LON; 1190 1191 usart_enable_rx(p_usart); 1192 usart_enable_tx(p_usart); 1193 1194 return 0; 1195 } 1196 1197 /** 1198 * \brief set LON parameter value. 1199 * 1200 * \param p_usart Pointer to a USART instance. 1201 * \param uc_type 0: LON comm_type = 1 mode, 1202 * 1: LON comm_type = 2 mode 1203 */ 1204 void usart_lon_set_comm_type(Usart *p_usart, uint8_t uc_type) 1205 { 1206 p_usart->US_LONMR = (p_usart->US_LONMR & ~US_LONMR_COMMT) | 1207 (uc_type << 0); 1208 } 1209 1210 /** 1211 * \brief Disable LON Collision Detection Feature. 1212 * 1213 * \param p_usart Pointer to a USART instance. 1214 */ 1215 void usart_lon_disable_coll_detection(Usart *p_usart) 1216 { 1217 p_usart->US_LONMR |= US_LONMR_COLDET; 1218 } 1219 1220 /** 1221 * \brief Enable LON Collision Detection Feature. 1222 * 1223 * \param p_usart Pointer to a USART instance. 1224 */ 1225 void usart_lon_enable_coll_detection(Usart *p_usart) 1226 { 1227 p_usart->US_LONMR &= ~US_LONMR_COLDET; 1228 } 1229 1230 /** 1231 * \brief set Terminate Frame upon Collision Notification. 1232 * 1233 * \param p_usart Pointer to a USART instance. 1234 * \param uc_type 0: Do not terminate the frame in LON comm_type = 1 mode upon collision detection. 1235 * 1:Terminate the frame in LON comm_type = 1 mode upon collision detection if possible. 1236 */ 1237 void usart_lon_set_tcol(Usart *p_usart, uint8_t uc_type) 1238 { 1239 p_usart->US_LONMR = (p_usart->US_LONMR & ~US_LONMR_TCOL) | 1240 (uc_type << 2); 1241 } 1242 1243 /** 1244 * \brief set LON Collision Detection on Frame Tail. 1245 * 1246 * \param p_usart Pointer to a USART instance. 1247 * \param uc_type 0: Detect collisions after CRC has been sent but prior end of transmission in LON comm_type = 1 mode. 1248 * 1: Ignore collisions after CRC has been sent but prior end of transmission in LON comm_type = 1 mode. 1249 */ 1250 void usart_lon_set_cdtail(Usart *p_usart, uint8_t uc_type) 1251 { 1252 p_usart->US_LONMR = (p_usart->US_LONMR & ~US_LONMR_CDTAIL) | 1253 (uc_type << 3); 1254 } 1255 1256 /** 1257 * \brief set LON DMA Mode. 1258 * 1259 * \param p_usart Pointer to a USART instance. 1260 * \param uc_type 0: The LON data length register US_LONDL is not written by the DMA. 1261 * 1: The LON data length register US_LONDL is written by the DMA. 1262 */ 1263 void usart_lon_set_dmam(Usart *p_usart, uint8_t uc_type) 1264 { 1265 p_usart->US_LONMR = (p_usart->US_LONMR & ~US_LONMR_DMAM) | 1266 (uc_type << 4); 1267 } 1268 1269 /** 1270 * \brief set LON Beta1 Length after Transmission. 1271 * 1272 * \param p_usart Pointer to a USART instance. 1273 * \param ul_len 1-16777215: LON beta1 length after transmission in tbit 1274 */ 1275 void usart_lon_set_beta1_tx_len(Usart *p_usart, uint32_t ul_len) 1276 { 1277 p_usart->US_LONB1TX = US_LONB1TX_BETA1TX(ul_len); 1278 } 1279 1280 /** 1281 * \brief set LON Beta1 Length after Reception. 1282 * 1283 * \param p_usart Pointer to a USART instance. 1284 * \param ul_len 1-16777215: LON beta1 length after reception in tbit. 1285 */ 1286 void usart_lon_set_beta1_rx_len(Usart *p_usart, uint32_t ul_len) 1287 { 1288 p_usart->US_LONB1RX = US_LONB1RX_BETA1RX(ul_len); 1289 } 1290 1291 /** 1292 * \brief set LON Priority. 1293 * 1294 * \param p_usart Pointer to a USART instance. 1295 * \param uc_psnb 0 -127: LON Priority Slot Number. 1296 * \param uc_nps 0 -127: LON Node Priority Slot. 1297 */ 1298 void usart_lon_set_priority(Usart *p_usart, uint8_t uc_psnb, uint8_t uc_nps) 1299 { 1300 p_usart->US_LONPRIO = US_LONPRIO_PSNB(uc_psnb) | US_LONPRIO_NPS(uc_nps); 1301 } 1302 1303 /** 1304 * \brief set LON Indeterminate Time after Transmission. 1305 * 1306 * \param p_usart Pointer to a USART instance. 1307 * \param ul_time 1-16777215: LON Indeterminate Time after Transmission (comm_type = 1 mode only). 1308 */ 1309 void usart_lon_set_tx_idt(Usart *p_usart, uint32_t ul_time) 1310 { 1311 p_usart->US_IDTTX = US_IDTTX_IDTTX(ul_time); 1312 } 1313 1314 /** 1315 * \brief set LON Indeterminate Time after Reception. 1316 * 1317 * \param p_usart Pointer to a USART instance. 1318 * \param ul_time 1-16777215: LON Indeterminate Time after Reception (comm_type = 1 mode only). 1319 */ 1320 void usart_lon_set_rx_idt(Usart *p_usart, uint32_t ul_time) 1321 { 1322 p_usart->US_IDTRX = US_IDTRX_IDTRX(ul_time); 1323 } 1324 1325 /** 1326 * \brief set LON Preamble Length. 1327 * 1328 * \param p_usart Pointer to a USART instance. 1329 * \param ul_len 1-16383: LON preamble length in tbit(without byte-sync). 1330 */ 1331 void usart_lon_set_pre_len(Usart *p_usart, uint32_t ul_len) 1332 { 1333 p_usart->US_LONPR = US_LONPR_LONPL(ul_len); 1334 } 1335 1336 /** 1337 * \brief set LON Data Length. 1338 * 1339 * \param p_usart Pointer to a USART instance. 1340 * \param uc_len 0-255: LON data length is LONDL+1 bytes. 1341 */ 1342 void usart_lon_set_data_len(Usart *p_usart, uint8_t uc_len) 1343 { 1344 p_usart->US_LONDL = US_LONDL_LONDL(uc_len); 1345 } 1346 1347 /** 1348 * \brief set LON Priority. 1349 * 1350 * \param p_usart Pointer to a USART instance. 1351 * \param uc_bli LON Backlog Increment. 1352 * \param uc_altp LON Alternate Path Bit. 1353 * \param uc_pb LON Priority Bit. 1354 */ 1355 void usart_lon_set_l2hdr(Usart *p_usart, uint8_t uc_bli, uint8_t uc_altp, uint8_t uc_pb) 1356 { 1357 p_usart->US_LONL2HDR = US_LONL2HDR_BLI(uc_bli) | (uc_altp << 6) | (uc_pb << 7); 1358 } 1359 1360 /** 1361 * \brief Check if LON Transmission End. 1362 * 1363 * \param p_usart Pointer to a USART instance. 1364 * 1365 * \retval 1 At least one transmission has been performed since the last RSTSTA. 1366 * \retval 0 Transmission on going or no transmission occurred since the last RSTSTA. 1367 */ 1368 uint32_t usart_lon_is_tx_end(Usart *p_usart) 1369 { 1370 return (p_usart->US_CSR & US_CSR_LTXD) > 0; 1371 } 1372 1373 /** 1374 * \brief Check if LON Reception End. 1375 * 1376 * \param p_usart Pointer to a USART instance. 1377 * 1378 * \retval 1 At least one Reception has been performed since the last RSTSTA. 1379 * \retval 0 Reception on going or no Reception occurred since the last RSTSTA. 1380 */ 1381 uint32_t usart_lon_is_rx_end(Usart *p_usart) 1382 { 1383 return (p_usart->US_CSR & US_CSR_LRXD) > 0; 1384 } 1385 #endif 1386 1387 /** 1388 * \brief Enable USART transmitter. 1389 * 1390 * \param p_usart Pointer to a USART instance. 1391 */ 1392 void usart_enable_tx(Usart *p_usart) 1393 { 1394 p_usart->US_CR = US_CR_TXEN; 1395 } 1396 1397 /** 1398 * \brief Disable USART transmitter. 1399 * 1400 * \param p_usart Pointer to a USART instance. 1401 */ 1402 void usart_disable_tx(Usart *p_usart) 1403 { 1404 p_usart->US_CR = US_CR_TXDIS; 1405 } 1406 1407 /** 1408 * \brief Immediately stop and disable USART transmitter. 1409 * 1410 * \param p_usart Pointer to a USART instance. 1411 */ 1412 void usart_reset_tx(Usart *p_usart) 1413 { 1414 /* Reset transmitter */ 1415 p_usart->US_CR = US_CR_RSTTX | US_CR_TXDIS; 1416 } 1417 1418 /** 1419 * \brief Configure the transmit timeguard register. 1420 * 1421 * \param p_usart Pointer to a USART instance. 1422 * \param timeguard The value of transmit timeguard. 1423 */ 1424 void usart_set_tx_timeguard(Usart *p_usart, uint32_t timeguard) 1425 { 1426 p_usart->US_TTGR = timeguard; 1427 } 1428 1429 /** 1430 * \brief Enable USART receiver. 1431 * 1432 * \param p_usart Pointer to a USART instance. 1433 */ 1434 void usart_enable_rx(Usart *p_usart) 1435 { 1436 p_usart->US_CR = US_CR_RXEN; 1437 } 1438 1439 /** 1440 * \brief Disable USART receiver. 1441 * 1442 * \param p_usart Pointer to a USART instance. 1443 */ 1444 void usart_disable_rx(Usart *p_usart) 1445 { 1446 p_usart->US_CR = US_CR_RXDIS; 1447 } 1448 1449 /** 1450 * \brief Immediately stop and disable USART receiver. 1451 * 1452 * \param p_usart Pointer to a USART instance. 1453 */ 1454 void usart_reset_rx(Usart *p_usart) 1455 { 1456 /* Reset Receiver */ 1457 p_usart->US_CR = US_CR_RSTRX | US_CR_RXDIS; 1458 } 1459 1460 /** 1461 * \brief Configure the receive timeout register. 1462 * 1463 * \param p_usart Pointer to a USART instance. 1464 * \param timeout The value of receive timeout. 1465 */ 1466 void usart_set_rx_timeout(Usart *p_usart, uint32_t timeout) 1467 { 1468 p_usart->US_RTOR = timeout; 1469 } 1470 1471 /** 1472 * \brief Enable USART interrupts. 1473 * 1474 * \param p_usart Pointer to a USART peripheral. 1475 * \param ul_sources Interrupt sources bit map. 1476 */ 1477 void usart_enable_interrupt(Usart *p_usart, uint32_t ul_sources) 1478 { 1479 p_usart->US_IER = ul_sources; 1480 } 1481 1482 /** 1483 * \brief Disable USART interrupts. 1484 * 1485 * \param p_usart Pointer to a USART peripheral. 1486 * \param ul_sources Interrupt sources bit map. 1487 */ 1488 void usart_disable_interrupt(Usart *p_usart, uint32_t ul_sources) 1489 { 1490 p_usart->US_IDR = ul_sources; 1491 } 1492 1493 /** 1494 * \brief Read USART interrupt mask. 1495 * 1496 * \param p_usart Pointer to a USART peripheral. 1497 * 1498 * \return The interrupt mask value. 1499 */ 1500 uint32_t usart_get_interrupt_mask(Usart *p_usart) 1501 { 1502 return p_usart->US_IMR; 1503 } 1504 1505 /** 1506 * \brief Get current status. 1507 * 1508 * \param p_usart Pointer to a USART instance. 1509 * 1510 * \return The current USART status. 1511 */ 1512 uint32_t usart_get_status(Usart *p_usart) 1513 { 1514 return p_usart->US_CSR; 1515 } 1516 1517 /** 1518 * \brief Reset status bits (PARE, OVER, MANERR, UNRE and PXBRK in US_CSR). 1519 * 1520 * \param p_usart Pointer to a USART instance. 1521 */ 1522 void usart_reset_status(Usart *p_usart) 1523 { 1524 p_usart->US_CR = US_CR_RSTSTA; 1525 } 1526 1527 /** 1528 * \brief Start transmission of a break. 1529 * 1530 * \param p_usart Pointer to a USART instance. 1531 */ 1532 void usart_start_tx_break(Usart *p_usart) 1533 { 1534 p_usart->US_CR = US_CR_STTBRK; 1535 } 1536 1537 /** 1538 * \brief Stop transmission of a break. 1539 * 1540 * \param p_usart Pointer to a USART instance. 1541 */ 1542 void usart_stop_tx_break(Usart *p_usart) 1543 { 1544 p_usart->US_CR = US_CR_STPBRK; 1545 } 1546 1547 /** 1548 * \brief Start waiting for a character before clocking the timeout count. 1549 * Reset the status bit TIMEOUT in US_CSR. 1550 * 1551 * \param p_usart Pointer to a USART instance. 1552 */ 1553 void usart_start_rx_timeout(Usart *p_usart) 1554 { 1555 p_usart->US_CR = US_CR_STTTO; 1556 } 1557 1558 /** 1559 * \brief In Multidrop mode only, the next character written to the US_THR 1560 * is sent with the address bit set. 1561 * 1562 * \param p_usart Pointer to a USART instance. 1563 * \param ul_addr The address to be sent out. 1564 * 1565 * \retval 0 on success. 1566 * \retval 1 on failure. 1567 */ 1568 uint32_t usart_send_address(Usart *p_usart, uint32_t ul_addr) 1569 { 1570 if ((p_usart->US_MR & US_MR_PAR_MULTIDROP) != US_MR_PAR_MULTIDROP) { 1571 return 1; 1572 } 1573 1574 p_usart->US_CR = US_CR_SENDA; 1575 1576 if (usart_write(p_usart, ul_addr)) { 1577 return 1; 1578 } else { 1579 return 0; 1580 } 1581 } 1582 1583 /** 1584 * \brief Restart the receive timeout. 1585 * 1586 * \param p_usart Pointer to a USART instance. 1587 */ 1588 void usart_restart_rx_timeout(Usart *p_usart) 1589 { 1590 p_usart->US_CR = US_CR_RETTO; 1591 } 1592 1593 #if (SAM3S || SAM4S || SAM3U || SAM4L || SAM4E) 1594 1595 /** 1596 * \brief Drive the pin DTR to 0. 1597 * 1598 * \param p_usart Pointer to a USART instance. 1599 */ 1600 void usart_drive_DTR_pin_low(Usart *p_usart) 1601 { 1602 p_usart->US_CR = US_CR_DTREN; 1603 } 1604 1605 /** 1606 * \brief Drive the pin DTR to 1. 1607 * 1608 * \param p_usart Pointer to a USART instance. 1609 */ 1610 void usart_drive_DTR_pin_high(Usart *p_usart) 1611 { 1612 p_usart->US_CR = US_CR_DTRDIS; 1613 } 1614 1615 #endif 1616 1617 /** 1618 * \brief Drive the pin RTS to 0. 1619 * 1620 * \param p_usart Pointer to a USART instance. 1621 */ 1622 void usart_drive_RTS_pin_low(Usart *p_usart) 1623 { 1624 p_usart->US_CR = US_CR_RTSEN; 1625 } 1626 1627 /** 1628 * \brief Drive the pin RTS to 1. 1629 * 1630 * \param p_usart Pointer to a USART instance. 1631 */ 1632 void usart_drive_RTS_pin_high(Usart *p_usart) 1633 { 1634 p_usart->US_CR = US_CR_RTSDIS; 1635 } 1636 1637 /** 1638 * \brief Drive the slave select line NSS (RTS pin) to 0 in SPI master mode. 1639 * 1640 * \param p_usart Pointer to a USART instance. 1641 */ 1642 void usart_spi_force_chip_select(Usart *p_usart) 1643 { 1644 p_usart->US_CR = US_CR_FCS; 1645 } 1646 1647 /** 1648 * \brief Drive the slave select line NSS (RTS pin) to 1 in SPI master mode. 1649 * 1650 * \param p_usart Pointer to a USART instance. 1651 */ 1652 void usart_spi_release_chip_select(Usart *p_usart) 1653 { 1654 p_usart->US_CR = US_CR_RCS; 1655 } 1656 1657 /** 1658 * \brief Check if Transmit is Ready. 1659 * Check if data have been loaded in USART_THR and are waiting to be loaded 1660 * into the Transmit Shift Register (TSR). 1661 * 1662 * \param p_usart Pointer to a USART instance. 1663 * 1664 * \retval 1 No data is in the Transmit Holding Register. 1665 * \retval 0 There is data in the Transmit Holding Register. 1666 */ 1667 uint32_t usart_is_tx_ready(Usart *p_usart) 1668 { 1669 return (p_usart->US_CSR & US_CSR_TXRDY) > 0; 1670 } 1671 1672 /** 1673 * \brief Check if Transmit Holding Register is empty. 1674 * Check if the last data written in USART_THR have been loaded in TSR and the 1675 * last data loaded in TSR have been transmitted. 1676 * 1677 * \param p_usart Pointer to a USART instance. 1678 * 1679 * \retval 1 Transmitter is empty. 1680 * \retval 0 Transmitter is not empty. 1681 */ 1682 uint32_t usart_is_tx_empty(Usart *p_usart) 1683 { 1684 return (p_usart->US_CSR & US_CSR_TXEMPTY) > 0; 1685 } 1686 1687 /** 1688 * \brief Check if the received data are ready. 1689 * Check if Data have been received and loaded into USART_RHR. 1690 * 1691 * \param p_usart Pointer to a USART instance. 1692 * 1693 * \retval 1 Some data has been received. 1694 * \retval 0 No data has been received. 1695 */ 1696 uint32_t usart_is_rx_ready(Usart *p_usart) 1697 { 1698 return (p_usart->US_CSR & US_CSR_RXRDY) > 0; 1699 } 1700 1701 /** 1702 * \brief Write to USART Transmit Holding Register. 1703 * 1704 * \note Before writing user should check if tx is ready (or empty). 1705 * 1706 * \param p_usart Pointer to a USART instance. 1707 * \param c Data to be sent. 1708 * 1709 * \retval 0 on success. 1710 * \retval 1 on failure. 1711 */ 1712 uint32_t usart_write(Usart *p_usart, uint32_t c) 1713 { 1714 if (!(p_usart->US_CSR & US_CSR_TXRDY)) { 1715 return 1; 1716 } 1717 1718 p_usart->US_THR = US_THR_TXCHR(c); 1719 return 0; 1720 } 1721 1722 /** 1723 * \brief Write to USART Transmit Holding Register. 1724 * 1725 * \note Before writing user should check if tx is ready (or empty). 1726 * 1727 * \param p_usart Pointer to a USART instance. 1728 * \param c Data to be sent. 1729 * 1730 * \retval 0 on success. 1731 * \retval 1 on failure. 1732 */ 1733 uint32_t usart_putchar(Usart *p_usart, uint32_t c) 1734 { 1735 while (!(p_usart->US_CSR & US_CSR_TXRDY)) { 1736 } 1737 1738 p_usart->US_THR = US_THR_TXCHR(c); 1739 1740 return 0; 1741 } 1742 1743 /** 1744 * \brief Write one-line string through USART. 1745 * 1746 * \param p_usart Pointer to a USART instance. 1747 * \param string Pointer to one-line string to be sent. 1748 */ 1749 void usart_write_line(Usart *p_usart, const char *string) 1750 { 1751 while (*string != '\0') { 1752 usart_putchar(p_usart, *string++); 1753 } 1754 } 1755 1756 /** 1757 * \brief Read from USART Receive Holding Register. 1758 * 1759 * \note Before reading user should check if rx is ready. 1760 * 1761 * \param p_usart Pointer to a USART instance. 1762 * \param c Pointer where the one-byte received data will be stored. 1763 * 1764 * \retval 0 on success. 1765 * \retval 1 if no data is available or errors. 1766 */ 1767 uint32_t usart_read(Usart *p_usart, uint32_t *c) 1768 { 1769 if (!(p_usart->US_CSR & US_CSR_RXRDY)) { 1770 return 1; 1771 } 1772 1773 /* Read character */ 1774 *c = p_usart->US_RHR & US_RHR_RXCHR_Msk; 1775 1776 return 0; 1777 } 1778 1779 /** 1780 * \brief Read from USART Receive Holding Register. 1781 * Before reading user should check if rx is ready. 1782 * 1783 * \param p_usart Pointer to a USART instance. 1784 * \param c Pointer where the one-byte received data will be stored. 1785 * 1786 * \retval 0 Data has been received. 1787 * \retval 1 on failure. 1788 */ 1789 uint32_t usart_getchar(Usart *p_usart, uint32_t *c) 1790 { 1791 /* Wait until it's not empty or timeout has reached. */ 1792 while (!(p_usart->US_CSR & US_CSR_RXRDY)) { 1793 } 1794 1795 /* Read character */ 1796 *c = p_usart->US_RHR & US_RHR_RXCHR_Msk; 1797 1798 return 0; 1799 } 1800 1801 #if (SAM3XA || SAM3U) 1802 /** 1803 * \brief Get Transmit address for DMA operation. 1804 * 1805 * \param p_usart Pointer to a USART instance. 1806 * 1807 * \return Transmit address for DMA access. 1808 */ 1809 uint32_t *usart_get_tx_access(Usart *p_usart) 1810 { 1811 return (uint32_t *)&(p_usart->US_THR); 1812 } 1813 1814 /** 1815 * \brief Get Receive address for DMA operation. 1816 * 1817 * \param p_usart Pointer to a USART instance. 1818 * 1819 * \return Receive address for DMA access. 1820 */ 1821 uint32_t *usart_get_rx_access(Usart *p_usart) 1822 { 1823 return (uint32_t *)&(p_usart->US_RHR); 1824 } 1825 #endif 1826 1827 #if (!SAM4L && !SAMV71 && !SAMV70 && !SAME70 && !SAMS70) 1828 /** 1829 * \brief Get USART PDC base address. 1830 * 1831 * \param p_usart Pointer to a UART instance. 1832 * 1833 * \return USART PDC registers base for PDC driver to access. 1834 */ 1835 Pdc *usart_get_pdc_base(Usart *p_usart) 1836 { 1837 Pdc *p_pdc_base; 1838 1839 p_pdc_base = (Pdc *)NULL; 1840 1841 #ifdef PDC_USART 1842 if (p_usart == USART) { 1843 p_pdc_base = PDC_USART; 1844 return p_pdc_base; 1845 } 1846 #endif 1847 #ifdef PDC_USART0 1848 if (p_usart == USART0) { 1849 p_pdc_base = PDC_USART0; 1850 return p_pdc_base; 1851 } 1852 #endif 1853 #ifdef PDC_USART1 1854 else if (p_usart == USART1) { 1855 p_pdc_base = PDC_USART1; 1856 return p_pdc_base; 1857 } 1858 #endif 1859 #ifdef PDC_USART2 1860 else if (p_usart == USART2) { 1861 p_pdc_base = PDC_USART2; 1862 return p_pdc_base; 1863 } 1864 #endif 1865 #ifdef PDC_USART3 1866 else if (p_usart == USART3) { 1867 p_pdc_base = PDC_USART3; 1868 return p_pdc_base; 1869 } 1870 #endif 1871 #ifdef PDC_USART4 1872 else if (p_usart == USART4) { 1873 p_pdc_base = PDC_USART4; 1874 return p_pdc_base; 1875 } 1876 #endif 1877 #ifdef PDC_USART5 1878 else if (p_usart == USART5) { 1879 p_pdc_base = PDC_USART5; 1880 return p_pdc_base; 1881 } 1882 #endif 1883 #ifdef PDC_USART6 1884 else if (p_usart == USART6) { 1885 p_pdc_base = PDC_USART6; 1886 return p_pdc_base; 1887 } 1888 #endif 1889 #ifdef PDC_USART7 1890 else if (p_usart == USART7) { 1891 p_pdc_base = PDC_USART7; 1892 return p_pdc_base; 1893 } 1894 #endif 1895 1896 return p_pdc_base; 1897 } 1898 #endif 1899 1900 /** 1901 * \brief Enable write protect of USART registers. 1902 * 1903 * \param p_usart Pointer to a USART instance. 1904 */ 1905 void usart_enable_writeprotect(Usart *p_usart) 1906 { 1907 p_usart->US_WPMR = US_WPMR_WPEN | US_WPMR_WPKEY_PASSWD; 1908 } 1909 1910 /** 1911 * \brief Disable write protect of USART registers. 1912 * 1913 * \param p_usart Pointer to a USART instance. 1914 */ 1915 void usart_disable_writeprotect(Usart *p_usart) 1916 { 1917 p_usart->US_WPMR = US_WPMR_WPKEY_PASSWD; 1918 } 1919 1920 /** 1921 * \brief Get write protect status. 1922 * 1923 * \param p_usart Pointer to a USART instance. 1924 * 1925 * \return 0 if no write protect violation occurred, or 16-bit write protect 1926 * violation source. 1927 */ 1928 uint32_t usart_get_writeprotect_status(Usart *p_usart) 1929 { 1930 uint32_t reg_value; 1931 1932 reg_value = p_usart->US_WPSR; 1933 if (reg_value & US_WPSR_WPVS) { 1934 return (reg_value & US_WPSR_WPVSRC_Msk) >> US_WPSR_WPVSRC_Pos; 1935 } else { 1936 return 0; 1937 } 1938 } 1939 1940 #if (SAM3S || SAM4S || SAM3U || SAM3XA || SAM4L || SAM4E || SAM4C || SAM4CP || SAM4CM) 1941 1942 /** 1943 * \brief Configure the transmitter preamble length when the Manchester 1944 * encode/decode is enabled. 1945 * 1946 * \param p_usart Pointer to a USART instance. 1947 * \param uc_len The transmitter preamble length, which should be 0 ~ 15. 1948 */ 1949 void usart_man_set_tx_pre_len(Usart *p_usart, uint8_t uc_len) 1950 { 1951 p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_TX_PL_Msk) | 1952 US_MAN_TX_PL(uc_len); 1953 } 1954 1955 /** 1956 * \brief Configure the transmitter preamble pattern when the Manchester 1957 * encode/decode is enabled, which should be 0 ~ 3. 1958 * 1959 * \param p_usart Pointer to a USART instance. 1960 * \param uc_pattern 0 if the preamble is composed of '1's; 1961 * 1 if the preamble is composed of '0's; 1962 * 2 if the preamble is composed of '01's; 1963 * 3 if the preamble is composed of '10's. 1964 */ 1965 void usart_man_set_tx_pre_pattern(Usart *p_usart, uint8_t uc_pattern) 1966 { 1967 p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_TX_PP_Msk) | 1968 (uc_pattern << US_MAN_TX_PP_Pos); 1969 } 1970 1971 /** 1972 * \brief Configure the transmitter Manchester polarity when the Manchester 1973 * encode/decode is enabled. 1974 * 1975 * \param p_usart Pointer to a USART instance. 1976 * \param uc_polarity Indicate the transmitter Manchester polarity, which 1977 * should be 0 or 1. 1978 */ 1979 void usart_man_set_tx_polarity(Usart *p_usart, uint8_t uc_polarity) 1980 { 1981 p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_TX_MPOL) | 1982 (uc_polarity << 12); 1983 } 1984 1985 /** 1986 * \brief Configure the detected receiver preamble length when the Manchester 1987 * encode/decode is enabled. 1988 * 1989 * \param p_usart Pointer to a USART instance. 1990 * \param uc_len The detected receiver preamble length, which should be 0 ~ 15. 1991 */ 1992 void usart_man_set_rx_pre_len(Usart *p_usart, uint8_t uc_len) 1993 { 1994 p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_RX_PL_Msk) | 1995 US_MAN_RX_PL(uc_len); 1996 } 1997 1998 /** 1999 * \brief Configure the detected receiver preamble pattern when the Manchester 2000 * encode/decode is enabled, which should be 0 ~ 3. 2001 * 2002 * \param p_usart Pointer to a USART instance. 2003 * \param uc_pattern 0 if the preamble is composed of '1's; 2004 * 1 if the preamble is composed of '0's; 2005 * 2 if the preamble is composed of '01's; 2006 * 3 if the preamble is composed of '10's. 2007 */ 2008 void usart_man_set_rx_pre_pattern(Usart *p_usart, uint8_t uc_pattern) 2009 { 2010 p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_RX_PP_Msk) | 2011 (uc_pattern << US_MAN_RX_PP_Pos); 2012 } 2013 2014 /** 2015 * \brief Configure the receiver Manchester polarity when the Manchester 2016 * encode/decode is enabled. 2017 * 2018 * \param p_usart Pointer to a USART instance. 2019 * \param uc_polarity Indicate the receiver Manchester polarity, which should 2020 * be 0 or 1. 2021 */ 2022 void usart_man_set_rx_polarity(Usart *p_usart, uint8_t uc_polarity) 2023 { 2024 p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_RX_MPOL) | 2025 (uc_polarity << 28); 2026 } 2027 2028 /** 2029 * \brief Enable drift compensation. 2030 * 2031 * \note The 16X clock mode must be enabled. 2032 * 2033 * \param p_usart Pointer to a USART instance. 2034 */ 2035 void usart_man_enable_drift_compensation(Usart *p_usart) 2036 { 2037 p_usart->US_MAN |= US_MAN_DRIFT; 2038 } 2039 2040 /** 2041 * \brief Disable drift compensation. 2042 * 2043 * \param p_usart Pointer to a USART instance. 2044 */ 2045 void usart_man_disable_drift_compensation(Usart *p_usart) 2046 { 2047 p_usart->US_MAN &= ~US_MAN_DRIFT; 2048 } 2049 2050 #endif 2051 2052 #if SAM4L 2053 2054 uint32_t usart_get_version(Usart *p_usart) 2055 { 2056 return p_usart->US_VERSION; 2057 } 2058 2059 #endif 2060 2061 #if SAMG55 2062 /** 2063 * \brief Set sleepwalking match mode. 2064 * 2065 * \param p_uart Pointer to a USART instance. 2066 * \param ul_low_value First comparison value for received character. 2067 * \param ul_high_value Second comparison value for received character. 2068 * \param cmpmode ture for start condition, false for flag only. 2069 * \param cmppar ture for parity check, false for no. 2070 */ 2071 void usart_set_sleepwalking(Usart *p_uart, uint8_t ul_low_value, 2072 bool cmpmode, bool cmppar, uint8_t ul_high_value) 2073 { 2074 Assert(ul_low_value <= ul_high_value); 2075 2076 uint32_t temp = 0; 2077 2078 if (cmpmode) { 2079 temp |= US_CMPR_CMPMODE_START_CONDITION; 2080 } 2081 2082 if (cmppar) { 2083 temp |= US_CMPR_CMPPAR; 2084 } 2085 2086 temp |= US_CMPR_VAL1(ul_low_value); 2087 2088 temp |= US_CMPR_VAL2(ul_high_value); 2089 2090 p_uart->US_CMPR= temp; 2091 } 2092 #endif 2093 2094 //@} 2095 2096 /// @cond 0 2097 /**INDENT-OFF**/ 2098 #ifdef __cplusplus 2099 } 2100 #endif 2101 /**INDENT-ON**/ 2102 /// @endcond 2103