1 /* generated HAL source file - do not edit */ 2 #include "hal_data.h" 3 4 flash_hp_instance_ctrl_t g_flash0_ctrl; 5 const flash_cfg_t g_flash0_cfg = 6 { .data_flash_bgo = false, .p_callback = NULL, .p_context = NULL, 7 #if defined(VECTOR_NUMBER_FCU_FRDYI) 8 .irq = VECTOR_NUMBER_FCU_FRDYI, 9 #else 10 .irq = FSP_INVALID_VECTOR, 11 #endif 12 #if defined(VECTOR_NUMBER_FCU_FIFERR) 13 .err_irq = VECTOR_NUMBER_FCU_FIFERR, 14 #else 15 .err_irq = FSP_INVALID_VECTOR, 16 #endif 17 .err_ipl = (BSP_IRQ_DISABLED), 18 .ipl = (BSP_IRQ_DISABLED), }; 19 /* Instance structure to use this module. */ 20 const flash_instance_t g_flash0 = 21 { .p_ctrl = &g_flash0_ctrl, .p_cfg = &g_flash0_cfg, .p_api = &g_flash_on_flash_hp }; 22 gpt_instance_ctrl_t g_timer0_ctrl; 23 #if 0 24 const gpt_extended_pwm_cfg_t g_timer0_pwm_extend = 25 { 26 .trough_ipl = (BSP_IRQ_DISABLED), 27 #if defined(VECTOR_NUMBER_GPT0_COUNTER_UNDERFLOW) 28 .trough_irq = VECTOR_NUMBER_GPT0_COUNTER_UNDERFLOW, 29 #else 30 .trough_irq = FSP_INVALID_VECTOR, 31 #endif 32 .poeg_link = GPT_POEG_LINK_POEG0, 33 .output_disable = GPT_OUTPUT_DISABLE_NONE, 34 .adc_trigger = GPT_ADC_TRIGGER_NONE, 35 .dead_time_count_up = 0, 36 .dead_time_count_down = 0, 37 .adc_a_compare_match = 0, 38 .adc_b_compare_match = 0, 39 .interrupt_skip_source = GPT_INTERRUPT_SKIP_SOURCE_NONE, 40 .interrupt_skip_count = GPT_INTERRUPT_SKIP_COUNT_0, 41 .interrupt_skip_adc = GPT_INTERRUPT_SKIP_ADC_NONE, 42 .gtioca_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED, 43 .gtiocb_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED, 44 }; 45 #endif 46 const gpt_extended_cfg_t g_timer0_extend = 47 { .gtioca = 48 { .output_enabled = false, .stop_level = GPT_PIN_LEVEL_LOW }, 49 .gtiocb = 50 { .output_enabled = false, .stop_level = GPT_PIN_LEVEL_LOW }, 51 .start_source = (gpt_source_t) (GPT_SOURCE_NONE), .stop_source = (gpt_source_t) (GPT_SOURCE_NONE), .clear_source = 52 (gpt_source_t) (GPT_SOURCE_NONE), 53 .count_up_source = (gpt_source_t) (GPT_SOURCE_NONE), .count_down_source = (gpt_source_t) (GPT_SOURCE_NONE), .capture_a_source = 54 (gpt_source_t) (GPT_SOURCE_NONE), 55 .capture_b_source = (gpt_source_t) (GPT_SOURCE_NONE), .capture_a_ipl = (BSP_IRQ_DISABLED), .capture_b_ipl = 56 (BSP_IRQ_DISABLED), 57 #if defined(VECTOR_NUMBER_GPT0_CAPTURE_COMPARE_A) 58 .capture_a_irq = VECTOR_NUMBER_GPT0_CAPTURE_COMPARE_A, 59 #else 60 .capture_a_irq = FSP_INVALID_VECTOR, 61 #endif 62 #if defined(VECTOR_NUMBER_GPT0_CAPTURE_COMPARE_B) 63 .capture_b_irq = VECTOR_NUMBER_GPT0_CAPTURE_COMPARE_B, 64 #else 65 .capture_b_irq = FSP_INVALID_VECTOR, 66 #endif 67 .capture_filter_gtioca = GPT_CAPTURE_FILTER_NONE, 68 .capture_filter_gtiocb = GPT_CAPTURE_FILTER_NONE, 69 #if 0 70 .p_pwm_cfg = &g_timer0_pwm_extend, 71 #else 72 .p_pwm_cfg = NULL, 73 #endif 74 #if 0 75 .gtior_setting.gtior_b.gtioa = (0U << 4U) | (0U << 2U) | (0U << 0U), 76 .gtior_setting.gtior_b.oadflt = (uint32_t) GPT_PIN_LEVEL_LOW, 77 .gtior_setting.gtior_b.oahld = 0U, 78 .gtior_setting.gtior_b.oae = (uint32_t) false, 79 .gtior_setting.gtior_b.oadf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED, 80 .gtior_setting.gtior_b.nfaen = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U), 81 .gtior_setting.gtior_b.nfcsa = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U), 82 .gtior_setting.gtior_b.gtiob = (0U << 4U) | (0U << 2U) | (0U << 0U), 83 .gtior_setting.gtior_b.obdflt = (uint32_t) GPT_PIN_LEVEL_LOW, 84 .gtior_setting.gtior_b.obhld = 0U, 85 .gtior_setting.gtior_b.obe = (uint32_t) false, 86 .gtior_setting.gtior_b.obdf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED, 87 .gtior_setting.gtior_b.nfben = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U), 88 .gtior_setting.gtior_b.nfcsb = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U), 89 #else 90 .gtior_setting.gtior = 0U, 91 #endif 92 }; 93 const timer_cfg_t g_timer0_cfg = 94 { .mode = TIMER_MODE_PERIODIC, 95 /* Actual period: 0.001 seconds. Actual duty: 50%. */.period_counts = (uint32_t) 0x186a0, 96 .duty_cycle_counts = 0xc350, .source_div = (timer_source_div_t) 0, .channel = 0, .p_callback = timer_1ms, 97 /** If NULL then do not add & */ 98 #if defined(NULL) 99 .p_context = NULL, 100 #else 101 .p_context = &NULL, 102 #endif 103 .p_extend = &g_timer0_extend, 104 .cycle_end_ipl = (15), 105 #if defined(VECTOR_NUMBER_GPT0_COUNTER_OVERFLOW) 106 .cycle_end_irq = VECTOR_NUMBER_GPT0_COUNTER_OVERFLOW, 107 #else 108 .cycle_end_irq = FSP_INVALID_VECTOR, 109 #endif 110 }; 111 /* Instance structure to use this module. */ 112 const timer_instance_t g_timer0 = 113 { .p_ctrl = &g_timer0_ctrl, .p_cfg = &g_timer0_cfg, .p_api = &g_timer_on_gpt }; 114 dtc_instance_ctrl_t g_transfer1_ctrl; 115 116 transfer_info_t g_transfer1_info = 117 { .transfer_settings_word_b.dest_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED, 118 .transfer_settings_word_b.repeat_area = TRANSFER_REPEAT_AREA_DESTINATION, 119 .transfer_settings_word_b.irq = TRANSFER_IRQ_END, 120 .transfer_settings_word_b.chain_mode = TRANSFER_CHAIN_MODE_DISABLED, 121 .transfer_settings_word_b.src_addr_mode = TRANSFER_ADDR_MODE_FIXED, 122 .transfer_settings_word_b.size = TRANSFER_SIZE_1_BYTE, 123 .transfer_settings_word_b.mode = TRANSFER_MODE_NORMAL, 124 .p_dest = (void*) NULL, 125 .p_src = (void const*) NULL, 126 .num_blocks = 0, 127 .length = 0, }; 128 129 const dtc_extended_cfg_t g_transfer1_cfg_extend = 130 { .activation_source = VECTOR_NUMBER_SCI7_RXI, }; 131 const transfer_cfg_t g_transfer1_cfg = 132 { .p_info = &g_transfer1_info, .p_extend = &g_transfer1_cfg_extend, }; 133 134 /* Instance structure to use this module. */ 135 const transfer_instance_t g_transfer1 = 136 { .p_ctrl = &g_transfer1_ctrl, .p_cfg = &g_transfer1_cfg, .p_api = &g_transfer_on_dtc }; 137 dtc_instance_ctrl_t g_transfer0_ctrl; 138 139 transfer_info_t g_transfer0_info = 140 { .transfer_settings_word_b.dest_addr_mode = TRANSFER_ADDR_MODE_FIXED, 141 .transfer_settings_word_b.repeat_area = TRANSFER_REPEAT_AREA_SOURCE, 142 .transfer_settings_word_b.irq = TRANSFER_IRQ_END, 143 .transfer_settings_word_b.chain_mode = TRANSFER_CHAIN_MODE_DISABLED, 144 .transfer_settings_word_b.src_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED, 145 .transfer_settings_word_b.size = TRANSFER_SIZE_1_BYTE, 146 .transfer_settings_word_b.mode = TRANSFER_MODE_NORMAL, 147 .p_dest = (void*) NULL, 148 .p_src = (void const*) NULL, 149 .num_blocks = 0, 150 .length = 0, }; 151 152 const dtc_extended_cfg_t g_transfer0_cfg_extend = 153 { .activation_source = VECTOR_NUMBER_SCI7_TXI, }; 154 const transfer_cfg_t g_transfer0_cfg = 155 { .p_info = &g_transfer0_info, .p_extend = &g_transfer0_cfg_extend, }; 156 157 /* Instance structure to use this module. */ 158 const transfer_instance_t g_transfer0 = 159 { .p_ctrl = &g_transfer0_ctrl, .p_cfg = &g_transfer0_cfg, .p_api = &g_transfer_on_dtc }; 160 sci_uart_instance_ctrl_t g_uart0_ctrl; 161 162 baud_setting_t g_uart0_baud_setting = 163 { 164 /* Baud rate calculated with 0.091% error. */.semr_baudrate_bits_b.abcse = 0, 165 .semr_baudrate_bits_b.abcs = 0, .semr_baudrate_bits_b.bgdm = 1, .cks = 0, .brr = 6, .mddr = (uint8_t) 132, .semr_baudrate_bits_b.brme = 166 true }; 167 168 /** UART extended configuration for UARTonSCI HAL driver */ 169 const sci_uart_extended_cfg_t g_uart0_cfg_extend = 170 { .clock = SCI_UART_CLOCK_INT, .rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE, .noise_cancel = 171 SCI_UART_NOISE_CANCELLATION_DISABLE, 172 .rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX, .p_baud_setting = &g_uart0_baud_setting, .flow_control = 173 SCI_UART_FLOW_CONTROL_RTS, 174 #if 0xFF != 0xFF 175 .flow_control_pin = BSP_IO_PORT_FF_PIN_0xFF, 176 #else 177 .flow_control_pin = (bsp_io_port_pin_t) UINT16_MAX, 178 #endif 179 .rs485_setting = 180 { .enable = SCI_UART_RS485_DISABLE, .polarity = SCI_UART_RS485_DE_POLARITY_HIGH, 181 #if 0xFF != 0xFF 182 .de_control_pin = BSP_IO_PORT_FF_PIN_0xFF, 183 #else 184 .de_control_pin = (bsp_io_port_pin_t) UINT16_MAX, 185 #endif 186 }, }; 187 188 /** UART interface configuration */ 189 const uart_cfg_t g_uart0_cfg = 190 { .channel = 7, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback = 191 user_uart_callback, 192 .p_context = NULL, .p_extend = &g_uart0_cfg_extend, 193 #define RA_NOT_DEFINED (1) 194 #if (RA_NOT_DEFINED == g_transfer0) 195 .p_transfer_tx = NULL, 196 #else 197 .p_transfer_tx = &g_transfer0, 198 #endif 199 #if (RA_NOT_DEFINED == g_transfer1) 200 .p_transfer_rx = NULL, 201 #else 202 .p_transfer_rx = &g_transfer1, 203 #endif 204 #undef RA_NOT_DEFINED 205 .rxi_ipl = (12), 206 .txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12), 207 #if defined(VECTOR_NUMBER_SCI7_RXI) 208 .rxi_irq = VECTOR_NUMBER_SCI7_RXI, 209 #else 210 .rxi_irq = FSP_INVALID_VECTOR, 211 #endif 212 #if defined(VECTOR_NUMBER_SCI7_TXI) 213 .txi_irq = VECTOR_NUMBER_SCI7_TXI, 214 #else 215 .txi_irq = FSP_INVALID_VECTOR, 216 #endif 217 #if defined(VECTOR_NUMBER_SCI7_TEI) 218 .tei_irq = VECTOR_NUMBER_SCI7_TEI, 219 #else 220 .tei_irq = FSP_INVALID_VECTOR, 221 #endif 222 #if defined(VECTOR_NUMBER_SCI7_ERI) 223 .eri_irq = VECTOR_NUMBER_SCI7_ERI, 224 #else 225 .eri_irq = FSP_INVALID_VECTOR, 226 #endif 227 }; 228 229 /* Instance structure to use this module. */ 230 const uart_instance_t g_uart0 = 231 { .p_ctrl = &g_uart0_ctrl, .p_cfg = &g_uart0_cfg, .p_api = &g_uart_on_sci }; 232 void g_hal_init(void) 233 { 234 g_common_init (); 235 } 236