1# BTstack Port for Renesas Eval Kit EK-RA6M4 with DA14531 2 3This port uses the [Renesas EK-RA6M4](https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra6m4-evaluation-kit-ra6m4-mcu-group) and a Renesas DA14531 Controller on the [MikroeE BLE Tiny Click board](https://www.mikroe.com/ble-tiny-click) 4 5Renesas e2 Studio (Eclise-based) was used with the FSP HAL and without an RTOS to generate project sources. 6Then, a new CMake buildfile was created to allow for cross-platform development and compilation of all examples. 7For easy debugging, Ozone project files are generated as well. 8 9## Hardware 10 11### Renesas Eval Kit EK-RA6M4: 12- The RA6 contains a build in J-Link programmer which supports debut output via SEGGER RTT. 13- It uses the MikroBus port for the DA1451 14 15| MikroBus | MCU | Function | 16|----------|-------|---------------------| 17| J21/2 | P115 | RESET (active high) | 18| P21/3 | P205 | RTS | 19| J21/4 | P204 | CTS | 20| J22/4 | P613 | TX | 21| J22/3 | P614 | RX | 22 23- UART RTS: Manual RTS control in UART callback handler. MikroBus slot with UART 7 does not have RTSCTS7 24 on the pin used by BLE Tiny Click module. 25- BSP 26``` 27// 0x1000 main stack 28#define BSP_CFG_STACK_MAIN_BYTES (0x1000) 29 30// printf allocates memory from the heap 31#define BSP_CFG_HEAP_BYTES (0x800) 32``` 33 34### Renesas DA14531 Module on MikroE BLE Tiny Click board with 35- The board comes with some demo application and needs to be programmed with an HCI firmware to use it with a regular Bluetooth stack. 36- Firmware details: 37 - Keil uVision project `DA145xx_SDK/x.x.xx.xxxx/projects/target_apps/hci` on Windows 38 39``` 40// Config: user_periph_setup.h 41#define UART1_TX_PORT GPIO_PORT_0 42#define UART1_TX_PIN GPIO_PIN_6 43#define UART1_RX_PORT GPIO_PORT_0 44#define UART1_RX_PIN GPIO_PIN_5 45#define UART1_RTSN_PORT GPIO_PORT_0 46#define UART1_RTSN_PIN GPIO_PIN_7 47#define UART1_CTSN_PORT GPIO_PORT_0 48#define UART1_CTSN_PIN GPIO_PIN_8 49#define UART1_BAUDRATE UART_BAUDRATE_460800 50#define UART1_DATABITS UART_DATABITS_8 51 52// Config: user_config.h 53static const sleep_state_t app_default_sleep_mode = ARCH_SLEEP_OFF; 54``` 55 56- Firmware installation: 57 - Connect GND (pin 5) and VCC (pin 6) with jumper wires to the RA6 dev board. 58 - Connect it with a ARM-Cortex 10-pin connector to a J-Link device 59 - Start [SmartBond Flash Programmer](https://www.renesas.com/kr/en/software-tool/smartbond-flash-programmer) 60 - The Programmer should auto-detect the DA14531 via the J-Link. 61 - Select `firmware/hci_531_rx05_tx06_rts07_cts08_468000.hex` as firmware file and click `Program` 62 63## Software 64 65The port provides a CMake project file that uses the installed Arm Gnu Toolchain. 66 67- Install [Arm GNU Toolchain](https://developer.arm.com/Tools%20and%20Software/GNU%20Toolchain) 68- Install [CMake](https://cmake.org) 69- Install [Ninja](https://ninja-build.org) 70- To compile, go to the port folder: 71 72 `cd btstack/port/renesas-ek-ra6me4a-da14531` 73 74- Create a build folder and go to build folder 75 76 `mkdir build && cd build` 77 78- Create Ninja build files 79 80 `cmake -G Ninja ..` 81 82- Build all examples 83 84 `ninja` 85 86This will build all examples as .elf files as well as .jdebug Ozone debug project files 87Alternatively, the CMakeLists.txt can be used to compile using Make (`cmake -G "Unix Makefiles" ..` and `make`) or 88or use the project in most modern IDEs (CLion, Visual Studio, Visual Studio Code, ...) 89 90 91## Run Example Project using Ozone 92 93After building the examples, the generated .elf file can be used with Ozone. 94Start Ozone and open the provided .jdebug file. The debug output is readily available in the RTT Terminal. 95 96 97## Debug output 98 99All debug output is send via SEGGER RTT. 100 101In src/btstack_config.h resp. in example/btstack_config.h of the generated projects. 102 103Also, the full packet log with addtional log information can be enabled in src/hal_entry.c by uncommenting the hci_dump_init(...) call. 104 105The console output can then be converted into .pklg files by running tool/create_packet_log.py. The .pklg file can be 106analyzed with the macOS X PacketLogger or WireShark. 107 108 109## Setup 110 111 112 113## Updating HAL Configuration 114- Start Renesas RA v3.7.0/e2-studio on Windows and open `e2-project` 115- Open `configuration.xml` to get to "FSP Configuration" perspective 116 - to add modules, click "New Stack" 117 - module is configured in "Properties" view (usually below next to 'Problems' etc) 118- Press button re-generates sources 119- Copy folder `e2-project` into this port 120- Check diff for unexpected changes 121- If needed: 122 - Update CMakeLists.txt to add new modules 123 - Add code to enable ('open') new module in `R_BSP_WarmStart` of `port/hal_entry.c` 124
