xref: /btstack/port/msp432p401lp-cc256x/ti/devices/msp432p4xx/inc/msp432p4xx.h (revision cd5f23a3250874824c01a2b3326a9522fea3f99f)
1 /******************************************************************************
2 *
3 * Copyright (C) 2012 - 18 Texas Instruments Incorporated - http://www.ti.com/
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 *  Redistributions of source code must retain the above copyright
10 *  notice, this list of conditions and the following disclaimer.
11 *
12 *  Redistributions in binary form must reproduce the above copyright
13 *  notice, this list of conditions and the following disclaimer in the
14 *  documentation and/or other materials provided with the
15 *  distribution.
16 *
17 *  Neither the name of Texas Instruments Incorporated nor the names of
18 *  its contributors may be used to endorse or promote products derived
19 *  from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 * MSP432P4XX Register Definitions
34 *
35 * This file includes CMSIS compliant component and register definitions
36 *
37 * For legacy components the definitions that are compatible with MSP430 code,
38 * are included with msp432p4xx_classic.h
39 *
40 * With CMSIS definitions, the register defines have been reformatted:
41 *     ModuleName[ModuleInstance]->RegisterName
42 *
43 * Writing to CMSIS bit fields can be done through register level
44 * or via bitband area access:
45 *  - ADC14->CTL0 |= ADC14_CTL0_ENC;
46 *  - BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_ENC_OFS) = 1;
47 *
48 * File creation date: 2018-01-26
49 *
50 ******************************************************************************/
51 
52 #ifndef __MSP432P4XX_H__
53 #define __MSP432P4XX_H__
54 
55 /* Use standard integer types with explicit width */
56 #include <stdint.h>
57 
58 #ifdef __cplusplus
59  extern "C" {
60 #endif
61 
62 #define __MSP432_HEADER_VERSION__ 3.231
63 
64 /* WARNING: The msp432p4xx.h file is indented to be used to rebuild TI Drivers for MSP432 MCUs. Do not use this file to build target code.*/
65 
66 /* Remap MSP432 intrinsics to ARM equivalents */
67 #include "msp_compatibility.h"
68 
69 #ifndef __CMSIS_CONFIG__
70 #define __CMSIS_CONFIG__
71 
72 /** @addtogroup MSP432P4XX_Definitions MSP432P4XX Definitions
73   This file defines all structures and symbols for MSP432P4XX:
74     - components and registers
75     - peripheral base address
76     - peripheral ID
77     - Peripheral definitions
78   @{
79 */
80 
81 /******************************************************************************
82 *                Processor and Core Peripherals                               *
83 ******************************************************************************/
84 /** @addtogroup MSP432P4XX_CMSIS Device CMSIS Definitions
85   Configuration of the Cortex-M4 Processor and Core Peripherals
86   @{
87 */
88 
89 /******************************************************************************
90 * CMSIS-compatible Interrupt Number Definition                                *
91 ******************************************************************************/
92 typedef enum IRQn
93 {
94   /* Cortex-M4 Processor Exceptions Numbers */
95   NonMaskableInt_IRQn         = -14,    /*  2 Non Maskable Interrupt */
96   HardFault_IRQn              = -13,    /*  3 Hard Fault Interrupt */
97   MemoryManagement_IRQn       = -12,    /*  4 Memory Management Interrupt */
98   BusFault_IRQn               = -11,    /*  5 Bus Fault Interrupt */
99   UsageFault_IRQn             = -10,    /*  6 Usage Fault Interrupt */
100   SVCall_IRQn                 = -5,     /* 11 SV Call Interrupt */
101   DebugMonitor_IRQn           = -4,     /* 12 Debug Monitor Interrupt */
102   PendSV_IRQn                 = -2,     /* 14 Pend SV Interrupt */
103   SysTick_IRQn                = -1,     /* 15 System Tick Interrupt */
104   /*  Peripheral Exceptions Numbers */
105   PSS_IRQn                    = 0,     /* 16 PSS Interrupt             */
106   CS_IRQn                     = 1,     /* 17 CS Interrupt              */
107   PCM_IRQn                    = 2,     /* 18 PCM Interrupt             */
108   WDT_A_IRQn                  = 3,     /* 19 WDT_A Interrupt           */
109   FPU_IRQn                    = 4,     /* 20 FPU Interrupt             */
110   FLCTL_IRQn                  = 5,     /* 21 Flash Controller Interrupt*/
111   COMP_E0_IRQn                = 6,     /* 22 COMP_E0 Interrupt         */
112   COMP_E1_IRQn                = 7,     /* 23 COMP_E1 Interrupt         */
113   TA0_0_IRQn                  = 8,     /* 24 TA0_0 Interrupt           */
114   TA0_N_IRQn                  = 9,     /* 25 TA0_N Interrupt           */
115   TA1_0_IRQn                  = 10,     /* 26 TA1_0 Interrupt           */
116   TA1_N_IRQn                  = 11,     /* 27 TA1_N Interrupt           */
117   TA2_0_IRQn                  = 12,     /* 28 TA2_0 Interrupt           */
118   TA2_N_IRQn                  = 13,     /* 29 TA2_N Interrupt           */
119   TA3_0_IRQn                  = 14,     /* 30 TA3_0 Interrupt           */
120   TA3_N_IRQn                  = 15,     /* 31 TA3_N Interrupt           */
121   EUSCIA0_IRQn                = 16,     /* 32 EUSCIA0 Interrupt         */
122   EUSCIA1_IRQn                = 17,     /* 33 EUSCIA1 Interrupt         */
123   EUSCIA2_IRQn                = 18,     /* 34 EUSCIA2 Interrupt         */
124   EUSCIA3_IRQn                = 19,     /* 35 EUSCIA3 Interrupt         */
125   EUSCIB0_IRQn                = 20,     /* 36 EUSCIB0 Interrupt         */
126   EUSCIB1_IRQn                = 21,     /* 37 EUSCIB1 Interrupt         */
127   EUSCIB2_IRQn                = 22,     /* 38 EUSCIB2 Interrupt         */
128   EUSCIB3_IRQn                = 23,     /* 39 EUSCIB3 Interrupt         */
129   ADC14_IRQn                  = 24,     /* 40 ADC14 Interrupt           */
130   T32_INT1_IRQn               = 25,     /* 41 T32_INT1 Interrupt        */
131   T32_INT2_IRQn               = 26,     /* 42 T32_INT2 Interrupt        */
132   T32_INTC_IRQn               = 27,     /* 43 T32_INTC Interrupt        */
133   AES256_IRQn                 = 28,     /* 44 AES256 Interrupt          */
134   RTC_C_IRQn                  = 29,     /* 45 RTC_C Interrupt           */
135   DMA_ERR_IRQn                = 30,     /* 46 DMA_ERR Interrupt         */
136   DMA_INT3_IRQn               = 31,     /* 47 DMA_INT3 Interrupt        */
137   DMA_INT2_IRQn               = 32,     /* 48 DMA_INT2 Interrupt        */
138   DMA_INT1_IRQn               = 33,     /* 49 DMA_INT1 Interrupt        */
139   DMA_INT0_IRQn               = 34,     /* 50 DMA_INT0 Interrupt        */
140   PORT1_IRQn                  = 35,     /* 51 Port1 Interrupt           */
141   PORT2_IRQn                  = 36,     /* 52 Port2 Interrupt           */
142   PORT3_IRQn                  = 37,     /* 53 Port3 Interrupt           */
143   PORT4_IRQn                  = 38,     /* 54 Port4 Interrupt           */
144   PORT5_IRQn                  = 39,     /* 55 Port5 Interrupt           */
145   FLCTL_A_IRQn                = 5,     /* 21 Flash Controller Interrupt*/
146   PORT6_IRQn                  = 40,     /* 56 Port6 Interrupt           */
147   LCD_F_IRQn                  = 41      /* 57 LCD_F Interrupt           */
148 } IRQn_Type;
149 
150 /******************************************************************************
151 * Processor and Core Peripheral Section                                       *
152 ******************************************************************************/
153 #define __CM4_REV               0x0001    /* Core revision r0p1 */
154 #define __MPU_PRESENT           1         /* MPU present or not */
155 #define __NVIC_PRIO_BITS        3         /* Number of Bits used for Prio Levels */
156 #define __Vendor_SysTickConfig  0         /* Set to 1 if different SysTick Config is used */
157 #define __FPU_PRESENT           1         /* FPU present or not */
158 
159 /******************************************************************************
160 * Available Peripherals                                                       *
161 ******************************************************************************/
162 #define __MCU_HAS_ADC14__                                                        /*!< Module ADC14 is available */
163 #define __MCU_HAS_AES256__                                                       /*!< Module AES256 is available */
164 #define __MCU_HAS_CAPTIO0__                                                      /*!< Module CAPTIO0 is available */
165 #define __MCU_HAS_CAPTIO1__                                                      /*!< Module CAPTIO1 is available */
166 #define __MCU_HAS_COMP_E0__                                                      /*!< Module COMP_E0 is available */
167 #define __MCU_HAS_COMP_E1__                                                      /*!< Module COMP_E1 is available */
168 #define __MCU_HAS_CRC32__                                                        /*!< Module CRC32 is available */
169 #define __MCU_HAS_CS__                                                           /*!< Module CS is available */
170 #define __MCU_HAS_DIO__                                                          /*!< Module DIO is available */
171 #define __MCU_HAS_DMA__                                                          /*!< Module DMA is available */
172 #define __MCU_HAS_EUSCI_A0__                                                     /*!< Module EUSCI_A0 is available */
173 #define __MCU_HAS_EUSCI_A1__                                                     /*!< Module EUSCI_A1 is available */
174 #define __MCU_HAS_EUSCI_A2__                                                     /*!< Module EUSCI_A2 is available */
175 #define __MCU_HAS_EUSCI_A3__                                                     /*!< Module EUSCI_A3 is available */
176 #define __MCU_HAS_EUSCI_B0__                                                     /*!< Module EUSCI_B0 is available */
177 #define __MCU_HAS_EUSCI_B1__                                                     /*!< Module EUSCI_B1 is available */
178 #define __MCU_HAS_EUSCI_B2__                                                     /*!< Module EUSCI_B2 is available */
179 #define __MCU_HAS_EUSCI_B3__                                                     /*!< Module EUSCI_B3 is available */
180 #define __MCU_HAS_FLCTL__                                                        /*!< Module FLCTL is available */
181 #define __MCU_HAS_FL_BOOTOVER_MAILBOX__                                          /*!< Module FL_BOOTOVER_MAILBOX is available */
182 #define __MCU_HAS_PCM__                                                          /*!< Module PCM is available */
183 #define __MCU_HAS_PMAP__                                                         /*!< Module PMAP is available */
184 #define __MCU_HAS_PSS__                                                          /*!< Module PSS is available */
185 #define __MCU_HAS_REF_A__                                                        /*!< Module REF_A is available */
186 #define __MCU_HAS_RSTCTL__                                                       /*!< Module RSTCTL is available */
187 #define __MCU_HAS_RTC_C__                                                        /*!< Module RTC_C is available */
188 #define __MCU_HAS_SYSCTL__                                                       /*!< Module SYSCTL is available */
189 #define __MCU_HAS_TIMER32__                                                      /*!< Module TIMER32 is available */
190 #define __MCU_HAS_TIMER_A0__                                                     /*!< Module TIMER_A0 is available */
191 #define __MCU_HAS_TIMER_A1__                                                     /*!< Module TIMER_A1 is available */
192 #define __MCU_HAS_TIMER_A2__                                                     /*!< Module TIMER_A2 is available */
193 #define __MCU_HAS_TIMER_A3__                                                     /*!< Module TIMER_A3 is available */
194 #define __MCU_HAS_TLV__                                                          /*!< Module TLV is available */
195 #define __MCU_HAS_WDT_A__                                                        /*!< Module WDT_A is available */
196 #define __MCU_HAS_FLCTL_A__                                                      /*!< Module FLCTL_A is available */
197 #define __MCU_HAS_LCD_F__                                                        /*!< Module LCD_F is available */
198 #define __MCU_HAS_SYSCTL_A__                                                     /*!< Module SYSCTL_A is available */
199 
200 #define __MSP432_HAS_PORTA_R__
201 #define __MSP432_HAS_PORTB_R__
202 #define __MSP432_HAS_PORTC_R__
203 #define __MSP432_HAS_PORTD_R__
204 #define __MSP432_HAS_PORTE_R__
205 #define __MSP432_HAS_PORTJ_R__
206 #define __MSP432_HAS_PORT1_R__
207 #define __MSP432_HAS_PORT2_R__
208 #define __MSP432_HAS_PORT3_R__
209 #define __MSP432_HAS_PORT4_R__
210 #define __MSP432_HAS_PORT5_R__
211 #define __MSP432_HAS_PORT6_R__
212 #define __MSP432_HAS_PORT7_R__
213 #define __MSP432_HAS_PORT8_R__
214 #define __MSP432_HAS_PORT9_R__
215 #define __MSP432_HAS_PORT10_R__
216 
217 
218 /*@}*/ /* end of group MSP432P4XX_CMSIS */
219 
220 /* Include CMSIS Cortex-M4 Core Peripheral Access Layer Header File */
221 #ifdef __TI_ARM__
222 /* disable the TI ULP advisor check for the core header file definitions */
223 #pragma diag_push
224 #pragma CHECK_ULP("none")
225 #include "core_cm4.h"
226 #pragma diag_pop
227 #else
228 #include "core_cm4.h"
229 #endif
230 
231 /* System Header */
232 #include "system_msp432p401r.h"
233 
234 /******************************************************************************
235 * Definition of standard bits                                                 *
236 ******************************************************************************/
237 #define BIT0                                     (uint16_t)(0x0001)
238 #define BIT1                                     (uint16_t)(0x0002)
239 #define BIT2                                     (uint16_t)(0x0004)
240 #define BIT3                                     (uint16_t)(0x0008)
241 #define BIT4                                     (uint16_t)(0x0010)
242 #define BIT5                                     (uint16_t)(0x0020)
243 #define BIT6                                     (uint16_t)(0x0040)
244 #define BIT7                                     (uint16_t)(0x0080)
245 #define BIT8                                     (uint16_t)(0x0100)
246 #define BIT9                                     (uint16_t)(0x0200)
247 #define BITA                                     (uint16_t)(0x0400)
248 #define BITB                                     (uint16_t)(0x0800)
249 #define BITC                                     (uint16_t)(0x1000)
250 #define BITD                                     (uint16_t)(0x2000)
251 #define BITE                                     (uint16_t)(0x4000)
252 #define BITF                                     (uint16_t)(0x8000)
253 #define BIT(x)                                 ((uint16_t)1 << (x))
254 
255 /******************************************************************************
256 * Device and peripheral memory map                                            *
257 ******************************************************************************/
258 /** @addtogroup MSP432P4XX_MemoryMap MSP432P4XX Memory Mapping
259   @{
260 */
261 
262 #define FLASH_BASE                               ((uint32_t)0x00000000)          /*!< Main Flash memory start address */
263 #define SRAM_BASE                                ((uint32_t)0x20000000)          /*!< SRAM memory start address */
264 #define PERIPH_BASE                              ((uint32_t)0x40000000)          /*!< Peripherals start address */
265 #define PERIPH_BASE2                             ((uint32_t)0xE0000000)          /*!< Peripherals start address */
266 #define ADC14_BASE                            (PERIPH_BASE +0x00012000)          /*!< Base address of module ADC14 registers */
267 #define AES256_BASE                           (PERIPH_BASE +0x00003C00)          /*!< Base address of module AES256 registers */
268 #define CAPTIO0_BASE                          (PERIPH_BASE +0x00005400)          /*!< Base address of module CAPTIO0 registers */
269 #define CAPTIO1_BASE                          (PERIPH_BASE +0x00005800)          /*!< Base address of module CAPTIO1 registers */
270 #define COMP_E0_BASE                          (PERIPH_BASE +0x00003400)          /*!< Base address of module COMP_E0 registers */
271 #define COMP_E1_BASE                          (PERIPH_BASE +0x00003800)          /*!< Base address of module COMP_E1 registers */
272 #define CRC32_BASE                            (PERIPH_BASE +0x00004000)          /*!< Base address of module CRC32 registers */
273 #define CS_BASE                               (PERIPH_BASE +0x00010400)          /*!< Base address of module CS registers */
274 #define DIO_BASE                              (PERIPH_BASE +0x00004C00)          /*!< Base address of module DIO registers */
275 #define DMA_BASE                              (PERIPH_BASE +0x0000E000)          /*!< Base address of module DMA registers */
276 #define EUSCI_A0_BASE                         (PERIPH_BASE +0x00001000)          /*!< Base address of module EUSCI_A0 registers */
277 #define EUSCI_A0_SPI_BASE                     (PERIPH_BASE +0x00001000)          /*!< Base address of module EUSCI_A0 registers */
278 #define EUSCI_A1_BASE                         (PERIPH_BASE +0x00001400)          /*!< Base address of module EUSCI_A1 registers */
279 #define EUSCI_A1_SPI_BASE                     (PERIPH_BASE +0x00001400)          /*!< Base address of module EUSCI_A1 registers */
280 #define EUSCI_A2_BASE                         (PERIPH_BASE +0x00001800)          /*!< Base address of module EUSCI_A2 registers */
281 #define EUSCI_A2_SPI_BASE                     (PERIPH_BASE +0x00001800)          /*!< Base address of module EUSCI_A2 registers */
282 #define EUSCI_A3_BASE                         (PERIPH_BASE +0x00001C00)          /*!< Base address of module EUSCI_A3 registers */
283 #define EUSCI_A3_SPI_BASE                     (PERIPH_BASE +0x00001C00)          /*!< Base address of module EUSCI_A3 registers */
284 #define EUSCI_B0_BASE                         (PERIPH_BASE +0x00002000)          /*!< Base address of module EUSCI_B0 registers */
285 #define EUSCI_B0_SPI_BASE                     (PERIPH_BASE +0x00002000)          /*!< Base address of module EUSCI_B0 registers */
286 #define EUSCI_B1_BASE                         (PERIPH_BASE +0x00002400)          /*!< Base address of module EUSCI_B1 registers */
287 #define EUSCI_B1_SPI_BASE                     (PERIPH_BASE +0x00002400)          /*!< Base address of module EUSCI_B1 registers */
288 #define EUSCI_B2_BASE                         (PERIPH_BASE +0x00002800)          /*!< Base address of module EUSCI_B2 registers */
289 #define EUSCI_B2_SPI_BASE                     (PERIPH_BASE +0x00002800)          /*!< Base address of module EUSCI_B2 registers */
290 #define EUSCI_B3_BASE                         (PERIPH_BASE +0x00002C00)          /*!< Base address of module EUSCI_B3 registers */
291 #define EUSCI_B3_SPI_BASE                     (PERIPH_BASE +0x00002C00)          /*!< Base address of module EUSCI_B3 registers */
292 #define FLCTL_BASE                            (PERIPH_BASE +0x00011000)          /*!< Base address of module FLCTL registers */
293 #define FL_BOOTOVER_MAILBOX_BASE                 ((uint32_t)0x00200000)          /*!< Base address of module FL_BOOTOVER_MAILBOX registers */
294 #define PCM_BASE                              (PERIPH_BASE +0x00010000)          /*!< Base address of module PCM registers */
295 #define PMAP_BASE                             (PERIPH_BASE +0x00005000)          /*!< Base address of module PMAP registers */
296 #define PSS_BASE                              (PERIPH_BASE +0x00010800)          /*!< Base address of module PSS registers */
297 #define REF_A_BASE                            (PERIPH_BASE +0x00003000)          /*!< Base address of module REF_A registers */
298 #define RSTCTL_BASE                           (PERIPH_BASE2+0x00042000)          /*!< Base address of module RSTCTL registers */
299 #define RTC_C_BASE                            (PERIPH_BASE +0x00004400)          /*!< Base address of module RTC_C registers */
300 #define RTC_C_BCD_BASE                        (PERIPH_BASE +0x00004400)          /*!< Base address of module RTC_C registers */
301 #define SYSCTL_BASE                           (PERIPH_BASE2+0x00043000)          /*!< Base address of module SYSCTL registers */
302 #define TIMER32_BASE                          (PERIPH_BASE +0x0000C000)          /*!< Base address of module TIMER32 registers */
303 #define TIMER_A0_BASE                         (PERIPH_BASE +0x00000000)          /*!< Base address of module TIMER_A0 registers */
304 #define TIMER_A1_BASE                         (PERIPH_BASE +0x00000400)          /*!< Base address of module TIMER_A1 registers */
305 #define TIMER_A2_BASE                         (PERIPH_BASE +0x00000800)          /*!< Base address of module TIMER_A2 registers */
306 #define TIMER_A3_BASE                         (PERIPH_BASE +0x00000C00)          /*!< Base address of module TIMER_A3 registers */
307 #define TLV_BASE                                 ((uint32_t)0x00201000)          /*!< Base address of module TLV registers */
308 #define WDT_A_BASE                            (PERIPH_BASE +0x00004800)          /*!< Base address of module WDT_A registers */
309 #define TLV_START_ADDR                    (TLV_BASE + 0x0004)                    /*!< Start Address of the TLV structure */
310 #define FLCTL_A_BASE                          (PERIPH_BASE +0x00011000)          /*!< Base address of module FLCTL_A registers */
311 #define LCD_F_BASE                            (PERIPH_BASE +0x00012400)          /*!< Base address of module LCD_F registers */
312 #define SYSCTL_A_BASE                         (PERIPH_BASE2+0x00043000)          /*!< Base address of module SYSCTL_A registers */
313 
314 
315 
316 /*@}*/ /* end of group MSP432P4XX_MemoryMap */
317 
318 /******************************************************************************
319 * Definitions for bit band access                                             *
320 ******************************************************************************/
321 #define BITBAND_SRAM_BASE                     ((uint32_t)(0x22000000))
322 #define BITBAND_PERI_BASE                     ((uint32_t)(0x42000000))
323 
324 /* SRAM allows 32 bit bit band access */
325 #define BITBAND_SRAM(x, b)  (*((__IO uint32_t *) (BITBAND_SRAM_BASE +  (((uint32_t)(volatile const uint32_t *)&(x)) - SRAM_BASE  )*32 + (b)*4)))
326 /* peripherals with 8 bit or 16 bit register access allow only 8 bit or 16 bit bit band access, so cast to 8 bit always */
327 #define BITBAND_PERI(x, b)  (*((__IO  uint8_t *) (BITBAND_PERI_BASE +  (((uint32_t)(volatile const uint32_t *)&(x)) - PERIPH_BASE)*32 + (b)*4)))
328 
329 /******************************************************************************
330 * Peripheral register definitions                                             *
331 ******************************************************************************/
332 /** @addtogroup MSP432P4XX_Peripherals MSP432P4XX Peripherals
333   MSP432P4XX Device Specific Peripheral registers structures
334   @{
335 */
336 
337 /* -------  Start of section using anonymous unions and disabling warnings  ------- */
338 #if defined (__CC_ARM)
339   #pragma push
340   #pragma anon_unions
341 #elif defined (__ICCARM__)
342   #pragma language=extended
343 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
344   #pragma clang diagnostic push
345   #pragma clang diagnostic ignored "-Wc11-extensions"
346 #elif defined (__GNUC__)
347   /* anonymous unions are enabled by default */
348 #elif defined (__TI_ARM__)
349   /* anonymous unions are enabled by default */
350 #else
351   #warning Not supported compiler type
352 #endif
353 
354 
355 
356 typedef struct {
357   __IO uint32_t CTL0;                                                            /*!< Control 0 Register */
358   __IO uint32_t CTL1;                                                            /*!< Control 1 Register */
359   __IO uint32_t LO0;                                                             /*!< Window Comparator Low Threshold 0 Register */
360   __IO uint32_t HI0;                                                             /*!< Window Comparator High Threshold 0 Register */
361   __IO uint32_t LO1;                                                             /*!< Window Comparator Low Threshold 1 Register */
362   __IO uint32_t HI1;                                                             /*!< Window Comparator High Threshold 1 Register */
363   __IO uint32_t MCTL[32];                                                        /*!< Conversion Memory Control Register */
364   __IO uint32_t MEM[32];                                                         /*!< Conversion Memory Register */
365        uint32_t RESERVED0[9];
366   __IO uint32_t IER0;                                                            /*!< Interrupt Enable 0 Register */
367   __IO uint32_t IER1;                                                            /*!< Interrupt Enable 1 Register */
368   __I  uint32_t IFGR0;                                                           /*!< Interrupt Flag 0 Register */
369   __I  uint32_t IFGR1;                                                           /*!< Interrupt Flag 1 Register */
370   __O  uint32_t CLRIFGR0;                                                        /*!< Clear Interrupt Flag 0 Register */
371   __IO uint32_t CLRIFGR1;                                                        /*!< Clear Interrupt Flag 1 Register */
372   __IO uint32_t IV;                                                              /*!< Interrupt Vector Register */
373 } ADC14_Type;
374 
375 typedef struct {
376   __IO uint16_t CTL0;                                                            /*!< AES Accelerator Control Register 0 */
377   __IO uint16_t CTL1;                                                            /*!< AES Accelerator Control Register 1 */
378   __IO uint16_t STAT;                                                            /*!< AES Accelerator Status Register */
379   __O  uint16_t KEY;                                                             /*!< AES Accelerator Key Register */
380   __O  uint16_t DIN;                                                             /*!< AES Accelerator Data In Register */
381   __O  uint16_t DOUT;                                                            /*!< AES Accelerator Data Out Register */
382   __O  uint16_t XDIN;                                                            /*!< AES Accelerator XORed Data In Register */
383   __O  uint16_t XIN;                                                             /*!< AES Accelerator XORed Data In Register */
384 } AES256_Type;
385 
386 typedef struct {
387        uint16_t RESERVED0[7];
388   __IO uint16_t CTL;                                                             /*!< Capacitive Touch IO x Control Register */
389 } CAPTIO_Type;
390 
391 typedef struct {
392   __IO uint16_t CTL0;                                                            /*!< Comparator Control Register 0 */
393   __IO uint16_t CTL1;                                                            /*!< Comparator Control Register 1 */
394   __IO uint16_t CTL2;                                                            /*!< Comparator Control Register 2 */
395   __IO uint16_t CTL3;                                                            /*!< Comparator Control Register 3 */
396        uint16_t RESERVED0[2];
397   __IO uint16_t INT;                                                             /*!< Comparator Interrupt Control Register */
398   __I  uint16_t IV;                                                              /*!< Comparator Interrupt Vector Word Register */
399 } COMP_E_Type;
400 
401 typedef struct {
402   __IO uint16_t DI32;                                                            /*!< Data Input for CRC32 Signature Computation */
403        uint16_t RESERVED0;
404   __IO uint16_t DIRB32;                                                          /*!< Data In Reverse for CRC32 Computation */
405        uint16_t RESERVED1;
406   __IO uint16_t INIRES32_LO;                                                     /*!< CRC32 Initialization and Result, lower 16 bits */
407   __IO uint16_t INIRES32_HI;                                                     /*!< CRC32 Initialization and Result, upper 16 bits */
408   __IO uint16_t RESR32_LO;                                                       /*!< CRC32 Result Reverse, lower 16 bits */
409   __IO uint16_t RESR32_HI;                                                       /*!< CRC32 Result Reverse, Upper 16 bits */
410   __IO uint16_t DI16;                                                            /*!< Data Input for CRC16 computation */
411        uint16_t RESERVED2;
412   __IO uint16_t DIRB16;                                                          /*!< CRC16 Data In Reverse */
413        uint16_t RESERVED3;
414   __IO uint16_t INIRES16;                                                        /*!< CRC16 Initialization and Result register */
415        uint16_t RESERVED4[2];
416   __IO uint16_t RESR16;                                                          /*!< CRC16 Result Reverse */
417 } CRC32_Type;
418 
419 typedef struct {
420   __IO uint32_t KEY;                                                             /*!< Key Register */
421   __IO uint32_t CTL0;                                                            /*!< Control 0 Register */
422   __IO uint32_t CTL1;                                                            /*!< Control 1 Register */
423   __IO uint32_t CTL2;                                                            /*!< Control 2 Register */
424   __IO uint32_t CTL3;                                                            /*!< Control 3 Register */
425        uint32_t RESERVED0[7];
426   __IO uint32_t CLKEN;                                                           /*!< Clock Enable Register */
427   __I  uint32_t STAT;                                                            /*!< Status Register */
428        uint32_t RESERVED1[2];
429   __IO uint32_t IE;                                                              /*!< Interrupt Enable Register */
430        uint32_t RESERVED2;
431   __I  uint32_t IFG;                                                             /*!< Interrupt Flag Register */
432        uint32_t RESERVED3;
433   __O  uint32_t CLRIFG;                                                          /*!< Clear Interrupt Flag Register */
434        uint32_t RESERVED4;
435   __O  uint32_t SETIFG;                                                          /*!< Set Interrupt Flag Register */
436        uint32_t RESERVED5;
437   __IO uint32_t DCOERCAL0;                                                       /*!< DCO External Resistor Cailbration 0 Register */
438   __IO uint32_t DCOERCAL1;                                                       /*!< DCO External Resistor Calibration 1 Register */
439 } CS_Type;
440 
441 typedef struct {
442   uint8_t RESERVED0;
443   __I uint8_t IN;                                                                 /*!< Port Input */
444   uint8_t RESERVED1;
445   __IO uint8_t OUT;                                                               /*!< Port Output */
446   uint8_t RESERVED2;
447   __IO uint8_t DIR;                                                               /*!< Port Direction */
448   uint8_t RESERVED3;
449   __IO uint8_t REN;                                                               /*!< Port Resistor Enable */
450   uint8_t RESERVED4;
451   __IO uint8_t DS;                                                                /*!< Port Drive Strength */
452   uint8_t RESERVED5;
453   __IO uint8_t SEL0;                                                              /*!< Port Select 0 */
454   uint8_t RESERVED6;
455   __IO uint8_t SEL1;                                                              /*!< Port Select 1 */
456   uint8_t RESERVED7[9];
457   __IO uint8_t SELC;                                                              /*!< Port Complement Select */
458   uint8_t RESERVED8;
459   __IO uint8_t IES;                                                               /*!< Port Interrupt Edge Select */
460   uint8_t RESERVED9;
461   __IO uint8_t IE;                                                                /*!< Port Interrupt Enable */
462   uint8_t RESERVED10;
463   __IO uint8_t IFG;                                                               /*!< Port Interrupt Flag */
464   __I uint16_t IV;                                                                /*!< Port Interrupt Vector Value */
465 } DIO_PORT_Even_Interruptable_Type;
466 
467 typedef struct {
468   union {
469     __I uint16_t IN;                                                              /*!< Port Pair Input */
470     struct {
471       __I uint8_t IN_L;                                                           /*!< Low Port Input */
472       __I uint8_t IN_H;                                                           /*!< High Port Input */
473     };
474   };
475   union {
476     __IO uint16_t OUT;                                                            /*!< Port Pair Output */
477     struct {
478       __IO uint8_t OUT_L;                                                         /*!< Low Port Output */
479       __IO uint8_t OUT_H;                                                         /*!< High Port Output */
480     };
481   };
482   union {
483     __IO uint16_t DIR;                                                            /*!< Port Pair Direction */
484     struct {
485       __IO uint8_t DIR_L;                                                         /*!< Low Port Direction */
486       __IO uint8_t DIR_H;                                                         /*!< High Port Direction */
487     };
488   };
489   union {
490     __IO uint16_t REN;                                                            /*!< Port Pair Resistor Enable */
491     struct {
492       __IO uint8_t REN_L;                                                         /*!< Low Port Resistor Enable */
493       __IO uint8_t REN_H;                                                         /*!< High Port Resistor Enable */
494     };
495   };
496   union {
497     __IO uint16_t DS;                                                             /*!< Port Pair Drive Strength */
498     struct {
499       __IO uint8_t DS_L;                                                          /*!< Low Port Drive Strength */
500       __IO uint8_t DS_H;                                                          /*!< High Port Drive Strength */
501     };
502   };
503   union {
504     __IO uint16_t SEL0;                                                           /*!< Port Pair Select 0 */
505     struct {
506       __IO uint8_t SEL0_L;                                                        /*!< Low Port Select 0 */
507       __IO uint8_t SEL0_H;                                                        /*!< High Port Select 0 */
508     };
509   };
510   union {
511     __IO uint16_t SEL1;                                                           /*!< Port Pair Select 1 */
512     struct {
513       __IO uint8_t SEL1_L;                                                        /*!< Low Port Select 1 */
514       __IO uint8_t SEL1_H;                                                        /*!< High Port Select 1 */
515     };
516   };
517   __I  uint16_t IV_L;                                                             /*!< Low Port Interrupt Vector Value */
518   uint16_t  RESERVED0[3];
519   union {
520     __IO uint16_t SELC;                                                           /*!< Port Pair Complement Select */
521     struct {
522       __IO uint8_t SELC_L;                                                        /*!< Low Port Complement Select */
523       __IO uint8_t SELC_H;                                                        /*!< High Port Complement Select */
524     };
525   };
526   union {
527     __IO uint16_t IES;                                                            /*!< Port Pair Interrupt Edge Select */
528     struct {
529       __IO uint8_t IES_L;                                                         /*!< Low Port Interrupt Edge Select */
530       __IO uint8_t IES_H;                                                         /*!< High Port Interrupt Edge Select */
531     };
532   };
533   union {
534     __IO uint16_t IE;                                                             /*!< Port Pair Interrupt Enable */
535     struct {
536       __IO uint8_t IE_L;                                                          /*!< Low Port Interrupt Enable */
537       __IO uint8_t IE_H;                                                          /*!< High Port Interrupt Enable */
538     };
539   };
540   union {
541     __IO uint16_t IFG;                                                            /*!< Port Pair Interrupt Flag */
542     struct {
543       __IO uint8_t IFG_L;                                                         /*!< Low Port Interrupt Flag */
544       __IO uint8_t IFG_H;                                                         /*!< High Port Interrupt Flag */
545     };
546   };
547   __I uint16_t IV_H;                                                              /*!< High Port Interrupt Vector Value */
548 } DIO_PORT_Interruptable_Type;
549 
550 typedef struct {
551   union {
552     __I uint16_t IN;                                                              /*!< Port Pair Input */
553     struct {
554       __I uint8_t IN_L;                                                           /*!< Low Port Input */
555       __I uint8_t IN_H;                                                           /*!< High Port Input */
556     };
557   };
558   union {
559     __IO uint16_t OUT;                                                            /*!< Port Pair Output */
560     struct {
561       __IO uint8_t OUT_L;                                                         /*!< Low Port Output */
562       __IO uint8_t OUT_H;                                                         /*!< High Port Output */
563     };
564   };
565   union {
566     __IO uint16_t DIR;                                                            /*!< Port Pair Direction */
567     struct {
568       __IO uint8_t DIR_L;                                                         /*!< Low Port Direction */
569       __IO uint8_t DIR_H;                                                         /*!< High Port Direction */
570     };
571   };
572   union {
573     __IO uint16_t REN;                                                            /*!< Port Pair Resistor Enable */
574     struct {
575       __IO uint8_t REN_L;                                                         /*!< Low Port Resistor Enable */
576       __IO uint8_t REN_H;                                                         /*!< High Port Resistor Enable */
577     };
578   };
579   union {
580     __IO uint16_t DS;                                                             /*!< Port Pair Drive Strength */
581     struct {
582       __IO uint8_t DS_L;                                                          /*!< Low Port Drive Strength */
583       __IO uint8_t DS_H;                                                          /*!< High Port Drive Strength */
584     };
585   };
586   union {
587     __IO uint16_t SEL0;                                                           /*!< Port Pair Select 0 */
588     struct {
589       __IO uint8_t SEL0_L;                                                        /*!< Low Port Select 0 */
590       __IO uint8_t SEL0_H;                                                        /*!< High Port Select 0 */
591     };
592   };
593   union {
594     __IO uint16_t SEL1;                                                           /*!< Port Pair Select 1 */
595     struct {
596       __IO uint8_t SEL1_L;                                                        /*!< Low Port Select 1 */
597       __IO uint8_t SEL1_H;                                                        /*!< High Port Select 1 */
598     };
599   };
600   uint16_t  RESERVED0[4];
601   union {
602     __IO uint16_t SELC;                                                           /*!< Port Pair Complement Select */
603     struct {
604       __IO uint8_t SELC_L;                                                        /*!< Low Port Complement Select */
605       __IO uint8_t SELC_H;                                                        /*!< High Port Complement Select */
606     };
607   };
608 } DIO_PORT_Not_Interruptable_Type;
609 
610 typedef struct {
611   __I uint8_t IN;                                                                 /*!< Port Input */
612   uint8_t RESERVED0;
613   __IO uint8_t OUT;                                                               /*!< Port Output */
614   uint8_t RESERVED1;
615   __IO uint8_t DIR;                                                               /*!< Port Direction */
616   uint8_t RESERVED2;
617   __IO uint8_t REN;                                                               /*!< Port Resistor Enable */
618   uint8_t RESERVED3;
619   __IO uint8_t DS;                                                                /*!< Port Drive Strength */
620   uint8_t RESERVED4;
621   __IO uint8_t SEL0;                                                              /*!< Port Select 0 */
622   uint8_t RESERVED5;
623   __IO uint8_t SEL1;                                                              /*!< Port Select 1 */
624   uint8_t RESERVED6;
625   __I  uint16_t IV;                                                               /*!< Port Interrupt Vector Value */
626   uint8_t RESERVED7[6];
627   __IO uint8_t SELC;                                                              /*!< Port Complement Select */
628   uint8_t RESERVED8;
629   __IO uint8_t IES;                                                               /*!< Port Interrupt Edge Select */
630   uint8_t RESERVED9;
631   __IO uint8_t IE;                                                                /*!< Port Interrupt Enable */
632   uint8_t RESERVED10;
633   __IO uint8_t IFG;                                                               /*!< Port Interrupt Flag */
634   uint8_t RESERVED11;
635 } DIO_PORT_Odd_Interruptable_Type;
636 
637 typedef struct {
638   __I  uint32_t DEVICE_CFG;                                                      /*!< Device Configuration Status */
639   __IO uint32_t SW_CHTRIG;                                                       /*!< Software Channel Trigger Register */
640        uint32_t RESERVED0[2];
641   __IO uint32_t CH_SRCCFG[32];                                                   /*!< Channel n Source Configuration Register */
642        uint32_t RESERVED1[28];
643   __IO uint32_t INT1_SRCCFG;                                                     /*!< Interrupt 1 Source Channel Configuration */
644   __IO uint32_t INT2_SRCCFG;                                                     /*!< Interrupt 2 Source Channel Configuration Register */
645   __IO uint32_t INT3_SRCCFG;                                                     /*!< Interrupt 3 Source Channel Configuration Register */
646        uint32_t RESERVED2;
647   __I  uint32_t INT0_SRCFLG;                                                     /*!< Interrupt 0 Source Channel Flag Register */
648   __O  uint32_t INT0_CLRFLG;                                                     /*!< Interrupt 0 Source Channel Clear Flag Register */
649 } DMA_Channel_Type;
650 
651 typedef struct {
652   __I  uint32_t STAT;                                                            /*!< Status Register */
653   __O  uint32_t CFG;                                                             /*!< Configuration Register */
654   __IO uint32_t CTLBASE;                                                         /*!< Channel Control Data Base Pointer Register */
655   __I  uint32_t ALTBASE;                                                         /*!< Channel Alternate Control Data Base Pointer Register */
656   __I  uint32_t WAITSTAT;                                                        /*!< Channel Wait on Request Status Register */
657   __O  uint32_t SWREQ;                                                           /*!< Channel Software Request Register */
658   __IO uint32_t USEBURSTSET;                                                     /*!< Channel Useburst Set Register */
659   __O  uint32_t USEBURSTCLR;                                                     /*!< Channel Useburst Clear Register */
660   __IO uint32_t REQMASKSET;                                                      /*!< Channel Request Mask Set Register */
661   __O  uint32_t REQMASKCLR;                                                      /*!< Channel Request Mask Clear Register */
662   __IO uint32_t ENASET;                                                          /*!< Channel Enable Set Register */
663   __O  uint32_t ENACLR;                                                          /*!< Channel Enable Clear Register */
664   __IO uint32_t ALTSET;                                                          /*!< Channel Primary-Alternate Set Register */
665   __O  uint32_t ALTCLR;                                                          /*!< Channel Primary-Alternate Clear Register */
666   __IO uint32_t PRIOSET;                                                         /*!< Channel Priority Set Register */
667   __O  uint32_t PRIOCLR;                                                         /*!< Channel Priority Clear Register */
668        uint32_t RESERVED4[3];
669   __IO uint32_t ERRCLR;                                                          /*!< Bus Error Clear Register */
670 } DMA_Control_Type;
671 
672 typedef struct {
673   __IO uint16_t CTLW0;                                                           /*!< eUSCI_Ax Control Word Register 0 */
674        uint16_t RESERVED0[2];
675   __IO uint16_t BRW;                                                             /*!< eUSCI_Ax Bit Rate Control Register 1 */
676        uint16_t RESERVED1;
677   __IO uint16_t STATW;
678   __I  uint16_t RXBUF;                                                           /*!< eUSCI_Ax Receive Buffer Register */
679   __IO uint16_t TXBUF;                                                           /*!< eUSCI_Ax Transmit Buffer Register */
680        uint16_t RESERVED2[5];
681   __IO uint16_t IE;                                                              /*!< eUSCI_Ax Interrupt Enable Register */
682   __IO uint16_t IFG;                                                             /*!< eUSCI_Ax Interrupt Flag Register */
683   __I  uint16_t IV;                                                              /*!< eUSCI_Ax Interrupt Vector Register */
684 } EUSCI_A_SPI_Type;
685 
686 typedef struct {
687   __IO uint16_t CTLW0;                                                           /*!< eUSCI_Ax Control Word Register 0 */
688   __IO uint16_t CTLW1;                                                           /*!< eUSCI_Ax Control Word Register 1 */
689        uint16_t RESERVED0;
690   __IO uint16_t BRW;                                                             /*!< eUSCI_Ax Baud Rate Control Word Register */
691   __IO uint16_t MCTLW;                                                           /*!< eUSCI_Ax Modulation Control Word Register */
692   __IO uint16_t STATW;                                                           /*!< eUSCI_Ax Status Register */
693   __I  uint16_t RXBUF;                                                           /*!< eUSCI_Ax Receive Buffer Register */
694   __IO uint16_t TXBUF;                                                           /*!< eUSCI_Ax Transmit Buffer Register */
695   __IO uint16_t ABCTL;                                                           /*!< eUSCI_Ax Auto Baud Rate Control Register */
696   __IO uint16_t IRCTL;                                                           /*!< eUSCI_Ax IrDA Control Word Register */
697        uint16_t RESERVED1[3];
698   __IO uint16_t IE;                                                              /*!< eUSCI_Ax Interrupt Enable Register */
699   __IO uint16_t IFG;                                                             /*!< eUSCI_Ax Interrupt Flag Register */
700   __I  uint16_t IV;                                                              /*!< eUSCI_Ax Interrupt Vector Register */
701 } EUSCI_A_Type;
702 
703 typedef struct {
704   __IO uint16_t CTLW0;                                                           /*!< eUSCI_Bx Control Word Register 0 */
705        uint16_t RESERVED0[2];
706   __IO uint16_t BRW;                                                             /*!< eUSCI_Bx Bit Rate Control Register 1 */
707   __IO uint16_t STATW;
708        uint16_t RESERVED1;
709   __I  uint16_t RXBUF;                                                           /*!< eUSCI_Bx Receive Buffer Register */
710   __IO uint16_t TXBUF;                                                           /*!< eUSCI_Bx Transmit Buffer Register */
711        uint16_t RESERVED2[13];
712   __IO uint16_t IE;                                                              /*!< eUSCI_Bx Interrupt Enable Register */
713   __IO uint16_t IFG;                                                             /*!< eUSCI_Bx Interrupt Flag Register */
714   __I  uint16_t IV;                                                              /*!< eUSCI_Bx Interrupt Vector Register */
715 } EUSCI_B_SPI_Type;
716 
717 typedef struct {
718   __IO uint16_t CTLW0;                                                           /*!< eUSCI_Bx Control Word Register 0 */
719   __IO uint16_t CTLW1;                                                           /*!< eUSCI_Bx Control Word Register 1 */
720        uint16_t RESERVED0;
721   __IO uint16_t BRW;                                                             /*!< eUSCI_Bx Baud Rate Control Word Register */
722   __IO uint16_t STATW;                                                           /*!< eUSCI_Bx Status Register */
723   __IO uint16_t TBCNT;                                                           /*!< eUSCI_Bx Byte Counter Threshold Register */
724   __I  uint16_t RXBUF;                                                           /*!< eUSCI_Bx Receive Buffer Register */
725   __IO uint16_t TXBUF;                                                           /*!< eUSCI_Bx Transmit Buffer Register */
726        uint16_t RESERVED1[2];
727   __IO uint16_t I2COA0;                                                          /*!< eUSCI_Bx I2C Own Address 0 Register */
728   __IO uint16_t I2COA1;                                                          /*!< eUSCI_Bx I2C Own Address 1 Register */
729   __IO uint16_t I2COA2;                                                          /*!< eUSCI_Bx I2C Own Address 2 Register */
730   __IO uint16_t I2COA3;                                                          /*!< eUSCI_Bx I2C Own Address 3 Register */
731   __I  uint16_t ADDRX;                                                           /*!< eUSCI_Bx I2C Received Address Register */
732   __IO uint16_t ADDMASK;                                                         /*!< eUSCI_Bx I2C Address Mask Register */
733   __IO uint16_t I2CSA;                                                           /*!< eUSCI_Bx I2C Slave Address Register */
734        uint16_t RESERVED2[4];
735   __IO uint16_t IE;                                                              /*!< eUSCI_Bx Interrupt Enable Register */
736   __IO uint16_t IFG;                                                             /*!< eUSCI_Bx Interrupt Flag Register */
737   __I  uint16_t IV;                                                              /*!< eUSCI_Bx Interrupt Vector Register */
738 } EUSCI_B_Type;
739 
740 typedef struct {
741   __I  uint32_t POWER_STAT;                                                      /*!< Power Status Register */
742        uint32_t RESERVED0[3];
743   __IO uint32_t BANK0_RDCTL;                                                     /*!< Bank0 Read Control Register */
744   __IO uint32_t BANK1_RDCTL;                                                     /*!< Bank1 Read Control Register */
745        uint32_t RESERVED1[2];
746   __IO uint32_t RDBRST_CTLSTAT;                                                  /*!< Read Burst/Compare Control and Status Register */
747   __IO uint32_t RDBRST_STARTADDR;                                                /*!< Read Burst/Compare Start Address Register */
748   __IO uint32_t RDBRST_LEN;                                                      /*!< Read Burst/Compare Length Register */
749        uint32_t RESERVED2[4];
750   __IO uint32_t RDBRST_FAILADDR;                                                 /*!< Read Burst/Compare Fail Address Register */
751   __IO uint32_t RDBRST_FAILCNT;                                                  /*!< Read Burst/Compare Fail Count Register */
752        uint32_t RESERVED3[3];
753   __IO uint32_t PRG_CTLSTAT;                                                     /*!< Program Control and Status Register */
754   __IO uint32_t PRGBRST_CTLSTAT;                                                 /*!< Program Burst Control and Status Register */
755   __IO uint32_t PRGBRST_STARTADDR;                                               /*!< Program Burst Start Address Register */
756        uint32_t RESERVED4;
757   __IO uint32_t PRGBRST_DATA0_0;                                                 /*!< Program Burst Data0 Register0 */
758   __IO uint32_t PRGBRST_DATA0_1;                                                 /*!< Program Burst Data0 Register1 */
759   __IO uint32_t PRGBRST_DATA0_2;                                                 /*!< Program Burst Data0 Register2 */
760   __IO uint32_t PRGBRST_DATA0_3;                                                 /*!< Program Burst Data0 Register3 */
761   __IO uint32_t PRGBRST_DATA1_0;                                                 /*!< Program Burst Data1 Register0 */
762   __IO uint32_t PRGBRST_DATA1_1;                                                 /*!< Program Burst Data1 Register1 */
763   __IO uint32_t PRGBRST_DATA1_2;                                                 /*!< Program Burst Data1 Register2 */
764   __IO uint32_t PRGBRST_DATA1_3;                                                 /*!< Program Burst Data1 Register3 */
765   __IO uint32_t PRGBRST_DATA2_0;                                                 /*!< Program Burst Data2 Register0 */
766   __IO uint32_t PRGBRST_DATA2_1;                                                 /*!< Program Burst Data2 Register1 */
767   __IO uint32_t PRGBRST_DATA2_2;                                                 /*!< Program Burst Data2 Register2 */
768   __IO uint32_t PRGBRST_DATA2_3;                                                 /*!< Program Burst Data2 Register3 */
769   __IO uint32_t PRGBRST_DATA3_0;                                                 /*!< Program Burst Data3 Register0 */
770   __IO uint32_t PRGBRST_DATA3_1;                                                 /*!< Program Burst Data3 Register1 */
771   __IO uint32_t PRGBRST_DATA3_2;                                                 /*!< Program Burst Data3 Register2 */
772   __IO uint32_t PRGBRST_DATA3_3;                                                 /*!< Program Burst Data3 Register3 */
773   __IO uint32_t ERASE_CTLSTAT;                                                   /*!< Erase Control and Status Register */
774   __IO uint32_t ERASE_SECTADDR;                                                  /*!< Erase Sector Address Register */
775        uint32_t RESERVED5[2];
776   __IO uint32_t BANK0_INFO_WEPROT;                                               /*!< Information Memory Bank0 Write/Erase Protection Register */
777   __IO uint32_t BANK0_MAIN_WEPROT;                                               /*!< Main Memory Bank0 Write/Erase Protection Register */
778        uint32_t RESERVED6[2];
779   __IO uint32_t BANK1_INFO_WEPROT;                                               /*!< Information Memory Bank1 Write/Erase Protection Register */
780   __IO uint32_t BANK1_MAIN_WEPROT;                                               /*!< Main Memory Bank1 Write/Erase Protection Register */
781        uint32_t RESERVED7[2];
782   __IO uint32_t BMRK_CTLSTAT;                                                    /*!< Benchmark Control and Status Register */
783   __IO uint32_t BMRK_IFETCH;                                                     /*!< Benchmark Instruction Fetch Count Register */
784   __IO uint32_t BMRK_DREAD;                                                      /*!< Benchmark Data Read Count Register */
785   __IO uint32_t BMRK_CMP;                                                        /*!< Benchmark Count Compare Register */
786        uint32_t RESERVED8[4];
787   __IO uint32_t IFG;                                                             /*!< Interrupt Flag Register */
788   __IO uint32_t IE;                                                              /*!< Interrupt Enable Register */
789   __IO uint32_t CLRIFG;                                                          /*!< Clear Interrupt Flag Register */
790   __IO uint32_t SETIFG;                                                          /*!< Set Interrupt Flag Register */
791   __I  uint32_t READ_TIMCTL;                                                     /*!< Read Timing Control Register */
792   __I  uint32_t READMARGIN_TIMCTL;                                               /*!< Read Margin Timing Control Register */
793   __I  uint32_t PRGVER_TIMCTL;                                                   /*!< Program Verify Timing Control Register */
794   __I  uint32_t ERSVER_TIMCTL;                                                   /*!< Erase Verify Timing Control Register */
795   __I  uint32_t LKGVER_TIMCTL;                                                   /*!< Leakage Verify Timing Control Register */
796   __I  uint32_t PROGRAM_TIMCTL;                                                  /*!< Program Timing Control Register */
797   __I  uint32_t ERASE_TIMCTL;                                                    /*!< Erase Timing Control Register */
798   __I  uint32_t MASSERASE_TIMCTL;                                                /*!< Mass Erase Timing Control Register */
799   __I  uint32_t BURSTPRG_TIMCTL;                                                 /*!< Burst Program Timing Control Register */
800        uint32_t RESERVED9[55];
801   __IO uint32_t BANK0_MAIN_WEPROT0;                                              /*!< Main Memory Bank0 Write/Erase Protection Register 0 */
802   __IO uint32_t BANK0_MAIN_WEPROT1;                                              /*!< Main Memory Bank0 Write/Erase Protection Register 1 */
803   __IO uint32_t BANK0_MAIN_WEPROT2;                                              /*!< Main Memory Bank0 Write/Erase Protection Register 2 */
804   __IO uint32_t BANK0_MAIN_WEPROT3;                                              /*!< Main Memory Bank0 Write/Erase Protection Register 3 */
805   __IO uint32_t BANK0_MAIN_WEPROT4;                                              /*!< Main Memory Bank0 Write/Erase Protection Register 4 */
806   __IO uint32_t BANK0_MAIN_WEPROT5;                                              /*!< Main Memory Bank0 Write/Erase Protection Register 5 */
807   __IO uint32_t BANK0_MAIN_WEPROT6;                                              /*!< Main Memory Bank0 Write/Erase Protection Register 6 */
808   __IO uint32_t BANK0_MAIN_WEPROT7;                                              /*!< Main Memory Bank0 Write/Erase Protection Register 7 */
809        uint32_t RESERVED10[8];
810   __IO uint32_t BANK1_MAIN_WEPROT0;                                              /*!< Main Memory Bank1 Write/Erase Protection Register 0 */
811   __IO uint32_t BANK1_MAIN_WEPROT1;                                              /*!< Main Memory Bank1 Write/Erase Protection Register 1 */
812   __IO uint32_t BANK1_MAIN_WEPROT2;                                              /*!< Main Memory Bank1 Write/Erase Protection Register 2 */
813   __IO uint32_t BANK1_MAIN_WEPROT3;                                              /*!< Main Memory Bank1 Write/Erase Protection Register 3 */
814   __IO uint32_t BANK1_MAIN_WEPROT4;                                              /*!< Main Memory Bank1 Write/Erase Protection Register 4 */
815   __IO uint32_t BANK1_MAIN_WEPROT5;                                              /*!< Main Memory Bank1 Write/Erase Protection Register 5 */
816   __IO uint32_t BANK1_MAIN_WEPROT6;                                              /*!< Main Memory Bank1 Write/Erase Protection Register 6 */
817   __IO uint32_t BANK1_MAIN_WEPROT7;                                              /*!< Main Memory Bank1 Write/Erase Protection Register 7 */
818 } FLCTL_A_Type;
819 
820 typedef struct {
821   __I  uint32_t POWER_STAT;                                                      /*!< Power Status Register */
822        uint32_t RESERVED0[3];
823   __IO uint32_t BANK0_RDCTL;                                                     /*!< Bank0 Read Control Register */
824   __IO uint32_t BANK1_RDCTL;                                                     /*!< Bank1 Read Control Register */
825        uint32_t RESERVED1[2];
826   __IO uint32_t RDBRST_CTLSTAT;                                                  /*!< Read Burst/Compare Control and Status Register */
827   __IO uint32_t RDBRST_STARTADDR;                                                /*!< Read Burst/Compare Start Address Register */
828   __IO uint32_t RDBRST_LEN;                                                      /*!< Read Burst/Compare Length Register */
829        uint32_t RESERVED2[4];
830   __IO uint32_t RDBRST_FAILADDR;                                                 /*!< Read Burst/Compare Fail Address Register */
831   __IO uint32_t RDBRST_FAILCNT;                                                  /*!< Read Burst/Compare Fail Count Register */
832        uint32_t RESERVED3[3];
833   __IO uint32_t PRG_CTLSTAT;                                                     /*!< Program Control and Status Register */
834   __IO uint32_t PRGBRST_CTLSTAT;                                                 /*!< Program Burst Control and Status Register */
835   __IO uint32_t PRGBRST_STARTADDR;                                               /*!< Program Burst Start Address Register */
836        uint32_t RESERVED4;
837   __IO uint32_t PRGBRST_DATA0_0;                                                 /*!< Program Burst Data0 Register0 */
838   __IO uint32_t PRGBRST_DATA0_1;                                                 /*!< Program Burst Data0 Register1 */
839   __IO uint32_t PRGBRST_DATA0_2;                                                 /*!< Program Burst Data0 Register2 */
840   __IO uint32_t PRGBRST_DATA0_3;                                                 /*!< Program Burst Data0 Register3 */
841   __IO uint32_t PRGBRST_DATA1_0;                                                 /*!< Program Burst Data1 Register0 */
842   __IO uint32_t PRGBRST_DATA1_1;                                                 /*!< Program Burst Data1 Register1 */
843   __IO uint32_t PRGBRST_DATA1_2;                                                 /*!< Program Burst Data1 Register2 */
844   __IO uint32_t PRGBRST_DATA1_3;                                                 /*!< Program Burst Data1 Register3 */
845   __IO uint32_t PRGBRST_DATA2_0;                                                 /*!< Program Burst Data2 Register0 */
846   __IO uint32_t PRGBRST_DATA2_1;                                                 /*!< Program Burst Data2 Register1 */
847   __IO uint32_t PRGBRST_DATA2_2;                                                 /*!< Program Burst Data2 Register2 */
848   __IO uint32_t PRGBRST_DATA2_3;                                                 /*!< Program Burst Data2 Register3 */
849   __IO uint32_t PRGBRST_DATA3_0;                                                 /*!< Program Burst Data3 Register0 */
850   __IO uint32_t PRGBRST_DATA3_1;                                                 /*!< Program Burst Data3 Register1 */
851   __IO uint32_t PRGBRST_DATA3_2;                                                 /*!< Program Burst Data3 Register2 */
852   __IO uint32_t PRGBRST_DATA3_3;                                                 /*!< Program Burst Data3 Register3 */
853   __IO uint32_t ERASE_CTLSTAT;                                                   /*!< Erase Control and Status Register */
854   __IO uint32_t ERASE_SECTADDR;                                                  /*!< Erase Sector Address Register */
855        uint32_t RESERVED5[2];
856   __IO uint32_t BANK0_INFO_WEPROT;                                               /*!< Information Memory Bank0 Write/Erase Protection Register */
857   __IO uint32_t BANK0_MAIN_WEPROT;                                               /*!< Main Memory Bank0 Write/Erase Protection Register */
858        uint32_t RESERVED6[2];
859   __IO uint32_t BANK1_INFO_WEPROT;                                               /*!< Information Memory Bank1 Write/Erase Protection Register */
860   __IO uint32_t BANK1_MAIN_WEPROT;                                               /*!< Main Memory Bank1 Write/Erase Protection Register */
861        uint32_t RESERVED7[2];
862   __IO uint32_t BMRK_CTLSTAT;                                                    /*!< Benchmark Control and Status Register */
863   __IO uint32_t BMRK_IFETCH;                                                     /*!< Benchmark Instruction Fetch Count Register */
864   __IO uint32_t BMRK_DREAD;                                                      /*!< Benchmark Data Read Count Register */
865   __IO uint32_t BMRK_CMP;                                                        /*!< Benchmark Count Compare Register */
866        uint32_t RESERVED8[4];
867   __IO uint32_t IFG;                                                             /*!< Interrupt Flag Register */
868   __IO uint32_t IE;                                                              /*!< Interrupt Enable Register */
869   __IO uint32_t CLRIFG;                                                          /*!< Clear Interrupt Flag Register */
870   __IO uint32_t SETIFG;                                                          /*!< Set Interrupt Flag Register */
871   __I  uint32_t READ_TIMCTL;                                                     /*!< Read Timing Control Register */
872   __I  uint32_t READMARGIN_TIMCTL;                                               /*!< Read Margin Timing Control Register */
873   __I  uint32_t PRGVER_TIMCTL;                                                   /*!< Program Verify Timing Control Register */
874   __I  uint32_t ERSVER_TIMCTL;                                                   /*!< Erase Verify Timing Control Register */
875   __I  uint32_t LKGVER_TIMCTL;                                                   /*!< Leakage Verify Timing Control Register */
876   __I  uint32_t PROGRAM_TIMCTL;                                                  /*!< Program Timing Control Register */
877   __I  uint32_t ERASE_TIMCTL;                                                    /*!< Erase Timing Control Register */
878   __I  uint32_t MASSERASE_TIMCTL;                                                /*!< Mass Erase Timing Control Register */
879   __I  uint32_t BURSTPRG_TIMCTL;                                                 /*!< Burst Program Timing Control Register */
880 } FLCTL_Type;
881 
882 typedef struct {
883   __IO uint32_t CTL;                                                             /*!< LCD_F control */
884   __IO uint32_t BMCTL;                                                           /*!< LCD_F blinking and memory control */
885   __IO uint32_t VCTL;                                                            /*!< LCD_F voltage control */
886   __IO uint32_t PCTL0;                                                           /*!< LCD_F port control 0 */
887   __IO uint32_t PCTL1;                                                           /*!< LCD_F port control 1 */
888   __IO uint32_t CSSEL0;                                                          /*!< LCD_F COM/SEG select register 0 */
889   __IO uint32_t CSSEL1;                                                          /*!< LCD_F COM/SEG select register 1 */
890   __IO uint32_t ANMCTL;                                                          /*!< LCD_F Animation Control Register */
891        uint32_t RESERVED0[60];
892   __IO uint32_t IE;                                                              /*!< LCD_F interrupt enable register */
893   __I  uint32_t IFG;                                                             /*!< LCD_F interrupt flag register */
894   __O  uint32_t SETIFG;                                                          /*!< LCD_F set interrupt flag register */
895   __O  uint32_t CLRIFG;                                                          /*!< LCD_F clear interrupt flag register */
896   __IO uint8_t M[48];                                                           /*!< LCD memory registers */
897        uint8_t  RESERVED1[16];
898   __IO uint8_t BM[48];                                                          /*!< LCD Blinking memory registers */
899        uint8_t  RESERVED2[16];
900   __IO uint8_t ANM[8];                                                          /*!< LCD Animation memory registers */
901 } LCD_F_Type;
902 
903 typedef struct {
904   __IO uint32_t CTL0;                                                            /*!< Control 0 Register */
905   __IO uint32_t CTL1;                                                            /*!< Control 1 Register */
906   __IO uint32_t IE;                                                              /*!< Interrupt Enable Register */
907   __I  uint32_t IFG;                                                             /*!< Interrupt Flag Register */
908   __O  uint32_t CLRIFG;                                                          /*!< Clear Interrupt Flag Register */
909 } PCM_Type;
910 
911 typedef struct {
912   __IO uint16_t KEYID;
913   __IO uint16_t CTL;
914 } PMAP_COMMON_Type;
915 
916 typedef struct {
917   union {
918     __IO uint16_t PMAP_REGISTER[4];
919     struct {
920       __IO uint8_t PMAP_REGISTER0;
921       __IO uint8_t PMAP_REGISTER1;
922       __IO uint8_t PMAP_REGISTER2;
923       __IO uint8_t PMAP_REGISTER3;
924       __IO uint8_t PMAP_REGISTER4;
925       __IO uint8_t PMAP_REGISTER5;
926       __IO uint8_t PMAP_REGISTER6;
927       __IO uint8_t PMAP_REGISTER7;
928     };
929   };
930 } PMAP_REGISTER_Type;
931 
932 typedef struct {
933   __IO uint32_t KEY;                                                             /*!< Key Register */
934   __IO uint32_t CTL0;                                                            /*!< Control 0 Register */
935        uint32_t RESERVED0[11];
936   __IO uint32_t IE;                                                              /*!< Interrupt Enable Register */
937   __I  uint32_t IFG;                                                             /*!< Interrupt Flag Register */
938   __IO uint32_t CLRIFG;                                                          /*!< Clear Interrupt Flag Register */
939 } PSS_Type;
940 
941 typedef struct {
942   __IO uint16_t CTL0;                                                            /*!< REF Control Register 0 */
943 } REF_A_Type;
944 
945 typedef struct {
946   __IO uint32_t RESET_REQ;                                                       /*!< Reset Request Register */
947   __I  uint32_t HARDRESET_STAT;                                                  /*!< Hard Reset Status Register */
948   __IO uint32_t HARDRESET_CLR;                                                   /*!< Hard Reset Status Clear Register */
949   __IO uint32_t HARDRESET_SET;                                                   /*!< Hard Reset Status Set Register */
950   __I  uint32_t SOFTRESET_STAT;                                                  /*!< Soft Reset Status Register */
951   __IO uint32_t SOFTRESET_CLR;                                                   /*!< Soft Reset Status Clear Register */
952   __IO uint32_t SOFTRESET_SET;                                                   /*!< Soft Reset Status Set Register */
953        uint32_t RESERVED0[57];
954   __I  uint32_t PSSRESET_STAT;                                                   /*!< PSS Reset Status Register */
955   __IO uint32_t PSSRESET_CLR;                                                    /*!< PSS Reset Status Clear Register */
956   __I  uint32_t PCMRESET_STAT;                                                   /*!< PCM Reset Status Register */
957   __IO uint32_t PCMRESET_CLR;                                                    /*!< PCM Reset Status Clear Register */
958   __I  uint32_t PINRESET_STAT;                                                   /*!< Pin Reset Status Register */
959   __IO uint32_t PINRESET_CLR;                                                    /*!< Pin Reset Status Clear Register */
960   __I  uint32_t REBOOTRESET_STAT;                                                /*!< Reboot Reset Status Register */
961   __IO uint32_t REBOOTRESET_CLR;                                                 /*!< Reboot Reset Status Clear Register */
962   __I  uint32_t CSRESET_STAT;                                                    /*!< CS Reset Status Register */
963   __IO uint32_t CSRESET_CLR;                                                     /*!< CS Reset Status Clear Register */
964 } RSTCTL_Type;
965 
966 typedef struct {
967        uint16_t RESERVED0[8];
968   __IO uint16_t TIM0;                                                            /*!< Real-Time Clock Seconds, Minutes Register - BCD Format */
969   __IO uint16_t TIM1;                                                            /*!< Real-Time Clock Hour, Day of Week - BCD Format */
970   __IO uint16_t DATE;                                                            /*!< Real-Time Clock Date - BCD Format */
971   __IO uint16_t YEAR;                                                            /*!< Real-Time Clock Year Register - BCD Format */
972   __IO uint16_t AMINHR;                                                          /*!< Real-Time Clock Minutes, Hour Alarm - BCD Format */
973   __IO uint16_t ADOWDAY;                                                         /*!< Real-Time Clock Day of Week, Day of Month Alarm - BCD Format */
974 } RTC_C_BCD_Type;
975 
976 typedef struct {
977   __IO uint16_t CTL0;                                                            /*!< RTCCTL0 Register */
978   __IO uint16_t CTL13;                                                           /*!< RTCCTL13 Register */
979   __IO uint16_t OCAL;                                                            /*!< RTCOCAL Register */
980   __IO uint16_t TCMP;                                                            /*!< RTCTCMP Register */
981   __IO uint16_t PS0CTL;                                                          /*!< Real-Time Clock Prescale Timer 0 Control Register */
982   __IO uint16_t PS1CTL;                                                          /*!< Real-Time Clock Prescale Timer 1 Control Register */
983   __IO uint16_t PS;                                                              /*!< Real-Time Clock Prescale Timer Counter Register */
984   __I  uint16_t IV;                                                              /*!< Real-Time Clock Interrupt Vector Register */
985   __IO uint16_t TIM0;                                                            /*!< RTCTIM0 Register  Hexadecimal Format */
986   __IO uint16_t TIM1;                                                            /*!< Real-Time Clock Hour, Day of Week */
987   __IO uint16_t DATE;                                                            /*!< RTCDATE - Hexadecimal Format */
988   __IO uint16_t YEAR;                                                            /*!< RTCYEAR Register  Hexadecimal Format */
989   __IO uint16_t AMINHR;                                                          /*!< RTCMINHR - Hexadecimal Format */
990   __IO uint16_t ADOWDAY;                                                         /*!< RTCADOWDAY - Hexadecimal Format */
991   __IO uint16_t BIN2BCD;                                                         /*!< Binary-to-BCD Conversion Register */
992   __IO uint16_t BCD2BIN;                                                         /*!< BCD-to-Binary Conversion Register */
993 } RTC_C_Type;
994 
995 typedef struct {
996   __IO uint32_t SEC_ZONE_SECEN;                                                  /*!< IP Protection Secure Zone Enable. */
997   __IO uint32_t SEC_ZONE_START_ADDR;                                             /*!< Start address of IP protected secure zone. */
998   __IO uint32_t SEC_ZONE_LENGTH;                                                 /*!< Length of IP protected secure zone in number of bytes. */
999   __IO uint32_t SEC_ZONE_AESINIT_VECT[4];                                        /*!< IP protected secure zone 0 AES initialization vector */
1000   __IO uint32_t SEC_ZONE_SECKEYS[8];                                             /*!< AES-CBC security keys. */
1001   __IO uint32_t SEC_ZONE_UNENC_PWD[4];                                           /*!< Unencrypted password for authentication. */
1002   __IO uint32_t SEC_ZONE_ENCUPDATE_EN;                                           /*!< IP Protected Secure Zone Encrypted In-field Update Enable */
1003   __IO uint32_t SEC_ZONE_DATA_EN;                                                /*!< IP Protected Secure Zone Data Access Enable */
1004   __IO uint32_t SEC_ZONE_ACK;                                                    /*!< Acknowledgment for IP Protection Secure Zone Enable Command. */
1005        uint32_t RESERVED0[2];
1006 } SEC_ZONE_PARAMS_Type;
1007 
1008 typedef struct {
1009   __IO uint32_t SEC_ZONE_PAYLOADADDR;                                            /*!< Start address where the payload is loaded in the device. */
1010   __IO uint32_t SEC_ZONE_PAYLOADLEN;                                             /*!< Length of the payload in bytes. */
1011   __IO uint32_t SEC_ZONE_UPDATE_ACK;                                             /*!< Acknowledgment for the IP Protected Secure Zone Update Command */
1012        uint32_t RESERVED0;
1013 } SEC_ZONE_UPDATE_Type;
1014 
1015 typedef struct {
1016   __IO uint32_t MASTER_UNLOCK;                                                   /*!< Master Unlock Register */
1017   __IO uint32_t BOOTOVER_REQ[2];                                                 /*!< Boot Override Request Register */
1018   __IO uint32_t BOOTOVER_ACK;                                                    /*!< Boot Override Acknowledge Register */
1019   __IO uint32_t RESET_REQ;                                                       /*!< Reset Request Register */
1020   __IO uint32_t RESET_STATOVER;                                                  /*!< Reset Status and Override Register */
1021        uint32_t RESERVED10[2];
1022   __I  uint32_t SYSTEM_STAT;                                                     /*!< System Status Register */
1023 } SYSCTL_A_Boot_Type;
1024 
1025 typedef struct {
1026   __IO uint32_t REBOOT_CTL;                                                      /*!< Reboot Control Register */
1027   __IO uint32_t NMI_CTLSTAT;                                                     /*!< NMI Control and Status Register */
1028   __IO uint32_t WDTRESET_CTL;                                                    /*!< Watchdog Reset Control Register */
1029   __IO uint32_t PERIHALT_CTL;                                                    /*!< Peripheral Halt Control Register */
1030   __I  uint32_t SRAM_SIZE;                                                       /*!< SRAM Size Register */
1031   __I  uint32_t SRAM_NUMBANKS;                                                   /*!< SRAM Number of Banks Register */
1032   __I  uint32_t SRAM_NUMBLOCKS;                                                  /*!< SRAM Number of Blocks Register */
1033        uint32_t RESERVED0;
1034   __I  uint32_t MAINFLASH_SIZE;                                                  /*!< Flash Main Memory Size Register */
1035   __I  uint32_t INFOFLASH_SIZE;                                                  /*!< Flash Information Memory Size Register */
1036        uint32_t RESERVED1[2];
1037   __IO uint32_t DIO_GLTFLT_CTL;                                                  /*!< Digital I/O Glitch Filter Control Register */
1038        uint32_t RESERVED2[3];
1039   __IO uint32_t SECDATA_UNLOCK;                                                  /*!< IP Protected Secure Zone Data Access Unlock Register */
1040        uint32_t RESERVED3[3];
1041   __IO uint32_t SRAM_BANKEN_CTL0;                                                /*!< SRAM Bank Enable Control Register 0 */
1042   __IO uint32_t SRAM_BANKEN_CTL1;                                                /*!< SRAM Bank Enable Control Register 1 */
1043   __IO uint32_t SRAM_BANKEN_CTL2;                                                /*!< SRAM Bank Enable Control Register 2 */
1044   __IO uint32_t SRAM_BANKEN_CTL3;                                                /*!< SRAM Bank Enable Control Register 3 */
1045        uint32_t RESERVED4[4];
1046   __IO uint32_t SRAM_BLKRET_CTL0;                                                /*!< SRAM Block Retention Control Register 0 */
1047   __IO uint32_t SRAM_BLKRET_CTL1;                                                /*!< SRAM Block Retention Control Register 1 */
1048   __IO uint32_t SRAM_BLKRET_CTL2;                                                /*!< SRAM Block Retention Control Register 2 */
1049   __IO uint32_t SRAM_BLKRET_CTL3;                                                /*!< SRAM Block Retention Control Register 3 */
1050        uint32_t RESERVED5[4];
1051   __I  uint32_t SRAM_STAT;                                                       /*!< SRAM Status Register */
1052 } SYSCTL_A_Type;
1053 
1054 typedef struct {
1055   __IO uint32_t MASTER_UNLOCK;                                                   /*!< Master Unlock Register */
1056   __IO uint32_t BOOTOVER_REQ[2];                                                 /*!< Boot Override Request Register */
1057   __IO uint32_t BOOTOVER_ACK;                                                    /*!< Boot Override Acknowledge Register */
1058   __IO uint32_t RESET_REQ;                                                       /*!< Reset Request Register */
1059   __IO uint32_t RESET_STATOVER;                                                  /*!< Reset Status and Override Register */
1060        uint32_t RESERVED7[2];
1061   __I  uint32_t SYSTEM_STAT;                                                     /*!< System Status Register */
1062 } SYSCTL_Boot_Type;
1063 
1064 typedef struct {
1065   __IO uint32_t REBOOT_CTL;                                                      /*!< Reboot Control Register */
1066   __IO uint32_t NMI_CTLSTAT;                                                     /*!< NMI Control and Status Register */
1067   __IO uint32_t WDTRESET_CTL;                                                    /*!< Watchdog Reset Control Register */
1068   __IO uint32_t PERIHALT_CTL;                                                    /*!< Peripheral Halt Control Register */
1069   __I  uint32_t SRAM_SIZE;                                                       /*!< SRAM Size Register */
1070   __IO uint32_t SRAM_BANKEN;                                                     /*!< SRAM Bank Enable Register */
1071   __IO uint32_t SRAM_BANKRET;                                                    /*!< SRAM Bank Retention Control Register */
1072        uint32_t RESERVED0;
1073   __I  uint32_t FLASH_SIZE;                                                      /*!< Flash Size Register */
1074        uint32_t RESERVED1[3];
1075   __IO uint32_t DIO_GLTFLT_CTL;                                                  /*!< Digital I/O Glitch Filter Control Register */
1076        uint32_t RESERVED2[3];
1077   __IO uint32_t SECDATA_UNLOCK;                                                  /*!< IP Protected Secure Zone Data Access Unlock Register */
1078 } SYSCTL_Type;
1079 
1080 typedef struct {
1081   __I  uint32_t TLV_CHECKSUM;                                                    /*!< TLV Checksum */
1082   __I  uint32_t DEVICE_INFO_TAG;                                                 /*!< Device Info Tag */
1083   __I  uint32_t DEVICE_INFO_LEN;                                                 /*!< Device Info Length */
1084   __I  uint32_t DEVICE_ID;                                                       /*!< Device ID */
1085   __I  uint32_t HWREV;                                                           /*!< HW Revision */
1086   __I  uint32_t BCREV;                                                           /*!< Boot Code Revision */
1087   __I  uint32_t ROM_DRVLIB_REV;                                                  /*!< ROM Driver Library Revision */
1088   __I  uint32_t DIE_REC_TAG;                                                     /*!< Die Record Tag */
1089   __I  uint32_t DIE_REC_LEN;                                                     /*!< Die Record Length */
1090   __I  uint32_t DIE_XPOS;                                                        /*!< Die X-Position */
1091   __I  uint32_t DIE_YPOS;                                                        /*!< Die Y-Position */
1092   __I  uint32_t WAFER_ID;                                                        /*!< Wafer ID */
1093   __I  uint32_t LOT_ID;                                                          /*!< Lot ID */
1094   __I  uint32_t RESERVED0;                                                       /*!< Reserved */
1095   __I  uint32_t RESERVED1;                                                       /*!< Reserved */
1096   __I  uint32_t RESERVED2;                                                       /*!< Reserved */
1097   __I  uint32_t TEST_RESULTS;                                                    /*!< Test Results */
1098   __I  uint32_t CS_CAL_TAG;                                                      /*!< Clock System Calibration Tag */
1099   __I  uint32_t CS_CAL_LEN;                                                      /*!< Clock System Calibration Length */
1100   __I  uint32_t DCOIR_FCAL_RSEL04;                                               /*!< DCO IR mode: Frequency calibration for DCORSEL 0 to 4 */
1101   __I  uint32_t DCOIR_FCAL_RSEL5;                                                /*!< DCO IR mode: Frequency calibration for DCORSEL 5 */
1102   __I  uint32_t RESERVED3;                                                       /*!< Reserved */
1103   __I  uint32_t RESERVED4;                                                       /*!< Reserved */
1104   __I  uint32_t RESERVED5;                                                       /*!< Reserved */
1105   __I  uint32_t RESERVED6;                                                       /*!< Reserved */
1106   __I  uint32_t DCOIR_CONSTK_RSEL04;                                             /*!< DCO IR mode: DCO Constant (K) for DCORSEL 0 to 4 */
1107   __I  uint32_t DCOIR_CONSTK_RSEL5;                                              /*!< DCO IR mode: DCO Constant (K) for DCORSEL 5 */
1108   __I  uint32_t DCOER_FCAL_RSEL04;                                               /*!< DCO ER mode: Frequency calibration for DCORSEL 0 to 4 */
1109   __I  uint32_t DCOER_FCAL_RSEL5;                                                /*!< DCO ER mode: Frequency calibration for DCORSEL 5 */
1110   __I  uint32_t RESERVED7;                                                       /*!< Reserved */
1111   __I  uint32_t RESERVED8;                                                       /*!< Reserved */
1112   __I  uint32_t RESERVED9;                                                       /*!< Reserved */
1113   __I  uint32_t RESERVED10;                                                      /*!< Reserved */
1114   __I  uint32_t DCOER_CONSTK_RSEL04;                                             /*!< DCO ER mode: DCO Constant (K) for DCORSEL 0 to 4 */
1115   __I  uint32_t DCOER_CONSTK_RSEL5;                                              /*!< DCO ER mode: DCO Constant (K) for DCORSEL 5 */
1116   __I  uint32_t ADC14_CAL_TAG;                                                   /*!< ADC14 Calibration Tag */
1117   __I  uint32_t ADC14_CAL_LEN;                                                   /*!< ADC14 Calibration Length */
1118   __I  uint32_t ADC_GAIN_FACTOR;                                                 /*!< ADC Gain Factor */
1119   __I  uint32_t ADC_OFFSET;                                                      /*!< ADC Offset */
1120   __I  uint32_t RESERVED11;                                                      /*!< Reserved */
1121   __I  uint32_t RESERVED12;                                                      /*!< Reserved */
1122   __I  uint32_t RESERVED13;                                                      /*!< Reserved */
1123   __I  uint32_t RESERVED14;                                                      /*!< Reserved */
1124   __I  uint32_t RESERVED15;                                                      /*!< Reserved */
1125   __I  uint32_t RESERVED16;                                                      /*!< Reserved */
1126   __I  uint32_t RESERVED17;                                                      /*!< Reserved */
1127   __I  uint32_t RESERVED18;                                                      /*!< Reserved */
1128   __I  uint32_t RESERVED19;                                                      /*!< Reserved */
1129   __I  uint32_t RESERVED20;                                                      /*!< Reserved */
1130   __I  uint32_t RESERVED21;                                                      /*!< Reserved */
1131   __I  uint32_t RESERVED22;                                                      /*!< Reserved */
1132   __I  uint32_t RESERVED23;                                                      /*!< Reserved */
1133   __I  uint32_t RESERVED24;                                                      /*!< Reserved */
1134   __I  uint32_t RESERVED25;                                                      /*!< Reserved */
1135   __I  uint32_t RESERVED26;                                                      /*!< Reserved */
1136   __I  uint32_t ADC14_REF1P2V_TS30C;                                             /*!< ADC14 1.2V Reference Temp. Sensor 30C */
1137   __I  uint32_t ADC14_REF1P2V_TS85C;                                             /*!< ADC14 1.2V Reference Temp. Sensor 85C */
1138   __I  uint32_t ADC14_REF1P45V_TS30C;                                            /*!< ADC14 1.45V Reference Temp. Sensor 30C */
1139   __I  uint32_t ADC14_REF1P45V_TS85C;                                            /*!< ADC14 1.45V Reference Temp. Sensor 85C */
1140   __I  uint32_t ADC14_REF2P5V_TS30C;                                             /*!< ADC14 2.5V Reference Temp. Sensor 30C */
1141   __I  uint32_t ADC14_REF2P5V_TS85C;                                             /*!< ADC14 2.5V Reference Temp. Sensor 85C */
1142   __I  uint32_t REF_CAL_TAG;                                                     /*!< REF Calibration Tag */
1143   __I  uint32_t REF_CAL_LEN;                                                     /*!< REF Calibration Length */
1144   __I  uint32_t REF_1P2V;                                                        /*!< REF 1.2V Reference */
1145   __I  uint32_t REF_1P45V;                                                       /*!< REF 1.45V Reference */
1146   __I  uint32_t REF_2P5V;                                                        /*!< REF 2.5V Reference */
1147   __I  uint32_t FLASH_INFO_TAG;                                                  /*!< Flash Info Tag */
1148   __I  uint32_t FLASH_INFO_LEN;                                                  /*!< Flash Info Length */
1149   __I  uint32_t FLASH_MAX_PROG_PULSES;                                           /*!< Flash Maximum Programming Pulses */
1150   __I  uint32_t FLASH_MAX_ERASE_PULSES;                                          /*!< Flash Maximum Erase Pulses */
1151   __I  uint32_t RANDOM_NUM_TAG;                                                  /*!< 128-bit Random Number Tag */
1152   __I  uint32_t RANDOM_NUM_LEN;                                                  /*!< 128-bit Random Number Length */
1153   __I  uint32_t RANDOM_NUM_1;                                                    /*!< 32-bit Random Number 1 */
1154   __I  uint32_t RANDOM_NUM_2;                                                    /*!< 32-bit Random Number 2 */
1155   __I  uint32_t RANDOM_NUM_3;                                                    /*!< 32-bit Random Number 3 */
1156   __I  uint32_t RANDOM_NUM_4;                                                    /*!< 32-bit Random Number 4 */
1157   __I  uint32_t BSL_CFG_TAG;                                                     /*!< BSL Configuration Tag */
1158   __I  uint32_t BSL_CFG_LEN;                                                     /*!< BSL Configuration Length */
1159   __I  uint32_t BSL_PERIPHIF_SEL;                                                /*!< BSL Peripheral Interface Selection */
1160   __I  uint32_t BSL_PORTIF_CFG_UART;                                             /*!< BSL Port Interface Configuration for UART */
1161   __I  uint32_t BSL_PORTIF_CFG_SPI;                                              /*!< BSL Port Interface Configuration for SPI */
1162   __I  uint32_t BSL_PORTIF_CFG_I2C;                                              /*!< BSL Port Interface Configuration for I2C */
1163   __I  uint32_t TLV_END;                                                         /*!< TLV End Word */
1164 } TLV_Type;
1165 
1166 typedef struct {
1167   __IO uint32_t LOAD;                                                            /*!< Timer Load Register */
1168   __I  uint32_t VALUE;                                                           /*!< Timer Current Value Register */
1169   __IO uint32_t CONTROL;                                                         /*!< Timer Control Register */
1170   __O  uint32_t INTCLR;                                                          /*!< Timer Interrupt Clear Register */
1171   __I  uint32_t RIS;                                                             /*!< Timer Raw Interrupt Status Register */
1172   __I  uint32_t MIS;                                                             /*!< Timer Interrupt Status Register */
1173   __IO uint32_t BGLOAD;                                                          /*!< Timer Background Load Register */
1174 } Timer32_Type;
1175 
1176 typedef struct {
1177   __IO uint16_t CTL;                                                             /*!< TimerAx Control Register */
1178   __IO uint16_t CCTL[5];                                                         /*!< Timer_A Capture/Compare Control Register */
1179        uint16_t RESERVED0[2];
1180   __IO uint16_t R;                                                               /*!< TimerA register */
1181   __IO uint16_t CCR[5];                                                          /*!< Timer_A Capture/Compare  Register */
1182        uint16_t RESERVED1[2];
1183   __IO uint16_t EX0;                                                             /*!< TimerAx Expansion 0 Register */
1184        uint16_t RESERVED2[6];
1185   __I  uint16_t IV;                                                              /*!< TimerAx Interrupt Vector Register */
1186 } Timer_A_Type;
1187 
1188 typedef struct {
1189        uint16_t RESERVED0[6];
1190   __IO uint16_t CTL;                                                             /*!< Watchdog Timer Control Register */
1191 } WDT_A_Type;
1192 
1193 typedef struct {
1194   __IO uint32_t MB_START;                                                        /*!< Flash MailBox start: 0x0115ACF6 */
1195   __IO uint32_t CMD;                                                             /*!< Command for Boot override operations. */
1196        uint32_t RESERVED0[2];
1197   __IO uint32_t JTAG_SWD_LOCK_SECEN;                                             /*!< JTAG and SWD Lock Enable */
1198   __IO uint32_t JTAG_SWD_LOCK_AES_INIT_VECT[4];                                  /*!< JTAG and SWD lock AES initialization vector for AES-CBC */
1199   __IO uint32_t JTAG_SWD_LOCK_AES_SECKEYS[8];                                    /*!< JTAG and SWD lock AES CBC security Keys 0-7. */
1200   __IO uint32_t JTAG_SWD_LOCK_UNENC_PWD[4];                                      /*!< JTAG and SWD lock unencrypted password */
1201   __IO uint32_t JTAG_SWD_LOCK_ACK;                                               /*!< Acknowledgment for JTAG and SWD Lock command */
1202        uint32_t RESERVED1[2];
1203   SEC_ZONE_PARAMS_Type SEC_ZONE_PARAMS[4];
1204   __IO uint32_t BSL_ENABLE;                                                      /*!< BSL Enable. */
1205   __IO uint32_t BSL_START_ADDRESS;                                               /*!< Contains the pointer to the BSL function. */
1206   __IO uint32_t BSL_PARAMETERS;                                                  /*!< BSL hardware invoke conifguration field. */
1207        uint32_t RESERVED2[2];
1208   __IO uint32_t BSL_ACK;                                                         /*!< Acknowledgment for the BSL Configuration Command */
1209   __IO uint32_t JTAG_SWD_LOCK_ENCPAYLOADADD;                                     /*!< Start address where the payload is loaded in the device. */
1210   __IO uint32_t JTAG_SWD_LOCK_ENCPAYLOADLEN;                                     /*!< Length of the encrypted payload in bytes */
1211   __IO uint32_t JTAG_SWD_LOCK_DST_ADDR;                                          /*!< Destination address where the final data needs to be stored into the device. */
1212   __IO uint32_t ENC_UPDATE_ACK;                                                  /*!< Acknowledgment for JTAG and SWD Lock Encrypted Update Command */
1213        uint32_t RESERVED3;
1214   SEC_ZONE_UPDATE_Type SEC_ZONE_UPDATE[4];
1215        uint32_t RESERVED4;
1216   __IO uint32_t FACTORY_RESET_ENABLE;                                            /*!< Enable/Disable Factory Reset */
1217   __IO uint32_t FACTORY_RESET_PWDEN;                                             /*!< Factory reset password enable */
1218   __IO uint32_t FACTORY_RESET_PWD[4];                                            /*!< 128-bit Password for factory reset to be saved into the device. */
1219   __IO uint32_t FACTORY_RESET_PARAMS_ACK;                                        /*!< Acknowledgment for the Factory Reset Params Command */
1220        uint32_t RESERVED5;
1221   __IO uint32_t FACTORY_RESET_PASSWORD[4];                                       /*!< 128-bit Password for factory reset. */
1222   __IO uint32_t FACTORY_RESET_ACK;                                               /*!< Acknowledgment for the Factory Reset Command */
1223        uint32_t RESERVED6[2];
1224   __IO uint32_t MB_END;                                                          /*!< Mailbox end */
1225 } FL_BOOTOVER_MAILBOX_Type;
1226 
1227 /* --------------------  End of section using anonymous unions  ------------------- */
1228 #if defined(__CC_ARM)
1229   #pragma pop
1230 #elif defined(__ICCARM__)
1231   /* leave anonymous unions enabled */
1232 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
1233   #pragma clang diagnostic pop
1234 #elif defined(__GNUC__)
1235   /* anonymous unions are enabled by default */
1236 #elif defined(__TI_ARM__)
1237   /* anonymous unions are enabled by default */
1238 #else
1239   #warning Not supported compiler type
1240 #endif
1241 
1242 /*@}*/ /* end of group MSP432P4XX_Peripherals */
1243 
1244 /******************************************************************************
1245 * Peripheral declaration                                                      *
1246 ******************************************************************************/
1247 /** @addtogroup MSP432P4XX_PeripheralDecl MSP432P4XX Peripheral Declaration
1248   @{
1249 */
1250 
1251 #define ADC14                            ((ADC14_Type *) ADC14_BASE)
1252 #define AES256                           ((AES256_Type *) AES256_BASE)
1253 #define CAPTIO0                          ((CAPTIO_Type *) CAPTIO0_BASE)
1254 #define CAPTIO1                          ((CAPTIO_Type *) CAPTIO1_BASE)
1255 #define COMP_E0                          ((COMP_E_Type *) COMP_E0_BASE)
1256 #define COMP_E1                          ((COMP_E_Type *) COMP_E1_BASE)
1257 #define CRC32                            ((CRC32_Type *) CRC32_BASE)
1258 #define CS                               ((CS_Type *) CS_BASE)
1259 #define PA                               ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0000))
1260 #define PB                               ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0020))
1261 #define PC                               ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0040))
1262 #define PD                               ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0060))
1263 #define PE                               ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0080))
1264 #define PJ                               ((DIO_PORT_Not_Interruptable_Type*) (DIO_BASE + 0x0120))
1265 #define P1                               ((DIO_PORT_Odd_Interruptable_Type*)  (DIO_BASE + 0x0000))
1266 #define P2                               ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0000))
1267 #define P3                               ((DIO_PORT_Odd_Interruptable_Type*)  (DIO_BASE + 0x0020))
1268 #define P4                               ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0020))
1269 #define P5                               ((DIO_PORT_Odd_Interruptable_Type*)  (DIO_BASE + 0x0040))
1270 #define P6                               ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0040))
1271 #define P7                               ((DIO_PORT_Odd_Interruptable_Type*)  (DIO_BASE + 0x0060))
1272 #define P8                               ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0060))
1273 #define P9                               ((DIO_PORT_Odd_Interruptable_Type*)  (DIO_BASE + 0x0080))
1274 #define P10                              ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0080))
1275 #define DMA_Channel                      ((DMA_Channel_Type *) DMA_BASE)
1276 #define DMA_Control                      ((DMA_Control_Type *) (DMA_BASE + 0x1000))
1277 #define EUSCI_A0                         ((EUSCI_A_Type *) EUSCI_A0_BASE)
1278 #define EUSCI_A0_SPI                     ((EUSCI_A_SPI_Type *) EUSCI_A0_SPI_BASE)
1279 #define EUSCI_A1                         ((EUSCI_A_Type *) EUSCI_A1_BASE)
1280 #define EUSCI_A1_SPI                     ((EUSCI_A_SPI_Type *) EUSCI_A1_SPI_BASE)
1281 #define EUSCI_A2                         ((EUSCI_A_Type *) EUSCI_A2_BASE)
1282 #define EUSCI_A2_SPI                     ((EUSCI_A_SPI_Type *) EUSCI_A2_SPI_BASE)
1283 #define EUSCI_A3                         ((EUSCI_A_Type *) EUSCI_A3_BASE)
1284 #define EUSCI_A3_SPI                     ((EUSCI_A_SPI_Type *) EUSCI_A3_SPI_BASE)
1285 #define EUSCI_B0                         ((EUSCI_B_Type *) EUSCI_B0_BASE)
1286 #define EUSCI_B0_SPI                     ((EUSCI_B_SPI_Type *) EUSCI_B0_SPI_BASE)
1287 #define EUSCI_B1                         ((EUSCI_B_Type *) EUSCI_B1_BASE)
1288 #define EUSCI_B1_SPI                     ((EUSCI_B_SPI_Type *) EUSCI_B1_SPI_BASE)
1289 #define EUSCI_B2                         ((EUSCI_B_Type *) EUSCI_B2_BASE)
1290 #define EUSCI_B2_SPI                     ((EUSCI_B_SPI_Type *) EUSCI_B2_SPI_BASE)
1291 #define EUSCI_B3                         ((EUSCI_B_Type *) EUSCI_B3_BASE)
1292 #define EUSCI_B3_SPI                     ((EUSCI_B_SPI_Type *) EUSCI_B3_SPI_BASE)
1293 #define FLCTL                            ((FLCTL_Type *) FLCTL_BASE)
1294 #define FL_BOOTOVER_MAILBOX              ((FL_BOOTOVER_MAILBOX_Type *) FL_BOOTOVER_MAILBOX_BASE)
1295 #define PCM                              ((PCM_Type *) PCM_BASE)
1296 #define PMAP                             ((PMAP_COMMON_Type*) PMAP_BASE)
1297 #define P1MAP                            ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0008))
1298 #define P2MAP                            ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0010))
1299 #define P3MAP                            ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0018))
1300 #define P4MAP                            ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0020))
1301 #define P5MAP                            ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0028))
1302 #define P6MAP                            ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0030))
1303 #define P7MAP                            ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0038))
1304 #define PSS                              ((PSS_Type *) PSS_BASE)
1305 #define REF_A                            ((REF_A_Type *) REF_A_BASE)
1306 #define RSTCTL                           ((RSTCTL_Type *) RSTCTL_BASE)
1307 #define RTC_C                            ((RTC_C_Type *) RTC_C_BASE)
1308 #define RTC_C_BCD                        ((RTC_C_BCD_Type *) RTC_C_BCD_BASE)
1309 #define SYSCTL                           ((SYSCTL_Type *) SYSCTL_BASE)
1310 #define SYSCTL_Boot                      ((SYSCTL_Boot_Type *) (SYSCTL_BASE + 0x1000))
1311 #define TIMER32_1                        ((Timer32_Type *) TIMER32_BASE)
1312 #define TIMER32_2                        ((Timer32_Type *) (TIMER32_BASE + 0x00020))
1313 #define TIMER_A0                         ((Timer_A_Type *) TIMER_A0_BASE)
1314 #define TIMER_A1                         ((Timer_A_Type *) TIMER_A1_BASE)
1315 #define TIMER_A2                         ((Timer_A_Type *) TIMER_A2_BASE)
1316 #define TIMER_A3                         ((Timer_A_Type *) TIMER_A3_BASE)
1317 #define TLV                              ((TLV_Type *) TLV_BASE)
1318 #define WDT_A                            ((WDT_A_Type *) WDT_A_BASE)
1319 #define FLCTL_A                          ((FLCTL_A_Type *) FLCTL_A_BASE)
1320 #define LCD_F                            ((LCD_F_Type *) LCD_F_BASE)
1321 #define SYSCTL_A                         ((SYSCTL_A_Type *) SYSCTL_A_BASE)
1322 #define SYSCTL_A_Boot                    ((SYSCTL_A_Boot_Type *) (SYSCTL_A_BASE + 0x1000))
1323 
1324 
1325 /*@}*/ /* end of group MSP432P4XX_PeripheralDecl */
1326 
1327 /*@}*/ /* end of group MSP432P4XX_Definitions */
1328 
1329 #endif /* __CMSIS_CONFIG__ */
1330 
1331 /******************************************************************************
1332 * Peripheral register control bits                                            *
1333 ******************************************************************************/
1334 #define ADC14_CTL0_SC_OFS                        ( 0)                            /*!< ADC14SC Bit Offset */
1335 #define ADC14_CTL0_SC                            ((uint32_t)0x00000001)          /*!< ADC14 start conversion */
1336 #define ADC14_CTL0_ENC_OFS                       ( 1)                            /*!< ADC14ENC Bit Offset */
1337 #define ADC14_CTL0_ENC                           ((uint32_t)0x00000002)          /*!< ADC14 enable conversion */
1338 #define ADC14_CTL0_ON_OFS                        ( 4)                            /*!< ADC14ON Bit Offset */
1339 #define ADC14_CTL0_ON                            ((uint32_t)0x00000010)          /*!< ADC14 on */
1340 #define ADC14_CTL0_MSC_OFS                       ( 7)                            /*!< ADC14MSC Bit Offset */
1341 #define ADC14_CTL0_MSC                           ((uint32_t)0x00000080)          /*!< ADC14 multiple sample and conversion */
1342 #define ADC14_CTL0_SHT0_OFS                      ( 8)                            /*!< ADC14SHT0 Bit Offset */
1343 #define ADC14_CTL0_SHT0_MASK                     ((uint32_t)0x00000F00)          /*!< ADC14SHT0 Bit Mask */
1344 #define ADC14_CTL0_SHT00                         ((uint32_t)0x00000100)          /*!< SHT0 Bit 0 */
1345 #define ADC14_CTL0_SHT01                         ((uint32_t)0x00000200)          /*!< SHT0 Bit 1 */
1346 #define ADC14_CTL0_SHT02                         ((uint32_t)0x00000400)          /*!< SHT0 Bit 2 */
1347 #define ADC14_CTL0_SHT03                         ((uint32_t)0x00000800)          /*!< SHT0 Bit 3 */
1348 #define ADC14_CTL0_SHT0_0                        ((uint32_t)0x00000000)          /*!< 4 */
1349 #define ADC14_CTL0_SHT0_1                        ((uint32_t)0x00000100)          /*!< 8 */
1350 #define ADC14_CTL0_SHT0_2                        ((uint32_t)0x00000200)          /*!< 16 */
1351 #define ADC14_CTL0_SHT0_3                        ((uint32_t)0x00000300)          /*!< 32 */
1352 #define ADC14_CTL0_SHT0_4                        ((uint32_t)0x00000400)          /*!< 64 */
1353 #define ADC14_CTL0_SHT0_5                        ((uint32_t)0x00000500)          /*!< 96 */
1354 #define ADC14_CTL0_SHT0_6                        ((uint32_t)0x00000600)          /*!< 128 */
1355 #define ADC14_CTL0_SHT0_7                        ((uint32_t)0x00000700)          /*!< 192 */
1356 #define ADC14_CTL0_SHT0__4                       ((uint32_t)0x00000000)          /*!< 4 */
1357 #define ADC14_CTL0_SHT0__8                       ((uint32_t)0x00000100)          /*!< 8 */
1358 #define ADC14_CTL0_SHT0__16                      ((uint32_t)0x00000200)          /*!< 16 */
1359 #define ADC14_CTL0_SHT0__32                      ((uint32_t)0x00000300)          /*!< 32 */
1360 #define ADC14_CTL0_SHT0__64                      ((uint32_t)0x00000400)          /*!< 64 */
1361 #define ADC14_CTL0_SHT0__96                      ((uint32_t)0x00000500)          /*!< 96 */
1362 #define ADC14_CTL0_SHT0__128                     ((uint32_t)0x00000600)          /*!< 128 */
1363 #define ADC14_CTL0_SHT0__192                     ((uint32_t)0x00000700)          /*!< 192 */
1364 #define ADC14_CTL0_SHT1_OFS                      (12)                            /*!< ADC14SHT1 Bit Offset */
1365 #define ADC14_CTL0_SHT1_MASK                     ((uint32_t)0x0000F000)          /*!< ADC14SHT1 Bit Mask */
1366 #define ADC14_CTL0_SHT10                         ((uint32_t)0x00001000)          /*!< SHT1 Bit 0 */
1367 #define ADC14_CTL0_SHT11                         ((uint32_t)0x00002000)          /*!< SHT1 Bit 1 */
1368 #define ADC14_CTL0_SHT12                         ((uint32_t)0x00004000)          /*!< SHT1 Bit 2 */
1369 #define ADC14_CTL0_SHT13                         ((uint32_t)0x00008000)          /*!< SHT1 Bit 3 */
1370 #define ADC14_CTL0_SHT1_0                        ((uint32_t)0x00000000)          /*!< 4 */
1371 #define ADC14_CTL0_SHT1_1                        ((uint32_t)0x00001000)          /*!< 8 */
1372 #define ADC14_CTL0_SHT1_2                        ((uint32_t)0x00002000)          /*!< 16 */
1373 #define ADC14_CTL0_SHT1_3                        ((uint32_t)0x00003000)          /*!< 32 */
1374 #define ADC14_CTL0_SHT1_4                        ((uint32_t)0x00004000)          /*!< 64 */
1375 #define ADC14_CTL0_SHT1_5                        ((uint32_t)0x00005000)          /*!< 96 */
1376 #define ADC14_CTL0_SHT1_6                        ((uint32_t)0x00006000)          /*!< 128 */
1377 #define ADC14_CTL0_SHT1_7                        ((uint32_t)0x00007000)          /*!< 192 */
1378 #define ADC14_CTL0_SHT1__4                       ((uint32_t)0x00000000)          /*!< 4 */
1379 #define ADC14_CTL0_SHT1__8                       ((uint32_t)0x00001000)          /*!< 8 */
1380 #define ADC14_CTL0_SHT1__16                      ((uint32_t)0x00002000)          /*!< 16 */
1381 #define ADC14_CTL0_SHT1__32                      ((uint32_t)0x00003000)          /*!< 32 */
1382 #define ADC14_CTL0_SHT1__64                      ((uint32_t)0x00004000)          /*!< 64 */
1383 #define ADC14_CTL0_SHT1__96                      ((uint32_t)0x00005000)          /*!< 96 */
1384 #define ADC14_CTL0_SHT1__128                     ((uint32_t)0x00006000)          /*!< 128 */
1385 #define ADC14_CTL0_SHT1__192                     ((uint32_t)0x00007000)          /*!< 192 */
1386 #define ADC14_CTL0_BUSY_OFS                      (16)                            /*!< ADC14BUSY Bit Offset */
1387 #define ADC14_CTL0_BUSY                          ((uint32_t)0x00010000)          /*!< ADC14 busy */
1388 #define ADC14_CTL0_CONSEQ_OFS                    (17)                            /*!< ADC14CONSEQ Bit Offset */
1389 #define ADC14_CTL0_CONSEQ_MASK                   ((uint32_t)0x00060000)          /*!< ADC14CONSEQ Bit Mask */
1390 #define ADC14_CTL0_CONSEQ0                       ((uint32_t)0x00020000)          /*!< CONSEQ Bit 0 */
1391 #define ADC14_CTL0_CONSEQ1                       ((uint32_t)0x00040000)          /*!< CONSEQ Bit 1 */
1392 #define ADC14_CTL0_CONSEQ_0                      ((uint32_t)0x00000000)          /*!< Single-channel, single-conversion */
1393 #define ADC14_CTL0_CONSEQ_1                      ((uint32_t)0x00020000)          /*!< Sequence-of-channels */
1394 #define ADC14_CTL0_CONSEQ_2                      ((uint32_t)0x00040000)          /*!< Repeat-single-channel */
1395 #define ADC14_CTL0_CONSEQ_3                      ((uint32_t)0x00060000)          /*!< Repeat-sequence-of-channels */
1396 #define ADC14_CTL0_SSEL_OFS                      (19)                            /*!< ADC14SSEL Bit Offset */
1397 #define ADC14_CTL0_SSEL_MASK                     ((uint32_t)0x00380000)          /*!< ADC14SSEL Bit Mask */
1398 #define ADC14_CTL0_SSEL0                         ((uint32_t)0x00080000)          /*!< SSEL Bit 0 */
1399 #define ADC14_CTL0_SSEL1                         ((uint32_t)0x00100000)          /*!< SSEL Bit 1 */
1400 #define ADC14_CTL0_SSEL2                         ((uint32_t)0x00200000)          /*!< SSEL Bit 2 */
1401 #define ADC14_CTL0_SSEL_0                        ((uint32_t)0x00000000)          /*!< MODCLK */
1402 #define ADC14_CTL0_SSEL_1                        ((uint32_t)0x00080000)          /*!< SYSCLK */
1403 #define ADC14_CTL0_SSEL_2                        ((uint32_t)0x00100000)          /*!< ACLK */
1404 #define ADC14_CTL0_SSEL_3                        ((uint32_t)0x00180000)          /*!< MCLK */
1405 #define ADC14_CTL0_SSEL_4                        ((uint32_t)0x00200000)          /*!< SMCLK */
1406 #define ADC14_CTL0_SSEL_5                        ((uint32_t)0x00280000)          /*!< HSMCLK */
1407 #define ADC14_CTL0_SSEL__MODCLK                  ((uint32_t)0x00000000)          /*!< MODCLK */
1408 #define ADC14_CTL0_SSEL__SYSCLK                  ((uint32_t)0x00080000)          /*!< SYSCLK */
1409 #define ADC14_CTL0_SSEL__ACLK                    ((uint32_t)0x00100000)          /*!< ACLK */
1410 #define ADC14_CTL0_SSEL__MCLK                    ((uint32_t)0x00180000)          /*!< MCLK */
1411 #define ADC14_CTL0_SSEL__SMCLK                   ((uint32_t)0x00200000)          /*!< SMCLK */
1412 #define ADC14_CTL0_SSEL__HSMCLK                  ((uint32_t)0x00280000)          /*!< HSMCLK */
1413 #define ADC14_CTL0_DIV_OFS                       (22)                            /*!< ADC14DIV Bit Offset */
1414 #define ADC14_CTL0_DIV_MASK                      ((uint32_t)0x01C00000)          /*!< ADC14DIV Bit Mask */
1415 #define ADC14_CTL0_DIV0                          ((uint32_t)0x00400000)          /*!< DIV Bit 0 */
1416 #define ADC14_CTL0_DIV1                          ((uint32_t)0x00800000)          /*!< DIV Bit 1 */
1417 #define ADC14_CTL0_DIV2                          ((uint32_t)0x01000000)          /*!< DIV Bit 2 */
1418 #define ADC14_CTL0_DIV_0                         ((uint32_t)0x00000000)          /*!< /1 */
1419 #define ADC14_CTL0_DIV_1                         ((uint32_t)0x00400000)          /*!< /2 */
1420 #define ADC14_CTL0_DIV_2                         ((uint32_t)0x00800000)          /*!< /3 */
1421 #define ADC14_CTL0_DIV_3                         ((uint32_t)0x00C00000)          /*!< /4 */
1422 #define ADC14_CTL0_DIV_4                         ((uint32_t)0x01000000)          /*!< /5 */
1423 #define ADC14_CTL0_DIV_5                         ((uint32_t)0x01400000)          /*!< /6 */
1424 #define ADC14_CTL0_DIV_6                         ((uint32_t)0x01800000)          /*!< /7 */
1425 #define ADC14_CTL0_DIV_7                         ((uint32_t)0x01C00000)          /*!< /8 */
1426 #define ADC14_CTL0_DIV__1                        ((uint32_t)0x00000000)          /*!< /1 */
1427 #define ADC14_CTL0_DIV__2                        ((uint32_t)0x00400000)          /*!< /2 */
1428 #define ADC14_CTL0_DIV__3                        ((uint32_t)0x00800000)          /*!< /3 */
1429 #define ADC14_CTL0_DIV__4                        ((uint32_t)0x00C00000)          /*!< /4 */
1430 #define ADC14_CTL0_DIV__5                        ((uint32_t)0x01000000)          /*!< /5 */
1431 #define ADC14_CTL0_DIV__6                        ((uint32_t)0x01400000)          /*!< /6 */
1432 #define ADC14_CTL0_DIV__7                        ((uint32_t)0x01800000)          /*!< /7 */
1433 #define ADC14_CTL0_DIV__8                        ((uint32_t)0x01C00000)          /*!< /8 */
1434 #define ADC14_CTL0_ISSH_OFS                      (25)                            /*!< ADC14ISSH Bit Offset */
1435 #define ADC14_CTL0_ISSH                          ((uint32_t)0x02000000)          /*!< ADC14 invert signal sample-and-hold */
1436 #define ADC14_CTL0_SHP_OFS                       (26)                            /*!< ADC14SHP Bit Offset */
1437 #define ADC14_CTL0_SHP                           ((uint32_t)0x04000000)          /*!< ADC14 sample-and-hold pulse-mode select */
1438 #define ADC14_CTL0_SHS_OFS                       (27)                            /*!< ADC14SHS Bit Offset */
1439 #define ADC14_CTL0_SHS_MASK                      ((uint32_t)0x38000000)          /*!< ADC14SHS Bit Mask */
1440 #define ADC14_CTL0_SHS0                          ((uint32_t)0x08000000)          /*!< SHS Bit 0 */
1441 #define ADC14_CTL0_SHS1                          ((uint32_t)0x10000000)          /*!< SHS Bit 1 */
1442 #define ADC14_CTL0_SHS2                          ((uint32_t)0x20000000)          /*!< SHS Bit 2 */
1443 #define ADC14_CTL0_SHS_0                         ((uint32_t)0x00000000)          /*!< ADC14SC bit */
1444 #define ADC14_CTL0_SHS_1                         ((uint32_t)0x08000000)          /*!< See device-specific data sheet for source */
1445 #define ADC14_CTL0_SHS_2                         ((uint32_t)0x10000000)          /*!< See device-specific data sheet for source */
1446 #define ADC14_CTL0_SHS_3                         ((uint32_t)0x18000000)          /*!< See device-specific data sheet for source */
1447 #define ADC14_CTL0_SHS_4                         ((uint32_t)0x20000000)          /*!< See device-specific data sheet for source */
1448 #define ADC14_CTL0_SHS_5                         ((uint32_t)0x28000000)          /*!< See device-specific data sheet for source */
1449 #define ADC14_CTL0_SHS_6                         ((uint32_t)0x30000000)          /*!< See device-specific data sheet for source */
1450 #define ADC14_CTL0_SHS_7                         ((uint32_t)0x38000000)          /*!< See device-specific data sheet for source */
1451 #define ADC14_CTL0_PDIV_OFS                      (30)                            /*!< ADC14PDIV Bit Offset */
1452 #define ADC14_CTL0_PDIV_MASK                     ((uint32_t)0xC0000000)          /*!< ADC14PDIV Bit Mask */
1453 #define ADC14_CTL0_PDIV0                         ((uint32_t)0x40000000)          /*!< PDIV Bit 0 */
1454 #define ADC14_CTL0_PDIV1                         ((uint32_t)0x80000000)          /*!< PDIV Bit 1 */
1455 #define ADC14_CTL0_PDIV_0                        ((uint32_t)0x00000000)          /*!< Predivide by 1 */
1456 #define ADC14_CTL0_PDIV_1                        ((uint32_t)0x40000000)          /*!< Predivide by 4 */
1457 #define ADC14_CTL0_PDIV_2                        ((uint32_t)0x80000000)          /*!< Predivide by 32 */
1458 #define ADC14_CTL0_PDIV_3                        ((uint32_t)0xC0000000)          /*!< Predivide by 64 */
1459 #define ADC14_CTL0_PDIV__1                       ((uint32_t)0x00000000)          /*!< Predivide by 1 */
1460 #define ADC14_CTL0_PDIV__4                       ((uint32_t)0x40000000)          /*!< Predivide by 4 */
1461 #define ADC14_CTL0_PDIV__32                      ((uint32_t)0x80000000)          /*!< Predivide by 32 */
1462 #define ADC14_CTL0_PDIV__64                      ((uint32_t)0xC0000000)          /*!< Predivide by 64 */
1463 #define ADC14_CTL1_PWRMD_OFS                     ( 0)                            /*!< ADC14PWRMD Bit Offset */
1464 #define ADC14_CTL1_PWRMD_MASK                    ((uint32_t)0x00000003)          /*!< ADC14PWRMD Bit Mask */
1465 #define ADC14_CTL1_PWRMD0                        ((uint32_t)0x00000001)          /*!< PWRMD Bit 0 */
1466 #define ADC14_CTL1_PWRMD1                        ((uint32_t)0x00000002)          /*!< PWRMD Bit 1 */
1467 #define ADC14_CTL1_PWRMD_0                       ((uint32_t)0x00000000)          /*!< Regular power mode for use with any resolution setting. Sample rate can be  */
1468 #define ADC14_CTL1_PWRMD_2                       ((uint32_t)0x00000002)          /*!< Low-power mode for 12-bit, 10-bit, and 8-bit resolution settings. Sample  */
1469 #define ADC14_CTL1_REFBURST_OFS                  ( 2)                            /*!< ADC14REFBURST Bit Offset */
1470 #define ADC14_CTL1_REFBURST                      ((uint32_t)0x00000004)          /*!< ADC14 reference buffer burst */
1471 #define ADC14_CTL1_DF_OFS                        ( 3)                            /*!< ADC14DF Bit Offset */
1472 #define ADC14_CTL1_DF                            ((uint32_t)0x00000008)          /*!< ADC14 data read-back format */
1473 #define ADC14_CTL1_RES_OFS                       ( 4)                            /*!< ADC14RES Bit Offset */
1474 #define ADC14_CTL1_RES_MASK                      ((uint32_t)0x00000030)          /*!< ADC14RES Bit Mask */
1475 #define ADC14_CTL1_RES0                          ((uint32_t)0x00000010)          /*!< RES Bit 0 */
1476 #define ADC14_CTL1_RES1                          ((uint32_t)0x00000020)          /*!< RES Bit 1 */
1477 #define ADC14_CTL1_RES_0                         ((uint32_t)0x00000000)          /*!< 8 bit (9 clock cycle conversion time) */
1478 #define ADC14_CTL1_RES_1                         ((uint32_t)0x00000010)          /*!< 10 bit (11 clock cycle conversion time) */
1479 #define ADC14_CTL1_RES_2                         ((uint32_t)0x00000020)          /*!< 12 bit (14 clock cycle conversion time) */
1480 #define ADC14_CTL1_RES_3                         ((uint32_t)0x00000030)          /*!< 14 bit (16 clock cycle conversion time) */
1481 #define ADC14_CTL1_RES__8BIT                     ((uint32_t)0x00000000)          /*!< 8 bit (9 clock cycle conversion time) */
1482 #define ADC14_CTL1_RES__10BIT                    ((uint32_t)0x00000010)          /*!< 10 bit (11 clock cycle conversion time) */
1483 #define ADC14_CTL1_RES__12BIT                    ((uint32_t)0x00000020)          /*!< 12 bit (14 clock cycle conversion time) */
1484 #define ADC14_CTL1_RES__14BIT                    ((uint32_t)0x00000030)          /*!< 14 bit (16 clock cycle conversion time) */
1485 #define ADC14_CTL1_CSTARTADD_OFS                 (16)                            /*!< ADC14CSTARTADD Bit Offset */
1486 #define ADC14_CTL1_CSTARTADD_MASK                ((uint32_t)0x001F0000)          /*!< ADC14CSTARTADD Bit Mask */
1487 #define ADC14_CTL1_BATMAP_OFS                    (22)                            /*!< ADC14BATMAP Bit Offset */
1488 #define ADC14_CTL1_BATMAP                        ((uint32_t)0x00400000)          /*!< Controls 1/2 AVCC ADC input channel selection */
1489 #define ADC14_CTL1_TCMAP_OFS                     (23)                            /*!< ADC14TCMAP Bit Offset */
1490 #define ADC14_CTL1_TCMAP                         ((uint32_t)0x00800000)          /*!< Controls temperature sensor ADC input channel selection */
1491 #define ADC14_CTL1_CH0MAP_OFS                    (24)                            /*!< ADC14CH0MAP Bit Offset */
1492 #define ADC14_CTL1_CH0MAP                        ((uint32_t)0x01000000)          /*!< Controls internal channel 0 selection to ADC input channel MAX-2 */
1493 #define ADC14_CTL1_CH1MAP_OFS                    (25)                            /*!< ADC14CH1MAP Bit Offset */
1494 #define ADC14_CTL1_CH1MAP                        ((uint32_t)0x02000000)          /*!< Controls internal channel 1 selection to ADC input channel MAX-3 */
1495 #define ADC14_CTL1_CH2MAP_OFS                    (26)                            /*!< ADC14CH2MAP Bit Offset */
1496 #define ADC14_CTL1_CH2MAP                        ((uint32_t)0x04000000)          /*!< Controls internal channel 2 selection to ADC input channel MAX-4 */
1497 #define ADC14_CTL1_CH3MAP_OFS                    (27)                            /*!< ADC14CH3MAP Bit Offset */
1498 #define ADC14_CTL1_CH3MAP                        ((uint32_t)0x08000000)          /*!< Controls internal channel 3 selection to ADC input channel MAX-5 */
1499 #define ADC14_LO0_LO0_OFS                        ( 0)                            /*!< ADC14LO0 Bit Offset */
1500 #define ADC14_LO0_LO0_MASK                       ((uint32_t)0x0000FFFF)          /*!< ADC14LO0 Bit Mask */
1501 #define ADC14_HI0_HI0_OFS                        ( 0)                            /*!< ADC14HI0 Bit Offset */
1502 #define ADC14_HI0_HI0_MASK                       ((uint32_t)0x0000FFFF)          /*!< ADC14HI0 Bit Mask */
1503 #define ADC14_LO1_LO1_OFS                        ( 0)                            /*!< ADC14LO1 Bit Offset */
1504 #define ADC14_LO1_LO1_MASK                       ((uint32_t)0x0000FFFF)          /*!< ADC14LO1 Bit Mask */
1505 #define ADC14_HI1_HI1_OFS                        ( 0)                            /*!< ADC14HI1 Bit Offset */
1506 #define ADC14_HI1_HI1_MASK                       ((uint32_t)0x0000FFFF)          /*!< ADC14HI1 Bit Mask */
1507 #define ADC14_MCTLN_INCH_OFS                     ( 0)                            /*!< ADC14INCH Bit Offset */
1508 #define ADC14_MCTLN_INCH_MASK                    ((uint32_t)0x0000001F)          /*!< ADC14INCH Bit Mask */
1509 #define ADC14_MCTLN_INCH0                        ((uint32_t)0x00000001)          /*!< INCH Bit 0 */
1510 #define ADC14_MCTLN_INCH1                        ((uint32_t)0x00000002)          /*!< INCH Bit 1 */
1511 #define ADC14_MCTLN_INCH2                        ((uint32_t)0x00000004)          /*!< INCH Bit 2 */
1512 #define ADC14_MCTLN_INCH3                        ((uint32_t)0x00000008)          /*!< INCH Bit 3 */
1513 #define ADC14_MCTLN_INCH4                        ((uint32_t)0x00000010)          /*!< INCH Bit 4 */
1514 #define ADC14_MCTLN_INCH_0                       ((uint32_t)0x00000000)          /*!< If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 */
1515 #define ADC14_MCTLN_INCH_1                       ((uint32_t)0x00000001)          /*!< If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 */
1516 #define ADC14_MCTLN_INCH_2                       ((uint32_t)0x00000002)          /*!< If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 */
1517 #define ADC14_MCTLN_INCH_3                       ((uint32_t)0x00000003)          /*!< If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 */
1518 #define ADC14_MCTLN_INCH_4                       ((uint32_t)0x00000004)          /*!< If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 */
1519 #define ADC14_MCTLN_INCH_5                       ((uint32_t)0x00000005)          /*!< If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 */
1520 #define ADC14_MCTLN_INCH_6                       ((uint32_t)0x00000006)          /*!< If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 */
1521 #define ADC14_MCTLN_INCH_7                       ((uint32_t)0x00000007)          /*!< If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 */
1522 #define ADC14_MCTLN_INCH_8                       ((uint32_t)0x00000008)          /*!< If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 */
1523 #define ADC14_MCTLN_INCH_9                       ((uint32_t)0x00000009)          /*!< If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 */
1524 #define ADC14_MCTLN_INCH_10                      ((uint32_t)0x0000000A)          /*!< If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 */
1525 #define ADC14_MCTLN_INCH_11                      ((uint32_t)0x0000000B)          /*!< If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 */
1526 #define ADC14_MCTLN_INCH_12                      ((uint32_t)0x0000000C)          /*!< If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 */
1527 #define ADC14_MCTLN_INCH_13                      ((uint32_t)0x0000000D)          /*!< If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 */
1528 #define ADC14_MCTLN_INCH_14                      ((uint32_t)0x0000000E)          /*!< If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 */
1529 #define ADC14_MCTLN_INCH_15                      ((uint32_t)0x0000000F)          /*!< If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 */
1530 #define ADC14_MCTLN_INCH_16                      ((uint32_t)0x00000010)          /*!< If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 */
1531 #define ADC14_MCTLN_INCH_17                      ((uint32_t)0x00000011)          /*!< If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 */
1532 #define ADC14_MCTLN_INCH_18                      ((uint32_t)0x00000012)          /*!< If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 */
1533 #define ADC14_MCTLN_INCH_19                      ((uint32_t)0x00000013)          /*!< If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 */
1534 #define ADC14_MCTLN_INCH_20                      ((uint32_t)0x00000014)          /*!< If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 */
1535 #define ADC14_MCTLN_INCH_21                      ((uint32_t)0x00000015)          /*!< If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 */
1536 #define ADC14_MCTLN_INCH_22                      ((uint32_t)0x00000016)          /*!< If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 */
1537 #define ADC14_MCTLN_INCH_23                      ((uint32_t)0x00000017)          /*!< If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 */
1538 #define ADC14_MCTLN_INCH_24                      ((uint32_t)0x00000018)          /*!< If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 */
1539 #define ADC14_MCTLN_INCH_25                      ((uint32_t)0x00000019)          /*!< If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 */
1540 #define ADC14_MCTLN_INCH_26                      ((uint32_t)0x0000001A)          /*!< If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 */
1541 #define ADC14_MCTLN_INCH_27                      ((uint32_t)0x0000001B)          /*!< If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 */
1542 #define ADC14_MCTLN_INCH_28                      ((uint32_t)0x0000001C)          /*!< If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 */
1543 #define ADC14_MCTLN_INCH_29                      ((uint32_t)0x0000001D)          /*!< If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 */
1544 #define ADC14_MCTLN_INCH_30                      ((uint32_t)0x0000001E)          /*!< If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 */
1545 #define ADC14_MCTLN_INCH_31                      ((uint32_t)0x0000001F)          /*!< If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 */
1546 #define ADC14_MCTLN_EOS_OFS                      ( 7)                            /*!< ADC14EOS Bit Offset */
1547 #define ADC14_MCTLN_EOS                          ((uint32_t)0x00000080)          /*!< End of sequence */
1548 #define ADC14_MCTLN_VRSEL_OFS                    ( 8)                            /*!< ADC14VRSEL Bit Offset */
1549 #define ADC14_MCTLN_VRSEL_MASK                   ((uint32_t)0x00000F00)          /*!< ADC14VRSEL Bit Mask */
1550 #define ADC14_MCTLN_VRSEL0                       ((uint32_t)0x00000100)          /*!< VRSEL Bit 0 */
1551 #define ADC14_MCTLN_VRSEL1                       ((uint32_t)0x00000200)          /*!< VRSEL Bit 1 */
1552 #define ADC14_MCTLN_VRSEL2                       ((uint32_t)0x00000400)          /*!< VRSEL Bit 2 */
1553 #define ADC14_MCTLN_VRSEL3                       ((uint32_t)0x00000800)          /*!< VRSEL Bit 3 */
1554 #define ADC14_MCTLN_VRSEL_0                      ((uint32_t)0x00000000)          /*!< V(R+) = AVCC, V(R-) = AVSS */
1555 #define ADC14_MCTLN_VRSEL_1                      ((uint32_t)0x00000100)          /*!< V(R+) = VREF buffered, V(R-) = AVSS */
1556 #define ADC14_MCTLN_VRSEL_14                     ((uint32_t)0x00000E00)          /*!< V(R+) = VeREF+, V(R-) = VeREF- */
1557 #define ADC14_MCTLN_VRSEL_15                     ((uint32_t)0x00000F00)          /*!< V(R+) = VeREF+ buffered, V(R-) = VeREF */
1558 #define ADC14_MCTLN_DIF_OFS                      (13)                            /*!< ADC14DIF Bit Offset */
1559 #define ADC14_MCTLN_DIF                          ((uint32_t)0x00002000)          /*!< Differential mode */
1560 #define ADC14_MCTLN_WINC_OFS                     (14)                            /*!< ADC14WINC Bit Offset */
1561 #define ADC14_MCTLN_WINC                         ((uint32_t)0x00004000)          /*!< Comparator window enable */
1562 #define ADC14_MCTLN_WINCTH_OFS                   (15)                            /*!< ADC14WINCTH Bit Offset */
1563 #define ADC14_MCTLN_WINCTH                       ((uint32_t)0x00008000)          /*!< Window comparator threshold register selection */
1564 #define ADC14_MEMN_CONVRES_OFS                   ( 0)                            /*!< Conversion_Results Bit Offset */
1565 #define ADC14_MEMN_CONVRES_MASK                  ((uint32_t)0x0000FFFF)          /*!< Conversion_Results Bit Mask */
1566 #define ADC14_IER0_IE0_OFS                       ( 0)                            /*!< ADC14IE0 Bit Offset */
1567 #define ADC14_IER0_IE0                           ((uint32_t)0x00000001)          /*!< Interrupt enable */
1568 #define ADC14_IER0_IE1_OFS                       ( 1)                            /*!< ADC14IE1 Bit Offset */
1569 #define ADC14_IER0_IE1                           ((uint32_t)0x00000002)          /*!< Interrupt enable */
1570 #define ADC14_IER0_IE2_OFS                       ( 2)                            /*!< ADC14IE2 Bit Offset */
1571 #define ADC14_IER0_IE2                           ((uint32_t)0x00000004)          /*!< Interrupt enable */
1572 #define ADC14_IER0_IE3_OFS                       ( 3)                            /*!< ADC14IE3 Bit Offset */
1573 #define ADC14_IER0_IE3                           ((uint32_t)0x00000008)          /*!< Interrupt enable */
1574 #define ADC14_IER0_IE4_OFS                       ( 4)                            /*!< ADC14IE4 Bit Offset */
1575 #define ADC14_IER0_IE4                           ((uint32_t)0x00000010)          /*!< Interrupt enable */
1576 #define ADC14_IER0_IE5_OFS                       ( 5)                            /*!< ADC14IE5 Bit Offset */
1577 #define ADC14_IER0_IE5                           ((uint32_t)0x00000020)          /*!< Interrupt enable */
1578 #define ADC14_IER0_IE6_OFS                       ( 6)                            /*!< ADC14IE6 Bit Offset */
1579 #define ADC14_IER0_IE6                           ((uint32_t)0x00000040)          /*!< Interrupt enable */
1580 #define ADC14_IER0_IE7_OFS                       ( 7)                            /*!< ADC14IE7 Bit Offset */
1581 #define ADC14_IER0_IE7                           ((uint32_t)0x00000080)          /*!< Interrupt enable */
1582 #define ADC14_IER0_IE8_OFS                       ( 8)                            /*!< ADC14IE8 Bit Offset */
1583 #define ADC14_IER0_IE8                           ((uint32_t)0x00000100)          /*!< Interrupt enable */
1584 #define ADC14_IER0_IE9_OFS                       ( 9)                            /*!< ADC14IE9 Bit Offset */
1585 #define ADC14_IER0_IE9                           ((uint32_t)0x00000200)          /*!< Interrupt enable */
1586 #define ADC14_IER0_IE10_OFS                      (10)                            /*!< ADC14IE10 Bit Offset */
1587 #define ADC14_IER0_IE10                          ((uint32_t)0x00000400)          /*!< Interrupt enable */
1588 #define ADC14_IER0_IE11_OFS                      (11)                            /*!< ADC14IE11 Bit Offset */
1589 #define ADC14_IER0_IE11                          ((uint32_t)0x00000800)          /*!< Interrupt enable */
1590 #define ADC14_IER0_IE12_OFS                      (12)                            /*!< ADC14IE12 Bit Offset */
1591 #define ADC14_IER0_IE12                          ((uint32_t)0x00001000)          /*!< Interrupt enable */
1592 #define ADC14_IER0_IE13_OFS                      (13)                            /*!< ADC14IE13 Bit Offset */
1593 #define ADC14_IER0_IE13                          ((uint32_t)0x00002000)          /*!< Interrupt enable */
1594 #define ADC14_IER0_IE14_OFS                      (14)                            /*!< ADC14IE14 Bit Offset */
1595 #define ADC14_IER0_IE14                          ((uint32_t)0x00004000)          /*!< Interrupt enable */
1596 #define ADC14_IER0_IE15_OFS                      (15)                            /*!< ADC14IE15 Bit Offset */
1597 #define ADC14_IER0_IE15                          ((uint32_t)0x00008000)          /*!< Interrupt enable */
1598 #define ADC14_IER0_IE16_OFS                      (16)                            /*!< ADC14IE16 Bit Offset */
1599 #define ADC14_IER0_IE16                          ((uint32_t)0x00010000)          /*!< Interrupt enable */
1600 #define ADC14_IER0_IE17_OFS                      (17)                            /*!< ADC14IE17 Bit Offset */
1601 #define ADC14_IER0_IE17                          ((uint32_t)0x00020000)          /*!< Interrupt enable */
1602 #define ADC14_IER0_IE19_OFS                      (19)                            /*!< ADC14IE19 Bit Offset */
1603 #define ADC14_IER0_IE19                          ((uint32_t)0x00080000)          /*!< Interrupt enable */
1604 #define ADC14_IER0_IE18_OFS                      (18)                            /*!< ADC14IE18 Bit Offset */
1605 #define ADC14_IER0_IE18                          ((uint32_t)0x00040000)          /*!< Interrupt enable */
1606 #define ADC14_IER0_IE20_OFS                      (20)                            /*!< ADC14IE20 Bit Offset */
1607 #define ADC14_IER0_IE20                          ((uint32_t)0x00100000)          /*!< Interrupt enable */
1608 #define ADC14_IER0_IE21_OFS                      (21)                            /*!< ADC14IE21 Bit Offset */
1609 #define ADC14_IER0_IE21                          ((uint32_t)0x00200000)          /*!< Interrupt enable */
1610 #define ADC14_IER0_IE22_OFS                      (22)                            /*!< ADC14IE22 Bit Offset */
1611 #define ADC14_IER0_IE22                          ((uint32_t)0x00400000)          /*!< Interrupt enable */
1612 #define ADC14_IER0_IE23_OFS                      (23)                            /*!< ADC14IE23 Bit Offset */
1613 #define ADC14_IER0_IE23                          ((uint32_t)0x00800000)          /*!< Interrupt enable */
1614 #define ADC14_IER0_IE24_OFS                      (24)                            /*!< ADC14IE24 Bit Offset */
1615 #define ADC14_IER0_IE24                          ((uint32_t)0x01000000)          /*!< Interrupt enable */
1616 #define ADC14_IER0_IE25_OFS                      (25)                            /*!< ADC14IE25 Bit Offset */
1617 #define ADC14_IER0_IE25                          ((uint32_t)0x02000000)          /*!< Interrupt enable */
1618 #define ADC14_IER0_IE26_OFS                      (26)                            /*!< ADC14IE26 Bit Offset */
1619 #define ADC14_IER0_IE26                          ((uint32_t)0x04000000)          /*!< Interrupt enable */
1620 #define ADC14_IER0_IE27_OFS                      (27)                            /*!< ADC14IE27 Bit Offset */
1621 #define ADC14_IER0_IE27                          ((uint32_t)0x08000000)          /*!< Interrupt enable */
1622 #define ADC14_IER0_IE28_OFS                      (28)                            /*!< ADC14IE28 Bit Offset */
1623 #define ADC14_IER0_IE28                          ((uint32_t)0x10000000)          /*!< Interrupt enable */
1624 #define ADC14_IER0_IE29_OFS                      (29)                            /*!< ADC14IE29 Bit Offset */
1625 #define ADC14_IER0_IE29                          ((uint32_t)0x20000000)          /*!< Interrupt enable */
1626 #define ADC14_IER0_IE30_OFS                      (30)                            /*!< ADC14IE30 Bit Offset */
1627 #define ADC14_IER0_IE30                          ((uint32_t)0x40000000)          /*!< Interrupt enable */
1628 #define ADC14_IER0_IE31_OFS                      (31)                            /*!< ADC14IE31 Bit Offset */
1629 #define ADC14_IER0_IE31                          ((uint32_t)0x80000000)          /*!< Interrupt enable */
1630 #define ADC14_IER1_INIE_OFS                      ( 1)                            /*!< ADC14INIE Bit Offset */
1631 #define ADC14_IER1_INIE                          ((uint32_t)0x00000002)          /*!< Interrupt enable for ADC14MEMx within comparator window */
1632 #define ADC14_IER1_LOIE_OFS                      ( 2)                            /*!< ADC14LOIE Bit Offset */
1633 #define ADC14_IER1_LOIE                          ((uint32_t)0x00000004)          /*!< Interrupt enable for ADC14MEMx below comparator window */
1634 #define ADC14_IER1_HIIE_OFS                      ( 3)                            /*!< ADC14HIIE Bit Offset */
1635 #define ADC14_IER1_HIIE                          ((uint32_t)0x00000008)          /*!< Interrupt enable for ADC14MEMx above comparator window */
1636 #define ADC14_IER1_OVIE_OFS                      ( 4)                            /*!< ADC14OVIE Bit Offset */
1637 #define ADC14_IER1_OVIE                          ((uint32_t)0x00000010)          /*!< ADC14MEMx overflow-interrupt enable */
1638 #define ADC14_IER1_TOVIE_OFS                     ( 5)                            /*!< ADC14TOVIE Bit Offset */
1639 #define ADC14_IER1_TOVIE                         ((uint32_t)0x00000020)          /*!< ADC14 conversion-time-overflow interrupt enable */
1640 #define ADC14_IER1_RDYIE_OFS                     ( 6)                            /*!< ADC14RDYIE Bit Offset */
1641 #define ADC14_IER1_RDYIE                         ((uint32_t)0x00000040)          /*!< ADC14 local buffered reference ready interrupt enable */
1642 #define ADC14_IFGR0_IFG0_OFS                     ( 0)                            /*!< ADC14IFG0 Bit Offset */
1643 #define ADC14_IFGR0_IFG0                         ((uint32_t)0x00000001)          /*!< ADC14MEM0 interrupt flag */
1644 #define ADC14_IFGR0_IFG1_OFS                     ( 1)                            /*!< ADC14IFG1 Bit Offset */
1645 #define ADC14_IFGR0_IFG1                         ((uint32_t)0x00000002)          /*!< ADC14MEM1 interrupt flag */
1646 #define ADC14_IFGR0_IFG2_OFS                     ( 2)                            /*!< ADC14IFG2 Bit Offset */
1647 #define ADC14_IFGR0_IFG2                         ((uint32_t)0x00000004)          /*!< ADC14MEM2 interrupt flag */
1648 #define ADC14_IFGR0_IFG3_OFS                     ( 3)                            /*!< ADC14IFG3 Bit Offset */
1649 #define ADC14_IFGR0_IFG3                         ((uint32_t)0x00000008)          /*!< ADC14MEM3 interrupt flag */
1650 #define ADC14_IFGR0_IFG4_OFS                     ( 4)                            /*!< ADC14IFG4 Bit Offset */
1651 #define ADC14_IFGR0_IFG4                         ((uint32_t)0x00000010)          /*!< ADC14MEM4 interrupt flag */
1652 #define ADC14_IFGR0_IFG5_OFS                     ( 5)                            /*!< ADC14IFG5 Bit Offset */
1653 #define ADC14_IFGR0_IFG5                         ((uint32_t)0x00000020)          /*!< ADC14MEM5 interrupt flag */
1654 #define ADC14_IFGR0_IFG6_OFS                     ( 6)                            /*!< ADC14IFG6 Bit Offset */
1655 #define ADC14_IFGR0_IFG6                         ((uint32_t)0x00000040)          /*!< ADC14MEM6 interrupt flag */
1656 #define ADC14_IFGR0_IFG7_OFS                     ( 7)                            /*!< ADC14IFG7 Bit Offset */
1657 #define ADC14_IFGR0_IFG7                         ((uint32_t)0x00000080)          /*!< ADC14MEM7 interrupt flag */
1658 #define ADC14_IFGR0_IFG8_OFS                     ( 8)                            /*!< ADC14IFG8 Bit Offset */
1659 #define ADC14_IFGR0_IFG8                         ((uint32_t)0x00000100)          /*!< ADC14MEM8 interrupt flag */
1660 #define ADC14_IFGR0_IFG9_OFS                     ( 9)                            /*!< ADC14IFG9 Bit Offset */
1661 #define ADC14_IFGR0_IFG9                         ((uint32_t)0x00000200)          /*!< ADC14MEM9 interrupt flag */
1662 #define ADC14_IFGR0_IFG10_OFS                    (10)                            /*!< ADC14IFG10 Bit Offset */
1663 #define ADC14_IFGR0_IFG10                        ((uint32_t)0x00000400)          /*!< ADC14MEM10 interrupt flag */
1664 #define ADC14_IFGR0_IFG11_OFS                    (11)                            /*!< ADC14IFG11 Bit Offset */
1665 #define ADC14_IFGR0_IFG11                        ((uint32_t)0x00000800)          /*!< ADC14MEM11 interrupt flag */
1666 #define ADC14_IFGR0_IFG12_OFS                    (12)                            /*!< ADC14IFG12 Bit Offset */
1667 #define ADC14_IFGR0_IFG12                        ((uint32_t)0x00001000)          /*!< ADC14MEM12 interrupt flag */
1668 #define ADC14_IFGR0_IFG13_OFS                    (13)                            /*!< ADC14IFG13 Bit Offset */
1669 #define ADC14_IFGR0_IFG13                        ((uint32_t)0x00002000)          /*!< ADC14MEM13 interrupt flag */
1670 #define ADC14_IFGR0_IFG14_OFS                    (14)                            /*!< ADC14IFG14 Bit Offset */
1671 #define ADC14_IFGR0_IFG14                        ((uint32_t)0x00004000)          /*!< ADC14MEM14 interrupt flag */
1672 #define ADC14_IFGR0_IFG15_OFS                    (15)                            /*!< ADC14IFG15 Bit Offset */
1673 #define ADC14_IFGR0_IFG15                        ((uint32_t)0x00008000)          /*!< ADC14MEM15 interrupt flag */
1674 #define ADC14_IFGR0_IFG16_OFS                    (16)                            /*!< ADC14IFG16 Bit Offset */
1675 #define ADC14_IFGR0_IFG16                        ((uint32_t)0x00010000)          /*!< ADC14MEM16 interrupt flag */
1676 #define ADC14_IFGR0_IFG17_OFS                    (17)                            /*!< ADC14IFG17 Bit Offset */
1677 #define ADC14_IFGR0_IFG17                        ((uint32_t)0x00020000)          /*!< ADC14MEM17 interrupt flag */
1678 #define ADC14_IFGR0_IFG18_OFS                    (18)                            /*!< ADC14IFG18 Bit Offset */
1679 #define ADC14_IFGR0_IFG18                        ((uint32_t)0x00040000)          /*!< ADC14MEM18 interrupt flag */
1680 #define ADC14_IFGR0_IFG19_OFS                    (19)                            /*!< ADC14IFG19 Bit Offset */
1681 #define ADC14_IFGR0_IFG19                        ((uint32_t)0x00080000)          /*!< ADC14MEM19 interrupt flag */
1682 #define ADC14_IFGR0_IFG20_OFS                    (20)                            /*!< ADC14IFG20 Bit Offset */
1683 #define ADC14_IFGR0_IFG20                        ((uint32_t)0x00100000)          /*!< ADC14MEM20 interrupt flag */
1684 #define ADC14_IFGR0_IFG21_OFS                    (21)                            /*!< ADC14IFG21 Bit Offset */
1685 #define ADC14_IFGR0_IFG21                        ((uint32_t)0x00200000)          /*!< ADC14MEM21 interrupt flag */
1686 #define ADC14_IFGR0_IFG22_OFS                    (22)                            /*!< ADC14IFG22 Bit Offset */
1687 #define ADC14_IFGR0_IFG22                        ((uint32_t)0x00400000)          /*!< ADC14MEM22 interrupt flag */
1688 #define ADC14_IFGR0_IFG23_OFS                    (23)                            /*!< ADC14IFG23 Bit Offset */
1689 #define ADC14_IFGR0_IFG23                        ((uint32_t)0x00800000)          /*!< ADC14MEM23 interrupt flag */
1690 #define ADC14_IFGR0_IFG24_OFS                    (24)                            /*!< ADC14IFG24 Bit Offset */
1691 #define ADC14_IFGR0_IFG24                        ((uint32_t)0x01000000)          /*!< ADC14MEM24 interrupt flag */
1692 #define ADC14_IFGR0_IFG25_OFS                    (25)                            /*!< ADC14IFG25 Bit Offset */
1693 #define ADC14_IFGR0_IFG25                        ((uint32_t)0x02000000)          /*!< ADC14MEM25 interrupt flag */
1694 #define ADC14_IFGR0_IFG26_OFS                    (26)                            /*!< ADC14IFG26 Bit Offset */
1695 #define ADC14_IFGR0_IFG26                        ((uint32_t)0x04000000)          /*!< ADC14MEM26 interrupt flag */
1696 #define ADC14_IFGR0_IFG27_OFS                    (27)                            /*!< ADC14IFG27 Bit Offset */
1697 #define ADC14_IFGR0_IFG27                        ((uint32_t)0x08000000)          /*!< ADC14MEM27 interrupt flag */
1698 #define ADC14_IFGR0_IFG28_OFS                    (28)                            /*!< ADC14IFG28 Bit Offset */
1699 #define ADC14_IFGR0_IFG28                        ((uint32_t)0x10000000)          /*!< ADC14MEM28 interrupt flag */
1700 #define ADC14_IFGR0_IFG29_OFS                    (29)                            /*!< ADC14IFG29 Bit Offset */
1701 #define ADC14_IFGR0_IFG29                        ((uint32_t)0x20000000)          /*!< ADC14MEM29 interrupt flag */
1702 #define ADC14_IFGR0_IFG30_OFS                    (30)                            /*!< ADC14IFG30 Bit Offset */
1703 #define ADC14_IFGR0_IFG30                        ((uint32_t)0x40000000)          /*!< ADC14MEM30 interrupt flag */
1704 #define ADC14_IFGR0_IFG31_OFS                    (31)                            /*!< ADC14IFG31 Bit Offset */
1705 #define ADC14_IFGR0_IFG31                        ((uint32_t)0x80000000)          /*!< ADC14MEM31 interrupt flag */
1706 #define ADC14_IFGR1_INIFG_OFS                    ( 1)                            /*!< ADC14INIFG Bit Offset */
1707 #define ADC14_IFGR1_INIFG                        ((uint32_t)0x00000002)          /*!< Interrupt flag for ADC14MEMx within comparator window */
1708 #define ADC14_IFGR1_LOIFG_OFS                    ( 2)                            /*!< ADC14LOIFG Bit Offset */
1709 #define ADC14_IFGR1_LOIFG                        ((uint32_t)0x00000004)          /*!< Interrupt flag for ADC14MEMx below comparator window */
1710 #define ADC14_IFGR1_HIIFG_OFS                    ( 3)                            /*!< ADC14HIIFG Bit Offset */
1711 #define ADC14_IFGR1_HIIFG                        ((uint32_t)0x00000008)          /*!< Interrupt flag for ADC14MEMx above comparator window */
1712 #define ADC14_IFGR1_OVIFG_OFS                    ( 4)                            /*!< ADC14OVIFG Bit Offset */
1713 #define ADC14_IFGR1_OVIFG                        ((uint32_t)0x00000010)          /*!< ADC14MEMx overflow interrupt flag */
1714 #define ADC14_IFGR1_TOVIFG_OFS                   ( 5)                            /*!< ADC14TOVIFG Bit Offset */
1715 #define ADC14_IFGR1_TOVIFG                       ((uint32_t)0x00000020)          /*!< ADC14 conversion time overflow interrupt flag */
1716 #define ADC14_IFGR1_RDYIFG_OFS                   ( 6)                            /*!< ADC14RDYIFG Bit Offset */
1717 #define ADC14_IFGR1_RDYIFG                       ((uint32_t)0x00000040)          /*!< ADC14 local buffered reference ready interrupt flag */
1718 #define ADC14_CLRIFGR0_CLRIFG0_OFS               ( 0)                            /*!< CLRADC14IFG0 Bit Offset */
1719 #define ADC14_CLRIFGR0_CLRIFG0                   ((uint32_t)0x00000001)          /*!< clear ADC14IFG0 */
1720 #define ADC14_CLRIFGR0_CLRIFG1_OFS               ( 1)                            /*!< CLRADC14IFG1 Bit Offset */
1721 #define ADC14_CLRIFGR0_CLRIFG1                   ((uint32_t)0x00000002)          /*!< clear ADC14IFG1 */
1722 #define ADC14_CLRIFGR0_CLRIFG2_OFS               ( 2)                            /*!< CLRADC14IFG2 Bit Offset */
1723 #define ADC14_CLRIFGR0_CLRIFG2                   ((uint32_t)0x00000004)          /*!< clear ADC14IFG2 */
1724 #define ADC14_CLRIFGR0_CLRIFG3_OFS               ( 3)                            /*!< CLRADC14IFG3 Bit Offset */
1725 #define ADC14_CLRIFGR0_CLRIFG3                   ((uint32_t)0x00000008)          /*!< clear ADC14IFG3 */
1726 #define ADC14_CLRIFGR0_CLRIFG4_OFS               ( 4)                            /*!< CLRADC14IFG4 Bit Offset */
1727 #define ADC14_CLRIFGR0_CLRIFG4                   ((uint32_t)0x00000010)          /*!< clear ADC14IFG4 */
1728 #define ADC14_CLRIFGR0_CLRIFG5_OFS               ( 5)                            /*!< CLRADC14IFG5 Bit Offset */
1729 #define ADC14_CLRIFGR0_CLRIFG5                   ((uint32_t)0x00000020)          /*!< clear ADC14IFG5 */
1730 #define ADC14_CLRIFGR0_CLRIFG6_OFS               ( 6)                            /*!< CLRADC14IFG6 Bit Offset */
1731 #define ADC14_CLRIFGR0_CLRIFG6                   ((uint32_t)0x00000040)          /*!< clear ADC14IFG6 */
1732 #define ADC14_CLRIFGR0_CLRIFG7_OFS               ( 7)                            /*!< CLRADC14IFG7 Bit Offset */
1733 #define ADC14_CLRIFGR0_CLRIFG7                   ((uint32_t)0x00000080)          /*!< clear ADC14IFG7 */
1734 #define ADC14_CLRIFGR0_CLRIFG8_OFS               ( 8)                            /*!< CLRADC14IFG8 Bit Offset */
1735 #define ADC14_CLRIFGR0_CLRIFG8                   ((uint32_t)0x00000100)          /*!< clear ADC14IFG8 */
1736 #define ADC14_CLRIFGR0_CLRIFG9_OFS               ( 9)                            /*!< CLRADC14IFG9 Bit Offset */
1737 #define ADC14_CLRIFGR0_CLRIFG9                   ((uint32_t)0x00000200)          /*!< clear ADC14IFG9 */
1738 #define ADC14_CLRIFGR0_CLRIFG10_OFS              (10)                            /*!< CLRADC14IFG10 Bit Offset */
1739 #define ADC14_CLRIFGR0_CLRIFG10                  ((uint32_t)0x00000400)          /*!< clear ADC14IFG10 */
1740 #define ADC14_CLRIFGR0_CLRIFG11_OFS              (11)                            /*!< CLRADC14IFG11 Bit Offset */
1741 #define ADC14_CLRIFGR0_CLRIFG11                  ((uint32_t)0x00000800)          /*!< clear ADC14IFG11 */
1742 #define ADC14_CLRIFGR0_CLRIFG12_OFS              (12)                            /*!< CLRADC14IFG12 Bit Offset */
1743 #define ADC14_CLRIFGR0_CLRIFG12                  ((uint32_t)0x00001000)          /*!< clear ADC14IFG12 */
1744 #define ADC14_CLRIFGR0_CLRIFG13_OFS              (13)                            /*!< CLRADC14IFG13 Bit Offset */
1745 #define ADC14_CLRIFGR0_CLRIFG13                  ((uint32_t)0x00002000)          /*!< clear ADC14IFG13 */
1746 #define ADC14_CLRIFGR0_CLRIFG14_OFS              (14)                            /*!< CLRADC14IFG14 Bit Offset */
1747 #define ADC14_CLRIFGR0_CLRIFG14                  ((uint32_t)0x00004000)          /*!< clear ADC14IFG14 */
1748 #define ADC14_CLRIFGR0_CLRIFG15_OFS              (15)                            /*!< CLRADC14IFG15 Bit Offset */
1749 #define ADC14_CLRIFGR0_CLRIFG15                  ((uint32_t)0x00008000)          /*!< clear ADC14IFG15 */
1750 #define ADC14_CLRIFGR0_CLRIFG16_OFS              (16)                            /*!< CLRADC14IFG16 Bit Offset */
1751 #define ADC14_CLRIFGR0_CLRIFG16                  ((uint32_t)0x00010000)          /*!< clear ADC14IFG16 */
1752 #define ADC14_CLRIFGR0_CLRIFG17_OFS              (17)                            /*!< CLRADC14IFG17 Bit Offset */
1753 #define ADC14_CLRIFGR0_CLRIFG17                  ((uint32_t)0x00020000)          /*!< clear ADC14IFG17 */
1754 #define ADC14_CLRIFGR0_CLRIFG18_OFS              (18)                            /*!< CLRADC14IFG18 Bit Offset */
1755 #define ADC14_CLRIFGR0_CLRIFG18                  ((uint32_t)0x00040000)          /*!< clear ADC14IFG18 */
1756 #define ADC14_CLRIFGR0_CLRIFG19_OFS              (19)                            /*!< CLRADC14IFG19 Bit Offset */
1757 #define ADC14_CLRIFGR0_CLRIFG19                  ((uint32_t)0x00080000)          /*!< clear ADC14IFG19 */
1758 #define ADC14_CLRIFGR0_CLRIFG20_OFS              (20)                            /*!< CLRADC14IFG20 Bit Offset */
1759 #define ADC14_CLRIFGR0_CLRIFG20                  ((uint32_t)0x00100000)          /*!< clear ADC14IFG20 */
1760 #define ADC14_CLRIFGR0_CLRIFG21_OFS              (21)                            /*!< CLRADC14IFG21 Bit Offset */
1761 #define ADC14_CLRIFGR0_CLRIFG21                  ((uint32_t)0x00200000)          /*!< clear ADC14IFG21 */
1762 #define ADC14_CLRIFGR0_CLRIFG22_OFS              (22)                            /*!< CLRADC14IFG22 Bit Offset */
1763 #define ADC14_CLRIFGR0_CLRIFG22                  ((uint32_t)0x00400000)          /*!< clear ADC14IFG22 */
1764 #define ADC14_CLRIFGR0_CLRIFG23_OFS              (23)                            /*!< CLRADC14IFG23 Bit Offset */
1765 #define ADC14_CLRIFGR0_CLRIFG23                  ((uint32_t)0x00800000)          /*!< clear ADC14IFG23 */
1766 #define ADC14_CLRIFGR0_CLRIFG24_OFS              (24)                            /*!< CLRADC14IFG24 Bit Offset */
1767 #define ADC14_CLRIFGR0_CLRIFG24                  ((uint32_t)0x01000000)          /*!< clear ADC14IFG24 */
1768 #define ADC14_CLRIFGR0_CLRIFG25_OFS              (25)                            /*!< CLRADC14IFG25 Bit Offset */
1769 #define ADC14_CLRIFGR0_CLRIFG25                  ((uint32_t)0x02000000)          /*!< clear ADC14IFG25 */
1770 #define ADC14_CLRIFGR0_CLRIFG26_OFS              (26)                            /*!< CLRADC14IFG26 Bit Offset */
1771 #define ADC14_CLRIFGR0_CLRIFG26                  ((uint32_t)0x04000000)          /*!< clear ADC14IFG26 */
1772 #define ADC14_CLRIFGR0_CLRIFG27_OFS              (27)                            /*!< CLRADC14IFG27 Bit Offset */
1773 #define ADC14_CLRIFGR0_CLRIFG27                  ((uint32_t)0x08000000)          /*!< clear ADC14IFG27 */
1774 #define ADC14_CLRIFGR0_CLRIFG28_OFS              (28)                            /*!< CLRADC14IFG28 Bit Offset */
1775 #define ADC14_CLRIFGR0_CLRIFG28                  ((uint32_t)0x10000000)          /*!< clear ADC14IFG28 */
1776 #define ADC14_CLRIFGR0_CLRIFG29_OFS              (29)                            /*!< CLRADC14IFG29 Bit Offset */
1777 #define ADC14_CLRIFGR0_CLRIFG29                  ((uint32_t)0x20000000)          /*!< clear ADC14IFG29 */
1778 #define ADC14_CLRIFGR0_CLRIFG30_OFS              (30)                            /*!< CLRADC14IFG30 Bit Offset */
1779 #define ADC14_CLRIFGR0_CLRIFG30                  ((uint32_t)0x40000000)          /*!< clear ADC14IFG30 */
1780 #define ADC14_CLRIFGR0_CLRIFG31_OFS              (31)                            /*!< CLRADC14IFG31 Bit Offset */
1781 #define ADC14_CLRIFGR0_CLRIFG31                  ((uint32_t)0x80000000)          /*!< clear ADC14IFG31 */
1782 #define ADC14_CLRIFGR1_CLRINIFG_OFS              ( 1)                            /*!< CLRADC14INIFG Bit Offset */
1783 #define ADC14_CLRIFGR1_CLRINIFG                  ((uint32_t)0x00000002)          /*!< clear ADC14INIFG */
1784 #define ADC14_CLRIFGR1_CLRLOIFG_OFS              ( 2)                            /*!< CLRADC14LOIFG Bit Offset */
1785 #define ADC14_CLRIFGR1_CLRLOIFG                  ((uint32_t)0x00000004)          /*!< clear ADC14LOIFG */
1786 #define ADC14_CLRIFGR1_CLRHIIFG_OFS              ( 3)                            /*!< CLRADC14HIIFG Bit Offset */
1787 #define ADC14_CLRIFGR1_CLRHIIFG                  ((uint32_t)0x00000008)          /*!< clear ADC14HIIFG */
1788 #define ADC14_CLRIFGR1_CLROVIFG_OFS              ( 4)                            /*!< CLRADC14OVIFG Bit Offset */
1789 #define ADC14_CLRIFGR1_CLROVIFG                  ((uint32_t)0x00000010)          /*!< clear ADC14OVIFG */
1790 #define ADC14_CLRIFGR1_CLRTOVIFG_OFS             ( 5)                            /*!< CLRADC14TOVIFG Bit Offset */
1791 #define ADC14_CLRIFGR1_CLRTOVIFG                 ((uint32_t)0x00000020)          /*!< clear ADC14TOVIFG */
1792 #define ADC14_CLRIFGR1_CLRRDYIFG_OFS             ( 6)                            /*!< CLRADC14RDYIFG Bit Offset */
1793 #define ADC14_CLRIFGR1_CLRRDYIFG                 ((uint32_t)0x00000040)          /*!< clear ADC14RDYIFG */
1794 #define AES256_CTL0_OP_OFS                       ( 0)                            /*!< AESOPx Bit Offset */
1795 #define AES256_CTL0_OP_MASK                      ((uint16_t)0x0003)              /*!< AESOPx Bit Mask */
1796 #define AES256_CTL0_OP0                          ((uint16_t)0x0001)              /*!< OP Bit 0 */
1797 #define AES256_CTL0_OP1                          ((uint16_t)0x0002)              /*!< OP Bit 1 */
1798 #define AES256_CTL0_OP_0                         ((uint16_t)0x0000)              /*!< Encryption */
1799 #define AES256_CTL0_OP_1                         ((uint16_t)0x0001)              /*!< Decryption. The provided key is the same key used for encryption */
1800 #define AES256_CTL0_OP_2                         ((uint16_t)0x0002)              /*!< Generate first round key required for decryption */
1801 #define AES256_CTL0_OP_3                         ((uint16_t)0x0003)              /*!< Decryption. The provided key is the first round key required for decryption */
1802 #define AES256_CTL0_KL_OFS                       ( 2)                            /*!< AESKLx Bit Offset */
1803 #define AES256_CTL0_KL_MASK                      ((uint16_t)0x000C)              /*!< AESKLx Bit Mask */
1804 #define AES256_CTL0_KL0                          ((uint16_t)0x0004)              /*!< KL Bit 0 */
1805 #define AES256_CTL0_KL1                          ((uint16_t)0x0008)              /*!< KL Bit 1 */
1806 #define AES256_CTL0_KL_0                         ((uint16_t)0x0000)              /*!< AES128. The key size is 128 bit */
1807 #define AES256_CTL0_KL_1                         ((uint16_t)0x0004)              /*!< AES192. The key size is 192 bit. */
1808 #define AES256_CTL0_KL_2                         ((uint16_t)0x0008)              /*!< AES256. The key size is 256 bit */
1809 #define AES256_CTL0_KL__128BIT                   ((uint16_t)0x0000)              /*!< AES128. The key size is 128 bit */
1810 #define AES256_CTL0_KL__192BIT                   ((uint16_t)0x0004)              /*!< AES192. The key size is 192 bit. */
1811 #define AES256_CTL0_KL__256BIT                   ((uint16_t)0x0008)              /*!< AES256. The key size is 256 bit */
1812 #define AES256_CTL0_CM_OFS                       ( 5)                            /*!< AESCMx Bit Offset */
1813 #define AES256_CTL0_CM_MASK                      ((uint16_t)0x0060)              /*!< AESCMx Bit Mask */
1814 #define AES256_CTL0_CM0                          ((uint16_t)0x0020)              /*!< CM Bit 0 */
1815 #define AES256_CTL0_CM1                          ((uint16_t)0x0040)              /*!< CM Bit 1 */
1816 #define AES256_CTL0_CM_0                         ((uint16_t)0x0000)              /*!< ECB */
1817 #define AES256_CTL0_CM_1                         ((uint16_t)0x0020)              /*!< CBC */
1818 #define AES256_CTL0_CM_2                         ((uint16_t)0x0040)              /*!< OFB */
1819 #define AES256_CTL0_CM_3                         ((uint16_t)0x0060)              /*!< CFB */
1820 #define AES256_CTL0_CM__ECB                      ((uint16_t)0x0000)              /*!< ECB */
1821 #define AES256_CTL0_CM__CBC                      ((uint16_t)0x0020)              /*!< CBC */
1822 #define AES256_CTL0_CM__OFB                      ((uint16_t)0x0040)              /*!< OFB */
1823 #define AES256_CTL0_CM__CFB                      ((uint16_t)0x0060)              /*!< CFB */
1824 #define AES256_CTL0_SWRST_OFS                    ( 7)                            /*!< AESSWRST Bit Offset */
1825 #define AES256_CTL0_SWRST                        ((uint16_t)0x0080)              /*!< AES software reset */
1826 #define AES256_CTL0_RDYIFG_OFS                   ( 8)                            /*!< AESRDYIFG Bit Offset */
1827 #define AES256_CTL0_RDYIFG                       ((uint16_t)0x0100)              /*!< AES ready interrupt flag */
1828 #define AES256_CTL0_ERRFG_OFS                    (11)                            /*!< AESERRFG Bit Offset */
1829 #define AES256_CTL0_ERRFG                        ((uint16_t)0x0800)              /*!< AES error flag */
1830 #define AES256_CTL0_RDYIE_OFS                    (12)                            /*!< AESRDYIE Bit Offset */
1831 #define AES256_CTL0_RDYIE                        ((uint16_t)0x1000)              /*!< AES ready interrupt enable */
1832 #define AES256_CTL0_CMEN_OFS                     (15)                            /*!< AESCMEN Bit Offset */
1833 #define AES256_CTL0_CMEN                         ((uint16_t)0x8000)              /*!< AES cipher mode enable */
1834 #define AES256_CTL1_BLKCNT_OFS                   ( 0)                            /*!< AESBLKCNTx Bit Offset */
1835 #define AES256_CTL1_BLKCNT_MASK                  ((uint16_t)0x00FF)              /*!< AESBLKCNTx Bit Mask */
1836 #define AES256_CTL1_BLKCNT0                      ((uint16_t)0x0001)              /*!< BLKCNT Bit 0 */
1837 #define AES256_CTL1_BLKCNT1                      ((uint16_t)0x0002)              /*!< BLKCNT Bit 1 */
1838 #define AES256_CTL1_BLKCNT2                      ((uint16_t)0x0004)              /*!< BLKCNT Bit 2 */
1839 #define AES256_CTL1_BLKCNT3                      ((uint16_t)0x0008)              /*!< BLKCNT Bit 3 */
1840 #define AES256_CTL1_BLKCNT4                      ((uint16_t)0x0010)              /*!< BLKCNT Bit 4 */
1841 #define AES256_CTL1_BLKCNT5                      ((uint16_t)0x0020)              /*!< BLKCNT Bit 5 */
1842 #define AES256_CTL1_BLKCNT6                      ((uint16_t)0x0040)              /*!< BLKCNT Bit 6 */
1843 #define AES256_CTL1_BLKCNT7                      ((uint16_t)0x0080)              /*!< BLKCNT Bit 7 */
1844 #define AES256_STAT_BUSY_OFS                     ( 0)                            /*!< AESBUSY Bit Offset */
1845 #define AES256_STAT_BUSY                         ((uint16_t)0x0001)              /*!< AES accelerator module busy */
1846 #define AES256_STAT_KEYWR_OFS                    ( 1)                            /*!< AESKEYWR Bit Offset */
1847 #define AES256_STAT_KEYWR                        ((uint16_t)0x0002)              /*!< All 16 bytes written to AESAKEY */
1848 #define AES256_STAT_DINWR_OFS                    ( 2)                            /*!< AESDINWR Bit Offset */
1849 #define AES256_STAT_DINWR                        ((uint16_t)0x0004)              /*!< All 16 bytes written to AESADIN, AESAXDIN or AESAXIN */
1850 #define AES256_STAT_DOUTRD_OFS                   ( 3)                            /*!< AESDOUTRD Bit Offset */
1851 #define AES256_STAT_DOUTRD                       ((uint16_t)0x0008)              /*!< All 16 bytes read from AESADOUT */
1852 #define AES256_STAT_KEYCNT_OFS                   ( 4)                            /*!< AESKEYCNTx Bit Offset */
1853 #define AES256_STAT_KEYCNT_MASK                  ((uint16_t)0x00F0)              /*!< AESKEYCNTx Bit Mask */
1854 #define AES256_STAT_KEYCNT0                      ((uint16_t)0x0010)              /*!< KEYCNT Bit 0 */
1855 #define AES256_STAT_KEYCNT1                      ((uint16_t)0x0020)              /*!< KEYCNT Bit 1 */
1856 #define AES256_STAT_KEYCNT2                      ((uint16_t)0x0040)              /*!< KEYCNT Bit 2 */
1857 #define AES256_STAT_KEYCNT3                      ((uint16_t)0x0080)              /*!< KEYCNT Bit 3 */
1858 #define AES256_STAT_DINCNT_OFS                   ( 8)                            /*!< AESDINCNTx Bit Offset */
1859 #define AES256_STAT_DINCNT_MASK                  ((uint16_t)0x0F00)              /*!< AESDINCNTx Bit Mask */
1860 #define AES256_STAT_DINCNT0                      ((uint16_t)0x0100)              /*!< DINCNT Bit 0 */
1861 #define AES256_STAT_DINCNT1                      ((uint16_t)0x0200)              /*!< DINCNT Bit 1 */
1862 #define AES256_STAT_DINCNT2                      ((uint16_t)0x0400)              /*!< DINCNT Bit 2 */
1863 #define AES256_STAT_DINCNT3                      ((uint16_t)0x0800)              /*!< DINCNT Bit 3 */
1864 #define AES256_STAT_DOUTCNT_OFS                  (12)                            /*!< AESDOUTCNTx Bit Offset */
1865 #define AES256_STAT_DOUTCNT_MASK                 ((uint16_t)0xF000)              /*!< AESDOUTCNTx Bit Mask */
1866 #define AES256_STAT_DOUTCNT0                     ((uint16_t)0x1000)              /*!< DOUTCNT Bit 0 */
1867 #define AES256_STAT_DOUTCNT1                     ((uint16_t)0x2000)              /*!< DOUTCNT Bit 1 */
1868 #define AES256_STAT_DOUTCNT2                     ((uint16_t)0x4000)              /*!< DOUTCNT Bit 2 */
1869 #define AES256_STAT_DOUTCNT3                     ((uint16_t)0x8000)              /*!< DOUTCNT Bit 3 */
1870 #define AES256_KEY_KEY0_OFS                      ( 0)                            /*!< AESKEY0x Bit Offset */
1871 #define AES256_KEY_KEY0_MASK                     ((uint16_t)0x00FF)              /*!< AESKEY0x Bit Mask */
1872 #define AES256_KEY_KEY00                         ((uint16_t)0x0001)              /*!< KEY0 Bit 0 */
1873 #define AES256_KEY_KEY01                         ((uint16_t)0x0002)              /*!< KEY0 Bit 1 */
1874 #define AES256_KEY_KEY02                         ((uint16_t)0x0004)              /*!< KEY0 Bit 2 */
1875 #define AES256_KEY_KEY03                         ((uint16_t)0x0008)              /*!< KEY0 Bit 3 */
1876 #define AES256_KEY_KEY04                         ((uint16_t)0x0010)              /*!< KEY0 Bit 4 */
1877 #define AES256_KEY_KEY05                         ((uint16_t)0x0020)              /*!< KEY0 Bit 5 */
1878 #define AES256_KEY_KEY06                         ((uint16_t)0x0040)              /*!< KEY0 Bit 6 */
1879 #define AES256_KEY_KEY07                         ((uint16_t)0x0080)              /*!< KEY0 Bit 7 */
1880 #define AES256_KEY_KEY1_OFS                      ( 8)                            /*!< AESKEY1x Bit Offset */
1881 #define AES256_KEY_KEY1_MASK                     ((uint16_t)0xFF00)              /*!< AESKEY1x Bit Mask */
1882 #define AES256_KEY_KEY10                         ((uint16_t)0x0100)              /*!< KEY1 Bit 0 */
1883 #define AES256_KEY_KEY11                         ((uint16_t)0x0200)              /*!< KEY1 Bit 1 */
1884 #define AES256_KEY_KEY12                         ((uint16_t)0x0400)              /*!< KEY1 Bit 2 */
1885 #define AES256_KEY_KEY13                         ((uint16_t)0x0800)              /*!< KEY1 Bit 3 */
1886 #define AES256_KEY_KEY14                         ((uint16_t)0x1000)              /*!< KEY1 Bit 4 */
1887 #define AES256_KEY_KEY15                         ((uint16_t)0x2000)              /*!< KEY1 Bit 5 */
1888 #define AES256_KEY_KEY16                         ((uint16_t)0x4000)              /*!< KEY1 Bit 6 */
1889 #define AES256_KEY_KEY17                         ((uint16_t)0x8000)              /*!< KEY1 Bit 7 */
1890 #define AES256_DIN_DIN0_OFS                      ( 0)                            /*!< AESDIN0x Bit Offset */
1891 #define AES256_DIN_DIN0_MASK                     ((uint16_t)0x00FF)              /*!< AESDIN0x Bit Mask */
1892 #define AES256_DIN_DIN00                         ((uint16_t)0x0001)              /*!< DIN0 Bit 0 */
1893 #define AES256_DIN_DIN01                         ((uint16_t)0x0002)              /*!< DIN0 Bit 1 */
1894 #define AES256_DIN_DIN02                         ((uint16_t)0x0004)              /*!< DIN0 Bit 2 */
1895 #define AES256_DIN_DIN03                         ((uint16_t)0x0008)              /*!< DIN0 Bit 3 */
1896 #define AES256_DIN_DIN04                         ((uint16_t)0x0010)              /*!< DIN0 Bit 4 */
1897 #define AES256_DIN_DIN05                         ((uint16_t)0x0020)              /*!< DIN0 Bit 5 */
1898 #define AES256_DIN_DIN06                         ((uint16_t)0x0040)              /*!< DIN0 Bit 6 */
1899 #define AES256_DIN_DIN07                         ((uint16_t)0x0080)              /*!< DIN0 Bit 7 */
1900 #define AES256_DIN_DIN1_OFS                      ( 8)                            /*!< AESDIN1x Bit Offset */
1901 #define AES256_DIN_DIN1_MASK                     ((uint16_t)0xFF00)              /*!< AESDIN1x Bit Mask */
1902 #define AES256_DIN_DIN10                         ((uint16_t)0x0100)              /*!< DIN1 Bit 0 */
1903 #define AES256_DIN_DIN11                         ((uint16_t)0x0200)              /*!< DIN1 Bit 1 */
1904 #define AES256_DIN_DIN12                         ((uint16_t)0x0400)              /*!< DIN1 Bit 2 */
1905 #define AES256_DIN_DIN13                         ((uint16_t)0x0800)              /*!< DIN1 Bit 3 */
1906 #define AES256_DIN_DIN14                         ((uint16_t)0x1000)              /*!< DIN1 Bit 4 */
1907 #define AES256_DIN_DIN15                         ((uint16_t)0x2000)              /*!< DIN1 Bit 5 */
1908 #define AES256_DIN_DIN16                         ((uint16_t)0x4000)              /*!< DIN1 Bit 6 */
1909 #define AES256_DIN_DIN17                         ((uint16_t)0x8000)              /*!< DIN1 Bit 7 */
1910 #define AES256_DOUT_DOUT0_OFS                    ( 0)                            /*!< AESDOUT0x Bit Offset */
1911 #define AES256_DOUT_DOUT0_MASK                   ((uint16_t)0x00FF)              /*!< AESDOUT0x Bit Mask */
1912 #define AES256_DOUT_DOUT00                       ((uint16_t)0x0001)              /*!< DOUT0 Bit 0 */
1913 #define AES256_DOUT_DOUT01                       ((uint16_t)0x0002)              /*!< DOUT0 Bit 1 */
1914 #define AES256_DOUT_DOUT02                       ((uint16_t)0x0004)              /*!< DOUT0 Bit 2 */
1915 #define AES256_DOUT_DOUT03                       ((uint16_t)0x0008)              /*!< DOUT0 Bit 3 */
1916 #define AES256_DOUT_DOUT04                       ((uint16_t)0x0010)              /*!< DOUT0 Bit 4 */
1917 #define AES256_DOUT_DOUT05                       ((uint16_t)0x0020)              /*!< DOUT0 Bit 5 */
1918 #define AES256_DOUT_DOUT06                       ((uint16_t)0x0040)              /*!< DOUT0 Bit 6 */
1919 #define AES256_DOUT_DOUT07                       ((uint16_t)0x0080)              /*!< DOUT0 Bit 7 */
1920 #define AES256_DOUT_DOUT1_OFS                    ( 8)                            /*!< AESDOUT1x Bit Offset */
1921 #define AES256_DOUT_DOUT1_MASK                   ((uint16_t)0xFF00)              /*!< AESDOUT1x Bit Mask */
1922 #define AES256_DOUT_DOUT10                       ((uint16_t)0x0100)              /*!< DOUT1 Bit 0 */
1923 #define AES256_DOUT_DOUT11                       ((uint16_t)0x0200)              /*!< DOUT1 Bit 1 */
1924 #define AES256_DOUT_DOUT12                       ((uint16_t)0x0400)              /*!< DOUT1 Bit 2 */
1925 #define AES256_DOUT_DOUT13                       ((uint16_t)0x0800)              /*!< DOUT1 Bit 3 */
1926 #define AES256_DOUT_DOUT14                       ((uint16_t)0x1000)              /*!< DOUT1 Bit 4 */
1927 #define AES256_DOUT_DOUT15                       ((uint16_t)0x2000)              /*!< DOUT1 Bit 5 */
1928 #define AES256_DOUT_DOUT16                       ((uint16_t)0x4000)              /*!< DOUT1 Bit 6 */
1929 #define AES256_DOUT_DOUT17                       ((uint16_t)0x8000)              /*!< DOUT1 Bit 7 */
1930 #define AES256_XDIN_XDIN0_OFS                    ( 0)                            /*!< AESXDIN0x Bit Offset */
1931 #define AES256_XDIN_XDIN0_MASK                   ((uint16_t)0x00FF)              /*!< AESXDIN0x Bit Mask */
1932 #define AES256_XDIN_XDIN00                       ((uint16_t)0x0001)              /*!< XDIN0 Bit 0 */
1933 #define AES256_XDIN_XDIN01                       ((uint16_t)0x0002)              /*!< XDIN0 Bit 1 */
1934 #define AES256_XDIN_XDIN02                       ((uint16_t)0x0004)              /*!< XDIN0 Bit 2 */
1935 #define AES256_XDIN_XDIN03                       ((uint16_t)0x0008)              /*!< XDIN0 Bit 3 */
1936 #define AES256_XDIN_XDIN04                       ((uint16_t)0x0010)              /*!< XDIN0 Bit 4 */
1937 #define AES256_XDIN_XDIN05                       ((uint16_t)0x0020)              /*!< XDIN0 Bit 5 */
1938 #define AES256_XDIN_XDIN06                       ((uint16_t)0x0040)              /*!< XDIN0 Bit 6 */
1939 #define AES256_XDIN_XDIN07                       ((uint16_t)0x0080)              /*!< XDIN0 Bit 7 */
1940 #define AES256_XDIN_XDIN1_OFS                    ( 8)                            /*!< AESXDIN1x Bit Offset */
1941 #define AES256_XDIN_XDIN1_MASK                   ((uint16_t)0xFF00)              /*!< AESXDIN1x Bit Mask */
1942 #define AES256_XDIN_XDIN10                       ((uint16_t)0x0100)              /*!< XDIN1 Bit 0 */
1943 #define AES256_XDIN_XDIN11                       ((uint16_t)0x0200)              /*!< XDIN1 Bit 1 */
1944 #define AES256_XDIN_XDIN12                       ((uint16_t)0x0400)              /*!< XDIN1 Bit 2 */
1945 #define AES256_XDIN_XDIN13                       ((uint16_t)0x0800)              /*!< XDIN1 Bit 3 */
1946 #define AES256_XDIN_XDIN14                       ((uint16_t)0x1000)              /*!< XDIN1 Bit 4 */
1947 #define AES256_XDIN_XDIN15                       ((uint16_t)0x2000)              /*!< XDIN1 Bit 5 */
1948 #define AES256_XDIN_XDIN16                       ((uint16_t)0x4000)              /*!< XDIN1 Bit 6 */
1949 #define AES256_XDIN_XDIN17                       ((uint16_t)0x8000)              /*!< XDIN1 Bit 7 */
1950 #define AES256_XIN_XIN0_OFS                      ( 0)                            /*!< AESXIN0x Bit Offset */
1951 #define AES256_XIN_XIN0_MASK                     ((uint16_t)0x00FF)              /*!< AESXIN0x Bit Mask */
1952 #define AES256_XIN_XIN00                         ((uint16_t)0x0001)              /*!< XIN0 Bit 0 */
1953 #define AES256_XIN_XIN01                         ((uint16_t)0x0002)              /*!< XIN0 Bit 1 */
1954 #define AES256_XIN_XIN02                         ((uint16_t)0x0004)              /*!< XIN0 Bit 2 */
1955 #define AES256_XIN_XIN03                         ((uint16_t)0x0008)              /*!< XIN0 Bit 3 */
1956 #define AES256_XIN_XIN04                         ((uint16_t)0x0010)              /*!< XIN0 Bit 4 */
1957 #define AES256_XIN_XIN05                         ((uint16_t)0x0020)              /*!< XIN0 Bit 5 */
1958 #define AES256_XIN_XIN06                         ((uint16_t)0x0040)              /*!< XIN0 Bit 6 */
1959 #define AES256_XIN_XIN07                         ((uint16_t)0x0080)              /*!< XIN0 Bit 7 */
1960 #define AES256_XIN_XIN1_OFS                      ( 8)                            /*!< AESXIN1x Bit Offset */
1961 #define AES256_XIN_XIN1_MASK                     ((uint16_t)0xFF00)              /*!< AESXIN1x Bit Mask */
1962 #define AES256_XIN_XIN10                         ((uint16_t)0x0100)              /*!< XIN1 Bit 0 */
1963 #define AES256_XIN_XIN11                         ((uint16_t)0x0200)              /*!< XIN1 Bit 1 */
1964 #define AES256_XIN_XIN12                         ((uint16_t)0x0400)              /*!< XIN1 Bit 2 */
1965 #define AES256_XIN_XIN13                         ((uint16_t)0x0800)              /*!< XIN1 Bit 3 */
1966 #define AES256_XIN_XIN14                         ((uint16_t)0x1000)              /*!< XIN1 Bit 4 */
1967 #define AES256_XIN_XIN15                         ((uint16_t)0x2000)              /*!< XIN1 Bit 5 */
1968 #define AES256_XIN_XIN16                         ((uint16_t)0x4000)              /*!< XIN1 Bit 6 */
1969 #define AES256_XIN_XIN17                         ((uint16_t)0x8000)              /*!< XIN1 Bit 7 */
1970 #define CAPTIO_CTL_PISEL_OFS                     ( 1)                            /*!< CAPTIOPISELx Bit Offset */
1971 #define CAPTIO_CTL_PISEL_MASK                    ((uint16_t)0x000E)              /*!< CAPTIOPISELx Bit Mask */
1972 #define CAPTIO_CTL_PISEL0                        ((uint16_t)0x0002)              /*!< PISEL Bit 0 */
1973 #define CAPTIO_CTL_PISEL1                        ((uint16_t)0x0004)              /*!< PISEL Bit 1 */
1974 #define CAPTIO_CTL_PISEL2                        ((uint16_t)0x0008)              /*!< PISEL Bit 2 */
1975 #define CAPTIO_CTL_PISEL_0                       ((uint16_t)0x0000)              /*!< Px.0 */
1976 #define CAPTIO_CTL_PISEL_1                       ((uint16_t)0x0002)              /*!< Px.1 */
1977 #define CAPTIO_CTL_PISEL_2                       ((uint16_t)0x0004)              /*!< Px.2 */
1978 #define CAPTIO_CTL_PISEL_3                       ((uint16_t)0x0006)              /*!< Px.3 */
1979 #define CAPTIO_CTL_PISEL_4                       ((uint16_t)0x0008)              /*!< Px.4 */
1980 #define CAPTIO_CTL_PISEL_5                       ((uint16_t)0x000A)              /*!< Px.5 */
1981 #define CAPTIO_CTL_PISEL_6                       ((uint16_t)0x000C)              /*!< Px.6 */
1982 #define CAPTIO_CTL_PISEL_7                       ((uint16_t)0x000E)              /*!< Px.7 */
1983 #define CAPTIO_CTL_POSEL_OFS                     ( 4)                            /*!< CAPTIOPOSELx Bit Offset */
1984 #define CAPTIO_CTL_POSEL_MASK                    ((uint16_t)0x00F0)              /*!< CAPTIOPOSELx Bit Mask */
1985 #define CAPTIO_CTL_POSEL0                        ((uint16_t)0x0010)              /*!< POSEL Bit 0 */
1986 #define CAPTIO_CTL_POSEL1                        ((uint16_t)0x0020)              /*!< POSEL Bit 1 */
1987 #define CAPTIO_CTL_POSEL2                        ((uint16_t)0x0040)              /*!< POSEL Bit 2 */
1988 #define CAPTIO_CTL_POSEL3                        ((uint16_t)0x0080)              /*!< POSEL Bit 3 */
1989 #define CAPTIO_CTL_POSEL_0                       ((uint16_t)0x0000)              /*!< Px = PJ */
1990 #define CAPTIO_CTL_POSEL_1                       ((uint16_t)0x0010)              /*!< Px = P1 */
1991 #define CAPTIO_CTL_POSEL_2                       ((uint16_t)0x0020)              /*!< Px = P2 */
1992 #define CAPTIO_CTL_POSEL_3                       ((uint16_t)0x0030)              /*!< Px = P3 */
1993 #define CAPTIO_CTL_POSEL_4                       ((uint16_t)0x0040)              /*!< Px = P4 */
1994 #define CAPTIO_CTL_POSEL_5                       ((uint16_t)0x0050)              /*!< Px = P5 */
1995 #define CAPTIO_CTL_POSEL_6                       ((uint16_t)0x0060)              /*!< Px = P6 */
1996 #define CAPTIO_CTL_POSEL_7                       ((uint16_t)0x0070)              /*!< Px = P7 */
1997 #define CAPTIO_CTL_POSEL_8                       ((uint16_t)0x0080)              /*!< Px = P8 */
1998 #define CAPTIO_CTL_POSEL_9                       ((uint16_t)0x0090)              /*!< Px = P9 */
1999 #define CAPTIO_CTL_POSEL_10                      ((uint16_t)0x00A0)              /*!< Px = P10 */
2000 #define CAPTIO_CTL_POSEL_11                      ((uint16_t)0x00B0)              /*!< Px = P11 */
2001 #define CAPTIO_CTL_POSEL_12                      ((uint16_t)0x00C0)              /*!< Px = P12 */
2002 #define CAPTIO_CTL_POSEL_13                      ((uint16_t)0x00D0)              /*!< Px = P13 */
2003 #define CAPTIO_CTL_POSEL_14                      ((uint16_t)0x00E0)              /*!< Px = P14 */
2004 #define CAPTIO_CTL_POSEL_15                      ((uint16_t)0x00F0)              /*!< Px = P15 */
2005 #define CAPTIO_CTL_POSEL__PJ                     ((uint16_t)0x0000)              /*!< Px = PJ */
2006 #define CAPTIO_CTL_POSEL__P1                     ((uint16_t)0x0010)              /*!< Px = P1 */
2007 #define CAPTIO_CTL_POSEL__P2                     ((uint16_t)0x0020)              /*!< Px = P2 */
2008 #define CAPTIO_CTL_POSEL__P3                     ((uint16_t)0x0030)              /*!< Px = P3 */
2009 #define CAPTIO_CTL_POSEL__P4                     ((uint16_t)0x0040)              /*!< Px = P4 */
2010 #define CAPTIO_CTL_POSEL__P5                     ((uint16_t)0x0050)              /*!< Px = P5 */
2011 #define CAPTIO_CTL_POSEL__P6                     ((uint16_t)0x0060)              /*!< Px = P6 */
2012 #define CAPTIO_CTL_POSEL__P7                     ((uint16_t)0x0070)              /*!< Px = P7 */
2013 #define CAPTIO_CTL_POSEL__P8                     ((uint16_t)0x0080)              /*!< Px = P8 */
2014 #define CAPTIO_CTL_POSEL__P9                     ((uint16_t)0x0090)              /*!< Px = P9 */
2015 #define CAPTIO_CTL_POSEL__P10                    ((uint16_t)0x00A0)              /*!< Px = P10 */
2016 #define CAPTIO_CTL_POSEL__P11                    ((uint16_t)0x00B0)              /*!< Px = P11 */
2017 #define CAPTIO_CTL_POSEL__P12                    ((uint16_t)0x00C0)              /*!< Px = P12 */
2018 #define CAPTIO_CTL_POSEL__P13                    ((uint16_t)0x00D0)              /*!< Px = P13 */
2019 #define CAPTIO_CTL_POSEL__P14                    ((uint16_t)0x00E0)              /*!< Px = P14 */
2020 #define CAPTIO_CTL_POSEL__P15                    ((uint16_t)0x00F0)              /*!< Px = P15 */
2021 #define CAPTIO_CTL_EN_OFS                        ( 8)                            /*!< CAPTIOEN Bit Offset */
2022 #define CAPTIO_CTL_EN                            ((uint16_t)0x0100)              /*!< Capacitive Touch IO enable */
2023 #define CAPTIO_CTL_STATE_OFS                     ( 9)                            /*!< CAPTIOSTATE Bit Offset */
2024 #define CAPTIO_CTL_STATE                         ((uint16_t)0x0200)              /*!< Capacitive Touch IO state */
2025 #define COMP_E_CTL0_IPSEL_OFS                    ( 0)                            /*!< CEIPSEL Bit Offset */
2026 #define COMP_E_CTL0_IPSEL_MASK                   ((uint16_t)0x000F)              /*!< CEIPSEL Bit Mask */
2027 #define COMP_E_CTL0_IPSEL0                       ((uint16_t)0x0001)              /*!< IPSEL Bit 0 */
2028 #define COMP_E_CTL0_IPSEL1                       ((uint16_t)0x0002)              /*!< IPSEL Bit 1 */
2029 #define COMP_E_CTL0_IPSEL2                       ((uint16_t)0x0004)              /*!< IPSEL Bit 2 */
2030 #define COMP_E_CTL0_IPSEL3                       ((uint16_t)0x0008)              /*!< IPSEL Bit 3 */
2031 #define COMP_E_CTL0_IPSEL_0                      ((uint16_t)0x0000)              /*!< Channel 0 selected */
2032 #define COMP_E_CTL0_IPSEL_1                      ((uint16_t)0x0001)              /*!< Channel 1 selected */
2033 #define COMP_E_CTL0_IPSEL_2                      ((uint16_t)0x0002)              /*!< Channel 2 selected */
2034 #define COMP_E_CTL0_IPSEL_3                      ((uint16_t)0x0003)              /*!< Channel 3 selected */
2035 #define COMP_E_CTL0_IPSEL_4                      ((uint16_t)0x0004)              /*!< Channel 4 selected */
2036 #define COMP_E_CTL0_IPSEL_5                      ((uint16_t)0x0005)              /*!< Channel 5 selected */
2037 #define COMP_E_CTL0_IPSEL_6                      ((uint16_t)0x0006)              /*!< Channel 6 selected */
2038 #define COMP_E_CTL0_IPSEL_7                      ((uint16_t)0x0007)              /*!< Channel 7 selected */
2039 #define COMP_E_CTL0_IPSEL_8                      ((uint16_t)0x0008)              /*!< Channel 8 selected */
2040 #define COMP_E_CTL0_IPSEL_9                      ((uint16_t)0x0009)              /*!< Channel 9 selected */
2041 #define COMP_E_CTL0_IPSEL_10                     ((uint16_t)0x000A)              /*!< Channel 10 selected */
2042 #define COMP_E_CTL0_IPSEL_11                     ((uint16_t)0x000B)              /*!< Channel 11 selected */
2043 #define COMP_E_CTL0_IPSEL_12                     ((uint16_t)0x000C)              /*!< Channel 12 selected */
2044 #define COMP_E_CTL0_IPSEL_13                     ((uint16_t)0x000D)              /*!< Channel 13 selected */
2045 #define COMP_E_CTL0_IPSEL_14                     ((uint16_t)0x000E)              /*!< Channel 14 selected */
2046 #define COMP_E_CTL0_IPSEL_15                     ((uint16_t)0x000F)              /*!< Channel 15 selected */
2047 #define COMP_E_CTL0_IPEN_OFS                     ( 7)                            /*!< CEIPEN Bit Offset */
2048 #define COMP_E_CTL0_IPEN                         ((uint16_t)0x0080)              /*!< Channel input enable for the V+ terminal */
2049 #define COMP_E_CTL0_IMSEL_OFS                    ( 8)                            /*!< CEIMSEL Bit Offset */
2050 #define COMP_E_CTL0_IMSEL_MASK                   ((uint16_t)0x0F00)              /*!< CEIMSEL Bit Mask */
2051 #define COMP_E_CTL0_IMSEL0                       ((uint16_t)0x0100)              /*!< IMSEL Bit 0 */
2052 #define COMP_E_CTL0_IMSEL1                       ((uint16_t)0x0200)              /*!< IMSEL Bit 1 */
2053 #define COMP_E_CTL0_IMSEL2                       ((uint16_t)0x0400)              /*!< IMSEL Bit 2 */
2054 #define COMP_E_CTL0_IMSEL3                       ((uint16_t)0x0800)              /*!< IMSEL Bit 3 */
2055 #define COMP_E_CTL0_IMSEL_0                      ((uint16_t)0x0000)              /*!< Channel 0 selected */
2056 #define COMP_E_CTL0_IMSEL_1                      ((uint16_t)0x0100)              /*!< Channel 1 selected */
2057 #define COMP_E_CTL0_IMSEL_2                      ((uint16_t)0x0200)              /*!< Channel 2 selected */
2058 #define COMP_E_CTL0_IMSEL_3                      ((uint16_t)0x0300)              /*!< Channel 3 selected */
2059 #define COMP_E_CTL0_IMSEL_4                      ((uint16_t)0x0400)              /*!< Channel 4 selected */
2060 #define COMP_E_CTL0_IMSEL_5                      ((uint16_t)0x0500)              /*!< Channel 5 selected */
2061 #define COMP_E_CTL0_IMSEL_6                      ((uint16_t)0x0600)              /*!< Channel 6 selected */
2062 #define COMP_E_CTL0_IMSEL_7                      ((uint16_t)0x0700)              /*!< Channel 7 selected */
2063 #define COMP_E_CTL0_IMSEL_8                      ((uint16_t)0x0800)              /*!< Channel 8 selected */
2064 #define COMP_E_CTL0_IMSEL_9                      ((uint16_t)0x0900)              /*!< Channel 9 selected */
2065 #define COMP_E_CTL0_IMSEL_10                     ((uint16_t)0x0A00)              /*!< Channel 10 selected */
2066 #define COMP_E_CTL0_IMSEL_11                     ((uint16_t)0x0B00)              /*!< Channel 11 selected */
2067 #define COMP_E_CTL0_IMSEL_12                     ((uint16_t)0x0C00)              /*!< Channel 12 selected */
2068 #define COMP_E_CTL0_IMSEL_13                     ((uint16_t)0x0D00)              /*!< Channel 13 selected */
2069 #define COMP_E_CTL0_IMSEL_14                     ((uint16_t)0x0E00)              /*!< Channel 14 selected */
2070 #define COMP_E_CTL0_IMSEL_15                     ((uint16_t)0x0F00)              /*!< Channel 15 selected */
2071 #define COMP_E_CTL0_IMEN_OFS                     (15)                            /*!< CEIMEN Bit Offset */
2072 #define COMP_E_CTL0_IMEN                         ((uint16_t)0x8000)              /*!< Channel input enable for the - terminal */
2073 #define COMP_E_CTL1_OUT_OFS                      ( 0)                            /*!< CEOUT Bit Offset */
2074 #define COMP_E_CTL1_OUT                          ((uint16_t)0x0001)              /*!< Comparator output value */
2075 #define COMP_E_CTL1_OUTPOL_OFS                   ( 1)                            /*!< CEOUTPOL Bit Offset */
2076 #define COMP_E_CTL1_OUTPOL                       ((uint16_t)0x0002)              /*!< Comparator output polarity */
2077 #define COMP_E_CTL1_F_OFS                        ( 2)                            /*!< CEF Bit Offset */
2078 #define COMP_E_CTL1_F                            ((uint16_t)0x0004)              /*!< Comparator output filter */
2079 #define COMP_E_CTL1_IES_OFS                      ( 3)                            /*!< CEIES Bit Offset */
2080 #define COMP_E_CTL1_IES                          ((uint16_t)0x0008)              /*!< Interrupt edge select for CEIIFG and CEIFG */
2081 #define COMP_E_CTL1_SHORT_OFS                    ( 4)                            /*!< CESHORT Bit Offset */
2082 #define COMP_E_CTL1_SHORT                        ((uint16_t)0x0010)              /*!< Input short */
2083 #define COMP_E_CTL1_EX_OFS                       ( 5)                            /*!< CEEX Bit Offset */
2084 #define COMP_E_CTL1_EX                           ((uint16_t)0x0020)              /*!< Exchange */
2085 #define COMP_E_CTL1_FDLY_OFS                     ( 6)                            /*!< CEFDLY Bit Offset */
2086 #define COMP_E_CTL1_FDLY_MASK                    ((uint16_t)0x00C0)              /*!< CEFDLY Bit Mask */
2087 #define COMP_E_CTL1_FDLY0                        ((uint16_t)0x0040)              /*!< FDLY Bit 0 */
2088 #define COMP_E_CTL1_FDLY1                        ((uint16_t)0x0080)              /*!< FDLY Bit 1 */
2089 #define COMP_E_CTL1_FDLY_0                       ((uint16_t)0x0000)              /*!< Typical filter delay of TBD (450) ns */
2090 #define COMP_E_CTL1_FDLY_1                       ((uint16_t)0x0040)              /*!< Typical filter delay of TBD (900) ns */
2091 #define COMP_E_CTL1_FDLY_2                       ((uint16_t)0x0080)              /*!< Typical filter delay of TBD (1800) ns */
2092 #define COMP_E_CTL1_FDLY_3                       ((uint16_t)0x00C0)              /*!< Typical filter delay of TBD (3600) ns */
2093 #define COMP_E_CTL1_PWRMD_OFS                    ( 8)                            /*!< CEPWRMD Bit Offset */
2094 #define COMP_E_CTL1_PWRMD_MASK                   ((uint16_t)0x0300)              /*!< CEPWRMD Bit Mask */
2095 #define COMP_E_CTL1_PWRMD0                       ((uint16_t)0x0100)              /*!< PWRMD Bit 0 */
2096 #define COMP_E_CTL1_PWRMD1                       ((uint16_t)0x0200)              /*!< PWRMD Bit 1 */
2097 #define COMP_E_CTL1_PWRMD_0                      ((uint16_t)0x0000)              /*!< High-speed mode */
2098 #define COMP_E_CTL1_PWRMD_1                      ((uint16_t)0x0100)              /*!< Normal mode */
2099 #define COMP_E_CTL1_PWRMD_2                      ((uint16_t)0x0200)              /*!< Ultra-low power mode */
2100 #define COMP_E_CTL1_ON_OFS                       (10)                            /*!< CEON Bit Offset */
2101 #define COMP_E_CTL1_ON                           ((uint16_t)0x0400)              /*!< Comparator On */
2102 #define COMP_E_CTL1_MRVL_OFS                     (11)                            /*!< CEMRVL Bit Offset */
2103 #define COMP_E_CTL1_MRVL                         ((uint16_t)0x0800)              /*!< This bit is valid of CEMRVS is set to 1 */
2104 #define COMP_E_CTL1_MRVS_OFS                     (12)                            /*!< CEMRVS Bit Offset */
2105 #define COMP_E_CTL1_MRVS                         ((uint16_t)0x1000)
2106 #define COMP_E_CTL2_REF0_OFS                     ( 0)                            /*!< CEREF0 Bit Offset */
2107 #define COMP_E_CTL2_REF0_MASK                    ((uint16_t)0x001F)              /*!< CEREF0 Bit Mask */
2108 #define COMP_E_CTL2_REF00                        ((uint16_t)0x0001)              /*!< REF0 Bit 0 */
2109 #define COMP_E_CTL2_REF01                        ((uint16_t)0x0002)              /*!< REF0 Bit 1 */
2110 #define COMP_E_CTL2_REF02                        ((uint16_t)0x0004)              /*!< REF0 Bit 2 */
2111 #define COMP_E_CTL2_REF03                        ((uint16_t)0x0008)              /*!< REF0 Bit 3 */
2112 #define COMP_E_CTL2_REF04                        ((uint16_t)0x0010)              /*!< REF0 Bit 4 */
2113 #define COMP_E_CTL2_REF0_0                       ((uint16_t)0x0000)              /*!< Reference resistor tap for setting 0. */
2114 #define COMP_E_CTL2_REF0_1                       ((uint16_t)0x0001)              /*!< Reference resistor tap for setting 1. */
2115 #define COMP_E_CTL2_REF0_2                       ((uint16_t)0x0002)              /*!< Reference resistor tap for setting 2. */
2116 #define COMP_E_CTL2_REF0_3                       ((uint16_t)0x0003)              /*!< Reference resistor tap for setting 3. */
2117 #define COMP_E_CTL2_REF0_4                       ((uint16_t)0x0004)              /*!< Reference resistor tap for setting 4. */
2118 #define COMP_E_CTL2_REF0_5                       ((uint16_t)0x0005)              /*!< Reference resistor tap for setting 5. */
2119 #define COMP_E_CTL2_REF0_6                       ((uint16_t)0x0006)              /*!< Reference resistor tap for setting 6. */
2120 #define COMP_E_CTL2_REF0_7                       ((uint16_t)0x0007)              /*!< Reference resistor tap for setting 7. */
2121 #define COMP_E_CTL2_REF0_8                       ((uint16_t)0x0008)              /*!< Reference resistor tap for setting 8. */
2122 #define COMP_E_CTL2_REF0_9                       ((uint16_t)0x0009)              /*!< Reference resistor tap for setting 9. */
2123 #define COMP_E_CTL2_REF0_10                      ((uint16_t)0x000A)              /*!< Reference resistor tap for setting 10. */
2124 #define COMP_E_CTL2_REF0_11                      ((uint16_t)0x000B)              /*!< Reference resistor tap for setting 11. */
2125 #define COMP_E_CTL2_REF0_12                      ((uint16_t)0x000C)              /*!< Reference resistor tap for setting 12. */
2126 #define COMP_E_CTL2_REF0_13                      ((uint16_t)0x000D)              /*!< Reference resistor tap for setting 13. */
2127 #define COMP_E_CTL2_REF0_14                      ((uint16_t)0x000E)              /*!< Reference resistor tap for setting 14. */
2128 #define COMP_E_CTL2_REF0_15                      ((uint16_t)0x000F)              /*!< Reference resistor tap for setting 15. */
2129 #define COMP_E_CTL2_REF0_16                      ((uint16_t)0x0010)              /*!< Reference resistor tap for setting 16. */
2130 #define COMP_E_CTL2_REF0_17                      ((uint16_t)0x0011)              /*!< Reference resistor tap for setting 17. */
2131 #define COMP_E_CTL2_REF0_18                      ((uint16_t)0x0012)              /*!< Reference resistor tap for setting 18. */
2132 #define COMP_E_CTL2_REF0_19                      ((uint16_t)0x0013)              /*!< Reference resistor tap for setting 19. */
2133 #define COMP_E_CTL2_REF0_20                      ((uint16_t)0x0014)              /*!< Reference resistor tap for setting 20. */
2134 #define COMP_E_CTL2_REF0_21                      ((uint16_t)0x0015)              /*!< Reference resistor tap for setting 21. */
2135 #define COMP_E_CTL2_REF0_22                      ((uint16_t)0x0016)              /*!< Reference resistor tap for setting 22. */
2136 #define COMP_E_CTL2_REF0_23                      ((uint16_t)0x0017)              /*!< Reference resistor tap for setting 23. */
2137 #define COMP_E_CTL2_REF0_24                      ((uint16_t)0x0018)              /*!< Reference resistor tap for setting 24. */
2138 #define COMP_E_CTL2_REF0_25                      ((uint16_t)0x0019)              /*!< Reference resistor tap for setting 25. */
2139 #define COMP_E_CTL2_REF0_26                      ((uint16_t)0x001A)              /*!< Reference resistor tap for setting 26. */
2140 #define COMP_E_CTL2_REF0_27                      ((uint16_t)0x001B)              /*!< Reference resistor tap for setting 27. */
2141 #define COMP_E_CTL2_REF0_28                      ((uint16_t)0x001C)              /*!< Reference resistor tap for setting 28. */
2142 #define COMP_E_CTL2_REF0_29                      ((uint16_t)0x001D)              /*!< Reference resistor tap for setting 29. */
2143 #define COMP_E_CTL2_REF0_30                      ((uint16_t)0x001E)              /*!< Reference resistor tap for setting 30. */
2144 #define COMP_E_CTL2_REF0_31                      ((uint16_t)0x001F)              /*!< Reference resistor tap for setting 31. */
2145 #define COMP_E_CTL2_RSEL_OFS                     ( 5)                            /*!< CERSEL Bit Offset */
2146 #define COMP_E_CTL2_RSEL                         ((uint16_t)0x0020)              /*!< Reference select */
2147 #define COMP_E_CTL2_RS_OFS                       ( 6)                            /*!< CERS Bit Offset */
2148 #define COMP_E_CTL2_RS_MASK                      ((uint16_t)0x00C0)              /*!< CERS Bit Mask */
2149 #define COMP_E_CTL2_RS0                          ((uint16_t)0x0040)              /*!< RS Bit 0 */
2150 #define COMP_E_CTL2_RS1                          ((uint16_t)0x0080)              /*!< RS Bit 1 */
2151 #define COMP_E_CTL2_RS_0                         ((uint16_t)0x0000)              /*!< No current is drawn by the reference circuitry */
2152 #define COMP_E_CTL2_RS_1                         ((uint16_t)0x0040)              /*!< VCC applied to the resistor ladder */
2153 #define COMP_E_CTL2_RS_2                         ((uint16_t)0x0080)              /*!< Shared reference voltage applied to the resistor ladder */
2154 #define COMP_E_CTL2_RS_3                         ((uint16_t)0x00C0)              /*!< Shared reference voltage supplied to V(CREF). Resistor ladder is off */
2155 #define COMP_E_CTL2_REF1_OFS                     ( 8)                            /*!< CEREF1 Bit Offset */
2156 #define COMP_E_CTL2_REF1_MASK                    ((uint16_t)0x1F00)              /*!< CEREF1 Bit Mask */
2157 #define COMP_E_CTL2_REF10                        ((uint16_t)0x0100)              /*!< REF1 Bit 0 */
2158 #define COMP_E_CTL2_REF11                        ((uint16_t)0x0200)              /*!< REF1 Bit 1 */
2159 #define COMP_E_CTL2_REF12                        ((uint16_t)0x0400)              /*!< REF1 Bit 2 */
2160 #define COMP_E_CTL2_REF13                        ((uint16_t)0x0800)              /*!< REF1 Bit 3 */
2161 #define COMP_E_CTL2_REF14                        ((uint16_t)0x1000)              /*!< REF1 Bit 4 */
2162 #define COMP_E_CTL2_REF1_0                       ((uint16_t)0x0000)              /*!< Reference resistor tap for setting 0. */
2163 #define COMP_E_CTL2_REF1_1                       ((uint16_t)0x0100)              /*!< Reference resistor tap for setting 1. */
2164 #define COMP_E_CTL2_REF1_2                       ((uint16_t)0x0200)              /*!< Reference resistor tap for setting 2. */
2165 #define COMP_E_CTL2_REF1_3                       ((uint16_t)0x0300)              /*!< Reference resistor tap for setting 3. */
2166 #define COMP_E_CTL2_REF1_4                       ((uint16_t)0x0400)              /*!< Reference resistor tap for setting 4. */
2167 #define COMP_E_CTL2_REF1_5                       ((uint16_t)0x0500)              /*!< Reference resistor tap for setting 5. */
2168 #define COMP_E_CTL2_REF1_6                       ((uint16_t)0x0600)              /*!< Reference resistor tap for setting 6. */
2169 #define COMP_E_CTL2_REF1_7                       ((uint16_t)0x0700)              /*!< Reference resistor tap for setting 7. */
2170 #define COMP_E_CTL2_REF1_8                       ((uint16_t)0x0800)              /*!< Reference resistor tap for setting 8. */
2171 #define COMP_E_CTL2_REF1_9                       ((uint16_t)0x0900)              /*!< Reference resistor tap for setting 9. */
2172 #define COMP_E_CTL2_REF1_10                      ((uint16_t)0x0A00)              /*!< Reference resistor tap for setting 10. */
2173 #define COMP_E_CTL2_REF1_11                      ((uint16_t)0x0B00)              /*!< Reference resistor tap for setting 11. */
2174 #define COMP_E_CTL2_REF1_12                      ((uint16_t)0x0C00)              /*!< Reference resistor tap for setting 12. */
2175 #define COMP_E_CTL2_REF1_13                      ((uint16_t)0x0D00)              /*!< Reference resistor tap for setting 13. */
2176 #define COMP_E_CTL2_REF1_14                      ((uint16_t)0x0E00)              /*!< Reference resistor tap for setting 14. */
2177 #define COMP_E_CTL2_REF1_15                      ((uint16_t)0x0F00)              /*!< Reference resistor tap for setting 15. */
2178 #define COMP_E_CTL2_REF1_16                      ((uint16_t)0x1000)              /*!< Reference resistor tap for setting 16. */
2179 #define COMP_E_CTL2_REF1_17                      ((uint16_t)0x1100)              /*!< Reference resistor tap for setting 17. */
2180 #define COMP_E_CTL2_REF1_18                      ((uint16_t)0x1200)              /*!< Reference resistor tap for setting 18. */
2181 #define COMP_E_CTL2_REF1_19                      ((uint16_t)0x1300)              /*!< Reference resistor tap for setting 19. */
2182 #define COMP_E_CTL2_REF1_20                      ((uint16_t)0x1400)              /*!< Reference resistor tap for setting 20. */
2183 #define COMP_E_CTL2_REF1_21                      ((uint16_t)0x1500)              /*!< Reference resistor tap for setting 21. */
2184 #define COMP_E_CTL2_REF1_22                      ((uint16_t)0x1600)              /*!< Reference resistor tap for setting 22. */
2185 #define COMP_E_CTL2_REF1_23                      ((uint16_t)0x1700)              /*!< Reference resistor tap for setting 23. */
2186 #define COMP_E_CTL2_REF1_24                      ((uint16_t)0x1800)              /*!< Reference resistor tap for setting 24. */
2187 #define COMP_E_CTL2_REF1_25                      ((uint16_t)0x1900)              /*!< Reference resistor tap for setting 25. */
2188 #define COMP_E_CTL2_REF1_26                      ((uint16_t)0x1A00)              /*!< Reference resistor tap for setting 26. */
2189 #define COMP_E_CTL2_REF1_27                      ((uint16_t)0x1B00)              /*!< Reference resistor tap for setting 27. */
2190 #define COMP_E_CTL2_REF1_28                      ((uint16_t)0x1C00)              /*!< Reference resistor tap for setting 28. */
2191 #define COMP_E_CTL2_REF1_29                      ((uint16_t)0x1D00)              /*!< Reference resistor tap for setting 29. */
2192 #define COMP_E_CTL2_REF1_30                      ((uint16_t)0x1E00)              /*!< Reference resistor tap for setting 30. */
2193 #define COMP_E_CTL2_REF1_31                      ((uint16_t)0x1F00)              /*!< Reference resistor tap for setting 31. */
2194 #define COMP_E_CTL2_REFL_OFS                     (13)                            /*!< CEREFL Bit Offset */
2195 #define COMP_E_CTL2_REFL_MASK                    ((uint16_t)0x6000)              /*!< CEREFL Bit Mask */
2196 #define COMP_E_CTL2_REFL0                        ((uint16_t)0x2000)              /*!< REFL Bit 0 */
2197 #define COMP_E_CTL2_REFL1                        ((uint16_t)0x4000)              /*!< REFL Bit 1 */
2198 #define COMP_E_CTL2_CEREFL_0                     ((uint16_t)0x0000)              /*!< Reference amplifier is disabled. No reference voltage is requested */
2199 #define COMP_E_CTL2_CEREFL_1                     ((uint16_t)0x2000)              /*!< 1.2 V is selected as shared reference voltage input */
2200 #define COMP_E_CTL2_CEREFL_2                     ((uint16_t)0x4000)              /*!< 2.0 V is selected as shared reference voltage input */
2201 #define COMP_E_CTL2_CEREFL_3                     ((uint16_t)0x6000)              /*!< 2.5 V is selected as shared reference voltage input */
2202 #define COMP_E_CTL2_REFL__OFF                    ((uint16_t)0x0000)              /*!< Reference amplifier is disabled. No reference voltage is requested */
2203 #define COMP_E_CTL2_REFL__1P2V                   ((uint16_t)0x2000)              /*!< 1.2 V is selected as shared reference voltage input */
2204 #define COMP_E_CTL2_REFL__2P0V                   ((uint16_t)0x4000)              /*!< 2.0 V is selected as shared reference voltage input */
2205 #define COMP_E_CTL2_REFL__2P5V                   ((uint16_t)0x6000)              /*!< 2.5 V is selected as shared reference voltage input */
2206 #define COMP_E_CTL2_REFACC_OFS                   (15)                            /*!< CEREFACC Bit Offset */
2207 #define COMP_E_CTL2_REFACC                       ((uint16_t)0x8000)              /*!< Reference accuracy */
2208 #define COMP_E_CTL3_PD0_OFS                      ( 0)                            /*!< CEPD0 Bit Offset */
2209 #define COMP_E_CTL3_PD0                          ((uint16_t)0x0001)              /*!< Port disable */
2210 #define COMP_E_CTL3_PD1_OFS                      ( 1)                            /*!< CEPD1 Bit Offset */
2211 #define COMP_E_CTL3_PD1                          ((uint16_t)0x0002)              /*!< Port disable */
2212 #define COMP_E_CTL3_PD2_OFS                      ( 2)                            /*!< CEPD2 Bit Offset */
2213 #define COMP_E_CTL3_PD2                          ((uint16_t)0x0004)              /*!< Port disable */
2214 #define COMP_E_CTL3_PD3_OFS                      ( 3)                            /*!< CEPD3 Bit Offset */
2215 #define COMP_E_CTL3_PD3                          ((uint16_t)0x0008)              /*!< Port disable */
2216 #define COMP_E_CTL3_PD4_OFS                      ( 4)                            /*!< CEPD4 Bit Offset */
2217 #define COMP_E_CTL3_PD4                          ((uint16_t)0x0010)              /*!< Port disable */
2218 #define COMP_E_CTL3_PD5_OFS                      ( 5)                            /*!< CEPD5 Bit Offset */
2219 #define COMP_E_CTL3_PD5                          ((uint16_t)0x0020)              /*!< Port disable */
2220 #define COMP_E_CTL3_PD6_OFS                      ( 6)                            /*!< CEPD6 Bit Offset */
2221 #define COMP_E_CTL3_PD6                          ((uint16_t)0x0040)              /*!< Port disable */
2222 #define COMP_E_CTL3_PD7_OFS                      ( 7)                            /*!< CEPD7 Bit Offset */
2223 #define COMP_E_CTL3_PD7                          ((uint16_t)0x0080)              /*!< Port disable */
2224 #define COMP_E_CTL3_PD8_OFS                      ( 8)                            /*!< CEPD8 Bit Offset */
2225 #define COMP_E_CTL3_PD8                          ((uint16_t)0x0100)              /*!< Port disable */
2226 #define COMP_E_CTL3_PD9_OFS                      ( 9)                            /*!< CEPD9 Bit Offset */
2227 #define COMP_E_CTL3_PD9                          ((uint16_t)0x0200)              /*!< Port disable */
2228 #define COMP_E_CTL3_PD10_OFS                     (10)                            /*!< CEPD10 Bit Offset */
2229 #define COMP_E_CTL3_PD10                         ((uint16_t)0x0400)              /*!< Port disable */
2230 #define COMP_E_CTL3_PD11_OFS                     (11)                            /*!< CEPD11 Bit Offset */
2231 #define COMP_E_CTL3_PD11                         ((uint16_t)0x0800)              /*!< Port disable */
2232 #define COMP_E_CTL3_PD12_OFS                     (12)                            /*!< CEPD12 Bit Offset */
2233 #define COMP_E_CTL3_PD12                         ((uint16_t)0x1000)              /*!< Port disable */
2234 #define COMP_E_CTL3_PD13_OFS                     (13)                            /*!< CEPD13 Bit Offset */
2235 #define COMP_E_CTL3_PD13                         ((uint16_t)0x2000)              /*!< Port disable */
2236 #define COMP_E_CTL3_PD14_OFS                     (14)                            /*!< CEPD14 Bit Offset */
2237 #define COMP_E_CTL3_PD14                         ((uint16_t)0x4000)              /*!< Port disable */
2238 #define COMP_E_CTL3_PD15_OFS                     (15)                            /*!< CEPD15 Bit Offset */
2239 #define COMP_E_CTL3_PD15                         ((uint16_t)0x8000)              /*!< Port disable */
2240 #define COMP_E_INT_IFG_OFS                       ( 0)                            /*!< CEIFG Bit Offset */
2241 #define COMP_E_INT_IFG                           ((uint16_t)0x0001)              /*!< Comparator output interrupt flag */
2242 #define COMP_E_INT_IIFG_OFS                      ( 1)                            /*!< CEIIFG Bit Offset */
2243 #define COMP_E_INT_IIFG                          ((uint16_t)0x0002)              /*!< Comparator output inverted interrupt flag */
2244 #define COMP_E_INT_RDYIFG_OFS                    ( 4)                            /*!< CERDYIFG Bit Offset */
2245 #define COMP_E_INT_RDYIFG                        ((uint16_t)0x0010)              /*!< Comparator ready interrupt flag */
2246 #define COMP_E_INT_IE_OFS                        ( 8)                            /*!< CEIE Bit Offset */
2247 #define COMP_E_INT_IE                            ((uint16_t)0x0100)              /*!< Comparator output interrupt enable */
2248 #define COMP_E_INT_IIE_OFS                       ( 9)                            /*!< CEIIE Bit Offset */
2249 #define COMP_E_INT_IIE                           ((uint16_t)0x0200)              /*!< Comparator output interrupt enable inverted polarity */
2250 #define COMP_E_INT_RDYIE_OFS                     (12)                            /*!< CERDYIE Bit Offset */
2251 #define COMP_E_INT_RDYIE                         ((uint16_t)0x1000)              /*!< Comparator ready interrupt enable */
2252 #define CS_KEY_KEY_OFS                           ( 0)                            /*!< CSKEY Bit Offset */
2253 #define CS_KEY_KEY_MASK                          ((uint32_t)0x0000FFFF)          /*!< CSKEY Bit Mask */
2254 #define CS_CTL0_DCOTUNE_OFS                      ( 0)                            /*!< DCOTUNE Bit Offset */
2255 #define CS_CTL0_DCOTUNE_MASK                     ((uint32_t)0x000003FF)          /*!< DCOTUNE Bit Mask */
2256 #define CS_CTL0_DCORSEL_OFS                      (16)                            /*!< DCORSEL Bit Offset */
2257 #define CS_CTL0_DCORSEL_MASK                     ((uint32_t)0x00070000)          /*!< DCORSEL Bit Mask */
2258 #define CS_CTL0_DCORSEL0                         ((uint32_t)0x00010000)          /*!< DCORSEL Bit 0 */
2259 #define CS_CTL0_DCORSEL1                         ((uint32_t)0x00020000)          /*!< DCORSEL Bit 1 */
2260 #define CS_CTL0_DCORSEL2                         ((uint32_t)0x00040000)          /*!< DCORSEL Bit 2 */
2261 #define CS_CTL0_DCORSEL_0                        ((uint32_t)0x00000000)          /*!< Nominal DCO Frequency Range (MHz): 1 to 2 */
2262 #define CS_CTL0_DCORSEL_1                        ((uint32_t)0x00010000)          /*!< Nominal DCO Frequency Range (MHz): 2 to 4 */
2263 #define CS_CTL0_DCORSEL_2                        ((uint32_t)0x00020000)          /*!< Nominal DCO Frequency Range (MHz): 4 to 8 */
2264 #define CS_CTL0_DCORSEL_3                        ((uint32_t)0x00030000)          /*!< Nominal DCO Frequency Range (MHz): 8 to 16 */
2265 #define CS_CTL0_DCORSEL_4                        ((uint32_t)0x00040000)          /*!< Nominal DCO Frequency Range (MHz): 16 to 32 */
2266 #define CS_CTL0_DCORSEL_5                        ((uint32_t)0x00050000)          /*!< Nominal DCO Frequency Range (MHz): 32 to 64 */
2267 #define CS_CTL0_DCORES_OFS                       (22)                            /*!< DCORES Bit Offset */
2268 #define CS_CTL0_DCORES                           ((uint32_t)0x00400000)          /*!< Enables the DCO external resistor mode */
2269 #define CS_CTL0_DCOEN_OFS                        (23)                            /*!< DCOEN Bit Offset */
2270 #define CS_CTL0_DCOEN                            ((uint32_t)0x00800000)          /*!< Enables the DCO oscillator */
2271 #define CS_CTL1_SELM_OFS                         ( 0)                            /*!< SELM Bit Offset */
2272 #define CS_CTL1_SELM_MASK                        ((uint32_t)0x00000007)          /*!< SELM Bit Mask */
2273 #define CS_CTL1_SELM0                            ((uint32_t)0x00000001)          /*!< SELM Bit 0 */
2274 #define CS_CTL1_SELM1                            ((uint32_t)0x00000002)          /*!< SELM Bit 1 */
2275 #define CS_CTL1_SELM2                            ((uint32_t)0x00000004)          /*!< SELM Bit 2 */
2276 #define CS_CTL1_SELM_0                           ((uint32_t)0x00000000)          /*!< when LFXT available, otherwise REFOCLK */
2277 #define CS_CTL1_SELM_1                           ((uint32_t)0x00000001)
2278 #define CS_CTL1_SELM_2                           ((uint32_t)0x00000002)
2279 #define CS_CTL1_SELM_3                           ((uint32_t)0x00000003)
2280 #define CS_CTL1_SELM_4                           ((uint32_t)0x00000004)
2281 #define CS_CTL1_SELM_5                           ((uint32_t)0x00000005)          /*!< when HFXT available, otherwise DCOCLK */
2282 #define CS_CTL1_SELM_6                           ((uint32_t)0x00000006)          /*!< when HFXT2 available, otherwise DCOCLK */
2283 #define CS_CTL1_SELM__LFXTCLK                    ((uint32_t)0x00000000)          /*!< when LFXT available, otherwise REFOCLK */
2284 #define CS_CTL1_SELM__VLOCLK                     ((uint32_t)0x00000001)
2285 #define CS_CTL1_SELM__REFOCLK                    ((uint32_t)0x00000002)
2286 #define CS_CTL1_SELM__DCOCLK                     ((uint32_t)0x00000003)
2287 #define CS_CTL1_SELM__MODOSC                     ((uint32_t)0x00000004)
2288 #define CS_CTL1_SELM__HFXTCLK                    ((uint32_t)0x00000005)          /*!< when HFXT available, otherwise DCOCLK */
2289 #define CS_CTL1_SELM__HFXT2CLK                   ((uint32_t)0x00000006)          /*!< when HFXT2 available, otherwise DCOCLK */
2290 #define CS_CTL1_SELS_OFS                         ( 4)                            /*!< SELS Bit Offset */
2291 #define CS_CTL1_SELS_MASK                        ((uint32_t)0x00000070)          /*!< SELS Bit Mask */
2292 #define CS_CTL1_SELS0                            ((uint32_t)0x00000010)          /*!< SELS Bit 0 */
2293 #define CS_CTL1_SELS1                            ((uint32_t)0x00000020)          /*!< SELS Bit 1 */
2294 #define CS_CTL1_SELS2                            ((uint32_t)0x00000040)          /*!< SELS Bit 2 */
2295 #define CS_CTL1_SELS_0                           ((uint32_t)0x00000000)          /*!< when LFXT available, otherwise REFOCLK */
2296 #define CS_CTL1_SELS_1                           ((uint32_t)0x00000010)
2297 #define CS_CTL1_SELS_2                           ((uint32_t)0x00000020)
2298 #define CS_CTL1_SELS_3                           ((uint32_t)0x00000030)
2299 #define CS_CTL1_SELS_4                           ((uint32_t)0x00000040)
2300 #define CS_CTL1_SELS_5                           ((uint32_t)0x00000050)          /*!< when HFXT available, otherwise DCOCLK */
2301 #define CS_CTL1_SELS_6                           ((uint32_t)0x00000060)          /*!< when HFXT2 available, otherwise DCOCLK */
2302 #define CS_CTL1_SELS__LFXTCLK                    ((uint32_t)0x00000000)          /*!< when LFXT available, otherwise REFOCLK */
2303 #define CS_CTL1_SELS__VLOCLK                     ((uint32_t)0x00000010)
2304 #define CS_CTL1_SELS__REFOCLK                    ((uint32_t)0x00000020)
2305 #define CS_CTL1_SELS__DCOCLK                     ((uint32_t)0x00000030)
2306 #define CS_CTL1_SELS__MODOSC                     ((uint32_t)0x00000040)
2307 #define CS_CTL1_SELS__HFXTCLK                    ((uint32_t)0x00000050)          /*!< when HFXT available, otherwise DCOCLK */
2308 #define CS_CTL1_SELS__HFXT2CLK                   ((uint32_t)0x00000060)          /*!< when HFXT2 available, otherwise DCOCLK */
2309 #define CS_CTL1_SELA_OFS                         ( 8)                            /*!< SELA Bit Offset */
2310 #define CS_CTL1_SELA_MASK                        ((uint32_t)0x00000700)          /*!< SELA Bit Mask */
2311 #define CS_CTL1_SELA0                            ((uint32_t)0x00000100)          /*!< SELA Bit 0 */
2312 #define CS_CTL1_SELA1                            ((uint32_t)0x00000200)          /*!< SELA Bit 1 */
2313 #define CS_CTL1_SELA2                            ((uint32_t)0x00000400)          /*!< SELA Bit 2 */
2314 #define CS_CTL1_SELA_0                           ((uint32_t)0x00000000)          /*!< when LFXT available, otherwise REFOCLK */
2315 #define CS_CTL1_SELA_1                           ((uint32_t)0x00000100)
2316 #define CS_CTL1_SELA_2                           ((uint32_t)0x00000200)
2317 #define CS_CTL1_SELA__LFXTCLK                    ((uint32_t)0x00000000)          /*!< when LFXT available, otherwise REFOCLK */
2318 #define CS_CTL1_SELA__VLOCLK                     ((uint32_t)0x00000100)
2319 #define CS_CTL1_SELA__REFOCLK                    ((uint32_t)0x00000200)
2320 #define CS_CTL1_SELB_OFS                         (12)                            /*!< SELB Bit Offset */
2321 #define CS_CTL1_SELB                             ((uint32_t)0x00001000)          /*!< Selects the BCLK source */
2322 #define CS_CTL1_DIVM_OFS                         (16)                            /*!< DIVM Bit Offset */
2323 #define CS_CTL1_DIVM_MASK                        ((uint32_t)0x00070000)          /*!< DIVM Bit Mask */
2324 #define CS_CTL1_DIVM0                            ((uint32_t)0x00010000)          /*!< DIVM Bit 0 */
2325 #define CS_CTL1_DIVM1                            ((uint32_t)0x00020000)          /*!< DIVM Bit 1 */
2326 #define CS_CTL1_DIVM2                            ((uint32_t)0x00040000)          /*!< DIVM Bit 2 */
2327 #define CS_CTL1_DIVM_0                           ((uint32_t)0x00000000)          /*!< f(MCLK)/1 */
2328 #define CS_CTL1_DIVM_1                           ((uint32_t)0x00010000)          /*!< f(MCLK)/2 */
2329 #define CS_CTL1_DIVM_2                           ((uint32_t)0x00020000)          /*!< f(MCLK)/4 */
2330 #define CS_CTL1_DIVM_3                           ((uint32_t)0x00030000)          /*!< f(MCLK)/8 */
2331 #define CS_CTL1_DIVM_4                           ((uint32_t)0x00040000)          /*!< f(MCLK)/16 */
2332 #define CS_CTL1_DIVM_5                           ((uint32_t)0x00050000)          /*!< f(MCLK)/32 */
2333 #define CS_CTL1_DIVM_6                           ((uint32_t)0x00060000)          /*!< f(MCLK)/64 */
2334 #define CS_CTL1_DIVM_7                           ((uint32_t)0x00070000)          /*!< f(MCLK)/128 */
2335 #define CS_CTL1_DIVM__1                          ((uint32_t)0x00000000)          /*!< f(MCLK)/1 */
2336 #define CS_CTL1_DIVM__2                          ((uint32_t)0x00010000)          /*!< f(MCLK)/2 */
2337 #define CS_CTL1_DIVM__4                          ((uint32_t)0x00020000)          /*!< f(MCLK)/4 */
2338 #define CS_CTL1_DIVM__8                          ((uint32_t)0x00030000)          /*!< f(MCLK)/8 */
2339 #define CS_CTL1_DIVM__16                         ((uint32_t)0x00040000)          /*!< f(MCLK)/16 */
2340 #define CS_CTL1_DIVM__32                         ((uint32_t)0x00050000)          /*!< f(MCLK)/32 */
2341 #define CS_CTL1_DIVM__64                         ((uint32_t)0x00060000)          /*!< f(MCLK)/64 */
2342 #define CS_CTL1_DIVM__128                        ((uint32_t)0x00070000)          /*!< f(MCLK)/128 */
2343 #define CS_CTL1_DIVHS_OFS                        (20)                            /*!< DIVHS Bit Offset */
2344 #define CS_CTL1_DIVHS_MASK                       ((uint32_t)0x00700000)          /*!< DIVHS Bit Mask */
2345 #define CS_CTL1_DIVHS0                           ((uint32_t)0x00100000)          /*!< DIVHS Bit 0 */
2346 #define CS_CTL1_DIVHS1                           ((uint32_t)0x00200000)          /*!< DIVHS Bit 1 */
2347 #define CS_CTL1_DIVHS2                           ((uint32_t)0x00400000)          /*!< DIVHS Bit 2 */
2348 #define CS_CTL1_DIVHS_0                          ((uint32_t)0x00000000)          /*!< f(HSMCLK)/1 */
2349 #define CS_CTL1_DIVHS_1                          ((uint32_t)0x00100000)          /*!< f(HSMCLK)/2 */
2350 #define CS_CTL1_DIVHS_2                          ((uint32_t)0x00200000)          /*!< f(HSMCLK)/4 */
2351 #define CS_CTL1_DIVHS_3                          ((uint32_t)0x00300000)          /*!< f(HSMCLK)/8 */
2352 #define CS_CTL1_DIVHS_4                          ((uint32_t)0x00400000)          /*!< f(HSMCLK)/16 */
2353 #define CS_CTL1_DIVHS_5                          ((uint32_t)0x00500000)          /*!< f(HSMCLK)/32 */
2354 #define CS_CTL1_DIVHS_6                          ((uint32_t)0x00600000)          /*!< f(HSMCLK)/64 */
2355 #define CS_CTL1_DIVHS_7                          ((uint32_t)0x00700000)          /*!< f(HSMCLK)/128 */
2356 #define CS_CTL1_DIVHS__1                         ((uint32_t)0x00000000)          /*!< f(HSMCLK)/1 */
2357 #define CS_CTL1_DIVHS__2                         ((uint32_t)0x00100000)          /*!< f(HSMCLK)/2 */
2358 #define CS_CTL1_DIVHS__4                         ((uint32_t)0x00200000)          /*!< f(HSMCLK)/4 */
2359 #define CS_CTL1_DIVHS__8                         ((uint32_t)0x00300000)          /*!< f(HSMCLK)/8 */
2360 #define CS_CTL1_DIVHS__16                        ((uint32_t)0x00400000)          /*!< f(HSMCLK)/16 */
2361 #define CS_CTL1_DIVHS__32                        ((uint32_t)0x00500000)          /*!< f(HSMCLK)/32 */
2362 #define CS_CTL1_DIVHS__64                        ((uint32_t)0x00600000)          /*!< f(HSMCLK)/64 */
2363 #define CS_CTL1_DIVHS__128                       ((uint32_t)0x00700000)          /*!< f(HSMCLK)/128 */
2364 #define CS_CTL1_DIVA_OFS                         (24)                            /*!< DIVA Bit Offset */
2365 #define CS_CTL1_DIVA_MASK                        ((uint32_t)0x07000000)          /*!< DIVA Bit Mask */
2366 #define CS_CTL1_DIVA0                            ((uint32_t)0x01000000)          /*!< DIVA Bit 0 */
2367 #define CS_CTL1_DIVA1                            ((uint32_t)0x02000000)          /*!< DIVA Bit 1 */
2368 #define CS_CTL1_DIVA2                            ((uint32_t)0x04000000)          /*!< DIVA Bit 2 */
2369 #define CS_CTL1_DIVA_0                           ((uint32_t)0x00000000)          /*!< f(ACLK)/1 */
2370 #define CS_CTL1_DIVA_1                           ((uint32_t)0x01000000)          /*!< f(ACLK)/2 */
2371 #define CS_CTL1_DIVA_2                           ((uint32_t)0x02000000)          /*!< f(ACLK)/4 */
2372 #define CS_CTL1_DIVA_3                           ((uint32_t)0x03000000)          /*!< f(ACLK)/8 */
2373 #define CS_CTL1_DIVA_4                           ((uint32_t)0x04000000)          /*!< f(ACLK)/16 */
2374 #define CS_CTL1_DIVA_5                           ((uint32_t)0x05000000)          /*!< f(ACLK)/32 */
2375 #define CS_CTL1_DIVA_6                           ((uint32_t)0x06000000)          /*!< f(ACLK)/64 */
2376 #define CS_CTL1_DIVA_7                           ((uint32_t)0x07000000)          /*!< f(ACLK)/128 */
2377 #define CS_CTL1_DIVA__1                          ((uint32_t)0x00000000)          /*!< f(ACLK)/1 */
2378 #define CS_CTL1_DIVA__2                          ((uint32_t)0x01000000)          /*!< f(ACLK)/2 */
2379 #define CS_CTL1_DIVA__4                          ((uint32_t)0x02000000)          /*!< f(ACLK)/4 */
2380 #define CS_CTL1_DIVA__8                          ((uint32_t)0x03000000)          /*!< f(ACLK)/8 */
2381 #define CS_CTL1_DIVA__16                         ((uint32_t)0x04000000)          /*!< f(ACLK)/16 */
2382 #define CS_CTL1_DIVA__32                         ((uint32_t)0x05000000)          /*!< f(ACLK)/32 */
2383 #define CS_CTL1_DIVA__64                         ((uint32_t)0x06000000)          /*!< f(ACLK)/64 */
2384 #define CS_CTL1_DIVA__128                        ((uint32_t)0x07000000)          /*!< f(ACLK)/128 */
2385 #define CS_CTL1_DIVS_OFS                         (28)                            /*!< DIVS Bit Offset */
2386 #define CS_CTL1_DIVS_MASK                        ((uint32_t)0x70000000)          /*!< DIVS Bit Mask */
2387 #define CS_CTL1_DIVS0                            ((uint32_t)0x10000000)          /*!< DIVS Bit 0 */
2388 #define CS_CTL1_DIVS1                            ((uint32_t)0x20000000)          /*!< DIVS Bit 1 */
2389 #define CS_CTL1_DIVS2                            ((uint32_t)0x40000000)          /*!< DIVS Bit 2 */
2390 #define CS_CTL1_DIVS_0                           ((uint32_t)0x00000000)          /*!< f(SMCLK)/1 */
2391 #define CS_CTL1_DIVS_1                           ((uint32_t)0x10000000)          /*!< f(SMCLK)/2 */
2392 #define CS_CTL1_DIVS_2                           ((uint32_t)0x20000000)          /*!< f(SMCLK)/4 */
2393 #define CS_CTL1_DIVS_3                           ((uint32_t)0x30000000)          /*!< f(SMCLK)/8 */
2394 #define CS_CTL1_DIVS_4                           ((uint32_t)0x40000000)          /*!< f(SMCLK)/16 */
2395 #define CS_CTL1_DIVS_5                           ((uint32_t)0x50000000)          /*!< f(SMCLK)/32 */
2396 #define CS_CTL1_DIVS_6                           ((uint32_t)0x60000000)          /*!< f(SMCLK)/64 */
2397 #define CS_CTL1_DIVS_7                           ((uint32_t)0x70000000)          /*!< f(SMCLK)/128 */
2398 #define CS_CTL1_DIVS__1                          ((uint32_t)0x00000000)          /*!< f(SMCLK)/1 */
2399 #define CS_CTL1_DIVS__2                          ((uint32_t)0x10000000)          /*!< f(SMCLK)/2 */
2400 #define CS_CTL1_DIVS__4                          ((uint32_t)0x20000000)          /*!< f(SMCLK)/4 */
2401 #define CS_CTL1_DIVS__8                          ((uint32_t)0x30000000)          /*!< f(SMCLK)/8 */
2402 #define CS_CTL1_DIVS__16                         ((uint32_t)0x40000000)          /*!< f(SMCLK)/16 */
2403 #define CS_CTL1_DIVS__32                         ((uint32_t)0x50000000)          /*!< f(SMCLK)/32 */
2404 #define CS_CTL1_DIVS__64                         ((uint32_t)0x60000000)          /*!< f(SMCLK)/64 */
2405 #define CS_CTL1_DIVS__128                        ((uint32_t)0x70000000)          /*!< f(SMCLK)/128 */
2406 #define CS_CTL2_LFXTDRIVE_OFS                    ( 0)                            /*!< LFXTDRIVE Bit Offset */
2407 #define CS_CTL2_LFXTDRIVE_MASK                   ((uint32_t)0x00000003)          /*!< LFXTDRIVE Bit Mask */
2408 #define CS_CTL2_LFXTDRIVE0                       ((uint32_t)0x00000001)          /*!< LFXTDRIVE Bit 0 */
2409 #define CS_CTL2_LFXTDRIVE1                       ((uint32_t)0x00000002)          /*!< LFXTDRIVE Bit 1 */
2410 #define CS_CTL2_LFXTDRIVE_0                      ((uint32_t)0x00000000)          /*!< Lowest drive strength and current consumption LFXT oscillator. */
2411 #define CS_CTL2_LFXTDRIVE_1                      ((uint32_t)0x00000001)          /*!< Increased drive strength LFXT oscillator. */
2412 #define CS_CTL2_LFXTDRIVE_2                      ((uint32_t)0x00000002)          /*!< Increased drive strength LFXT oscillator. */
2413 #define CS_CTL2_LFXTDRIVE_3                      ((uint32_t)0x00000003)          /*!< Maximum drive strength and maximum current consumption LFXT oscillator. */
2414 #define CS_CTL2_LFXT_EN_OFS                      ( 8)                            /*!< LFXT_EN Bit Offset */
2415 #define CS_CTL2_LFXT_EN                          ((uint32_t)0x00000100)          /*!< Turns on the LFXT oscillator regardless if used as a clock resource */
2416 #define CS_CTL2_LFXTBYPASS_OFS                   ( 9)                            /*!< LFXTBYPASS Bit Offset */
2417 #define CS_CTL2_LFXTBYPASS                       ((uint32_t)0x00000200)          /*!< LFXT bypass select */
2418 #define CS_CTL2_HFXTDRIVE_OFS                    (16)                            /*!< HFXTDRIVE Bit Offset */
2419 #define CS_CTL2_HFXTDRIVE                        ((uint32_t)0x00010000)          /*!< HFXT oscillator drive selection */
2420 #define CS_CTL2_HFXTFREQ_OFS                     (20)                            /*!< HFXTFREQ Bit Offset */
2421 #define CS_CTL2_HFXTFREQ_MASK                    ((uint32_t)0x00700000)          /*!< HFXTFREQ Bit Mask */
2422 #define CS_CTL2_HFXTFREQ0                        ((uint32_t)0x00100000)          /*!< HFXTFREQ Bit 0 */
2423 #define CS_CTL2_HFXTFREQ1                        ((uint32_t)0x00200000)          /*!< HFXTFREQ Bit 1 */
2424 #define CS_CTL2_HFXTFREQ2                        ((uint32_t)0x00400000)          /*!< HFXTFREQ Bit 2 */
2425 #define CS_CTL2_HFXTFREQ_0                       ((uint32_t)0x00000000)          /*!< 1 MHz to 4 MHz */
2426 #define CS_CTL2_HFXTFREQ_1                       ((uint32_t)0x00100000)          /*!< >4 MHz to 8 MHz */
2427 #define CS_CTL2_HFXTFREQ_2                       ((uint32_t)0x00200000)          /*!< >8 MHz to 16 MHz */
2428 #define CS_CTL2_HFXTFREQ_3                       ((uint32_t)0x00300000)          /*!< >16 MHz to 24 MHz */
2429 #define CS_CTL2_HFXTFREQ_4                       ((uint32_t)0x00400000)          /*!< >24 MHz to 32 MHz */
2430 #define CS_CTL2_HFXTFREQ_5                       ((uint32_t)0x00500000)          /*!< >32 MHz to 40 MHz */
2431 #define CS_CTL2_HFXTFREQ_6                       ((uint32_t)0x00600000)          /*!< >40 MHz to 48 MHz */
2432 #define CS_CTL2_HFXTFREQ_7                       ((uint32_t)0x00700000)          /*!< Reserved for future use. */
2433 #define CS_CTL2_HFXT_EN_OFS                      (24)                            /*!< HFXT_EN Bit Offset */
2434 #define CS_CTL2_HFXT_EN                          ((uint32_t)0x01000000)          /*!< Turns on the HFXT oscillator regardless if used as a clock resource */
2435 #define CS_CTL2_HFXTBYPASS_OFS                   (25)                            /*!< HFXTBYPASS Bit Offset */
2436 #define CS_CTL2_HFXTBYPASS                       ((uint32_t)0x02000000)          /*!< HFXT bypass select */
2437 #define CS_CTL3_FCNTLF_OFS                       ( 0)                            /*!< FCNTLF Bit Offset */
2438 #define CS_CTL3_FCNTLF_MASK                      ((uint32_t)0x00000003)          /*!< FCNTLF Bit Mask */
2439 #define CS_CTL3_FCNTLF0                          ((uint32_t)0x00000001)          /*!< FCNTLF Bit 0 */
2440 #define CS_CTL3_FCNTLF1                          ((uint32_t)0x00000002)          /*!< FCNTLF Bit 1 */
2441 #define CS_CTL3_FCNTLF_0                         ((uint32_t)0x00000000)          /*!< 4096 cycles */
2442 #define CS_CTL3_FCNTLF_1                         ((uint32_t)0x00000001)          /*!< 8192 cycles */
2443 #define CS_CTL3_FCNTLF_2                         ((uint32_t)0x00000002)          /*!< 16384 cycles */
2444 #define CS_CTL3_FCNTLF_3                         ((uint32_t)0x00000003)          /*!< 32768 cycles */
2445 #define CS_CTL3_FCNTLF__4096                     ((uint32_t)0x00000000)          /*!< 4096 cycles */
2446 #define CS_CTL3_FCNTLF__8192                     ((uint32_t)0x00000001)          /*!< 8192 cycles */
2447 #define CS_CTL3_FCNTLF__16384                    ((uint32_t)0x00000002)          /*!< 16384 cycles */
2448 #define CS_CTL3_FCNTLF__32768                    ((uint32_t)0x00000003)          /*!< 32768 cycles */
2449 #define CS_CTL3_RFCNTLF_OFS                      ( 2)                            /*!< RFCNTLF Bit Offset */
2450 #define CS_CTL3_RFCNTLF                          ((uint32_t)0x00000004)          /*!< Reset start fault counter for LFXT */
2451 #define CS_CTL3_FCNTLF_EN_OFS                    ( 3)                            /*!< FCNTLF_EN Bit Offset */
2452 #define CS_CTL3_FCNTLF_EN                        ((uint32_t)0x00000008)          /*!< Enable start fault counter for LFXT */
2453 #define CS_CTL3_FCNTHF_OFS                       ( 4)                            /*!< FCNTHF Bit Offset */
2454 #define CS_CTL3_FCNTHF_MASK                      ((uint32_t)0x00000030)          /*!< FCNTHF Bit Mask */
2455 #define CS_CTL3_FCNTHF0                          ((uint32_t)0x00000010)          /*!< FCNTHF Bit 0 */
2456 #define CS_CTL3_FCNTHF1                          ((uint32_t)0x00000020)          /*!< FCNTHF Bit 1 */
2457 #define CS_CTL3_FCNTHF_0                         ((uint32_t)0x00000000)          /*!< 2048 cycles */
2458 #define CS_CTL3_FCNTHF_1                         ((uint32_t)0x00000010)          /*!< 4096 cycles */
2459 #define CS_CTL3_FCNTHF_2                         ((uint32_t)0x00000020)          /*!< 8192 cycles */
2460 #define CS_CTL3_FCNTHF_3                         ((uint32_t)0x00000030)          /*!< 16384 cycles */
2461 #define CS_CTL3_FCNTHF__2048                     ((uint32_t)0x00000000)          /*!< 2048 cycles */
2462 #define CS_CTL3_FCNTHF__4096                     ((uint32_t)0x00000010)          /*!< 4096 cycles */
2463 #define CS_CTL3_FCNTHF__8192                     ((uint32_t)0x00000020)          /*!< 8192 cycles */
2464 #define CS_CTL3_FCNTHF__16384                    ((uint32_t)0x00000030)          /*!< 16384 cycles */
2465 #define CS_CTL3_RFCNTHF_OFS                      ( 6)                            /*!< RFCNTHF Bit Offset */
2466 #define CS_CTL3_RFCNTHF                          ((uint32_t)0x00000040)          /*!< Reset start fault counter for HFXT */
2467 #define CS_CTL3_FCNTHF_EN_OFS                    ( 7)                            /*!< FCNTHF_EN Bit Offset */
2468 #define CS_CTL3_FCNTHF_EN                        ((uint32_t)0x00000080)          /*!< Enable start fault counter for HFXT */
2469 #define CS_CLKEN_ACLK_EN_OFS                     ( 0)                            /*!< ACLK_EN Bit Offset */
2470 #define CS_CLKEN_ACLK_EN                         ((uint32_t)0x00000001)          /*!< ACLK system clock conditional request enable */
2471 #define CS_CLKEN_MCLK_EN_OFS                     ( 1)                            /*!< MCLK_EN Bit Offset */
2472 #define CS_CLKEN_MCLK_EN                         ((uint32_t)0x00000002)          /*!< MCLK system clock conditional request enable */
2473 #define CS_CLKEN_HSMCLK_EN_OFS                   ( 2)                            /*!< HSMCLK_EN Bit Offset */
2474 #define CS_CLKEN_HSMCLK_EN                       ((uint32_t)0x00000004)          /*!< HSMCLK system clock conditional request enable */
2475 #define CS_CLKEN_SMCLK_EN_OFS                    ( 3)                            /*!< SMCLK_EN Bit Offset */
2476 #define CS_CLKEN_SMCLK_EN                        ((uint32_t)0x00000008)          /*!< SMCLK system clock conditional request enable */
2477 #define CS_CLKEN_VLO_EN_OFS                      ( 8)                            /*!< VLO_EN Bit Offset */
2478 #define CS_CLKEN_VLO_EN                          ((uint32_t)0x00000100)          /*!< Turns on the VLO oscillator */
2479 #define CS_CLKEN_REFO_EN_OFS                     ( 9)                            /*!< REFO_EN Bit Offset */
2480 #define CS_CLKEN_REFO_EN                         ((uint32_t)0x00000200)          /*!< Turns on the REFO oscillator */
2481 #define CS_CLKEN_MODOSC_EN_OFS                   (10)                            /*!< MODOSC_EN Bit Offset */
2482 #define CS_CLKEN_MODOSC_EN                       ((uint32_t)0x00000400)          /*!< Turns on the MODOSC oscillator */
2483 #define CS_CLKEN_REFOFSEL_OFS                    (15)                            /*!< REFOFSEL Bit Offset */
2484 #define CS_CLKEN_REFOFSEL                        ((uint32_t)0x00008000)          /*!< Selects REFO nominal frequency */
2485 #define CS_STAT_DCO_ON_OFS                       ( 0)                            /*!< DCO_ON Bit Offset */
2486 #define CS_STAT_DCO_ON                           ((uint32_t)0x00000001)          /*!< DCO status */
2487 #define CS_STAT_DCOBIAS_ON_OFS                   ( 1)                            /*!< DCOBIAS_ON Bit Offset */
2488 #define CS_STAT_DCOBIAS_ON                       ((uint32_t)0x00000002)          /*!< DCO bias status */
2489 #define CS_STAT_HFXT_ON_OFS                      ( 2)                            /*!< HFXT_ON Bit Offset */
2490 #define CS_STAT_HFXT_ON                          ((uint32_t)0x00000004)          /*!< HFXT status */
2491 #define CS_STAT_MODOSC_ON_OFS                    ( 4)                            /*!< MODOSC_ON Bit Offset */
2492 #define CS_STAT_MODOSC_ON                        ((uint32_t)0x00000010)          /*!< MODOSC status */
2493 #define CS_STAT_VLO_ON_OFS                       ( 5)                            /*!< VLO_ON Bit Offset */
2494 #define CS_STAT_VLO_ON                           ((uint32_t)0x00000020)          /*!< VLO status */
2495 #define CS_STAT_LFXT_ON_OFS                      ( 6)                            /*!< LFXT_ON Bit Offset */
2496 #define CS_STAT_LFXT_ON                          ((uint32_t)0x00000040)          /*!< LFXT status */
2497 #define CS_STAT_REFO_ON_OFS                      ( 7)                            /*!< REFO_ON Bit Offset */
2498 #define CS_STAT_REFO_ON                          ((uint32_t)0x00000080)          /*!< REFO status */
2499 #define CS_STAT_ACLK_ON_OFS                      (16)                            /*!< ACLK_ON Bit Offset */
2500 #define CS_STAT_ACLK_ON                          ((uint32_t)0x00010000)          /*!< ACLK system clock status */
2501 #define CS_STAT_MCLK_ON_OFS                      (17)                            /*!< MCLK_ON Bit Offset */
2502 #define CS_STAT_MCLK_ON                          ((uint32_t)0x00020000)          /*!< MCLK system clock status */
2503 #define CS_STAT_HSMCLK_ON_OFS                    (18)                            /*!< HSMCLK_ON Bit Offset */
2504 #define CS_STAT_HSMCLK_ON                        ((uint32_t)0x00040000)          /*!< HSMCLK system clock status */
2505 #define CS_STAT_SMCLK_ON_OFS                     (19)                            /*!< SMCLK_ON Bit Offset */
2506 #define CS_STAT_SMCLK_ON                         ((uint32_t)0x00080000)          /*!< SMCLK system clock status */
2507 #define CS_STAT_MODCLK_ON_OFS                    (20)                            /*!< MODCLK_ON Bit Offset */
2508 #define CS_STAT_MODCLK_ON                        ((uint32_t)0x00100000)          /*!< MODCLK system clock status */
2509 #define CS_STAT_VLOCLK_ON_OFS                    (21)                            /*!< VLOCLK_ON Bit Offset */
2510 #define CS_STAT_VLOCLK_ON                        ((uint32_t)0x00200000)          /*!< VLOCLK system clock status */
2511 #define CS_STAT_LFXTCLK_ON_OFS                   (22)                            /*!< LFXTCLK_ON Bit Offset */
2512 #define CS_STAT_LFXTCLK_ON                       ((uint32_t)0x00400000)          /*!< LFXTCLK system clock status */
2513 #define CS_STAT_REFOCLK_ON_OFS                   (23)                            /*!< REFOCLK_ON Bit Offset */
2514 #define CS_STAT_REFOCLK_ON                       ((uint32_t)0x00800000)          /*!< REFOCLK system clock status */
2515 #define CS_STAT_ACLK_READY_OFS                   (24)                            /*!< ACLK_READY Bit Offset */
2516 #define CS_STAT_ACLK_READY                       ((uint32_t)0x01000000)          /*!< ACLK Ready status */
2517 #define CS_STAT_MCLK_READY_OFS                   (25)                            /*!< MCLK_READY Bit Offset */
2518 #define CS_STAT_MCLK_READY                       ((uint32_t)0x02000000)          /*!< MCLK Ready status */
2519 #define CS_STAT_HSMCLK_READY_OFS                 (26)                            /*!< HSMCLK_READY Bit Offset */
2520 #define CS_STAT_HSMCLK_READY                     ((uint32_t)0x04000000)          /*!< HSMCLK Ready status */
2521 #define CS_STAT_SMCLK_READY_OFS                  (27)                            /*!< SMCLK_READY Bit Offset */
2522 #define CS_STAT_SMCLK_READY                      ((uint32_t)0x08000000)          /*!< SMCLK Ready status */
2523 #define CS_STAT_BCLK_READY_OFS                   (28)                            /*!< BCLK_READY Bit Offset */
2524 #define CS_STAT_BCLK_READY                       ((uint32_t)0x10000000)          /*!< BCLK Ready status */
2525 #define CS_IE_LFXTIE_OFS                         ( 0)                            /*!< LFXTIE Bit Offset */
2526 #define CS_IE_LFXTIE                             ((uint32_t)0x00000001)          /*!< LFXT oscillator fault flag interrupt enable */
2527 #define CS_IE_HFXTIE_OFS                         ( 1)                            /*!< HFXTIE Bit Offset */
2528 #define CS_IE_HFXTIE                             ((uint32_t)0x00000002)          /*!< HFXT oscillator fault flag interrupt enable */
2529 #define CS_IE_DCOR_OPNIE_OFS                     ( 6)                            /*!< DCOR_OPNIE Bit Offset */
2530 #define CS_IE_DCOR_OPNIE                         ((uint32_t)0x00000040)          /*!< DCO external resistor open circuit fault flag interrupt enable. */
2531 #define CS_IE_FCNTLFIE_OFS                       ( 8)                            /*!< FCNTLFIE Bit Offset */
2532 #define CS_IE_FCNTLFIE                           ((uint32_t)0x00000100)          /*!< Start fault counter interrupt enable LFXT */
2533 #define CS_IE_FCNTHFIE_OFS                       ( 9)                            /*!< FCNTHFIE Bit Offset */
2534 #define CS_IE_FCNTHFIE                           ((uint32_t)0x00000200)          /*!< Start fault counter interrupt enable HFXT */
2535 #define CS_IFG_LFXTIFG_OFS                       ( 0)                            /*!< LFXTIFG Bit Offset */
2536 #define CS_IFG_LFXTIFG                           ((uint32_t)0x00000001)          /*!< LFXT oscillator fault flag */
2537 #define CS_IFG_HFXTIFG_OFS                       ( 1)                            /*!< HFXTIFG Bit Offset */
2538 #define CS_IFG_HFXTIFG                           ((uint32_t)0x00000002)          /*!< HFXT oscillator fault flag */
2539 #define CS_IFG_DCOR_SHTIFG_OFS                   ( 5)                            /*!< DCOR_SHTIFG Bit Offset */
2540 #define CS_IFG_DCOR_SHTIFG                       ((uint32_t)0x00000020)          /*!< DCO external resistor short circuit fault flag. */
2541 #define CS_IFG_DCOR_OPNIFG_OFS                   ( 6)                            /*!< DCOR_OPNIFG Bit Offset */
2542 #define CS_IFG_DCOR_OPNIFG                       ((uint32_t)0x00000040)          /*!< DCO external resistor open circuit fault flag. */
2543 #define CS_IFG_FCNTLFIFG_OFS                     ( 8)                            /*!< FCNTLFIFG Bit Offset */
2544 #define CS_IFG_FCNTLFIFG                         ((uint32_t)0x00000100)          /*!< Start fault counter interrupt flag LFXT */
2545 #define CS_IFG_FCNTHFIFG_OFS                     ( 9)                            /*!< FCNTHFIFG Bit Offset */
2546 #define CS_IFG_FCNTHFIFG                         ((uint32_t)0x00000200)          /*!< Start fault counter interrupt flag HFXT */
2547 #define CS_CLRIFG_CLR_LFXTIFG_OFS                ( 0)                            /*!< CLR_LFXTIFG Bit Offset */
2548 #define CS_CLRIFG_CLR_LFXTIFG                    ((uint32_t)0x00000001)          /*!< Clear LFXT oscillator fault interrupt flag */
2549 #define CS_CLRIFG_CLR_HFXTIFG_OFS                ( 1)                            /*!< CLR_HFXTIFG Bit Offset */
2550 #define CS_CLRIFG_CLR_HFXTIFG                    ((uint32_t)0x00000002)          /*!< Clear HFXT oscillator fault interrupt flag */
2551 #define CS_CLRIFG_CLR_DCOR_OPNIFG_OFS            ( 6)                            /*!< CLR_DCOR_OPNIFG Bit Offset */
2552 #define CS_CLRIFG_CLR_DCOR_OPNIFG                ((uint32_t)0x00000040)          /*!< Clear DCO external resistor open circuit fault interrupt flag. */
2553 #define CS_CLRIFG_CLR_FCNTLFIFG_OFS              ( 8)                            /*!< CLR_FCNTLFIFG Bit Offset */
2554 #define CS_CLRIFG_CLR_FCNTLFIFG                  ((uint32_t)0x00000100)          /*!< Start fault counter clear interrupt flag LFXT */
2555 #define CS_CLRIFG_CLR_FCNTHFIFG_OFS              ( 9)                            /*!< CLR_FCNTHFIFG Bit Offset */
2556 #define CS_CLRIFG_CLR_FCNTHFIFG                  ((uint32_t)0x00000200)          /*!< Start fault counter clear interrupt flag HFXT */
2557 #define CS_SETIFG_SET_LFXTIFG_OFS                ( 0)                            /*!< SET_LFXTIFG Bit Offset */
2558 #define CS_SETIFG_SET_LFXTIFG                    ((uint32_t)0x00000001)          /*!< Set LFXT oscillator fault interrupt flag */
2559 #define CS_SETIFG_SET_HFXTIFG_OFS                ( 1)                            /*!< SET_HFXTIFG Bit Offset */
2560 #define CS_SETIFG_SET_HFXTIFG                    ((uint32_t)0x00000002)          /*!< Set HFXT oscillator fault interrupt flag */
2561 #define CS_SETIFG_SET_DCOR_OPNIFG_OFS            ( 6)                            /*!< SET_DCOR_OPNIFG Bit Offset */
2562 #define CS_SETIFG_SET_DCOR_OPNIFG                ((uint32_t)0x00000040)          /*!< Set DCO external resistor open circuit fault interrupt flag. */
2563 #define CS_SETIFG_SET_FCNTHFIFG_OFS              ( 9)                            /*!< SET_FCNTHFIFG Bit Offset */
2564 #define CS_SETIFG_SET_FCNTHFIFG                  ((uint32_t)0x00000200)          /*!< Start fault counter set interrupt flag HFXT */
2565 #define CS_SETIFG_SET_FCNTLFIFG_OFS              ( 8)                            /*!< SET_FCNTLFIFG Bit Offset */
2566 #define CS_SETIFG_SET_FCNTLFIFG                  ((uint32_t)0x00000100)          /*!< Start fault counter set interrupt flag LFXT */
2567 #define CS_DCOERCAL0_DCO_TCCAL_OFS               ( 0)                            /*!< DCO_TCCAL Bit Offset */
2568 #define CS_DCOERCAL0_DCO_TCCAL_MASK              ((uint32_t)0x00000003)          /*!< DCO_TCCAL Bit Mask */
2569 #define CS_DCOERCAL0_DCO_FCAL_RSEL04_OFS         (16)                            /*!< DCO_FCAL_RSEL04 Bit Offset */
2570 #define CS_DCOERCAL0_DCO_FCAL_RSEL04_MASK        ((uint32_t)0x03FF0000)          /*!< DCO_FCAL_RSEL04 Bit Mask */
2571 #define CS_DCOERCAL1_DCO_FCAL_RSEL5_OFS          ( 0)                            /*!< DCO_FCAL_RSEL5 Bit Offset */
2572 #define CS_DCOERCAL1_DCO_FCAL_RSEL5_MASK         ((uint32_t)0x000003FF)          /*!< DCO_FCAL_RSEL5 Bit Mask */
2573 #define CS_KEY_VAL                               ((uint32_t)0x0000695A)          /*!< CS control key value */
2574 #define DIO_PORT_IV_OFS                          ( 0)                            /*!< DIO Port IV Bit Offset */
2575 #define DIO_PORT_IV_MASK                         ((uint16_t)0x001F)              /*!< DIO Port IV Bit Mask */
2576 #define DIO_PORT_IV0                             ((uint16_t)0x0001)              /*!< DIO Port IV Bit 0 */
2577 #define DIO_PORT_IV1                             ((uint16_t)0x0002)              /*!< DIO Port IV Bit 1 */
2578 #define DIO_PORT_IV2                             ((uint16_t)0x0004)              /*!< DIO Port IV Bit 2 */
2579 #define DIO_PORT_IV3                             ((uint16_t)0x0008)              /*!< DIO Port IV Bit 3 */
2580 #define DIO_PORT_IV4                             ((uint16_t)0x0010)              /*!< DIO Port IV Bit 4 */
2581 #define DIO_PORT_IV_0                            ((uint16_t)0x0000)              /*!< No interrupt pending */
2582 #define DIO_PORT_IV_2                            ((uint16_t)0x0002)              /*!< Interrupt Source: Port x.0 interrupt; Interrupt Flag: IFG0; Interrupt  */
2583 #define DIO_PORT_IV_4                            ((uint16_t)0x0004)              /*!< Interrupt Source: Port x.1 interrupt; Interrupt Flag: IFG1 */
2584 #define DIO_PORT_IV_6                            ((uint16_t)0x0006)              /*!< Interrupt Source: Port x.2 interrupt; Interrupt Flag: IFG2 */
2585 #define DIO_PORT_IV_8                            ((uint16_t)0x0008)              /*!< Interrupt Source: Port x.3 interrupt; Interrupt Flag: IFG3 */
2586 #define DIO_PORT_IV_10                           ((uint16_t)0x000A)              /*!< Interrupt Source: Port x.4 interrupt; Interrupt Flag: IFG4 */
2587 #define DIO_PORT_IV_12                           ((uint16_t)0x000C)              /*!< Interrupt Source: Port x.5 interrupt; Interrupt Flag: IFG5 */
2588 #define DIO_PORT_IV_14                           ((uint16_t)0x000E)              /*!< Interrupt Source: Port x.6 interrupt; Interrupt Flag: IFG6 */
2589 #define DIO_PORT_IV_16                           ((uint16_t)0x0010)              /*!< Interrupt Source: Port x.7 interrupt; Interrupt Flag: IFG7; Interrupt  */
2590 #define DIO_PORT_IV__NONE                        ((uint16_t)0x0000)              /*!< No interrupt pending */
2591 #define DIO_PORT_IV__IFG0                        ((uint16_t)0x0002)              /*!< Interrupt Source: Port x.0 interrupt; Interrupt Flag: IFG0; Interrupt  */
2592 #define DIO_PORT_IV__IFG1                        ((uint16_t)0x0004)              /*!< Interrupt Source: Port x.1 interrupt; Interrupt Flag: IFG1 */
2593 #define DIO_PORT_IV__IFG2                        ((uint16_t)0x0006)              /*!< Interrupt Source: Port x.2 interrupt; Interrupt Flag: IFG2 */
2594 #define DIO_PORT_IV__IFG3                        ((uint16_t)0x0008)              /*!< Interrupt Source: Port x.3 interrupt; Interrupt Flag: IFG3 */
2595 #define DIO_PORT_IV__IFG4                        ((uint16_t)0x000A)              /*!< Interrupt Source: Port x.4 interrupt; Interrupt Flag: IFG4 */
2596 #define DIO_PORT_IV__IFG5                        ((uint16_t)0x000C)              /*!< Interrupt Source: Port x.5 interrupt; Interrupt Flag: IFG5 */
2597 #define DIO_PORT_IV__IFG6                        ((uint16_t)0x000E)              /*!< Interrupt Source: Port x.6 interrupt; Interrupt Flag: IFG6 */
2598 #define DIO_PORT_IV__IFG7                        ((uint16_t)0x0010)              /*!< Interrupt Source: Port x.7 interrupt; Interrupt Flag: IFG7; Interrupt  */
2599 #define DMA_DEVICE_CFG_NUM_DMA_CHANNELS_OFS      ( 0)                            /*!< NUM_DMA_CHANNELS Bit Offset */
2600 #define DMA_DEVICE_CFG_NUM_DMA_CHANNELS_MASK     ((uint32_t)0x000000FF)          /*!< NUM_DMA_CHANNELS Bit Mask */
2601 #define DMA_DEVICE_CFG_NUM_SRC_PER_CHANNEL_OFS   ( 8)                            /*!< NUM_SRC_PER_CHANNEL Bit Offset */
2602 #define DMA_DEVICE_CFG_NUM_SRC_PER_CHANNEL_MASK  ((uint32_t)0x0000FF00)          /*!< NUM_SRC_PER_CHANNEL Bit Mask */
2603 #define DMA_SW_CHTRIG_CH0_OFS                    ( 0)                            /*!< CH0 Bit Offset */
2604 #define DMA_SW_CHTRIG_CH0                        ((uint32_t)0x00000001)          /*!< Write 1, triggers DMA_CHANNEL0 */
2605 #define DMA_SW_CHTRIG_CH1_OFS                    ( 1)                            /*!< CH1 Bit Offset */
2606 #define DMA_SW_CHTRIG_CH1                        ((uint32_t)0x00000002)          /*!< Write 1, triggers DMA_CHANNEL1 */
2607 #define DMA_SW_CHTRIG_CH2_OFS                    ( 2)                            /*!< CH2 Bit Offset */
2608 #define DMA_SW_CHTRIG_CH2                        ((uint32_t)0x00000004)          /*!< Write 1, triggers DMA_CHANNEL2 */
2609 #define DMA_SW_CHTRIG_CH3_OFS                    ( 3)                            /*!< CH3 Bit Offset */
2610 #define DMA_SW_CHTRIG_CH3                        ((uint32_t)0x00000008)          /*!< Write 1, triggers DMA_CHANNEL3 */
2611 #define DMA_SW_CHTRIG_CH4_OFS                    ( 4)                            /*!< CH4 Bit Offset */
2612 #define DMA_SW_CHTRIG_CH4                        ((uint32_t)0x00000010)          /*!< Write 1, triggers DMA_CHANNEL4 */
2613 #define DMA_SW_CHTRIG_CH5_OFS                    ( 5)                            /*!< CH5 Bit Offset */
2614 #define DMA_SW_CHTRIG_CH5                        ((uint32_t)0x00000020)          /*!< Write 1, triggers DMA_CHANNEL5 */
2615 #define DMA_SW_CHTRIG_CH6_OFS                    ( 6)                            /*!< CH6 Bit Offset */
2616 #define DMA_SW_CHTRIG_CH6                        ((uint32_t)0x00000040)          /*!< Write 1, triggers DMA_CHANNEL6 */
2617 #define DMA_SW_CHTRIG_CH7_OFS                    ( 7)                            /*!< CH7 Bit Offset */
2618 #define DMA_SW_CHTRIG_CH7                        ((uint32_t)0x00000080)          /*!< Write 1, triggers DMA_CHANNEL7 */
2619 #define DMA_SW_CHTRIG_CH8_OFS                    ( 8)                            /*!< CH8 Bit Offset */
2620 #define DMA_SW_CHTRIG_CH8                        ((uint32_t)0x00000100)          /*!< Write 1, triggers DMA_CHANNEL8 */
2621 #define DMA_SW_CHTRIG_CH9_OFS                    ( 9)                            /*!< CH9 Bit Offset */
2622 #define DMA_SW_CHTRIG_CH9                        ((uint32_t)0x00000200)          /*!< Write 1, triggers DMA_CHANNEL9 */
2623 #define DMA_SW_CHTRIG_CH10_OFS                   (10)                            /*!< CH10 Bit Offset */
2624 #define DMA_SW_CHTRIG_CH10                       ((uint32_t)0x00000400)          /*!< Write 1, triggers DMA_CHANNEL10 */
2625 #define DMA_SW_CHTRIG_CH11_OFS                   (11)                            /*!< CH11 Bit Offset */
2626 #define DMA_SW_CHTRIG_CH11                       ((uint32_t)0x00000800)          /*!< Write 1, triggers DMA_CHANNEL11 */
2627 #define DMA_SW_CHTRIG_CH12_OFS                   (12)                            /*!< CH12 Bit Offset */
2628 #define DMA_SW_CHTRIG_CH12                       ((uint32_t)0x00001000)          /*!< Write 1, triggers DMA_CHANNEL12 */
2629 #define DMA_SW_CHTRIG_CH13_OFS                   (13)                            /*!< CH13 Bit Offset */
2630 #define DMA_SW_CHTRIG_CH13                       ((uint32_t)0x00002000)          /*!< Write 1, triggers DMA_CHANNEL13 */
2631 #define DMA_SW_CHTRIG_CH14_OFS                   (14)                            /*!< CH14 Bit Offset */
2632 #define DMA_SW_CHTRIG_CH14                       ((uint32_t)0x00004000)          /*!< Write 1, triggers DMA_CHANNEL14 */
2633 #define DMA_SW_CHTRIG_CH15_OFS                   (15)                            /*!< CH15 Bit Offset */
2634 #define DMA_SW_CHTRIG_CH15                       ((uint32_t)0x00008000)          /*!< Write 1, triggers DMA_CHANNEL15 */
2635 #define DMA_SW_CHTRIG_CH16_OFS                   (16)                            /*!< CH16 Bit Offset */
2636 #define DMA_SW_CHTRIG_CH16                       ((uint32_t)0x00010000)          /*!< Write 1, triggers DMA_CHANNEL16 */
2637 #define DMA_SW_CHTRIG_CH17_OFS                   (17)                            /*!< CH17 Bit Offset */
2638 #define DMA_SW_CHTRIG_CH17                       ((uint32_t)0x00020000)          /*!< Write 1, triggers DMA_CHANNEL17 */
2639 #define DMA_SW_CHTRIG_CH18_OFS                   (18)                            /*!< CH18 Bit Offset */
2640 #define DMA_SW_CHTRIG_CH18                       ((uint32_t)0x00040000)          /*!< Write 1, triggers DMA_CHANNEL18 */
2641 #define DMA_SW_CHTRIG_CH19_OFS                   (19)                            /*!< CH19 Bit Offset */
2642 #define DMA_SW_CHTRIG_CH19                       ((uint32_t)0x00080000)          /*!< Write 1, triggers DMA_CHANNEL19 */
2643 #define DMA_SW_CHTRIG_CH20_OFS                   (20)                            /*!< CH20 Bit Offset */
2644 #define DMA_SW_CHTRIG_CH20                       ((uint32_t)0x00100000)          /*!< Write 1, triggers DMA_CHANNEL20 */
2645 #define DMA_SW_CHTRIG_CH21_OFS                   (21)                            /*!< CH21 Bit Offset */
2646 #define DMA_SW_CHTRIG_CH21                       ((uint32_t)0x00200000)          /*!< Write 1, triggers DMA_CHANNEL21 */
2647 #define DMA_SW_CHTRIG_CH22_OFS                   (22)                            /*!< CH22 Bit Offset */
2648 #define DMA_SW_CHTRIG_CH22                       ((uint32_t)0x00400000)          /*!< Write 1, triggers DMA_CHANNEL22 */
2649 #define DMA_SW_CHTRIG_CH23_OFS                   (23)                            /*!< CH23 Bit Offset */
2650 #define DMA_SW_CHTRIG_CH23                       ((uint32_t)0x00800000)          /*!< Write 1, triggers DMA_CHANNEL23 */
2651 #define DMA_SW_CHTRIG_CH24_OFS                   (24)                            /*!< CH24 Bit Offset */
2652 #define DMA_SW_CHTRIG_CH24                       ((uint32_t)0x01000000)          /*!< Write 1, triggers DMA_CHANNEL24 */
2653 #define DMA_SW_CHTRIG_CH25_OFS                   (25)                            /*!< CH25 Bit Offset */
2654 #define DMA_SW_CHTRIG_CH25                       ((uint32_t)0x02000000)          /*!< Write 1, triggers DMA_CHANNEL25 */
2655 #define DMA_SW_CHTRIG_CH26_OFS                   (26)                            /*!< CH26 Bit Offset */
2656 #define DMA_SW_CHTRIG_CH26                       ((uint32_t)0x04000000)          /*!< Write 1, triggers DMA_CHANNEL26 */
2657 #define DMA_SW_CHTRIG_CH27_OFS                   (27)                            /*!< CH27 Bit Offset */
2658 #define DMA_SW_CHTRIG_CH27                       ((uint32_t)0x08000000)          /*!< Write 1, triggers DMA_CHANNEL27 */
2659 #define DMA_SW_CHTRIG_CH28_OFS                   (28)                            /*!< CH28 Bit Offset */
2660 #define DMA_SW_CHTRIG_CH28                       ((uint32_t)0x10000000)          /*!< Write 1, triggers DMA_CHANNEL28 */
2661 #define DMA_SW_CHTRIG_CH29_OFS                   (29)                            /*!< CH29 Bit Offset */
2662 #define DMA_SW_CHTRIG_CH29                       ((uint32_t)0x20000000)          /*!< Write 1, triggers DMA_CHANNEL29 */
2663 #define DMA_SW_CHTRIG_CH30_OFS                   (30)                            /*!< CH30 Bit Offset */
2664 #define DMA_SW_CHTRIG_CH30                       ((uint32_t)0x40000000)          /*!< Write 1, triggers DMA_CHANNEL30 */
2665 #define DMA_SW_CHTRIG_CH31_OFS                   (31)                            /*!< CH31 Bit Offset */
2666 #define DMA_SW_CHTRIG_CH31                       ((uint32_t)0x80000000)          /*!< Write 1, triggers DMA_CHANNEL31 */
2667 #define DMA_CHN_SRCCFG_DMA_SRC_OFS               ( 0)                            /*!< DMA_SRC Bit Offset */
2668 #define DMA_CHN_SRCCFG_DMA_SRC_MASK              ((uint32_t)0x000000FF)          /*!< DMA_SRC Bit Mask */
2669 #define DMA_INT1_SRCCFG_INT_SRC_OFS              ( 0)                            /*!< INT_SRC Bit Offset */
2670 #define DMA_INT1_SRCCFG_INT_SRC_MASK             ((uint32_t)0x0000001F)          /*!< INT_SRC Bit Mask */
2671 #define DMA_INT1_SRCCFG_EN_OFS                   ( 5)                            /*!< EN Bit Offset */
2672 #define DMA_INT1_SRCCFG_EN                       ((uint32_t)0x00000020)          /*!< Enables DMA_INT1 mapping */
2673 #define DMA_INT2_SRCCFG_INT_SRC_OFS              ( 0)                            /*!< INT_SRC Bit Offset */
2674 #define DMA_INT2_SRCCFG_INT_SRC_MASK             ((uint32_t)0x0000001F)          /*!< INT_SRC Bit Mask */
2675 #define DMA_INT2_SRCCFG_EN_OFS                   ( 5)                            /*!< EN Bit Offset */
2676 #define DMA_INT2_SRCCFG_EN                       ((uint32_t)0x00000020)          /*!< Enables DMA_INT2 mapping */
2677 #define DMA_INT3_SRCCFG_INT_SRC_OFS              ( 0)                            /*!< INT_SRC Bit Offset */
2678 #define DMA_INT3_SRCCFG_INT_SRC_MASK             ((uint32_t)0x0000001F)          /*!< INT_SRC Bit Mask */
2679 #define DMA_INT3_SRCCFG_EN_OFS                   ( 5)                            /*!< EN Bit Offset */
2680 #define DMA_INT3_SRCCFG_EN                       ((uint32_t)0x00000020)          /*!< Enables DMA_INT3 mapping */
2681 #define DMA_INT0_SRCFLG_CH0_OFS                  ( 0)                            /*!< CH0 Bit Offset */
2682 #define DMA_INT0_SRCFLG_CH0                      ((uint32_t)0x00000001)          /*!< Channel 0 was the source of DMA_INT0 */
2683 #define DMA_INT0_SRCFLG_CH1_OFS                  ( 1)                            /*!< CH1 Bit Offset */
2684 #define DMA_INT0_SRCFLG_CH1                      ((uint32_t)0x00000002)          /*!< Channel 1 was the source of DMA_INT0 */
2685 #define DMA_INT0_SRCFLG_CH2_OFS                  ( 2)                            /*!< CH2 Bit Offset */
2686 #define DMA_INT0_SRCFLG_CH2                      ((uint32_t)0x00000004)          /*!< Channel 2 was the source of DMA_INT0 */
2687 #define DMA_INT0_SRCFLG_CH3_OFS                  ( 3)                            /*!< CH3 Bit Offset */
2688 #define DMA_INT0_SRCFLG_CH3                      ((uint32_t)0x00000008)          /*!< Channel 3 was the source of DMA_INT0 */
2689 #define DMA_INT0_SRCFLG_CH4_OFS                  ( 4)                            /*!< CH4 Bit Offset */
2690 #define DMA_INT0_SRCFLG_CH4                      ((uint32_t)0x00000010)          /*!< Channel 4 was the source of DMA_INT0 */
2691 #define DMA_INT0_SRCFLG_CH5_OFS                  ( 5)                            /*!< CH5 Bit Offset */
2692 #define DMA_INT0_SRCFLG_CH5                      ((uint32_t)0x00000020)          /*!< Channel 5 was the source of DMA_INT0 */
2693 #define DMA_INT0_SRCFLG_CH6_OFS                  ( 6)                            /*!< CH6 Bit Offset */
2694 #define DMA_INT0_SRCFLG_CH6                      ((uint32_t)0x00000040)          /*!< Channel 6 was the source of DMA_INT0 */
2695 #define DMA_INT0_SRCFLG_CH7_OFS                  ( 7)                            /*!< CH7 Bit Offset */
2696 #define DMA_INT0_SRCFLG_CH7                      ((uint32_t)0x00000080)          /*!< Channel 7 was the source of DMA_INT0 */
2697 #define DMA_INT0_SRCFLG_CH8_OFS                  ( 8)                            /*!< CH8 Bit Offset */
2698 #define DMA_INT0_SRCFLG_CH8                      ((uint32_t)0x00000100)          /*!< Channel 8 was the source of DMA_INT0 */
2699 #define DMA_INT0_SRCFLG_CH9_OFS                  ( 9)                            /*!< CH9 Bit Offset */
2700 #define DMA_INT0_SRCFLG_CH9                      ((uint32_t)0x00000200)          /*!< Channel 9 was the source of DMA_INT0 */
2701 #define DMA_INT0_SRCFLG_CH10_OFS                 (10)                            /*!< CH10 Bit Offset */
2702 #define DMA_INT0_SRCFLG_CH10                     ((uint32_t)0x00000400)          /*!< Channel 10 was the source of DMA_INT0 */
2703 #define DMA_INT0_SRCFLG_CH11_OFS                 (11)                            /*!< CH11 Bit Offset */
2704 #define DMA_INT0_SRCFLG_CH11                     ((uint32_t)0x00000800)          /*!< Channel 11 was the source of DMA_INT0 */
2705 #define DMA_INT0_SRCFLG_CH12_OFS                 (12)                            /*!< CH12 Bit Offset */
2706 #define DMA_INT0_SRCFLG_CH12                     ((uint32_t)0x00001000)          /*!< Channel 12 was the source of DMA_INT0 */
2707 #define DMA_INT0_SRCFLG_CH13_OFS                 (13)                            /*!< CH13 Bit Offset */
2708 #define DMA_INT0_SRCFLG_CH13                     ((uint32_t)0x00002000)          /*!< Channel 13 was the source of DMA_INT0 */
2709 #define DMA_INT0_SRCFLG_CH14_OFS                 (14)                            /*!< CH14 Bit Offset */
2710 #define DMA_INT0_SRCFLG_CH14                     ((uint32_t)0x00004000)          /*!< Channel 14 was the source of DMA_INT0 */
2711 #define DMA_INT0_SRCFLG_CH15_OFS                 (15)                            /*!< CH15 Bit Offset */
2712 #define DMA_INT0_SRCFLG_CH15                     ((uint32_t)0x00008000)          /*!< Channel 15 was the source of DMA_INT0 */
2713 #define DMA_INT0_SRCFLG_CH16_OFS                 (16)                            /*!< CH16 Bit Offset */
2714 #define DMA_INT0_SRCFLG_CH16                     ((uint32_t)0x00010000)          /*!< Channel 16 was the source of DMA_INT0 */
2715 #define DMA_INT0_SRCFLG_CH17_OFS                 (17)                            /*!< CH17 Bit Offset */
2716 #define DMA_INT0_SRCFLG_CH17                     ((uint32_t)0x00020000)          /*!< Channel 17 was the source of DMA_INT0 */
2717 #define DMA_INT0_SRCFLG_CH18_OFS                 (18)                            /*!< CH18 Bit Offset */
2718 #define DMA_INT0_SRCFLG_CH18                     ((uint32_t)0x00040000)          /*!< Channel 18 was the source of DMA_INT0 */
2719 #define DMA_INT0_SRCFLG_CH19_OFS                 (19)                            /*!< CH19 Bit Offset */
2720 #define DMA_INT0_SRCFLG_CH19                     ((uint32_t)0x00080000)          /*!< Channel 19 was the source of DMA_INT0 */
2721 #define DMA_INT0_SRCFLG_CH20_OFS                 (20)                            /*!< CH20 Bit Offset */
2722 #define DMA_INT0_SRCFLG_CH20                     ((uint32_t)0x00100000)          /*!< Channel 20 was the source of DMA_INT0 */
2723 #define DMA_INT0_SRCFLG_CH21_OFS                 (21)                            /*!< CH21 Bit Offset */
2724 #define DMA_INT0_SRCFLG_CH21                     ((uint32_t)0x00200000)          /*!< Channel 21 was the source of DMA_INT0 */
2725 #define DMA_INT0_SRCFLG_CH22_OFS                 (22)                            /*!< CH22 Bit Offset */
2726 #define DMA_INT0_SRCFLG_CH22                     ((uint32_t)0x00400000)          /*!< Channel 22 was the source of DMA_INT0 */
2727 #define DMA_INT0_SRCFLG_CH23_OFS                 (23)                            /*!< CH23 Bit Offset */
2728 #define DMA_INT0_SRCFLG_CH23                     ((uint32_t)0x00800000)          /*!< Channel 23 was the source of DMA_INT0 */
2729 #define DMA_INT0_SRCFLG_CH24_OFS                 (24)                            /*!< CH24 Bit Offset */
2730 #define DMA_INT0_SRCFLG_CH24                     ((uint32_t)0x01000000)          /*!< Channel 24 was the source of DMA_INT0 */
2731 #define DMA_INT0_SRCFLG_CH25_OFS                 (25)                            /*!< CH25 Bit Offset */
2732 #define DMA_INT0_SRCFLG_CH25                     ((uint32_t)0x02000000)          /*!< Channel 25 was the source of DMA_INT0 */
2733 #define DMA_INT0_SRCFLG_CH26_OFS                 (26)                            /*!< CH26 Bit Offset */
2734 #define DMA_INT0_SRCFLG_CH26                     ((uint32_t)0x04000000)          /*!< Channel 26 was the source of DMA_INT0 */
2735 #define DMA_INT0_SRCFLG_CH27_OFS                 (27)                            /*!< CH27 Bit Offset */
2736 #define DMA_INT0_SRCFLG_CH27                     ((uint32_t)0x08000000)          /*!< Channel 27 was the source of DMA_INT0 */
2737 #define DMA_INT0_SRCFLG_CH28_OFS                 (28)                            /*!< CH28 Bit Offset */
2738 #define DMA_INT0_SRCFLG_CH28                     ((uint32_t)0x10000000)          /*!< Channel 28 was the source of DMA_INT0 */
2739 #define DMA_INT0_SRCFLG_CH29_OFS                 (29)                            /*!< CH29 Bit Offset */
2740 #define DMA_INT0_SRCFLG_CH29                     ((uint32_t)0x20000000)          /*!< Channel 29 was the source of DMA_INT0 */
2741 #define DMA_INT0_SRCFLG_CH30_OFS                 (30)                            /*!< CH30 Bit Offset */
2742 #define DMA_INT0_SRCFLG_CH30                     ((uint32_t)0x40000000)          /*!< Channel 30 was the source of DMA_INT0 */
2743 #define DMA_INT0_SRCFLG_CH31_OFS                 (31)                            /*!< CH31 Bit Offset */
2744 #define DMA_INT0_SRCFLG_CH31                     ((uint32_t)0x80000000)          /*!< Channel 31 was the source of DMA_INT0 */
2745 #define DMA_INT0_CLRFLG_CH0_OFS                  ( 0)                            /*!< CH0 Bit Offset */
2746 #define DMA_INT0_CLRFLG_CH0                      ((uint32_t)0x00000001)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
2747 #define DMA_INT0_CLRFLG_CH1_OFS                  ( 1)                            /*!< CH1 Bit Offset */
2748 #define DMA_INT0_CLRFLG_CH1                      ((uint32_t)0x00000002)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
2749 #define DMA_INT0_CLRFLG_CH2_OFS                  ( 2)                            /*!< CH2 Bit Offset */
2750 #define DMA_INT0_CLRFLG_CH2                      ((uint32_t)0x00000004)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
2751 #define DMA_INT0_CLRFLG_CH3_OFS                  ( 3)                            /*!< CH3 Bit Offset */
2752 #define DMA_INT0_CLRFLG_CH3                      ((uint32_t)0x00000008)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
2753 #define DMA_INT0_CLRFLG_CH4_OFS                  ( 4)                            /*!< CH4 Bit Offset */
2754 #define DMA_INT0_CLRFLG_CH4                      ((uint32_t)0x00000010)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
2755 #define DMA_INT0_CLRFLG_CH5_OFS                  ( 5)                            /*!< CH5 Bit Offset */
2756 #define DMA_INT0_CLRFLG_CH5                      ((uint32_t)0x00000020)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
2757 #define DMA_INT0_CLRFLG_CH6_OFS                  ( 6)                            /*!< CH6 Bit Offset */
2758 #define DMA_INT0_CLRFLG_CH6                      ((uint32_t)0x00000040)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
2759 #define DMA_INT0_CLRFLG_CH7_OFS                  ( 7)                            /*!< CH7 Bit Offset */
2760 #define DMA_INT0_CLRFLG_CH7                      ((uint32_t)0x00000080)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
2761 #define DMA_INT0_CLRFLG_CH8_OFS                  ( 8)                            /*!< CH8 Bit Offset */
2762 #define DMA_INT0_CLRFLG_CH8                      ((uint32_t)0x00000100)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
2763 #define DMA_INT0_CLRFLG_CH9_OFS                  ( 9)                            /*!< CH9 Bit Offset */
2764 #define DMA_INT0_CLRFLG_CH9                      ((uint32_t)0x00000200)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
2765 #define DMA_INT0_CLRFLG_CH10_OFS                 (10)                            /*!< CH10 Bit Offset */
2766 #define DMA_INT0_CLRFLG_CH10                     ((uint32_t)0x00000400)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
2767 #define DMA_INT0_CLRFLG_CH11_OFS                 (11)                            /*!< CH11 Bit Offset */
2768 #define DMA_INT0_CLRFLG_CH11                     ((uint32_t)0x00000800)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
2769 #define DMA_INT0_CLRFLG_CH12_OFS                 (12)                            /*!< CH12 Bit Offset */
2770 #define DMA_INT0_CLRFLG_CH12                     ((uint32_t)0x00001000)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
2771 #define DMA_INT0_CLRFLG_CH13_OFS                 (13)                            /*!< CH13 Bit Offset */
2772 #define DMA_INT0_CLRFLG_CH13                     ((uint32_t)0x00002000)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
2773 #define DMA_INT0_CLRFLG_CH14_OFS                 (14)                            /*!< CH14 Bit Offset */
2774 #define DMA_INT0_CLRFLG_CH14                     ((uint32_t)0x00004000)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
2775 #define DMA_INT0_CLRFLG_CH15_OFS                 (15)                            /*!< CH15 Bit Offset */
2776 #define DMA_INT0_CLRFLG_CH15                     ((uint32_t)0x00008000)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
2777 #define DMA_INT0_CLRFLG_CH16_OFS                 (16)                            /*!< CH16 Bit Offset */
2778 #define DMA_INT0_CLRFLG_CH16                     ((uint32_t)0x00010000)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
2779 #define DMA_INT0_CLRFLG_CH17_OFS                 (17)                            /*!< CH17 Bit Offset */
2780 #define DMA_INT0_CLRFLG_CH17                     ((uint32_t)0x00020000)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
2781 #define DMA_INT0_CLRFLG_CH18_OFS                 (18)                            /*!< CH18 Bit Offset */
2782 #define DMA_INT0_CLRFLG_CH18                     ((uint32_t)0x00040000)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
2783 #define DMA_INT0_CLRFLG_CH19_OFS                 (19)                            /*!< CH19 Bit Offset */
2784 #define DMA_INT0_CLRFLG_CH19                     ((uint32_t)0x00080000)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
2785 #define DMA_INT0_CLRFLG_CH20_OFS                 (20)                            /*!< CH20 Bit Offset */
2786 #define DMA_INT0_CLRFLG_CH20                     ((uint32_t)0x00100000)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
2787 #define DMA_INT0_CLRFLG_CH21_OFS                 (21)                            /*!< CH21 Bit Offset */
2788 #define DMA_INT0_CLRFLG_CH21                     ((uint32_t)0x00200000)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
2789 #define DMA_INT0_CLRFLG_CH22_OFS                 (22)                            /*!< CH22 Bit Offset */
2790 #define DMA_INT0_CLRFLG_CH22                     ((uint32_t)0x00400000)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
2791 #define DMA_INT0_CLRFLG_CH23_OFS                 (23)                            /*!< CH23 Bit Offset */
2792 #define DMA_INT0_CLRFLG_CH23                     ((uint32_t)0x00800000)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
2793 #define DMA_INT0_CLRFLG_CH24_OFS                 (24)                            /*!< CH24 Bit Offset */
2794 #define DMA_INT0_CLRFLG_CH24                     ((uint32_t)0x01000000)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
2795 #define DMA_INT0_CLRFLG_CH25_OFS                 (25)                            /*!< CH25 Bit Offset */
2796 #define DMA_INT0_CLRFLG_CH25                     ((uint32_t)0x02000000)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
2797 #define DMA_INT0_CLRFLG_CH26_OFS                 (26)                            /*!< CH26 Bit Offset */
2798 #define DMA_INT0_CLRFLG_CH26                     ((uint32_t)0x04000000)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
2799 #define DMA_INT0_CLRFLG_CH27_OFS                 (27)                            /*!< CH27 Bit Offset */
2800 #define DMA_INT0_CLRFLG_CH27                     ((uint32_t)0x08000000)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
2801 #define DMA_INT0_CLRFLG_CH28_OFS                 (28)                            /*!< CH28 Bit Offset */
2802 #define DMA_INT0_CLRFLG_CH28                     ((uint32_t)0x10000000)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
2803 #define DMA_INT0_CLRFLG_CH29_OFS                 (29)                            /*!< CH29 Bit Offset */
2804 #define DMA_INT0_CLRFLG_CH29                     ((uint32_t)0x20000000)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
2805 #define DMA_INT0_CLRFLG_CH30_OFS                 (30)                            /*!< CH30 Bit Offset */
2806 #define DMA_INT0_CLRFLG_CH30                     ((uint32_t)0x40000000)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
2807 #define DMA_INT0_CLRFLG_CH31_OFS                 (31)                            /*!< CH31 Bit Offset */
2808 #define DMA_INT0_CLRFLG_CH31                     ((uint32_t)0x80000000)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
2809 #define DMA_STAT_MASTEN_OFS                      ( 0)                            /*!< MASTEN Bit Offset */
2810 #define DMA_STAT_MASTEN                          ((uint32_t)0x00000001)
2811 #define DMA_STAT_STATE_OFS                       ( 4)                            /*!< STATE Bit Offset */
2812 #define DMA_STAT_STATE_MASK                      ((uint32_t)0x000000F0)          /*!< STATE Bit Mask */
2813 #define DMA_STAT_STATE0                          ((uint32_t)0x00000010)          /*!< STATE Bit 0 */
2814 #define DMA_STAT_STATE1                          ((uint32_t)0x00000020)          /*!< STATE Bit 1 */
2815 #define DMA_STAT_STATE2                          ((uint32_t)0x00000040)          /*!< STATE Bit 2 */
2816 #define DMA_STAT_STATE3                          ((uint32_t)0x00000080)          /*!< STATE Bit 3 */
2817 #define DMA_STAT_STATE_0                         ((uint32_t)0x00000000)          /*!< idle */
2818 #define DMA_STAT_STATE_1                         ((uint32_t)0x00000010)          /*!< reading channel controller data */
2819 #define DMA_STAT_STATE_2                         ((uint32_t)0x00000020)          /*!< reading source data end pointer */
2820 #define DMA_STAT_STATE_3                         ((uint32_t)0x00000030)          /*!< reading destination data end pointer */
2821 #define DMA_STAT_STATE_4                         ((uint32_t)0x00000040)          /*!< reading source data */
2822 #define DMA_STAT_STATE_5                         ((uint32_t)0x00000050)          /*!< writing destination data */
2823 #define DMA_STAT_STATE_6                         ((uint32_t)0x00000060)          /*!< waiting for DMA request to clear */
2824 #define DMA_STAT_STATE_7                         ((uint32_t)0x00000070)          /*!< writing channel controller data */
2825 #define DMA_STAT_STATE_8                         ((uint32_t)0x00000080)          /*!< stalled */
2826 #define DMA_STAT_STATE_9                         ((uint32_t)0x00000090)          /*!< done */
2827 #define DMA_STAT_STATE_10                        ((uint32_t)0x000000A0)          /*!< peripheral scatter-gather transition */
2828 #define DMA_STAT_STATE_11                        ((uint32_t)0x000000B0)          /*!< Reserved */
2829 #define DMA_STAT_STATE_12                        ((uint32_t)0x000000C0)          /*!< Reserved */
2830 #define DMA_STAT_STATE_13                        ((uint32_t)0x000000D0)          /*!< Reserved */
2831 #define DMA_STAT_STATE_14                        ((uint32_t)0x000000E0)          /*!< Reserved */
2832 #define DMA_STAT_STATE_15                        ((uint32_t)0x000000F0)          /*!< Reserved */
2833 #define DMA_STAT_DMACHANS_OFS                    (16)                            /*!< DMACHANS Bit Offset */
2834 #define DMA_STAT_DMACHANS_MASK                   ((uint32_t)0x001F0000)          /*!< DMACHANS Bit Mask */
2835 #define DMA_STAT_DMACHANS0                       ((uint32_t)0x00010000)          /*!< DMACHANS Bit 0 */
2836 #define DMA_STAT_DMACHANS1                       ((uint32_t)0x00020000)          /*!< DMACHANS Bit 1 */
2837 #define DMA_STAT_DMACHANS2                       ((uint32_t)0x00040000)          /*!< DMACHANS Bit 2 */
2838 #define DMA_STAT_DMACHANS3                       ((uint32_t)0x00080000)          /*!< DMACHANS Bit 3 */
2839 #define DMA_STAT_DMACHANS4                       ((uint32_t)0x00100000)          /*!< DMACHANS Bit 4 */
2840 #define DMA_STAT_DMACHANS_0                      ((uint32_t)0x00000000)          /*!< Controller configured to use 1 DMA channel */
2841 #define DMA_STAT_DMACHANS_1                      ((uint32_t)0x00010000)          /*!< Controller configured to use 2 DMA channels */
2842 #define DMA_STAT_DMACHANS_30                     ((uint32_t)0x001E0000)          /*!< Controller configured to use 31 DMA channels */
2843 #define DMA_STAT_DMACHANS_31                     ((uint32_t)0x001F0000)          /*!< Controller configured to use 32 DMA channels */
2844 #define DMA_STAT_TESTSTAT_OFS                    (28)                            /*!< TESTSTAT Bit Offset */
2845 #define DMA_STAT_TESTSTAT_MASK                   ((uint32_t)0xF0000000)          /*!< TESTSTAT Bit Mask */
2846 #define DMA_STAT_TESTSTAT0                       ((uint32_t)0x10000000)          /*!< TESTSTAT Bit 0 */
2847 #define DMA_STAT_TESTSTAT1                       ((uint32_t)0x20000000)          /*!< TESTSTAT Bit 1 */
2848 #define DMA_STAT_TESTSTAT2                       ((uint32_t)0x40000000)          /*!< TESTSTAT Bit 2 */
2849 #define DMA_STAT_TESTSTAT3                       ((uint32_t)0x80000000)          /*!< TESTSTAT Bit 3 */
2850 #define DMA_STAT_TESTSTAT_0                      ((uint32_t)0x00000000)          /*!< Controller does not include the integration test logic */
2851 #define DMA_STAT_TESTSTAT_1                      ((uint32_t)0x10000000)          /*!< Controller includes the integration test logic */
2852 #define DMA_CFG_MASTEN_OFS                       ( 0)                            /*!< MASTEN Bit Offset */
2853 #define DMA_CFG_MASTEN                           ((uint32_t)0x00000001)
2854 #define DMA_CFG_CHPROTCTRL_OFS                   ( 5)                            /*!< CHPROTCTRL Bit Offset */
2855 #define DMA_CFG_CHPROTCTRL_MASK                  ((uint32_t)0x000000E0)          /*!< CHPROTCTRL Bit Mask */
2856 #define DMA_CTLBASE_ADDR_OFS                     ( 5)                            /*!< ADDR Bit Offset */
2857 #define DMA_CTLBASE_ADDR_MASK                    ((uint32_t)0xFFFFFFE0)          /*!< ADDR Bit Mask */
2858 #define DMA_ERRCLR_ERRCLR_OFS                    ( 0)                            /*!< ERRCLR Bit Offset */
2859 #define DMA_ERRCLR_ERRCLR                        ((uint32_t)0x00000001)
2860 #define __MCU_NUM_DMA_CHANNELS__                8
2861 #define DMA_CHANNEL_CONTROL_STRUCT_SIZE         0x10
2862 #define DMA_CONTROL_MEMORY_ALIGNMENT            (__MCU_NUM_DMA_CHANNELS__ * DMA_CHANNEL_CONTROL_STRUCT_SIZE)
2863 #define UDMA_STAT_DMACHANS_M                    ((uint32_t)0x001F0000)           /*!< Available uDMA Channels Minus 1 */
2864 #define UDMA_STAT_STATE_M                       ((uint32_t)0x000000F0)           /*!< Control State Machine Status */
2865 #define UDMA_STAT_STATE_IDLE                    ((uint32_t)0x00000000)           /*!< Idle */
2866 #define UDMA_STAT_STATE_RD_CTRL                 ((uint32_t)0x00000010)           /*!< Reading channel controller data */
2867 #define UDMA_STAT_STATE_RD_SRCENDP              ((uint32_t)0x00000020)           /*!< Reading source end pointer */
2868 #define UDMA_STAT_STATE_RD_DSTENDP              ((uint32_t)0x00000030)           /*!< Reading destination end pointer */
2869 #define UDMA_STAT_STATE_RD_SRCDAT               ((uint32_t)0x00000040)           /*!< Reading source data */
2870 #define UDMA_STAT_STATE_WR_DSTDAT               ((uint32_t)0x00000050)           /*!< Writing destination data */
2871 #define UDMA_STAT_STATE_WAIT                    ((uint32_t)0x00000060)           /*!< Waiting for uDMA request to clear */
2872 #define UDMA_STAT_STATE_WR_CTRL                 ((uint32_t)0x00000070)           /*!< Writing channel controller data */
2873 #define UDMA_STAT_STATE_STALL                   ((uint32_t)0x00000080)           /*!< Stalled */
2874 #define UDMA_STAT_STATE_DONE                    ((uint32_t)0x00000090)           /*!< Done */
2875 #define UDMA_STAT_STATE_UNDEF                   ((uint32_t)0x000000A0)           /*!< Undefined */
2876 #define UDMA_STAT_MASTEN                        ((uint32_t)0x00000001)           /*!< Master Enable Status */
2877 #define UDMA_STAT_DMACHANS_S                    (16)
2878 #define UDMA_CFG_MASTEN                         ((uint32_t)0x00000001)           /*!< Controller Master Enable */
2879 #define UDMA_CTLBASE_ADDR_M                     ((uint32_t)0xFFFFFC00)           /*!< Channel Control Base Address */
2880 #define UDMA_CTLBASE_ADDR_S                     (10)
2881 #define UDMA_ALTBASE_ADDR_M                     ((uint32_t)0xFFFFFFFF)           /*!< Alternate Channel Address Pointer */
2882 #define UDMA_ALTBASE_ADDR_S                     ( 0)
2883 #define UDMA_WAITSTAT_WAITREQ_M                 ((uint32_t)0xFFFFFFFF)           /*!< Channel [n] Wait Status */
2884 #define UDMA_SWREQ_M                            ((uint32_t)0xFFFFFFFF)           /*!< Channel [n] Software Request */
2885 #define UDMA_USEBURSTSET_SET_M                  ((uint32_t)0xFFFFFFFF)           /*!< Channel [n] Useburst Set */
2886 #define UDMA_USEBURSTCLR_CLR_M                  ((uint32_t)0xFFFFFFFF)           /*!< Channel [n] Useburst Clear */
2887 #define UDMA_REQMASKSET_SET_M                   ((uint32_t)0xFFFFFFFF)           /*!< Channel [n] Request Mask Set */
2888 #define UDMA_REQMASKCLR_CLR_M                   ((uint32_t)0xFFFFFFFF)           /*!< Channel [n] Request Mask Clear */
2889 #define UDMA_ENASET_SET_M                       ((uint32_t)0xFFFFFFFF)           /*!< Channel [n] Enable Set */
2890 #define UDMA_ENACLR_CLR_M                       ((uint32_t)0xFFFFFFFF)           /*!< Clear Channel [n] Enable Clear */
2891 #define UDMA_ALTSET_SET_M                       ((uint32_t)0xFFFFFFFF)           /*!< Channel [n] Alternate Set */
2892 #define UDMA_ALTCLR_CLR_M                       ((uint32_t)0xFFFFFFFF)           /*!< Channel [n] Alternate Clear */
2893 #define UDMA_PRIOSET_SET_M                      ((uint32_t)0xFFFFFFFF)           /*!< Channel [n] Priority Set */
2894 #define UDMA_PRIOCLR_CLR_M                      ((uint32_t)0xFFFFFFFF)           /*!< Channel [n] Priority Clear */
2895 #define UDMA_ERRCLR_ERRCLR                      ((uint32_t)0x00000001)           /*!< uDMA Bus Error Status */
2896 #define UDMA_CHASGN_M                           ((uint32_t)0xFFFFFFFF)           /*!< Channel [n] Assignment Select */
2897 #define UDMA_CHASGN_PRIMARY                     ((uint32_t)0x00000000)           /*!< Use the primary channel assignment */
2898 #define UDMA_CHASGN_SECONDARY                   ((uint32_t)0x00000001)           /*!< Use the secondary channel assignment */
2899 #define UDMA_O_SRCENDP                          ((uint32_t)0x00000000)           /*!< DMA Channel Source Address End Pointer */
2900 #define UDMA_O_DSTENDP                          ((uint32_t)0x00000004)           /*!< DMA Channel Destination Address End Pointer */
2901 #define UDMA_O_CHCTL                            ((uint32_t)0x00000008)           /*!< DMA Channel Control Word */
2902 #define UDMA_SRCENDP_ADDR_M                     ((uint32_t)0xFFFFFFFF)           /*!< Source Address End Pointer */
2903 #define UDMA_SRCENDP_ADDR_S                     ( 0)
2904 #define UDMA_DSTENDP_ADDR_M                     ((uint32_t)0xFFFFFFFF)           /*!< Destination Address End Pointer */
2905 #define UDMA_DSTENDP_ADDR_S                     ( 0)
2906 #define UDMA_CHCTL_DSTINC_M                     ((uint32_t)0xC0000000)           /*!< Destination Address Increment */
2907 #define UDMA_CHCTL_DSTINC_8                     ((uint32_t)0x00000000)           /*!< Byte */
2908 #define UDMA_CHCTL_DSTINC_16                    ((uint32_t)0x40000000)           /*!< Half-word */
2909 #define UDMA_CHCTL_DSTINC_32                    ((uint32_t)0x80000000)           /*!< Word */
2910 #define UDMA_CHCTL_DSTINC_NONE                  ((uint32_t)0xC0000000)           /*!< No increment */
2911 #define UDMA_CHCTL_DSTSIZE_M                    ((uint32_t)0x30000000)           /*!< Destination Data Size */
2912 #define UDMA_CHCTL_DSTSIZE_8                    ((uint32_t)0x00000000)           /*!< Byte */
2913 #define UDMA_CHCTL_DSTSIZE_16                   ((uint32_t)0x10000000)           /*!< Half-word */
2914 #define UDMA_CHCTL_DSTSIZE_32                   ((uint32_t)0x20000000)           /*!< Word */
2915 #define UDMA_CHCTL_SRCINC_M                     ((uint32_t)0x0C000000)           /*!< Source Address Increment */
2916 #define UDMA_CHCTL_SRCINC_8                     ((uint32_t)0x00000000)           /*!< Byte */
2917 #define UDMA_CHCTL_SRCINC_16                    ((uint32_t)0x04000000)           /*!< Half-word */
2918 #define UDMA_CHCTL_SRCINC_32                    ((uint32_t)0x08000000)           /*!< Word */
2919 #define UDMA_CHCTL_SRCINC_NONE                  ((uint32_t)0x0C000000)           /*!< No increment */
2920 #define UDMA_CHCTL_SRCSIZE_M                    ((uint32_t)0x03000000)           /*!< Source Data Size */
2921 #define UDMA_CHCTL_SRCSIZE_8                    ((uint32_t)0x00000000)           /*!< Byte */
2922 #define UDMA_CHCTL_SRCSIZE_16                   ((uint32_t)0x01000000)           /*!< Half-word */
2923 #define UDMA_CHCTL_SRCSIZE_32                   ((uint32_t)0x02000000)           /*!< Word */
2924 #define UDMA_CHCTL_ARBSIZE_M                    ((uint32_t)0x0003C000)           /*!< Arbitration Size */
2925 #define UDMA_CHCTL_ARBSIZE_1                    ((uint32_t)0x00000000)           /*!< 1 Transfer */
2926 #define UDMA_CHCTL_ARBSIZE_2                    ((uint32_t)0x00004000)           /*!< 2 Transfers */
2927 #define UDMA_CHCTL_ARBSIZE_4                    ((uint32_t)0x00008000)           /*!< 4 Transfers */
2928 #define UDMA_CHCTL_ARBSIZE_8                    ((uint32_t)0x0000C000)           /*!< 8 Transfers */
2929 #define UDMA_CHCTL_ARBSIZE_16                   ((uint32_t)0x00010000)           /*!< 16 Transfers */
2930 #define UDMA_CHCTL_ARBSIZE_32                   ((uint32_t)0x00014000)           /*!< 32 Transfers */
2931 #define UDMA_CHCTL_ARBSIZE_64                   ((uint32_t)0x00018000)           /*!< 64 Transfers */
2932 #define UDMA_CHCTL_ARBSIZE_128                  ((uint32_t)0x0001C000)           /*!< 128 Transfers */
2933 #define UDMA_CHCTL_ARBSIZE_256                  ((uint32_t)0x00020000)           /*!< 256 Transfers */
2934 #define UDMA_CHCTL_ARBSIZE_512                  ((uint32_t)0x00024000)           /*!< 512 Transfers */
2935 #define UDMA_CHCTL_ARBSIZE_1024                 ((uint32_t)0x00028000)           /*!< 1024 Transfers */
2936 #define UDMA_CHCTL_XFERSIZE_M                   ((uint32_t)0x00003FF0)           /*!< Transfer Size (minus 1) */
2937 #define UDMA_CHCTL_NXTUSEBURST                  ((uint32_t)0x00000008)           /*!< Next Useburst */
2938 #define UDMA_CHCTL_XFERMODE_M                   ((uint32_t)0x00000007)           /*!< uDMA Transfer Mode */
2939 #define UDMA_CHCTL_XFERMODE_STOP                ((uint32_t)0x00000000)           /*!< Stop */
2940 #define UDMA_CHCTL_XFERMODE_BASIC               ((uint32_t)0x00000001)           /*!< Basic */
2941 #define UDMA_CHCTL_XFERMODE_AUTO                ((uint32_t)0x00000002)           /*!< Auto-Request */
2942 #define UDMA_CHCTL_XFERMODE_PINGPONG            ((uint32_t)0x00000003)           /*!< Ping-Pong */
2943 #define UDMA_CHCTL_XFERMODE_MEM_SG              ((uint32_t)0x00000004)           /*!< Memory Scatter-Gather */
2944 #define UDMA_CHCTL_XFERMODE_MEM_SGA             ((uint32_t)0x00000005)           /*!< Alternate Memory Scatter-Gather */
2945 #define UDMA_CHCTL_XFERMODE_PER_SG              ((uint32_t)0x00000006)           /*!< Peripheral Scatter-Gather */
2946 #define UDMA_CHCTL_XFERMODE_PER_SGA             ((uint32_t)0x00000007)           /*!< Alternate Peripheral Scatter-Gather */
2947 #define UDMA_CHCTL_XFERSIZE_S                   ( 4)
2948 #define EUSCI_A_CTLW0_SWRST_OFS                  ( 0)                            /*!< UCSWRST Bit Offset */
2949 #define EUSCI_A_CTLW0_SWRST                      ((uint16_t)0x0001)              /*!< Software reset enable */
2950 #define EUSCI_A_CTLW0_TXBRK_OFS                  ( 1)                            /*!< UCTXBRK Bit Offset */
2951 #define EUSCI_A_CTLW0_TXBRK                      ((uint16_t)0x0002)              /*!< Transmit break */
2952 #define EUSCI_A_CTLW0_TXADDR_OFS                 ( 2)                            /*!< UCTXADDR Bit Offset */
2953 #define EUSCI_A_CTLW0_TXADDR                     ((uint16_t)0x0004)              /*!< Transmit address */
2954 #define EUSCI_A_CTLW0_DORM_OFS                   ( 3)                            /*!< UCDORM Bit Offset */
2955 #define EUSCI_A_CTLW0_DORM                       ((uint16_t)0x0008)              /*!< Dormant */
2956 #define EUSCI_A_CTLW0_BRKIE_OFS                  ( 4)                            /*!< UCBRKIE Bit Offset */
2957 #define EUSCI_A_CTLW0_BRKIE                      ((uint16_t)0x0010)              /*!< Receive break character interrupt enable */
2958 #define EUSCI_A_CTLW0_RXEIE_OFS                  ( 5)                            /*!< UCRXEIE Bit Offset */
2959 #define EUSCI_A_CTLW0_RXEIE                      ((uint16_t)0x0020)              /*!< Receive erroneous-character interrupt enable */
2960 #define EUSCI_A_CTLW0_SSEL_OFS                   ( 6)                            /*!< UCSSEL Bit Offset */
2961 #define EUSCI_A_CTLW0_SSEL_MASK                  ((uint16_t)0x00C0)              /*!< UCSSEL Bit Mask */
2962 #define EUSCI_A_CTLW0_SSEL0                      ((uint16_t)0x0040)              /*!< SSEL Bit 0 */
2963 #define EUSCI_A_CTLW0_SSEL1                      ((uint16_t)0x0080)              /*!< SSEL Bit 1 */
2964 #define EUSCI_A_CTLW0_UCSSEL_0                   ((uint16_t)0x0000)              /*!< UCLK */
2965 #define EUSCI_A_CTLW0_UCSSEL_1                   ((uint16_t)0x0040)              /*!< ACLK */
2966 #define EUSCI_A_CTLW0_UCSSEL_2                   ((uint16_t)0x0080)              /*!< SMCLK */
2967 #define EUSCI_A_CTLW0_SSEL__UCLK                 ((uint16_t)0x0000)              /*!< UCLK */
2968 #define EUSCI_A_CTLW0_SSEL__ACLK                 ((uint16_t)0x0040)              /*!< ACLK */
2969 #define EUSCI_A_CTLW0_SSEL__SMCLK                ((uint16_t)0x0080)              /*!< SMCLK */
2970 #define EUSCI_A_CTLW0_SYNC_OFS                   ( 8)                            /*!< UCSYNC Bit Offset */
2971 #define EUSCI_A_CTLW0_SYNC                       ((uint16_t)0x0100)              /*!< Synchronous mode enable */
2972 #define EUSCI_A_CTLW0_MODE_OFS                   ( 9)                            /*!< UCMODE Bit Offset */
2973 #define EUSCI_A_CTLW0_MODE_MASK                  ((uint16_t)0x0600)              /*!< UCMODE Bit Mask */
2974 #define EUSCI_A_CTLW0_MODE0                      ((uint16_t)0x0200)              /*!< MODE Bit 0 */
2975 #define EUSCI_A_CTLW0_MODE1                      ((uint16_t)0x0400)              /*!< MODE Bit 1 */
2976 #define EUSCI_A_CTLW0_MODE_0                     ((uint16_t)0x0000)              /*!< UART mode */
2977 #define EUSCI_A_CTLW0_MODE_1                     ((uint16_t)0x0200)              /*!< Idle-line multiprocessor mode */
2978 #define EUSCI_A_CTLW0_MODE_2                     ((uint16_t)0x0400)              /*!< Address-bit multiprocessor mode */
2979 #define EUSCI_A_CTLW0_MODE_3                     ((uint16_t)0x0600)              /*!< UART mode with automatic baud-rate detection */
2980 #define EUSCI_A_CTLW0_SPB_OFS                    (11)                            /*!< UCSPB Bit Offset */
2981 #define EUSCI_A_CTLW0_SPB                        ((uint16_t)0x0800)              /*!< Stop bit select */
2982 #define EUSCI_A_CTLW0_SEVENBIT_OFS               (12)                            /*!< UC7BIT Bit Offset */
2983 #define EUSCI_A_CTLW0_SEVENBIT                   ((uint16_t)0x1000)              /*!< Character length */
2984 #define EUSCI_A_CTLW0_MSB_OFS                    (13)                            /*!< UCMSB Bit Offset */
2985 #define EUSCI_A_CTLW0_MSB                        ((uint16_t)0x2000)              /*!< MSB first select */
2986 #define EUSCI_A_CTLW0_PAR_OFS                    (14)                            /*!< UCPAR Bit Offset */
2987 #define EUSCI_A_CTLW0_PAR                        ((uint16_t)0x4000)              /*!< Parity select */
2988 #define EUSCI_A_CTLW0_PEN_OFS                    (15)                            /*!< UCPEN Bit Offset */
2989 #define EUSCI_A_CTLW0_PEN                        ((uint16_t)0x8000)              /*!< Parity enable */
2990 #define EUSCI_A_CTLW0_STEM_OFS                   ( 1)                            /*!< UCSTEM Bit Offset */
2991 #define EUSCI_A_CTLW0_STEM                       ((uint16_t)0x0002)              /*!< STE mode select in master mode. */
2992 #define EUSCI_A_CTLW0_MST_OFS                    (11)                            /*!< UCMST Bit Offset */
2993 #define EUSCI_A_CTLW0_MST                        ((uint16_t)0x0800)              /*!< Master mode select */
2994 #define EUSCI_A_CTLW0_CKPL_OFS                   (14)                            /*!< UCCKPL Bit Offset */
2995 #define EUSCI_A_CTLW0_CKPL                       ((uint16_t)0x4000)              /*!< Clock polarity select */
2996 #define EUSCI_A_CTLW0_CKPH_OFS                   (15)                            /*!< UCCKPH Bit Offset */
2997 #define EUSCI_A_CTLW0_CKPH                       ((uint16_t)0x8000)              /*!< Clock phase select */
2998 #define EUSCI_A_CTLW1_GLIT_OFS                   ( 0)                            /*!< UCGLIT Bit Offset */
2999 #define EUSCI_A_CTLW1_GLIT_MASK                  ((uint16_t)0x0003)              /*!< UCGLIT Bit Mask */
3000 #define EUSCI_A_CTLW1_GLIT0                      ((uint16_t)0x0001)              /*!< GLIT Bit 0 */
3001 #define EUSCI_A_CTLW1_GLIT1                      ((uint16_t)0x0002)              /*!< GLIT Bit 1 */
3002 #define EUSCI_A_CTLW1_GLIT_0                     ((uint16_t)0x0000)              /*!< Approximately 2 ns (equivalent of 1 delay element) */
3003 #define EUSCI_A_CTLW1_GLIT_1                     ((uint16_t)0x0001)              /*!< Approximately 50 ns */
3004 #define EUSCI_A_CTLW1_GLIT_2                     ((uint16_t)0x0002)              /*!< Approximately 100 ns */
3005 #define EUSCI_A_CTLW1_GLIT_3                     ((uint16_t)0x0003)              /*!< Approximately 200 ns */
3006 #define EUSCI_A_MCTLW_OS16_OFS                   ( 0)                            /*!< UCOS16 Bit Offset */
3007 #define EUSCI_A_MCTLW_OS16                       ((uint16_t)0x0001)              /*!< Oversampling mode enabled */
3008 #define EUSCI_A_MCTLW_BRF_OFS                    ( 4)                            /*!< UCBRF Bit Offset */
3009 #define EUSCI_A_MCTLW_BRF_MASK                   ((uint16_t)0x00F0)              /*!< UCBRF Bit Mask */
3010 #define EUSCI_A_MCTLW_BRS_OFS                    ( 8)                            /*!< UCBRS Bit Offset */
3011 #define EUSCI_A_MCTLW_BRS_MASK                   ((uint16_t)0xFF00)              /*!< UCBRS Bit Mask */
3012 #define EUSCI_A_STATW_BUSY_OFS                   ( 0)                            /*!< UCBUSY Bit Offset */
3013 #define EUSCI_A_STATW_BUSY                       ((uint16_t)0x0001)              /*!< eUSCI_A busy */
3014 #define EUSCI_A_STATW_ADDR_IDLE_OFS              ( 1)                            /*!< UCADDR_UCIDLE Bit Offset */
3015 #define EUSCI_A_STATW_ADDR_IDLE                  ((uint16_t)0x0002)              /*!< Address received / Idle line detected */
3016 #define EUSCI_A_STATW_RXERR_OFS                  ( 2)                            /*!< UCRXERR Bit Offset */
3017 #define EUSCI_A_STATW_RXERR                      ((uint16_t)0x0004)              /*!< Receive error flag */
3018 #define EUSCI_A_STATW_BRK_OFS                    ( 3)                            /*!< UCBRK Bit Offset */
3019 #define EUSCI_A_STATW_BRK                        ((uint16_t)0x0008)              /*!< Break detect flag */
3020 #define EUSCI_A_STATW_PE_OFS                     ( 4)                            /*!< UCPE Bit Offset */
3021 #define EUSCI_A_STATW_PE                         ((uint16_t)0x0010)
3022 #define EUSCI_A_STATW_OE_OFS                     ( 5)                            /*!< UCOE Bit Offset */
3023 #define EUSCI_A_STATW_OE                         ((uint16_t)0x0020)              /*!< Overrun error flag */
3024 #define EUSCI_A_STATW_FE_OFS                     ( 6)                            /*!< UCFE Bit Offset */
3025 #define EUSCI_A_STATW_FE                         ((uint16_t)0x0040)              /*!< Framing error flag */
3026 #define EUSCI_A_STATW_LISTEN_OFS                 ( 7)                            /*!< UCLISTEN Bit Offset */
3027 #define EUSCI_A_STATW_LISTEN                     ((uint16_t)0x0080)              /*!< Listen enable */
3028 #define EUSCI_A_STATW_SPI_BUSY_OFS               ( 0)                            /*!< UCBUSY Bit Offset */
3029 #define EUSCI_A_STATW_SPI_BUSY                   ((uint16_t)0x0001)              /*!< eUSCI_A busy */
3030 #define EUSCI_A_RXBUF_RXBUF_OFS                  ( 0)                            /*!< UCRXBUF Bit Offset */
3031 #define EUSCI_A_RXBUF_RXBUF_MASK                 ((uint16_t)0x00FF)              /*!< UCRXBUF Bit Mask */
3032 #define EUSCI_A_TXBUF_TXBUF_OFS                  ( 0)                            /*!< UCTXBUF Bit Offset */
3033 #define EUSCI_A_TXBUF_TXBUF_MASK                 ((uint16_t)0x00FF)              /*!< UCTXBUF Bit Mask */
3034 #define EUSCI_A_ABCTL_ABDEN_OFS                  ( 0)                            /*!< UCABDEN Bit Offset */
3035 #define EUSCI_A_ABCTL_ABDEN                      ((uint16_t)0x0001)              /*!< Automatic baud-rate detect enable */
3036 #define EUSCI_A_ABCTL_BTOE_OFS                   ( 2)                            /*!< UCBTOE Bit Offset */
3037 #define EUSCI_A_ABCTL_BTOE                       ((uint16_t)0x0004)              /*!< Break time out error */
3038 #define EUSCI_A_ABCTL_STOE_OFS                   ( 3)                            /*!< UCSTOE Bit Offset */
3039 #define EUSCI_A_ABCTL_STOE                       ((uint16_t)0x0008)              /*!< Synch field time out error */
3040 #define EUSCI_A_ABCTL_DELIM_OFS                  ( 4)                            /*!< UCDELIM Bit Offset */
3041 #define EUSCI_A_ABCTL_DELIM_MASK                 ((uint16_t)0x0030)              /*!< UCDELIM Bit Mask */
3042 #define EUSCI_A_ABCTL_DELIM0                     ((uint16_t)0x0010)              /*!< DELIM Bit 0 */
3043 #define EUSCI_A_ABCTL_DELIM1                     ((uint16_t)0x0020)              /*!< DELIM Bit 1 */
3044 #define EUSCI_A_ABCTL_DELIM_0                    ((uint16_t)0x0000)              /*!< 1 bit time */
3045 #define EUSCI_A_ABCTL_DELIM_1                    ((uint16_t)0x0010)              /*!< 2 bit times */
3046 #define EUSCI_A_ABCTL_DELIM_2                    ((uint16_t)0x0020)              /*!< 3 bit times */
3047 #define EUSCI_A_ABCTL_DELIM_3                    ((uint16_t)0x0030)              /*!< 4 bit times */
3048 #define EUSCI_A_IRCTL_IREN_OFS                   ( 0)                            /*!< UCIREN Bit Offset */
3049 #define EUSCI_A_IRCTL_IREN                       ((uint16_t)0x0001)              /*!< IrDA encoder/decoder enable */
3050 #define EUSCI_A_IRCTL_IRTXCLK_OFS                ( 1)                            /*!< UCIRTXCLK Bit Offset */
3051 #define EUSCI_A_IRCTL_IRTXCLK                    ((uint16_t)0x0002)              /*!< IrDA transmit pulse clock select */
3052 #define EUSCI_A_IRCTL_IRTXPL_OFS                 ( 2)                            /*!< UCIRTXPL Bit Offset */
3053 #define EUSCI_A_IRCTL_IRTXPL_MASK                ((uint16_t)0x00FC)              /*!< UCIRTXPL Bit Mask */
3054 #define EUSCI_A_IRCTL_IRRXFE_OFS                 ( 8)                            /*!< UCIRRXFE Bit Offset */
3055 #define EUSCI_A_IRCTL_IRRXFE                     ((uint16_t)0x0100)              /*!< IrDA receive filter enabled */
3056 #define EUSCI_A_IRCTL_IRRXPL_OFS                 ( 9)                            /*!< UCIRRXPL Bit Offset */
3057 #define EUSCI_A_IRCTL_IRRXPL                     ((uint16_t)0x0200)              /*!< IrDA receive input UCAxRXD polarity */
3058 #define EUSCI_A_IRCTL_IRRXFL_OFS                 (10)                            /*!< UCIRRXFL Bit Offset */
3059 #define EUSCI_A_IRCTL_IRRXFL_MASK                ((uint16_t)0x3C00)              /*!< UCIRRXFL Bit Mask */
3060 #define EUSCI_A_IE_RXIE_OFS                      ( 0)                            /*!< UCRXIE Bit Offset */
3061 #define EUSCI_A_IE_RXIE                          ((uint16_t)0x0001)              /*!< Receive interrupt enable */
3062 #define EUSCI_A_IE_TXIE_OFS                      ( 1)                            /*!< UCTXIE Bit Offset */
3063 #define EUSCI_A_IE_TXIE                          ((uint16_t)0x0002)              /*!< Transmit interrupt enable */
3064 #define EUSCI_A_IE_STTIE_OFS                     ( 2)                            /*!< UCSTTIE Bit Offset */
3065 #define EUSCI_A_IE_STTIE                         ((uint16_t)0x0004)              /*!< Start bit interrupt enable */
3066 #define EUSCI_A_IE_TXCPTIE_OFS                   ( 3)                            /*!< UCTXCPTIE Bit Offset */
3067 #define EUSCI_A_IE_TXCPTIE                       ((uint16_t)0x0008)              /*!< Transmit complete interrupt enable */
3068 #define EUSCI_A_IFG_RXIFG_OFS                    ( 0)                            /*!< UCRXIFG Bit Offset */
3069 #define EUSCI_A_IFG_RXIFG                        ((uint16_t)0x0001)              /*!< Receive interrupt flag */
3070 #define EUSCI_A_IFG_TXIFG_OFS                    ( 1)                            /*!< UCTXIFG Bit Offset */
3071 #define EUSCI_A_IFG_TXIFG                        ((uint16_t)0x0002)              /*!< Transmit interrupt flag */
3072 #define EUSCI_A_IFG_STTIFG_OFS                   ( 2)                            /*!< UCSTTIFG Bit Offset */
3073 #define EUSCI_A_IFG_STTIFG                       ((uint16_t)0x0004)              /*!< Start bit interrupt flag */
3074 #define EUSCI_A_IFG_TXCPTIFG_OFS                 ( 3)                            /*!< UCTXCPTIFG Bit Offset */
3075 #define EUSCI_A_IFG_TXCPTIFG                     ((uint16_t)0x0008)              /*!< Transmit ready interrupt enable */
3076 #define EUSCI_A__RXIE_OFS                        EUSCI_A_IE_RXIE_OFS             /*!< UCRXIE Bit Offset */
3077 #define EUSCI_A__RXIE                            EUSCI_A_IE_RXIE                 /*!< Receive interrupt enable */
3078 #define EUSCI_A__TXIE_OFS                        EUSCI_A_IE_TXIE_OFS             /*!< UCTXIE Bit Offset */
3079 #define EUSCI_A__TXIE                            EUSCI_A_IE_TXIE                 /*!< Transmit interrupt enable */
3080 #define EUSCI_B_CTLW0_SWRST_OFS                  ( 0)                            /*!< UCSWRST Bit Offset */
3081 #define EUSCI_B_CTLW0_SWRST                      ((uint16_t)0x0001)              /*!< Software reset enable */
3082 #define EUSCI_B_CTLW0_TXSTT_OFS                  ( 1)                            /*!< UCTXSTT Bit Offset */
3083 #define EUSCI_B_CTLW0_TXSTT                      ((uint16_t)0x0002)              /*!< Transmit START condition in master mode */
3084 #define EUSCI_B_CTLW0_TXSTP_OFS                  ( 2)                            /*!< UCTXSTP Bit Offset */
3085 #define EUSCI_B_CTLW0_TXSTP                      ((uint16_t)0x0004)              /*!< Transmit STOP condition in master mode */
3086 #define EUSCI_B_CTLW0_TXNACK_OFS                 ( 3)                            /*!< UCTXNACK Bit Offset */
3087 #define EUSCI_B_CTLW0_TXNACK                     ((uint16_t)0x0008)              /*!< Transmit a NACK */
3088 #define EUSCI_B_CTLW0_TR_OFS                     ( 4)                            /*!< UCTR Bit Offset */
3089 #define EUSCI_B_CTLW0_TR                         ((uint16_t)0x0010)              /*!< Transmitter/receiver */
3090 #define EUSCI_B_CTLW0_TXACK_OFS                  ( 5)                            /*!< UCTXACK Bit Offset */
3091 #define EUSCI_B_CTLW0_TXACK                      ((uint16_t)0x0020)              /*!< Transmit ACK condition in slave mode */
3092 #define EUSCI_B_CTLW0_SSEL_OFS                   ( 6)                            /*!< UCSSEL Bit Offset */
3093 #define EUSCI_B_CTLW0_SSEL_MASK                  ((uint16_t)0x00C0)              /*!< UCSSEL Bit Mask */
3094 #define EUSCI_B_CTLW0_SSEL0                      ((uint16_t)0x0040)              /*!< SSEL Bit 0 */
3095 #define EUSCI_B_CTLW0_SSEL1                      ((uint16_t)0x0080)              /*!< SSEL Bit 1 */
3096 #define EUSCI_B_CTLW0_UCSSEL_0                   ((uint16_t)0x0000)              /*!< UCLKI */
3097 #define EUSCI_B_CTLW0_UCSSEL_1                   ((uint16_t)0x0040)              /*!< ACLK */
3098 #define EUSCI_B_CTLW0_UCSSEL_2                   ((uint16_t)0x0080)              /*!< SMCLK */
3099 #define EUSCI_B_CTLW0_UCSSEL_3                   ((uint16_t)0x00C0)              /*!< SMCLK */
3100 #define EUSCI_B_CTLW0_SSEL__UCLKI                ((uint16_t)0x0000)              /*!< UCLKI */
3101 #define EUSCI_B_CTLW0_SSEL__ACLK                 ((uint16_t)0x0040)              /*!< ACLK */
3102 #define EUSCI_B_CTLW0_SSEL__SMCLK                ((uint16_t)0x0080)              /*!< SMCLK */
3103 #define EUSCI_B_CTLW0_SYNC_OFS                   ( 8)                            /*!< UCSYNC Bit Offset */
3104 #define EUSCI_B_CTLW0_SYNC                       ((uint16_t)0x0100)              /*!< Synchronous mode enable */
3105 #define EUSCI_B_CTLW0_MODE_OFS                   ( 9)                            /*!< UCMODE Bit Offset */
3106 #define EUSCI_B_CTLW0_MODE_MASK                  ((uint16_t)0x0600)              /*!< UCMODE Bit Mask */
3107 #define EUSCI_B_CTLW0_MODE0                      ((uint16_t)0x0200)              /*!< MODE Bit 0 */
3108 #define EUSCI_B_CTLW0_MODE1                      ((uint16_t)0x0400)              /*!< MODE Bit 1 */
3109 #define EUSCI_B_CTLW0_MODE_0                     ((uint16_t)0x0000)              /*!< 3-pin SPI */
3110 #define EUSCI_B_CTLW0_MODE_1                     ((uint16_t)0x0200)              /*!< 4-pin SPI (master or slave enabled if STE = 1) */
3111 #define EUSCI_B_CTLW0_MODE_2                     ((uint16_t)0x0400)              /*!< 4-pin SPI (master or slave enabled if STE = 0) */
3112 #define EUSCI_B_CTLW0_MODE_3                     ((uint16_t)0x0600)              /*!< I2C mode */
3113 #define EUSCI_B_CTLW0_MST_OFS                    (11)                            /*!< UCMST Bit Offset */
3114 #define EUSCI_B_CTLW0_MST                        ((uint16_t)0x0800)              /*!< Master mode select */
3115 #define EUSCI_B_CTLW0_MM_OFS                     (13)                            /*!< UCMM Bit Offset */
3116 #define EUSCI_B_CTLW0_MM                         ((uint16_t)0x2000)              /*!< Multi-master environment select */
3117 #define EUSCI_B_CTLW0_SLA10_OFS                  (14)                            /*!< UCSLA10 Bit Offset */
3118 #define EUSCI_B_CTLW0_SLA10                      ((uint16_t)0x4000)              /*!< Slave addressing mode select */
3119 #define EUSCI_B_CTLW0_A10_OFS                    (15)                            /*!< UCA10 Bit Offset */
3120 #define EUSCI_B_CTLW0_A10                        ((uint16_t)0x8000)              /*!< Own addressing mode select */
3121 #define EUSCI_B_CTLW0_STEM_OFS                   ( 1)                            /*!< UCSTEM Bit Offset */
3122 #define EUSCI_B_CTLW0_STEM                       ((uint16_t)0x0002)              /*!< STE mode select in master mode. */
3123 #define EUSCI_B_CTLW0_SEVENBIT_OFS               (12)                            /*!< UC7BIT Bit Offset */
3124 #define EUSCI_B_CTLW0_SEVENBIT                   ((uint16_t)0x1000)              /*!< Character length */
3125 #define EUSCI_B_CTLW0_MSB_OFS                    (13)                            /*!< UCMSB Bit Offset */
3126 #define EUSCI_B_CTLW0_MSB                        ((uint16_t)0x2000)              /*!< MSB first select */
3127 #define EUSCI_B_CTLW0_CKPL_OFS                   (14)                            /*!< UCCKPL Bit Offset */
3128 #define EUSCI_B_CTLW0_CKPL                       ((uint16_t)0x4000)              /*!< Clock polarity select */
3129 #define EUSCI_B_CTLW0_CKPH_OFS                   (15)                            /*!< UCCKPH Bit Offset */
3130 #define EUSCI_B_CTLW0_CKPH                       ((uint16_t)0x8000)              /*!< Clock phase select */
3131 #define EUSCI_B_CTLW1_GLIT_OFS                   ( 0)                            /*!< UCGLIT Bit Offset */
3132 #define EUSCI_B_CTLW1_GLIT_MASK                  ((uint16_t)0x0003)              /*!< UCGLIT Bit Mask */
3133 #define EUSCI_B_CTLW1_GLIT0                      ((uint16_t)0x0001)              /*!< GLIT Bit 0 */
3134 #define EUSCI_B_CTLW1_GLIT1                      ((uint16_t)0x0002)              /*!< GLIT Bit 1 */
3135 #define EUSCI_B_CTLW1_GLIT_0                     ((uint16_t)0x0000)              /*!< 50 ns */
3136 #define EUSCI_B_CTLW1_GLIT_1                     ((uint16_t)0x0001)              /*!< 25 ns */
3137 #define EUSCI_B_CTLW1_GLIT_2                     ((uint16_t)0x0002)              /*!< 12.5 ns */
3138 #define EUSCI_B_CTLW1_GLIT_3                     ((uint16_t)0x0003)              /*!< 6.25 ns */
3139 #define EUSCI_B_CTLW1_ASTP_OFS                   ( 2)                            /*!< UCASTP Bit Offset */
3140 #define EUSCI_B_CTLW1_ASTP_MASK                  ((uint16_t)0x000C)              /*!< UCASTP Bit Mask */
3141 #define EUSCI_B_CTLW1_ASTP0                      ((uint16_t)0x0004)              /*!< ASTP Bit 0 */
3142 #define EUSCI_B_CTLW1_ASTP1                      ((uint16_t)0x0008)              /*!< ASTP Bit 1 */
3143 #define EUSCI_B_CTLW1_ASTP_0                     ((uint16_t)0x0000)              /*!< No automatic STOP generation. The STOP condition is generated after the user  */
3144 #define EUSCI_B_CTLW1_ASTP_1                     ((uint16_t)0x0004)              /*!< UCBCNTIFG is set with the byte counter reaches the threshold defined in  */
3145 #define EUSCI_B_CTLW1_ASTP_2                     ((uint16_t)0x0008)              /*!< A STOP condition is generated automatically after the byte counter value  */
3146 #define EUSCI_B_CTLW1_SWACK_OFS                  ( 4)                            /*!< UCSWACK Bit Offset */
3147 #define EUSCI_B_CTLW1_SWACK                      ((uint16_t)0x0010)              /*!< SW or HW ACK control */
3148 #define EUSCI_B_CTLW1_STPNACK_OFS                ( 5)                            /*!< UCSTPNACK Bit Offset */
3149 #define EUSCI_B_CTLW1_STPNACK                    ((uint16_t)0x0020)              /*!< ACK all master bytes */
3150 #define EUSCI_B_CTLW1_CLTO_OFS                   ( 6)                            /*!< UCCLTO Bit Offset */
3151 #define EUSCI_B_CTLW1_CLTO_MASK                  ((uint16_t)0x00C0)              /*!< UCCLTO Bit Mask */
3152 #define EUSCI_B_CTLW1_CLTO0                      ((uint16_t)0x0040)              /*!< CLTO Bit 0 */
3153 #define EUSCI_B_CTLW1_CLTO1                      ((uint16_t)0x0080)              /*!< CLTO Bit 1 */
3154 #define EUSCI_B_CTLW1_CLTO_0                     ((uint16_t)0x0000)              /*!< Disable clock low timeout counter */
3155 #define EUSCI_B_CTLW1_CLTO_1                     ((uint16_t)0x0040)              /*!< 135 000 SYSCLK cycles (approximately 28 ms) */
3156 #define EUSCI_B_CTLW1_CLTO_2                     ((uint16_t)0x0080)              /*!< 150 000 SYSCLK cycles (approximately 31 ms) */
3157 #define EUSCI_B_CTLW1_CLTO_3                     ((uint16_t)0x00C0)              /*!< 165 000 SYSCLK cycles (approximately 34 ms) */
3158 #define EUSCI_B_CTLW1_ETXINT_OFS                 ( 8)                            /*!< UCETXINT Bit Offset */
3159 #define EUSCI_B_CTLW1_ETXINT                     ((uint16_t)0x0100)              /*!< Early UCTXIFG0 */
3160 #define EUSCI_B_STATW_BBUSY_OFS                  ( 4)                            /*!< UCBBUSY Bit Offset */
3161 #define EUSCI_B_STATW_BBUSY                      ((uint16_t)0x0010)              /*!< Bus busy */
3162 #define EUSCI_B_STATW_GC_OFS                     ( 5)                            /*!< UCGC Bit Offset */
3163 #define EUSCI_B_STATW_GC                         ((uint16_t)0x0020)              /*!< General call address received */
3164 #define EUSCI_B_STATW_SCLLOW_OFS                 ( 6)                            /*!< UCSCLLOW Bit Offset */
3165 #define EUSCI_B_STATW_SCLLOW                     ((uint16_t)0x0040)              /*!< SCL low */
3166 #define EUSCI_B_STATW_BCNT_OFS                   ( 8)                            /*!< UCBCNT Bit Offset */
3167 #define EUSCI_B_STATW_BCNT_MASK                  ((uint16_t)0xFF00)              /*!< UCBCNT Bit Mask */
3168 #define EUSCI_B_STATW_SPI_BUSY_OFS               ( 0)                            /*!< UCBUSY Bit Offset */
3169 #define EUSCI_B_STATW_SPI_BUSY                   ((uint16_t)0x0001)              /*!< eUSCI_B busy */
3170 #define EUSCI_B_STATW_OE_OFS                     ( 5)                            /*!< UCOE Bit Offset */
3171 #define EUSCI_B_STATW_OE                         ((uint16_t)0x0020)              /*!< Overrun error flag */
3172 #define EUSCI_B_STATW_FE_OFS                     ( 6)                            /*!< UCFE Bit Offset */
3173 #define EUSCI_B_STATW_FE                         ((uint16_t)0x0040)              /*!< Framing error flag */
3174 #define EUSCI_B_STATW_LISTEN_OFS                 ( 7)                            /*!< UCLISTEN Bit Offset */
3175 #define EUSCI_B_STATW_LISTEN                     ((uint16_t)0x0080)              /*!< Listen enable */
3176 #define EUSCI_B_TBCNT_TBCNT_OFS                  ( 0)                            /*!< UCTBCNT Bit Offset */
3177 #define EUSCI_B_TBCNT_TBCNT_MASK                 ((uint16_t)0x00FF)              /*!< UCTBCNT Bit Mask */
3178 #define EUSCI_B_RXBUF_RXBUF_OFS                  ( 0)                            /*!< UCRXBUF Bit Offset */
3179 #define EUSCI_B_RXBUF_RXBUF_MASK                 ((uint16_t)0x00FF)              /*!< UCRXBUF Bit Mask */
3180 #define EUSCI_B_TXBUF_TXBUF_OFS                  ( 0)                            /*!< UCTXBUF Bit Offset */
3181 #define EUSCI_B_TXBUF_TXBUF_MASK                 ((uint16_t)0x00FF)              /*!< UCTXBUF Bit Mask */
3182 #define EUSCI_B_I2COA0_I2COA0_OFS                ( 0)                            /*!< I2COA0 Bit Offset */
3183 #define EUSCI_B_I2COA0_I2COA0_MASK               ((uint16_t)0x03FF)              /*!< I2COA0 Bit Mask */
3184 #define EUSCI_B_I2COA0_OAEN_OFS                  (10)                            /*!< UCOAEN Bit Offset */
3185 #define EUSCI_B_I2COA0_OAEN                      ((uint16_t)0x0400)              /*!< Own Address enable register */
3186 #define EUSCI_B_I2COA0_GCEN_OFS                  (15)                            /*!< UCGCEN Bit Offset */
3187 #define EUSCI_B_I2COA0_GCEN                      ((uint16_t)0x8000)              /*!< General call response enable */
3188 #define EUSCI_B_I2COA1_I2COA1_OFS                ( 0)                            /*!< I2COA1 Bit Offset */
3189 #define EUSCI_B_I2COA1_I2COA1_MASK               ((uint16_t)0x03FF)              /*!< I2COA1 Bit Mask */
3190 #define EUSCI_B_I2COA1_OAEN_OFS                  (10)                            /*!< UCOAEN Bit Offset */
3191 #define EUSCI_B_I2COA1_OAEN                      ((uint16_t)0x0400)              /*!< Own Address enable register */
3192 #define EUSCI_B_I2COA2_I2COA2_OFS                ( 0)                            /*!< I2COA2 Bit Offset */
3193 #define EUSCI_B_I2COA2_I2COA2_MASK               ((uint16_t)0x03FF)              /*!< I2COA2 Bit Mask */
3194 #define EUSCI_B_I2COA2_OAEN_OFS                  (10)                            /*!< UCOAEN Bit Offset */
3195 #define EUSCI_B_I2COA2_OAEN                      ((uint16_t)0x0400)              /*!< Own Address enable register */
3196 #define EUSCI_B_I2COA3_I2COA3_OFS                ( 0)                            /*!< I2COA3 Bit Offset */
3197 #define EUSCI_B_I2COA3_I2COA3_MASK               ((uint16_t)0x03FF)              /*!< I2COA3 Bit Mask */
3198 #define EUSCI_B_I2COA3_OAEN_OFS                  (10)                            /*!< UCOAEN Bit Offset */
3199 #define EUSCI_B_I2COA3_OAEN                      ((uint16_t)0x0400)              /*!< Own Address enable register */
3200 #define EUSCI_B_ADDRX_ADDRX_OFS                  ( 0)                            /*!< ADDRX Bit Offset */
3201 #define EUSCI_B_ADDRX_ADDRX_MASK                 ((uint16_t)0x03FF)              /*!< ADDRX Bit Mask */
3202 #define EUSCI_B_ADDRX_ADDRX0                     ((uint16_t)0x0001)              /*!< ADDRX Bit 0 */
3203 #define EUSCI_B_ADDRX_ADDRX1                     ((uint16_t)0x0002)              /*!< ADDRX Bit 1 */
3204 #define EUSCI_B_ADDRX_ADDRX2                     ((uint16_t)0x0004)              /*!< ADDRX Bit 2 */
3205 #define EUSCI_B_ADDRX_ADDRX3                     ((uint16_t)0x0008)              /*!< ADDRX Bit 3 */
3206 #define EUSCI_B_ADDRX_ADDRX4                     ((uint16_t)0x0010)              /*!< ADDRX Bit 4 */
3207 #define EUSCI_B_ADDRX_ADDRX5                     ((uint16_t)0x0020)              /*!< ADDRX Bit 5 */
3208 #define EUSCI_B_ADDRX_ADDRX6                     ((uint16_t)0x0040)              /*!< ADDRX Bit 6 */
3209 #define EUSCI_B_ADDRX_ADDRX7                     ((uint16_t)0x0080)              /*!< ADDRX Bit 7 */
3210 #define EUSCI_B_ADDRX_ADDRX8                     ((uint16_t)0x0100)              /*!< ADDRX Bit 8 */
3211 #define EUSCI_B_ADDRX_ADDRX9                     ((uint16_t)0x0200)              /*!< ADDRX Bit 9 */
3212 #define EUSCI_B_ADDMASK_ADDMASK_OFS              ( 0)                            /*!< ADDMASK Bit Offset */
3213 #define EUSCI_B_ADDMASK_ADDMASK_MASK             ((uint16_t)0x03FF)              /*!< ADDMASK Bit Mask */
3214 #define EUSCI_B_I2CSA_I2CSA_OFS                  ( 0)                            /*!< I2CSA Bit Offset */
3215 #define EUSCI_B_I2CSA_I2CSA_MASK                 ((uint16_t)0x03FF)              /*!< I2CSA Bit Mask */
3216 #define EUSCI_B_IE_RXIE0_OFS                     ( 0)                            /*!< UCRXIE0 Bit Offset */
3217 #define EUSCI_B_IE_RXIE0                         ((uint16_t)0x0001)              /*!< Receive interrupt enable 0 */
3218 #define EUSCI_B_IE_TXIE0_OFS                     ( 1)                            /*!< UCTXIE0 Bit Offset */
3219 #define EUSCI_B_IE_TXIE0                         ((uint16_t)0x0002)              /*!< Transmit interrupt enable 0 */
3220 #define EUSCI_B_IE_STTIE_OFS                     ( 2)                            /*!< UCSTTIE Bit Offset */
3221 #define EUSCI_B_IE_STTIE                         ((uint16_t)0x0004)              /*!< START condition interrupt enable */
3222 #define EUSCI_B_IE_STPIE_OFS                     ( 3)                            /*!< UCSTPIE Bit Offset */
3223 #define EUSCI_B_IE_STPIE                         ((uint16_t)0x0008)              /*!< STOP condition interrupt enable */
3224 #define EUSCI_B_IE_ALIE_OFS                      ( 4)                            /*!< UCALIE Bit Offset */
3225 #define EUSCI_B_IE_ALIE                          ((uint16_t)0x0010)              /*!< Arbitration lost interrupt enable */
3226 #define EUSCI_B_IE_NACKIE_OFS                    ( 5)                            /*!< UCNACKIE Bit Offset */
3227 #define EUSCI_B_IE_NACKIE                        ((uint16_t)0x0020)              /*!< Not-acknowledge interrupt enable */
3228 #define EUSCI_B_IE_BCNTIE_OFS                    ( 6)                            /*!< UCBCNTIE Bit Offset */
3229 #define EUSCI_B_IE_BCNTIE                        ((uint16_t)0x0040)              /*!< Byte counter interrupt enable */
3230 #define EUSCI_B_IE_CLTOIE_OFS                    ( 7)                            /*!< UCCLTOIE Bit Offset */
3231 #define EUSCI_B_IE_CLTOIE                        ((uint16_t)0x0080)              /*!< Clock low timeout interrupt enable */
3232 #define EUSCI_B_IE_RXIE1_OFS                     ( 8)                            /*!< UCRXIE1 Bit Offset */
3233 #define EUSCI_B_IE_RXIE1                         ((uint16_t)0x0100)              /*!< Receive interrupt enable 1 */
3234 #define EUSCI_B_IE_TXIE1_OFS                     ( 9)                            /*!< UCTXIE1 Bit Offset */
3235 #define EUSCI_B_IE_TXIE1                         ((uint16_t)0x0200)              /*!< Transmit interrupt enable 1 */
3236 #define EUSCI_B_IE_RXIE2_OFS                     (10)                            /*!< UCRXIE2 Bit Offset */
3237 #define EUSCI_B_IE_RXIE2                         ((uint16_t)0x0400)              /*!< Receive interrupt enable 2 */
3238 #define EUSCI_B_IE_TXIE2_OFS                     (11)                            /*!< UCTXIE2 Bit Offset */
3239 #define EUSCI_B_IE_TXIE2                         ((uint16_t)0x0800)              /*!< Transmit interrupt enable 2 */
3240 #define EUSCI_B_IE_RXIE3_OFS                     (12)                            /*!< UCRXIE3 Bit Offset */
3241 #define EUSCI_B_IE_RXIE3                         ((uint16_t)0x1000)              /*!< Receive interrupt enable 3 */
3242 #define EUSCI_B_IE_TXIE3_OFS                     (13)                            /*!< UCTXIE3 Bit Offset */
3243 #define EUSCI_B_IE_TXIE3                         ((uint16_t)0x2000)              /*!< Transmit interrupt enable 3 */
3244 #define EUSCI_B_IE_BIT9IE_OFS                    (14)                            /*!< UCBIT9IE Bit Offset */
3245 #define EUSCI_B_IE_BIT9IE                        ((uint16_t)0x4000)              /*!< Bit position 9 interrupt enable */
3246 #define EUSCI_B_IE_RXIE_OFS                      ( 0)                            /*!< UCRXIE Bit Offset */
3247 #define EUSCI_B_IE_RXIE                          ((uint16_t)0x0001)              /*!< Receive interrupt enable */
3248 #define EUSCI_B_IE_TXIE_OFS                      ( 1)                            /*!< UCTXIE Bit Offset */
3249 #define EUSCI_B_IE_TXIE                          ((uint16_t)0x0002)              /*!< Transmit interrupt enable */
3250 #define EUSCI_B_IFG_RXIFG0_OFS                   ( 0)                            /*!< UCRXIFG0 Bit Offset */
3251 #define EUSCI_B_IFG_RXIFG0                       ((uint16_t)0x0001)              /*!< eUSCI_B receive interrupt flag 0 */
3252 #define EUSCI_B_IFG_TXIFG0_OFS                   ( 1)                            /*!< UCTXIFG0 Bit Offset */
3253 #define EUSCI_B_IFG_TXIFG0                       ((uint16_t)0x0002)              /*!< eUSCI_B transmit interrupt flag 0 */
3254 #define EUSCI_B_IFG_STTIFG_OFS                   ( 2)                            /*!< UCSTTIFG Bit Offset */
3255 #define EUSCI_B_IFG_STTIFG                       ((uint16_t)0x0004)              /*!< START condition interrupt flag */
3256 #define EUSCI_B_IFG_STPIFG_OFS                   ( 3)                            /*!< UCSTPIFG Bit Offset */
3257 #define EUSCI_B_IFG_STPIFG                       ((uint16_t)0x0008)              /*!< STOP condition interrupt flag */
3258 #define EUSCI_B_IFG_ALIFG_OFS                    ( 4)                            /*!< UCALIFG Bit Offset */
3259 #define EUSCI_B_IFG_ALIFG                        ((uint16_t)0x0010)              /*!< Arbitration lost interrupt flag */
3260 #define EUSCI_B_IFG_NACKIFG_OFS                  ( 5)                            /*!< UCNACKIFG Bit Offset */
3261 #define EUSCI_B_IFG_NACKIFG                      ((uint16_t)0x0020)              /*!< Not-acknowledge received interrupt flag */
3262 #define EUSCI_B_IFG_BCNTIFG_OFS                  ( 6)                            /*!< UCBCNTIFG Bit Offset */
3263 #define EUSCI_B_IFG_BCNTIFG                      ((uint16_t)0x0040)              /*!< Byte counter interrupt flag */
3264 #define EUSCI_B_IFG_CLTOIFG_OFS                  ( 7)                            /*!< UCCLTOIFG Bit Offset */
3265 #define EUSCI_B_IFG_CLTOIFG                      ((uint16_t)0x0080)              /*!< Clock low timeout interrupt flag */
3266 #define EUSCI_B_IFG_RXIFG1_OFS                   ( 8)                            /*!< UCRXIFG1 Bit Offset */
3267 #define EUSCI_B_IFG_RXIFG1                       ((uint16_t)0x0100)              /*!< eUSCI_B receive interrupt flag 1 */
3268 #define EUSCI_B_IFG_TXIFG1_OFS                   ( 9)                            /*!< UCTXIFG1 Bit Offset */
3269 #define EUSCI_B_IFG_TXIFG1                       ((uint16_t)0x0200)              /*!< eUSCI_B transmit interrupt flag 1 */
3270 #define EUSCI_B_IFG_RXIFG2_OFS                   (10)                            /*!< UCRXIFG2 Bit Offset */
3271 #define EUSCI_B_IFG_RXIFG2                       ((uint16_t)0x0400)              /*!< eUSCI_B receive interrupt flag 2 */
3272 #define EUSCI_B_IFG_TXIFG2_OFS                   (11)                            /*!< UCTXIFG2 Bit Offset */
3273 #define EUSCI_B_IFG_TXIFG2                       ((uint16_t)0x0800)              /*!< eUSCI_B transmit interrupt flag 2 */
3274 #define EUSCI_B_IFG_RXIFG3_OFS                   (12)                            /*!< UCRXIFG3 Bit Offset */
3275 #define EUSCI_B_IFG_RXIFG3                       ((uint16_t)0x1000)              /*!< eUSCI_B receive interrupt flag 3 */
3276 #define EUSCI_B_IFG_TXIFG3_OFS                   (13)                            /*!< UCTXIFG3 Bit Offset */
3277 #define EUSCI_B_IFG_TXIFG3                       ((uint16_t)0x2000)              /*!< eUSCI_B transmit interrupt flag 3 */
3278 #define EUSCI_B_IFG_BIT9IFG_OFS                  (14)                            /*!< UCBIT9IFG Bit Offset */
3279 #define EUSCI_B_IFG_BIT9IFG                      ((uint16_t)0x4000)              /*!< Bit position 9 interrupt flag */
3280 #define EUSCI_B_IFG_RXIFG_OFS                    ( 0)                            /*!< UCRXIFG Bit Offset */
3281 #define EUSCI_B_IFG_RXIFG                        ((uint16_t)0x0001)              /*!< Receive interrupt flag */
3282 #define EUSCI_B_IFG_TXIFG_OFS                    ( 1)                            /*!< UCTXIFG Bit Offset */
3283 #define EUSCI_B_IFG_TXIFG                        ((uint16_t)0x0002)              /*!< Transmit interrupt flag */
3284 #define EUSCI_B__RXIE_OFS                        EUSCI_B_IE_RXIE_OFS             /*!< UCRXIE Bit Offset */
3285 #define EUSCI_B__RXIE                            EUSCI_B_IE_RXIE                 /*!< Receive interrupt enable */
3286 #define EUSCI_B__TXIE_OFS                        EUSCI_B_IE_TXIE_OFS             /*!< UCTXIE Bit Offset */
3287 #define EUSCI_B__TXIE                            EUSCI_B_IE_TXIE                 /*!< Transmit interrupt enable */
3288 #define FLCTL_POWER_STAT_PSTAT_OFS               ( 0)                            /*!< PSTAT Bit Offset */
3289 #define FLCTL_POWER_STAT_PSTAT_MASK              ((uint32_t)0x00000007)          /*!< PSTAT Bit Mask */
3290 #define FLCTL_POWER_STAT_PSTAT0                  ((uint32_t)0x00000001)          /*!< PSTAT Bit 0 */
3291 #define FLCTL_POWER_STAT_PSTAT1                  ((uint32_t)0x00000002)          /*!< PSTAT Bit 1 */
3292 #define FLCTL_POWER_STAT_PSTAT2                  ((uint32_t)0x00000004)          /*!< PSTAT Bit 2 */
3293 #define FLCTL_POWER_STAT_PSTAT_0                 ((uint32_t)0x00000000)          /*!< Flash IP in power-down mode */
3294 #define FLCTL_POWER_STAT_PSTAT_1                 ((uint32_t)0x00000001)          /*!< Flash IP Vdd domain power-up in progress */
3295 #define FLCTL_POWER_STAT_PSTAT_2                 ((uint32_t)0x00000002)          /*!< PSS LDO_GOOD, IREF_OK and VREF_OK check in progress */
3296 #define FLCTL_POWER_STAT_PSTAT_3                 ((uint32_t)0x00000003)          /*!< Flash IP SAFE_LV check in progress */
3297 #define FLCTL_POWER_STAT_PSTAT_4                 ((uint32_t)0x00000004)          /*!< Flash IP Active */
3298 #define FLCTL_POWER_STAT_PSTAT_5                 ((uint32_t)0x00000005)          /*!< Flash IP Active in Low-Frequency Active and Low-Frequency LPM0 modes. */
3299 #define FLCTL_POWER_STAT_PSTAT_6                 ((uint32_t)0x00000006)          /*!< Flash IP in Standby mode */
3300 #define FLCTL_POWER_STAT_PSTAT_7                 ((uint32_t)0x00000007)          /*!< Flash IP in Current mirror boost state */
3301 #define FLCTL_POWER_STAT_LDOSTAT_OFS             ( 3)                            /*!< LDOSTAT Bit Offset */
3302 #define FLCTL_POWER_STAT_LDOSTAT                 ((uint32_t)0x00000008)          /*!< PSS FLDO GOOD status */
3303 #define FLCTL_POWER_STAT_VREFSTAT_OFS            ( 4)                            /*!< VREFSTAT Bit Offset */
3304 #define FLCTL_POWER_STAT_VREFSTAT                ((uint32_t)0x00000010)          /*!< PSS VREF stable status */
3305 #define FLCTL_POWER_STAT_IREFSTAT_OFS            ( 5)                            /*!< IREFSTAT Bit Offset */
3306 #define FLCTL_POWER_STAT_IREFSTAT                ((uint32_t)0x00000020)          /*!< PSS IREF stable status */
3307 #define FLCTL_POWER_STAT_TRIMSTAT_OFS            ( 6)                            /*!< TRIMSTAT Bit Offset */
3308 #define FLCTL_POWER_STAT_TRIMSTAT                ((uint32_t)0x00000040)          /*!< PSS trim done status */
3309 #define FLCTL_POWER_STAT_RD_2T_OFS               ( 7)                            /*!< RD_2T Bit Offset */
3310 #define FLCTL_POWER_STAT_RD_2T                   ((uint32_t)0x00000080)          /*!< Indicates if Flash is being accessed in 2T mode */
3311 #define FLCTL_BANK0_RDCTL_RD_MODE_OFS            ( 0)                            /*!< RD_MODE Bit Offset */
3312 #define FLCTL_BANK0_RDCTL_RD_MODE_MASK           ((uint32_t)0x0000000F)          /*!< RD_MODE Bit Mask */
3313 #define FLCTL_BANK0_RDCTL_RD_MODE0               ((uint32_t)0x00000001)          /*!< RD_MODE Bit 0 */
3314 #define FLCTL_BANK0_RDCTL_RD_MODE1               ((uint32_t)0x00000002)          /*!< RD_MODE Bit 1 */
3315 #define FLCTL_BANK0_RDCTL_RD_MODE2               ((uint32_t)0x00000004)          /*!< RD_MODE Bit 2 */
3316 #define FLCTL_BANK0_RDCTL_RD_MODE3               ((uint32_t)0x00000008)          /*!< RD_MODE Bit 3 */
3317 #define FLCTL_BANK0_RDCTL_RD_MODE_0              ((uint32_t)0x00000000)          /*!< Normal read mode */
3318 #define FLCTL_BANK0_RDCTL_RD_MODE_1              ((uint32_t)0x00000001)          /*!< Read Margin 0 */
3319 #define FLCTL_BANK0_RDCTL_RD_MODE_2              ((uint32_t)0x00000002)          /*!< Read Margin 1 */
3320 #define FLCTL_BANK0_RDCTL_RD_MODE_3              ((uint32_t)0x00000003)          /*!< Program Verify */
3321 #define FLCTL_BANK0_RDCTL_RD_MODE_4              ((uint32_t)0x00000004)          /*!< Erase Verify */
3322 #define FLCTL_BANK0_RDCTL_RD_MODE_5              ((uint32_t)0x00000005)          /*!< Leakage Verify */
3323 #define FLCTL_BANK0_RDCTL_RD_MODE_9              ((uint32_t)0x00000009)          /*!< Read Margin 0B */
3324 #define FLCTL_BANK0_RDCTL_RD_MODE_10             ((uint32_t)0x0000000A)          /*!< Read Margin 1B */
3325 #define FLCTL_BANK0_RDCTL_BUFI_OFS               ( 4)                            /*!< BUFI Bit Offset */
3326 #define FLCTL_BANK0_RDCTL_BUFI                   ((uint32_t)0x00000010)          /*!< Enables read buffering feature for instruction fetches to this Bank */
3327 #define FLCTL_BANK0_RDCTL_BUFD_OFS               ( 5)                            /*!< BUFD Bit Offset */
3328 #define FLCTL_BANK0_RDCTL_BUFD                   ((uint32_t)0x00000020)          /*!< Enables read buffering feature for data reads to this Bank */
3329 #define FLCTL_BANK0_RDCTL_WAIT_OFS               (12)                            /*!< WAIT Bit Offset */
3330 #define FLCTL_BANK0_RDCTL_WAIT_MASK              ((uint32_t)0x0000F000)          /*!< WAIT Bit Mask */
3331 #define FLCTL_BANK0_RDCTL_WAIT0                  ((uint32_t)0x00001000)          /*!< WAIT Bit 0 */
3332 #define FLCTL_BANK0_RDCTL_WAIT1                  ((uint32_t)0x00002000)          /*!< WAIT Bit 1 */
3333 #define FLCTL_BANK0_RDCTL_WAIT2                  ((uint32_t)0x00004000)          /*!< WAIT Bit 2 */
3334 #define FLCTL_BANK0_RDCTL_WAIT3                  ((uint32_t)0x00008000)          /*!< WAIT Bit 3 */
3335 #define FLCTL_BANK0_RDCTL_WAIT_0                 ((uint32_t)0x00000000)          /*!< 0 wait states */
3336 #define FLCTL_BANK0_RDCTL_WAIT_1                 ((uint32_t)0x00001000)          /*!< 1 wait states */
3337 #define FLCTL_BANK0_RDCTL_WAIT_2                 ((uint32_t)0x00002000)          /*!< 2 wait states */
3338 #define FLCTL_BANK0_RDCTL_WAIT_3                 ((uint32_t)0x00003000)          /*!< 3 wait states */
3339 #define FLCTL_BANK0_RDCTL_WAIT_4                 ((uint32_t)0x00004000)          /*!< 4 wait states */
3340 #define FLCTL_BANK0_RDCTL_WAIT_5                 ((uint32_t)0x00005000)          /*!< 5 wait states */
3341 #define FLCTL_BANK0_RDCTL_WAIT_6                 ((uint32_t)0x00006000)          /*!< 6 wait states */
3342 #define FLCTL_BANK0_RDCTL_WAIT_7                 ((uint32_t)0x00007000)          /*!< 7 wait states */
3343 #define FLCTL_BANK0_RDCTL_WAIT_8                 ((uint32_t)0x00008000)          /*!< 8 wait states */
3344 #define FLCTL_BANK0_RDCTL_WAIT_9                 ((uint32_t)0x00009000)          /*!< 9 wait states */
3345 #define FLCTL_BANK0_RDCTL_WAIT_10                ((uint32_t)0x0000A000)          /*!< 10 wait states */
3346 #define FLCTL_BANK0_RDCTL_WAIT_11                ((uint32_t)0x0000B000)          /*!< 11 wait states */
3347 #define FLCTL_BANK0_RDCTL_WAIT_12                ((uint32_t)0x0000C000)          /*!< 12 wait states */
3348 #define FLCTL_BANK0_RDCTL_WAIT_13                ((uint32_t)0x0000D000)          /*!< 13 wait states */
3349 #define FLCTL_BANK0_RDCTL_WAIT_14                ((uint32_t)0x0000E000)          /*!< 14 wait states */
3350 #define FLCTL_BANK0_RDCTL_WAIT_15                ((uint32_t)0x0000F000)          /*!< 15 wait states */
3351 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_OFS     (16)                            /*!< RD_MODE_STATUS Bit Offset */
3352 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_MASK    ((uint32_t)0x000F0000)          /*!< RD_MODE_STATUS Bit Mask */
3353 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS0        ((uint32_t)0x00010000)          /*!< RD_MODE_STATUS Bit 0 */
3354 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS1        ((uint32_t)0x00020000)          /*!< RD_MODE_STATUS Bit 1 */
3355 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS2        ((uint32_t)0x00040000)          /*!< RD_MODE_STATUS Bit 2 */
3356 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS3        ((uint32_t)0x00080000)          /*!< RD_MODE_STATUS Bit 3 */
3357 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_0       ((uint32_t)0x00000000)          /*!< Normal read mode */
3358 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_1       ((uint32_t)0x00010000)          /*!< Read Margin 0 */
3359 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_2       ((uint32_t)0x00020000)          /*!< Read Margin 1 */
3360 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_3       ((uint32_t)0x00030000)          /*!< Program Verify */
3361 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_4       ((uint32_t)0x00040000)          /*!< Erase Verify */
3362 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_5       ((uint32_t)0x00050000)          /*!< Leakage Verify */
3363 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_9       ((uint32_t)0x00090000)          /*!< Read Margin 0B */
3364 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_10      ((uint32_t)0x000A0000)          /*!< Read Margin 1B */
3365 #define FLCTL_BANK1_RDCTL_RD_MODE_OFS            ( 0)                            /*!< RD_MODE Bit Offset */
3366 #define FLCTL_BANK1_RDCTL_RD_MODE_MASK           ((uint32_t)0x0000000F)          /*!< RD_MODE Bit Mask */
3367 #define FLCTL_BANK1_RDCTL_RD_MODE0               ((uint32_t)0x00000001)          /*!< RD_MODE Bit 0 */
3368 #define FLCTL_BANK1_RDCTL_RD_MODE1               ((uint32_t)0x00000002)          /*!< RD_MODE Bit 1 */
3369 #define FLCTL_BANK1_RDCTL_RD_MODE2               ((uint32_t)0x00000004)          /*!< RD_MODE Bit 2 */
3370 #define FLCTL_BANK1_RDCTL_RD_MODE3               ((uint32_t)0x00000008)          /*!< RD_MODE Bit 3 */
3371 #define FLCTL_BANK1_RDCTL_RD_MODE_0              ((uint32_t)0x00000000)          /*!< Normal read mode */
3372 #define FLCTL_BANK1_RDCTL_RD_MODE_1              ((uint32_t)0x00000001)          /*!< Read Margin 0 */
3373 #define FLCTL_BANK1_RDCTL_RD_MODE_2              ((uint32_t)0x00000002)          /*!< Read Margin 1 */
3374 #define FLCTL_BANK1_RDCTL_RD_MODE_3              ((uint32_t)0x00000003)          /*!< Program Verify */
3375 #define FLCTL_BANK1_RDCTL_RD_MODE_4              ((uint32_t)0x00000004)          /*!< Erase Verify */
3376 #define FLCTL_BANK1_RDCTL_RD_MODE_5              ((uint32_t)0x00000005)          /*!< Leakage Verify */
3377 #define FLCTL_BANK1_RDCTL_RD_MODE_9              ((uint32_t)0x00000009)          /*!< Read Margin 0B */
3378 #define FLCTL_BANK1_RDCTL_RD_MODE_10             ((uint32_t)0x0000000A)          /*!< Read Margin 1B */
3379 #define FLCTL_BANK1_RDCTL_BUFI_OFS               ( 4)                            /*!< BUFI Bit Offset */
3380 #define FLCTL_BANK1_RDCTL_BUFI                   ((uint32_t)0x00000010)          /*!< Enables read buffering feature for instruction fetches to this Bank */
3381 #define FLCTL_BANK1_RDCTL_BUFD_OFS               ( 5)                            /*!< BUFD Bit Offset */
3382 #define FLCTL_BANK1_RDCTL_BUFD                   ((uint32_t)0x00000020)          /*!< Enables read buffering feature for data reads to this Bank */
3383 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_OFS     (16)                            /*!< RD_MODE_STATUS Bit Offset */
3384 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_MASK    ((uint32_t)0x000F0000)          /*!< RD_MODE_STATUS Bit Mask */
3385 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS0        ((uint32_t)0x00010000)          /*!< RD_MODE_STATUS Bit 0 */
3386 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS1        ((uint32_t)0x00020000)          /*!< RD_MODE_STATUS Bit 1 */
3387 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS2        ((uint32_t)0x00040000)          /*!< RD_MODE_STATUS Bit 2 */
3388 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS3        ((uint32_t)0x00080000)          /*!< RD_MODE_STATUS Bit 3 */
3389 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_0       ((uint32_t)0x00000000)          /*!< Normal read mode */
3390 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_1       ((uint32_t)0x00010000)          /*!< Read Margin 0 */
3391 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_2       ((uint32_t)0x00020000)          /*!< Read Margin 1 */
3392 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_3       ((uint32_t)0x00030000)          /*!< Program Verify */
3393 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_4       ((uint32_t)0x00040000)          /*!< Erase Verify */
3394 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_5       ((uint32_t)0x00050000)          /*!< Leakage Verify */
3395 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_9       ((uint32_t)0x00090000)          /*!< Read Margin 0B */
3396 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_10      ((uint32_t)0x000A0000)          /*!< Read Margin 1B */
3397 #define FLCTL_BANK1_RDCTL_WAIT_OFS               (12)                            /*!< WAIT Bit Offset */
3398 #define FLCTL_BANK1_RDCTL_WAIT_MASK              ((uint32_t)0x0000F000)          /*!< WAIT Bit Mask */
3399 #define FLCTL_BANK1_RDCTL_WAIT0                  ((uint32_t)0x00001000)          /*!< WAIT Bit 0 */
3400 #define FLCTL_BANK1_RDCTL_WAIT1                  ((uint32_t)0x00002000)          /*!< WAIT Bit 1 */
3401 #define FLCTL_BANK1_RDCTL_WAIT2                  ((uint32_t)0x00004000)          /*!< WAIT Bit 2 */
3402 #define FLCTL_BANK1_RDCTL_WAIT3                  ((uint32_t)0x00008000)          /*!< WAIT Bit 3 */
3403 #define FLCTL_BANK1_RDCTL_WAIT_0                 ((uint32_t)0x00000000)          /*!< 0 wait states */
3404 #define FLCTL_BANK1_RDCTL_WAIT_1                 ((uint32_t)0x00001000)          /*!< 1 wait states */
3405 #define FLCTL_BANK1_RDCTL_WAIT_2                 ((uint32_t)0x00002000)          /*!< 2 wait states */
3406 #define FLCTL_BANK1_RDCTL_WAIT_3                 ((uint32_t)0x00003000)          /*!< 3 wait states */
3407 #define FLCTL_BANK1_RDCTL_WAIT_4                 ((uint32_t)0x00004000)          /*!< 4 wait states */
3408 #define FLCTL_BANK1_RDCTL_WAIT_5                 ((uint32_t)0x00005000)          /*!< 5 wait states */
3409 #define FLCTL_BANK1_RDCTL_WAIT_6                 ((uint32_t)0x00006000)          /*!< 6 wait states */
3410 #define FLCTL_BANK1_RDCTL_WAIT_7                 ((uint32_t)0x00007000)          /*!< 7 wait states */
3411 #define FLCTL_BANK1_RDCTL_WAIT_8                 ((uint32_t)0x00008000)          /*!< 8 wait states */
3412 #define FLCTL_BANK1_RDCTL_WAIT_9                 ((uint32_t)0x00009000)          /*!< 9 wait states */
3413 #define FLCTL_BANK1_RDCTL_WAIT_10                ((uint32_t)0x0000A000)          /*!< 10 wait states */
3414 #define FLCTL_BANK1_RDCTL_WAIT_11                ((uint32_t)0x0000B000)          /*!< 11 wait states */
3415 #define FLCTL_BANK1_RDCTL_WAIT_12                ((uint32_t)0x0000C000)          /*!< 12 wait states */
3416 #define FLCTL_BANK1_RDCTL_WAIT_13                ((uint32_t)0x0000D000)          /*!< 13 wait states */
3417 #define FLCTL_BANK1_RDCTL_WAIT_14                ((uint32_t)0x0000E000)          /*!< 14 wait states */
3418 #define FLCTL_BANK1_RDCTL_WAIT_15                ((uint32_t)0x0000F000)          /*!< 15 wait states */
3419 #define FLCTL_RDBRST_CTLSTAT_START_OFS           ( 0)                            /*!< START Bit Offset */
3420 #define FLCTL_RDBRST_CTLSTAT_START               ((uint32_t)0x00000001)          /*!< Start of burst/compare operation */
3421 #define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_OFS        ( 1)                            /*!< MEM_TYPE Bit Offset */
3422 #define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_MASK       ((uint32_t)0x00000006)          /*!< MEM_TYPE Bit Mask */
3423 #define FLCTL_RDBRST_CTLSTAT_MEM_TYPE0           ((uint32_t)0x00000002)          /*!< MEM_TYPE Bit 0 */
3424 #define FLCTL_RDBRST_CTLSTAT_MEM_TYPE1           ((uint32_t)0x00000004)          /*!< MEM_TYPE Bit 1 */
3425 #define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_0          ((uint32_t)0x00000000)          /*!< Main Memory */
3426 #define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_1          ((uint32_t)0x00000002)          /*!< Information Memory */
3427 #define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_2          ((uint32_t)0x00000004)          /*!< Reserved */
3428 #define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_3          ((uint32_t)0x00000006)          /*!< Engineering Memory */
3429 #define FLCTL_RDBRST_CTLSTAT_STOP_FAIL_OFS       ( 3)                            /*!< STOP_FAIL Bit Offset */
3430 #define FLCTL_RDBRST_CTLSTAT_STOP_FAIL           ((uint32_t)0x00000008)          /*!< Terminate burst/compare operation */
3431 #define FLCTL_RDBRST_CTLSTAT_DATA_CMP_OFS        ( 4)                            /*!< DATA_CMP Bit Offset */
3432 #define FLCTL_RDBRST_CTLSTAT_DATA_CMP            ((uint32_t)0x00000010)          /*!< Data pattern used for comparison against memory read data */
3433 #define FLCTL_RDBRST_CTLSTAT_TEST_EN_OFS         ( 6)                            /*!< TEST_EN Bit Offset */
3434 #define FLCTL_RDBRST_CTLSTAT_TEST_EN             ((uint32_t)0x00000040)          /*!< Enable comparison against test data compare registers */
3435 #define FLCTL_RDBRST_CTLSTAT_BRST_STAT_OFS       (16)                            /*!< BRST_STAT Bit Offset */
3436 #define FLCTL_RDBRST_CTLSTAT_BRST_STAT_MASK      ((uint32_t)0x00030000)          /*!< BRST_STAT Bit Mask */
3437 #define FLCTL_RDBRST_CTLSTAT_BRST_STAT0          ((uint32_t)0x00010000)          /*!< BRST_STAT Bit 0 */
3438 #define FLCTL_RDBRST_CTLSTAT_BRST_STAT1          ((uint32_t)0x00020000)          /*!< BRST_STAT Bit 1 */
3439 #define FLCTL_RDBRST_CTLSTAT_BRST_STAT_0         ((uint32_t)0x00000000)          /*!< Idle */
3440 #define FLCTL_RDBRST_CTLSTAT_BRST_STAT_1         ((uint32_t)0x00010000)          /*!< Burst/Compare START bit written, but operation pending */
3441 #define FLCTL_RDBRST_CTLSTAT_BRST_STAT_2         ((uint32_t)0x00020000)          /*!< Burst/Compare in progress */
3442 #define FLCTL_RDBRST_CTLSTAT_BRST_STAT_3         ((uint32_t)0x00030000)          /*!< Burst complete (status of completed burst remains in this state unless  */
3443 #define FLCTL_RDBRST_CTLSTAT_CMP_ERR_OFS         (18)                            /*!< CMP_ERR Bit Offset */
3444 #define FLCTL_RDBRST_CTLSTAT_CMP_ERR             ((uint32_t)0x00040000)          /*!< Burst/Compare Operation encountered atleast one data */
3445 #define FLCTL_RDBRST_CTLSTAT_ADDR_ERR_OFS        (19)                            /*!< ADDR_ERR Bit Offset */
3446 #define FLCTL_RDBRST_CTLSTAT_ADDR_ERR            ((uint32_t)0x00080000)          /*!< Burst/Compare Operation was terminated due to access to */
3447 #define FLCTL_RDBRST_CTLSTAT_CLR_STAT_OFS        (23)                            /*!< CLR_STAT Bit Offset */
3448 #define FLCTL_RDBRST_CTLSTAT_CLR_STAT            ((uint32_t)0x00800000)          /*!< Clear status bits 19-16 of this register */
3449 #define FLCTL_RDBRST_STARTADDR_START_ADDRESS_OFS ( 0)                            /*!< START_ADDRESS Bit Offset */
3450 #define FLCTL_RDBRST_STARTADDR_START_ADDRESS_MASK ((uint32_t)0x001FFFFF)          /*!< START_ADDRESS Bit Mask */
3451 #define FLCTL_RDBRST_LEN_BURST_LENGTH_OFS        ( 0)                            /*!< BURST_LENGTH Bit Offset */
3452 #define FLCTL_RDBRST_LEN_BURST_LENGTH_MASK       ((uint32_t)0x001FFFFF)          /*!< BURST_LENGTH Bit Mask */
3453 #define FLCTL_RDBRST_FAILADDR_FAIL_ADDRESS_OFS   ( 0)                            /*!< FAIL_ADDRESS Bit Offset */
3454 #define FLCTL_RDBRST_FAILADDR_FAIL_ADDRESS_MASK  ((uint32_t)0x001FFFFF)          /*!< FAIL_ADDRESS Bit Mask */
3455 #define FLCTL_RDBRST_FAILCNT_FAIL_COUNT_OFS      ( 0)                            /*!< FAIL_COUNT Bit Offset */
3456 #define FLCTL_RDBRST_FAILCNT_FAIL_COUNT_MASK     ((uint32_t)0x0001FFFF)          /*!< FAIL_COUNT Bit Mask */
3457 #define FLCTL_PRG_CTLSTAT_ENABLE_OFS             ( 0)                            /*!< ENABLE Bit Offset */
3458 #define FLCTL_PRG_CTLSTAT_ENABLE                 ((uint32_t)0x00000001)          /*!< Master control for all word program operations */
3459 #define FLCTL_PRG_CTLSTAT_MODE_OFS               ( 1)                            /*!< MODE Bit Offset */
3460 #define FLCTL_PRG_CTLSTAT_MODE                   ((uint32_t)0x00000002)          /*!< Write mode */
3461 #define FLCTL_PRG_CTLSTAT_VER_PRE_OFS            ( 2)                            /*!< VER_PRE Bit Offset */
3462 #define FLCTL_PRG_CTLSTAT_VER_PRE                ((uint32_t)0x00000004)          /*!< Controls automatic pre program verify operations */
3463 #define FLCTL_PRG_CTLSTAT_VER_PST_OFS            ( 3)                            /*!< VER_PST Bit Offset */
3464 #define FLCTL_PRG_CTLSTAT_VER_PST                ((uint32_t)0x00000008)          /*!< Controls automatic post program verify operations */
3465 #define FLCTL_PRG_CTLSTAT_STATUS_OFS             (16)                            /*!< STATUS Bit Offset */
3466 #define FLCTL_PRG_CTLSTAT_STATUS_MASK            ((uint32_t)0x00030000)          /*!< STATUS Bit Mask */
3467 #define FLCTL_PRG_CTLSTAT_STATUS0                ((uint32_t)0x00010000)          /*!< STATUS Bit 0 */
3468 #define FLCTL_PRG_CTLSTAT_STATUS1                ((uint32_t)0x00020000)          /*!< STATUS Bit 1 */
3469 #define FLCTL_PRG_CTLSTAT_STATUS_0               ((uint32_t)0x00000000)          /*!< Idle (no program operation currently active) */
3470 #define FLCTL_PRG_CTLSTAT_STATUS_1               ((uint32_t)0x00010000)          /*!< Single word program operation triggered, but pending */
3471 #define FLCTL_PRG_CTLSTAT_STATUS_2               ((uint32_t)0x00020000)          /*!< Single word program in progress */
3472 #define FLCTL_PRG_CTLSTAT_STATUS_3               ((uint32_t)0x00030000)          /*!< Reserved (Idle) */
3473 #define FLCTL_PRG_CTLSTAT_BNK_ACT_OFS            (18)                            /*!< BNK_ACT Bit Offset */
3474 #define FLCTL_PRG_CTLSTAT_BNK_ACT                ((uint32_t)0x00040000)          /*!< Bank active */
3475 #define FLCTL_PRGBRST_CTLSTAT_START_OFS          ( 0)                            /*!< START Bit Offset */
3476 #define FLCTL_PRGBRST_CTLSTAT_START              ((uint32_t)0x00000001)          /*!< Trigger start of burst program operation */
3477 #define FLCTL_PRGBRST_CTLSTAT_TYPE_OFS           ( 1)                            /*!< TYPE Bit Offset */
3478 #define FLCTL_PRGBRST_CTLSTAT_TYPE_MASK          ((uint32_t)0x00000006)          /*!< TYPE Bit Mask */
3479 #define FLCTL_PRGBRST_CTLSTAT_TYPE0              ((uint32_t)0x00000002)          /*!< TYPE Bit 0 */
3480 #define FLCTL_PRGBRST_CTLSTAT_TYPE1              ((uint32_t)0x00000004)          /*!< TYPE Bit 1 */
3481 #define FLCTL_PRGBRST_CTLSTAT_TYPE_0             ((uint32_t)0x00000000)          /*!< Main Memory */
3482 #define FLCTL_PRGBRST_CTLSTAT_TYPE_1             ((uint32_t)0x00000002)          /*!< Information Memory */
3483 #define FLCTL_PRGBRST_CTLSTAT_TYPE_2             ((uint32_t)0x00000004)          /*!< Reserved */
3484 #define FLCTL_PRGBRST_CTLSTAT_TYPE_3             ((uint32_t)0x00000006)          /*!< Engineering Memory */
3485 #define FLCTL_PRGBRST_CTLSTAT_LEN_OFS            ( 3)                            /*!< LEN Bit Offset */
3486 #define FLCTL_PRGBRST_CTLSTAT_LEN_MASK           ((uint32_t)0x00000038)          /*!< LEN Bit Mask */
3487 #define FLCTL_PRGBRST_CTLSTAT_LEN0               ((uint32_t)0x00000008)          /*!< LEN Bit 0 */
3488 #define FLCTL_PRGBRST_CTLSTAT_LEN1               ((uint32_t)0x00000010)          /*!< LEN Bit 1 */
3489 #define FLCTL_PRGBRST_CTLSTAT_LEN2               ((uint32_t)0x00000020)          /*!< LEN Bit 2 */
3490 #define FLCTL_PRGBRST_CTLSTAT_LEN_0              ((uint32_t)0x00000000)          /*!< No burst operation */
3491 #define FLCTL_PRGBRST_CTLSTAT_LEN_1              ((uint32_t)0x00000008)          /*!< 1 word burst of 128 bits, starting with address in the  */
3492 #define FLCTL_PRGBRST_CTLSTAT_LEN_2              ((uint32_t)0x00000010)          /*!< 2*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR  */
3493 #define FLCTL_PRGBRST_CTLSTAT_LEN_3              ((uint32_t)0x00000018)          /*!< 3*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR  */
3494 #define FLCTL_PRGBRST_CTLSTAT_LEN_4              ((uint32_t)0x00000020)          /*!< 4*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR  */
3495 #define FLCTL_PRGBRST_CTLSTAT_AUTO_PRE_OFS       ( 6)                            /*!< AUTO_PRE Bit Offset */
3496 #define FLCTL_PRGBRST_CTLSTAT_AUTO_PRE           ((uint32_t)0x00000040)          /*!< Auto-Verify operation before the Burst Program */
3497 #define FLCTL_PRGBRST_CTLSTAT_AUTO_PST_OFS       ( 7)                            /*!< AUTO_PST Bit Offset */
3498 #define FLCTL_PRGBRST_CTLSTAT_AUTO_PST           ((uint32_t)0x00000080)          /*!< Auto-Verify operation after the Burst Program */
3499 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_OFS   (16)                            /*!< BURST_STATUS Bit Offset */
3500 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_MASK  ((uint32_t)0x00070000)          /*!< BURST_STATUS Bit Mask */
3501 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS0      ((uint32_t)0x00010000)          /*!< BURST_STATUS Bit 0 */
3502 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS1      ((uint32_t)0x00020000)          /*!< BURST_STATUS Bit 1 */
3503 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS2      ((uint32_t)0x00040000)          /*!< BURST_STATUS Bit 2 */
3504 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_0     ((uint32_t)0x00000000)          /*!< Idle (Burst not active) */
3505 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_1     ((uint32_t)0x00010000)          /*!< Burst program started but pending */
3506 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_2     ((uint32_t)0x00020000)          /*!< Burst active, with 1st 128 bit word being written into Flash */
3507 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_3     ((uint32_t)0x00030000)          /*!< Burst active, with 2nd 128 bit word being written into Flash */
3508 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_4     ((uint32_t)0x00040000)          /*!< Burst active, with 3rd 128 bit word being written into Flash */
3509 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_5     ((uint32_t)0x00050000)          /*!< Burst active, with 4th 128 bit word being written into Flash */
3510 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_6     ((uint32_t)0x00060000)          /*!< Reserved (Idle) */
3511 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_7     ((uint32_t)0x00070000)          /*!< Burst Complete (status of completed burst remains in this state unless  */
3512 #define FLCTL_PRGBRST_CTLSTAT_PRE_ERR_OFS        (19)                            /*!< PRE_ERR Bit Offset */
3513 #define FLCTL_PRGBRST_CTLSTAT_PRE_ERR            ((uint32_t)0x00080000)          /*!< Burst Operation encountered preprogram auto-verify errors */
3514 #define FLCTL_PRGBRST_CTLSTAT_PST_ERR_OFS        (20)                            /*!< PST_ERR Bit Offset */
3515 #define FLCTL_PRGBRST_CTLSTAT_PST_ERR            ((uint32_t)0x00100000)          /*!< Burst Operation encountered postprogram auto-verify errors */
3516 #define FLCTL_PRGBRST_CTLSTAT_ADDR_ERR_OFS       (21)                            /*!< ADDR_ERR Bit Offset */
3517 #define FLCTL_PRGBRST_CTLSTAT_ADDR_ERR           ((uint32_t)0x00200000)          /*!< Burst Operation was terminated due to attempted program of reserved memory */
3518 #define FLCTL_PRGBRST_CTLSTAT_CLR_STAT_OFS       (23)                            /*!< CLR_STAT Bit Offset */
3519 #define FLCTL_PRGBRST_CTLSTAT_CLR_STAT           ((uint32_t)0x00800000)          /*!< Clear status bits 21-16 of this register */
3520 #define FLCTL_PRGBRST_STARTADDR_START_ADDRESS_OFS ( 0)                            /*!< START_ADDRESS Bit Offset */
3521 #define FLCTL_PRGBRST_STARTADDR_START_ADDRESS_MASK ((uint32_t)0x003FFFFF)          /*!< START_ADDRESS Bit Mask */
3522 #define FLCTL_ERASE_CTLSTAT_START_OFS            ( 0)                            /*!< START Bit Offset */
3523 #define FLCTL_ERASE_CTLSTAT_START                ((uint32_t)0x00000001)          /*!< Start of Erase operation */
3524 #define FLCTL_ERASE_CTLSTAT_MODE_OFS             ( 1)                            /*!< MODE Bit Offset */
3525 #define FLCTL_ERASE_CTLSTAT_MODE                 ((uint32_t)0x00000002)          /*!< Erase mode selected by application */
3526 #define FLCTL_ERASE_CTLSTAT_TYPE_OFS             ( 2)                            /*!< TYPE Bit Offset */
3527 #define FLCTL_ERASE_CTLSTAT_TYPE_MASK            ((uint32_t)0x0000000C)          /*!< TYPE Bit Mask */
3528 #define FLCTL_ERASE_CTLSTAT_TYPE0                ((uint32_t)0x00000004)          /*!< TYPE Bit 0 */
3529 #define FLCTL_ERASE_CTLSTAT_TYPE1                ((uint32_t)0x00000008)          /*!< TYPE Bit 1 */
3530 #define FLCTL_ERASE_CTLSTAT_TYPE_0               ((uint32_t)0x00000000)          /*!< Main Memory */
3531 #define FLCTL_ERASE_CTLSTAT_TYPE_1               ((uint32_t)0x00000004)          /*!< Information Memory */
3532 #define FLCTL_ERASE_CTLSTAT_TYPE_2               ((uint32_t)0x00000008)          /*!< Reserved */
3533 #define FLCTL_ERASE_CTLSTAT_TYPE_3               ((uint32_t)0x0000000C)          /*!< Engineering Memory */
3534 #define FLCTL_ERASE_CTLSTAT_STATUS_OFS           (16)                            /*!< STATUS Bit Offset */
3535 #define FLCTL_ERASE_CTLSTAT_STATUS_MASK          ((uint32_t)0x00030000)          /*!< STATUS Bit Mask */
3536 #define FLCTL_ERASE_CTLSTAT_STATUS0              ((uint32_t)0x00010000)          /*!< STATUS Bit 0 */
3537 #define FLCTL_ERASE_CTLSTAT_STATUS1              ((uint32_t)0x00020000)          /*!< STATUS Bit 1 */
3538 #define FLCTL_ERASE_CTLSTAT_STATUS_0             ((uint32_t)0x00000000)          /*!< Idle (no program operation currently active) */
3539 #define FLCTL_ERASE_CTLSTAT_STATUS_1             ((uint32_t)0x00010000)          /*!< Erase operation triggered to START but pending */
3540 #define FLCTL_ERASE_CTLSTAT_STATUS_2             ((uint32_t)0x00020000)          /*!< Erase operation in progress */
3541 #define FLCTL_ERASE_CTLSTAT_STATUS_3             ((uint32_t)0x00030000)          /*!< Erase operation completed (status of completed erase remains in this state  */
3542 #define FLCTL_ERASE_CTLSTAT_ADDR_ERR_OFS         (18)                            /*!< ADDR_ERR Bit Offset */
3543 #define FLCTL_ERASE_CTLSTAT_ADDR_ERR             ((uint32_t)0x00040000)          /*!< Erase Operation was terminated due to attempted erase of reserved memory  */
3544 #define FLCTL_ERASE_CTLSTAT_CLR_STAT_OFS         (19)                            /*!< CLR_STAT Bit Offset */
3545 #define FLCTL_ERASE_CTLSTAT_CLR_STAT             ((uint32_t)0x00080000)          /*!< Clear status bits 18-16 of this register */
3546 #define FLCTL_ERASE_SECTADDR_SECT_ADDRESS_OFS    ( 0)                            /*!< SECT_ADDRESS Bit Offset */
3547 #define FLCTL_ERASE_SECTADDR_SECT_ADDRESS_MASK   ((uint32_t)0x003FFFFF)          /*!< SECT_ADDRESS Bit Mask */
3548 #define FLCTL_BANK0_INFO_WEPROT_PROT0_OFS        ( 0)                            /*!< PROT0 Bit Offset */
3549 #define FLCTL_BANK0_INFO_WEPROT_PROT0            ((uint32_t)0x00000001)          /*!< Protects Sector 0 from program or erase */
3550 #define FLCTL_BANK0_INFO_WEPROT_PROT1_OFS        ( 1)                            /*!< PROT1 Bit Offset */
3551 #define FLCTL_BANK0_INFO_WEPROT_PROT1            ((uint32_t)0x00000002)          /*!< Protects Sector 1 from program or erase */
3552 #define FLCTL_BANK0_MAIN_WEPROT_PROT0_OFS        ( 0)                            /*!< PROT0 Bit Offset */
3553 #define FLCTL_BANK0_MAIN_WEPROT_PROT0            ((uint32_t)0x00000001)          /*!< Protects Sector 0 from program or erase */
3554 #define FLCTL_BANK0_MAIN_WEPROT_PROT1_OFS        ( 1)                            /*!< PROT1 Bit Offset */
3555 #define FLCTL_BANK0_MAIN_WEPROT_PROT1            ((uint32_t)0x00000002)          /*!< Protects Sector 1 from program or erase */
3556 #define FLCTL_BANK0_MAIN_WEPROT_PROT2_OFS        ( 2)                            /*!< PROT2 Bit Offset */
3557 #define FLCTL_BANK0_MAIN_WEPROT_PROT2            ((uint32_t)0x00000004)          /*!< Protects Sector 2 from program or erase */
3558 #define FLCTL_BANK0_MAIN_WEPROT_PROT3_OFS        ( 3)                            /*!< PROT3 Bit Offset */
3559 #define FLCTL_BANK0_MAIN_WEPROT_PROT3            ((uint32_t)0x00000008)          /*!< Protects Sector 3 from program or erase */
3560 #define FLCTL_BANK0_MAIN_WEPROT_PROT4_OFS        ( 4)                            /*!< PROT4 Bit Offset */
3561 #define FLCTL_BANK0_MAIN_WEPROT_PROT4            ((uint32_t)0x00000010)          /*!< Protects Sector 4 from program or erase */
3562 #define FLCTL_BANK0_MAIN_WEPROT_PROT5_OFS        ( 5)                            /*!< PROT5 Bit Offset */
3563 #define FLCTL_BANK0_MAIN_WEPROT_PROT5            ((uint32_t)0x00000020)          /*!< Protects Sector 5 from program or erase */
3564 #define FLCTL_BANK0_MAIN_WEPROT_PROT6_OFS        ( 6)                            /*!< PROT6 Bit Offset */
3565 #define FLCTL_BANK0_MAIN_WEPROT_PROT6            ((uint32_t)0x00000040)          /*!< Protects Sector 6 from program or erase */
3566 #define FLCTL_BANK0_MAIN_WEPROT_PROT7_OFS        ( 7)                            /*!< PROT7 Bit Offset */
3567 #define FLCTL_BANK0_MAIN_WEPROT_PROT7            ((uint32_t)0x00000080)          /*!< Protects Sector 7 from program or erase */
3568 #define FLCTL_BANK0_MAIN_WEPROT_PROT8_OFS        ( 8)                            /*!< PROT8 Bit Offset */
3569 #define FLCTL_BANK0_MAIN_WEPROT_PROT8            ((uint32_t)0x00000100)          /*!< Protects Sector 8 from program or erase */
3570 #define FLCTL_BANK0_MAIN_WEPROT_PROT9_OFS        ( 9)                            /*!< PROT9 Bit Offset */
3571 #define FLCTL_BANK0_MAIN_WEPROT_PROT9            ((uint32_t)0x00000200)          /*!< Protects Sector 9 from program or erase */
3572 #define FLCTL_BANK0_MAIN_WEPROT_PROT10_OFS       (10)                            /*!< PROT10 Bit Offset */
3573 #define FLCTL_BANK0_MAIN_WEPROT_PROT10           ((uint32_t)0x00000400)          /*!< Protects Sector 10 from program or erase */
3574 #define FLCTL_BANK0_MAIN_WEPROT_PROT11_OFS       (11)                            /*!< PROT11 Bit Offset */
3575 #define FLCTL_BANK0_MAIN_WEPROT_PROT11           ((uint32_t)0x00000800)          /*!< Protects Sector 11 from program or erase */
3576 #define FLCTL_BANK0_MAIN_WEPROT_PROT12_OFS       (12)                            /*!< PROT12 Bit Offset */
3577 #define FLCTL_BANK0_MAIN_WEPROT_PROT12           ((uint32_t)0x00001000)          /*!< Protects Sector 12 from program or erase */
3578 #define FLCTL_BANK0_MAIN_WEPROT_PROT13_OFS       (13)                            /*!< PROT13 Bit Offset */
3579 #define FLCTL_BANK0_MAIN_WEPROT_PROT13           ((uint32_t)0x00002000)          /*!< Protects Sector 13 from program or erase */
3580 #define FLCTL_BANK0_MAIN_WEPROT_PROT14_OFS       (14)                            /*!< PROT14 Bit Offset */
3581 #define FLCTL_BANK0_MAIN_WEPROT_PROT14           ((uint32_t)0x00004000)          /*!< Protects Sector 14 from program or erase */
3582 #define FLCTL_BANK0_MAIN_WEPROT_PROT15_OFS       (15)                            /*!< PROT15 Bit Offset */
3583 #define FLCTL_BANK0_MAIN_WEPROT_PROT15           ((uint32_t)0x00008000)          /*!< Protects Sector 15 from program or erase */
3584 #define FLCTL_BANK0_MAIN_WEPROT_PROT16_OFS       (16)                            /*!< PROT16 Bit Offset */
3585 #define FLCTL_BANK0_MAIN_WEPROT_PROT16           ((uint32_t)0x00010000)          /*!< Protects Sector 16 from program or erase */
3586 #define FLCTL_BANK0_MAIN_WEPROT_PROT17_OFS       (17)                            /*!< PROT17 Bit Offset */
3587 #define FLCTL_BANK0_MAIN_WEPROT_PROT17           ((uint32_t)0x00020000)          /*!< Protects Sector 17 from program or erase */
3588 #define FLCTL_BANK0_MAIN_WEPROT_PROT18_OFS       (18)                            /*!< PROT18 Bit Offset */
3589 #define FLCTL_BANK0_MAIN_WEPROT_PROT18           ((uint32_t)0x00040000)          /*!< Protects Sector 18 from program or erase */
3590 #define FLCTL_BANK0_MAIN_WEPROT_PROT19_OFS       (19)                            /*!< PROT19 Bit Offset */
3591 #define FLCTL_BANK0_MAIN_WEPROT_PROT19           ((uint32_t)0x00080000)          /*!< Protects Sector 19 from program or erase */
3592 #define FLCTL_BANK0_MAIN_WEPROT_PROT20_OFS       (20)                            /*!< PROT20 Bit Offset */
3593 #define FLCTL_BANK0_MAIN_WEPROT_PROT20           ((uint32_t)0x00100000)          /*!< Protects Sector 20 from program or erase */
3594 #define FLCTL_BANK0_MAIN_WEPROT_PROT21_OFS       (21)                            /*!< PROT21 Bit Offset */
3595 #define FLCTL_BANK0_MAIN_WEPROT_PROT21           ((uint32_t)0x00200000)          /*!< Protects Sector 21 from program or erase */
3596 #define FLCTL_BANK0_MAIN_WEPROT_PROT22_OFS       (22)                            /*!< PROT22 Bit Offset */
3597 #define FLCTL_BANK0_MAIN_WEPROT_PROT22           ((uint32_t)0x00400000)          /*!< Protects Sector 22 from program or erase */
3598 #define FLCTL_BANK0_MAIN_WEPROT_PROT23_OFS       (23)                            /*!< PROT23 Bit Offset */
3599 #define FLCTL_BANK0_MAIN_WEPROT_PROT23           ((uint32_t)0x00800000)          /*!< Protects Sector 23 from program or erase */
3600 #define FLCTL_BANK0_MAIN_WEPROT_PROT24_OFS       (24)                            /*!< PROT24 Bit Offset */
3601 #define FLCTL_BANK0_MAIN_WEPROT_PROT24           ((uint32_t)0x01000000)          /*!< Protects Sector 24 from program or erase */
3602 #define FLCTL_BANK0_MAIN_WEPROT_PROT25_OFS       (25)                            /*!< PROT25 Bit Offset */
3603 #define FLCTL_BANK0_MAIN_WEPROT_PROT25           ((uint32_t)0x02000000)          /*!< Protects Sector 25 from program or erase */
3604 #define FLCTL_BANK0_MAIN_WEPROT_PROT26_OFS       (26)                            /*!< PROT26 Bit Offset */
3605 #define FLCTL_BANK0_MAIN_WEPROT_PROT26           ((uint32_t)0x04000000)          /*!< Protects Sector 26 from program or erase */
3606 #define FLCTL_BANK0_MAIN_WEPROT_PROT27_OFS       (27)                            /*!< PROT27 Bit Offset */
3607 #define FLCTL_BANK0_MAIN_WEPROT_PROT27           ((uint32_t)0x08000000)          /*!< Protects Sector 27 from program or erase */
3608 #define FLCTL_BANK0_MAIN_WEPROT_PROT28_OFS       (28)                            /*!< PROT28 Bit Offset */
3609 #define FLCTL_BANK0_MAIN_WEPROT_PROT28           ((uint32_t)0x10000000)          /*!< Protects Sector 28 from program or erase */
3610 #define FLCTL_BANK0_MAIN_WEPROT_PROT29_OFS       (29)                            /*!< PROT29 Bit Offset */
3611 #define FLCTL_BANK0_MAIN_WEPROT_PROT29           ((uint32_t)0x20000000)          /*!< Protects Sector 29 from program or erase */
3612 #define FLCTL_BANK0_MAIN_WEPROT_PROT30_OFS       (30)                            /*!< PROT30 Bit Offset */
3613 #define FLCTL_BANK0_MAIN_WEPROT_PROT30           ((uint32_t)0x40000000)          /*!< Protects Sector 30 from program or erase */
3614 #define FLCTL_BANK0_MAIN_WEPROT_PROT31_OFS       (31)                            /*!< PROT31 Bit Offset */
3615 #define FLCTL_BANK0_MAIN_WEPROT_PROT31           ((uint32_t)0x80000000)          /*!< Protects Sector 31 from program or erase */
3616 #define FLCTL_BANK1_INFO_WEPROT_PROT0_OFS        ( 0)                            /*!< PROT0 Bit Offset */
3617 #define FLCTL_BANK1_INFO_WEPROT_PROT0            ((uint32_t)0x00000001)          /*!< Protects Sector 0 from program or erase operations */
3618 #define FLCTL_BANK1_INFO_WEPROT_PROT1_OFS        ( 1)                            /*!< PROT1 Bit Offset */
3619 #define FLCTL_BANK1_INFO_WEPROT_PROT1            ((uint32_t)0x00000002)          /*!< Protects Sector 1 from program or erase operations */
3620 #define FLCTL_BANK1_MAIN_WEPROT_PROT0_OFS        ( 0)                            /*!< PROT0 Bit Offset */
3621 #define FLCTL_BANK1_MAIN_WEPROT_PROT0            ((uint32_t)0x00000001)          /*!< Protects Sector 0 from program or erase operations */
3622 #define FLCTL_BANK1_MAIN_WEPROT_PROT1_OFS        ( 1)                            /*!< PROT1 Bit Offset */
3623 #define FLCTL_BANK1_MAIN_WEPROT_PROT1            ((uint32_t)0x00000002)          /*!< Protects Sector 1 from program or erase operations */
3624 #define FLCTL_BANK1_MAIN_WEPROT_PROT2_OFS        ( 2)                            /*!< PROT2 Bit Offset */
3625 #define FLCTL_BANK1_MAIN_WEPROT_PROT2            ((uint32_t)0x00000004)          /*!< Protects Sector 2 from program or erase operations */
3626 #define FLCTL_BANK1_MAIN_WEPROT_PROT3_OFS        ( 3)                            /*!< PROT3 Bit Offset */
3627 #define FLCTL_BANK1_MAIN_WEPROT_PROT3            ((uint32_t)0x00000008)          /*!< Protects Sector 3 from program or erase operations */
3628 #define FLCTL_BANK1_MAIN_WEPROT_PROT4_OFS        ( 4)                            /*!< PROT4 Bit Offset */
3629 #define FLCTL_BANK1_MAIN_WEPROT_PROT4            ((uint32_t)0x00000010)          /*!< Protects Sector 4 from program or erase operations */
3630 #define FLCTL_BANK1_MAIN_WEPROT_PROT5_OFS        ( 5)                            /*!< PROT5 Bit Offset */
3631 #define FLCTL_BANK1_MAIN_WEPROT_PROT5            ((uint32_t)0x00000020)          /*!< Protects Sector 5 from program or erase operations */
3632 #define FLCTL_BANK1_MAIN_WEPROT_PROT6_OFS        ( 6)                            /*!< PROT6 Bit Offset */
3633 #define FLCTL_BANK1_MAIN_WEPROT_PROT6            ((uint32_t)0x00000040)          /*!< Protects Sector 6 from program or erase operations */
3634 #define FLCTL_BANK1_MAIN_WEPROT_PROT7_OFS        ( 7)                            /*!< PROT7 Bit Offset */
3635 #define FLCTL_BANK1_MAIN_WEPROT_PROT7            ((uint32_t)0x00000080)          /*!< Protects Sector 7 from program or erase operations */
3636 #define FLCTL_BANK1_MAIN_WEPROT_PROT8_OFS        ( 8)                            /*!< PROT8 Bit Offset */
3637 #define FLCTL_BANK1_MAIN_WEPROT_PROT8            ((uint32_t)0x00000100)          /*!< Protects Sector 8 from program or erase operations */
3638 #define FLCTL_BANK1_MAIN_WEPROT_PROT9_OFS        ( 9)                            /*!< PROT9 Bit Offset */
3639 #define FLCTL_BANK1_MAIN_WEPROT_PROT9            ((uint32_t)0x00000200)          /*!< Protects Sector 9 from program or erase operations */
3640 #define FLCTL_BANK1_MAIN_WEPROT_PROT10_OFS       (10)                            /*!< PROT10 Bit Offset */
3641 #define FLCTL_BANK1_MAIN_WEPROT_PROT10           ((uint32_t)0x00000400)          /*!< Protects Sector 10 from program or erase operations */
3642 #define FLCTL_BANK1_MAIN_WEPROT_PROT11_OFS       (11)                            /*!< PROT11 Bit Offset */
3643 #define FLCTL_BANK1_MAIN_WEPROT_PROT11           ((uint32_t)0x00000800)          /*!< Protects Sector 11 from program or erase operations */
3644 #define FLCTL_BANK1_MAIN_WEPROT_PROT12_OFS       (12)                            /*!< PROT12 Bit Offset */
3645 #define FLCTL_BANK1_MAIN_WEPROT_PROT12           ((uint32_t)0x00001000)          /*!< Protects Sector 12 from program or erase operations */
3646 #define FLCTL_BANK1_MAIN_WEPROT_PROT13_OFS       (13)                            /*!< PROT13 Bit Offset */
3647 #define FLCTL_BANK1_MAIN_WEPROT_PROT13           ((uint32_t)0x00002000)          /*!< Protects Sector 13 from program or erase operations */
3648 #define FLCTL_BANK1_MAIN_WEPROT_PROT14_OFS       (14)                            /*!< PROT14 Bit Offset */
3649 #define FLCTL_BANK1_MAIN_WEPROT_PROT14           ((uint32_t)0x00004000)          /*!< Protects Sector 14 from program or erase operations */
3650 #define FLCTL_BANK1_MAIN_WEPROT_PROT15_OFS       (15)                            /*!< PROT15 Bit Offset */
3651 #define FLCTL_BANK1_MAIN_WEPROT_PROT15           ((uint32_t)0x00008000)          /*!< Protects Sector 15 from program or erase operations */
3652 #define FLCTL_BANK1_MAIN_WEPROT_PROT16_OFS       (16)                            /*!< PROT16 Bit Offset */
3653 #define FLCTL_BANK1_MAIN_WEPROT_PROT16           ((uint32_t)0x00010000)          /*!< Protects Sector 16 from program or erase operations */
3654 #define FLCTL_BANK1_MAIN_WEPROT_PROT17_OFS       (17)                            /*!< PROT17 Bit Offset */
3655 #define FLCTL_BANK1_MAIN_WEPROT_PROT17           ((uint32_t)0x00020000)          /*!< Protects Sector 17 from program or erase operations */
3656 #define FLCTL_BANK1_MAIN_WEPROT_PROT18_OFS       (18)                            /*!< PROT18 Bit Offset */
3657 #define FLCTL_BANK1_MAIN_WEPROT_PROT18           ((uint32_t)0x00040000)          /*!< Protects Sector 18 from program or erase operations */
3658 #define FLCTL_BANK1_MAIN_WEPROT_PROT19_OFS       (19)                            /*!< PROT19 Bit Offset */
3659 #define FLCTL_BANK1_MAIN_WEPROT_PROT19           ((uint32_t)0x00080000)          /*!< Protects Sector 19 from program or erase operations */
3660 #define FLCTL_BANK1_MAIN_WEPROT_PROT20_OFS       (20)                            /*!< PROT20 Bit Offset */
3661 #define FLCTL_BANK1_MAIN_WEPROT_PROT20           ((uint32_t)0x00100000)          /*!< Protects Sector 20 from program or erase operations */
3662 #define FLCTL_BANK1_MAIN_WEPROT_PROT21_OFS       (21)                            /*!< PROT21 Bit Offset */
3663 #define FLCTL_BANK1_MAIN_WEPROT_PROT21           ((uint32_t)0x00200000)          /*!< Protects Sector 21 from program or erase operations */
3664 #define FLCTL_BANK1_MAIN_WEPROT_PROT22_OFS       (22)                            /*!< PROT22 Bit Offset */
3665 #define FLCTL_BANK1_MAIN_WEPROT_PROT22           ((uint32_t)0x00400000)          /*!< Protects Sector 22 from program or erase operations */
3666 #define FLCTL_BANK1_MAIN_WEPROT_PROT23_OFS       (23)                            /*!< PROT23 Bit Offset */
3667 #define FLCTL_BANK1_MAIN_WEPROT_PROT23           ((uint32_t)0x00800000)          /*!< Protects Sector 23 from program or erase operations */
3668 #define FLCTL_BANK1_MAIN_WEPROT_PROT24_OFS       (24)                            /*!< PROT24 Bit Offset */
3669 #define FLCTL_BANK1_MAIN_WEPROT_PROT24           ((uint32_t)0x01000000)          /*!< Protects Sector 24 from program or erase operations */
3670 #define FLCTL_BANK1_MAIN_WEPROT_PROT25_OFS       (25)                            /*!< PROT25 Bit Offset */
3671 #define FLCTL_BANK1_MAIN_WEPROT_PROT25           ((uint32_t)0x02000000)          /*!< Protects Sector 25 from program or erase operations */
3672 #define FLCTL_BANK1_MAIN_WEPROT_PROT26_OFS       (26)                            /*!< PROT26 Bit Offset */
3673 #define FLCTL_BANK1_MAIN_WEPROT_PROT26           ((uint32_t)0x04000000)          /*!< Protects Sector 26 from program or erase operations */
3674 #define FLCTL_BANK1_MAIN_WEPROT_PROT27_OFS       (27)                            /*!< PROT27 Bit Offset */
3675 #define FLCTL_BANK1_MAIN_WEPROT_PROT27           ((uint32_t)0x08000000)          /*!< Protects Sector 27 from program or erase operations */
3676 #define FLCTL_BANK1_MAIN_WEPROT_PROT28_OFS       (28)                            /*!< PROT28 Bit Offset */
3677 #define FLCTL_BANK1_MAIN_WEPROT_PROT28           ((uint32_t)0x10000000)          /*!< Protects Sector 28 from program or erase operations */
3678 #define FLCTL_BANK1_MAIN_WEPROT_PROT29_OFS       (29)                            /*!< PROT29 Bit Offset */
3679 #define FLCTL_BANK1_MAIN_WEPROT_PROT29           ((uint32_t)0x20000000)          /*!< Protects Sector 29 from program or erase operations */
3680 #define FLCTL_BANK1_MAIN_WEPROT_PROT30_OFS       (30)                            /*!< PROT30 Bit Offset */
3681 #define FLCTL_BANK1_MAIN_WEPROT_PROT30           ((uint32_t)0x40000000)          /*!< Protects Sector 30 from program or erase operations */
3682 #define FLCTL_BANK1_MAIN_WEPROT_PROT31_OFS       (31)                            /*!< PROT31 Bit Offset */
3683 #define FLCTL_BANK1_MAIN_WEPROT_PROT31           ((uint32_t)0x80000000)          /*!< Protects Sector 31 from program or erase operations */
3684 #define FLCTL_BMRK_CTLSTAT_I_BMRK_OFS            ( 0)                            /*!< I_BMRK Bit Offset */
3685 #define FLCTL_BMRK_CTLSTAT_I_BMRK                ((uint32_t)0x00000001)
3686 #define FLCTL_BMRK_CTLSTAT_D_BMRK_OFS            ( 1)                            /*!< D_BMRK Bit Offset */
3687 #define FLCTL_BMRK_CTLSTAT_D_BMRK                ((uint32_t)0x00000002)
3688 #define FLCTL_BMRK_CTLSTAT_CMP_EN_OFS            ( 2)                            /*!< CMP_EN Bit Offset */
3689 #define FLCTL_BMRK_CTLSTAT_CMP_EN                ((uint32_t)0x00000004)
3690 #define FLCTL_BMRK_CTLSTAT_CMP_SEL_OFS           ( 3)                            /*!< CMP_SEL Bit Offset */
3691 #define FLCTL_BMRK_CTLSTAT_CMP_SEL               ((uint32_t)0x00000008)
3692 #define FLCTL_IFG_RDBRST_OFS                     ( 0)                            /*!< RDBRST Bit Offset */
3693 #define FLCTL_IFG_RDBRST                         ((uint32_t)0x00000001)
3694 #define FLCTL_IFG_AVPRE_OFS                      ( 1)                            /*!< AVPRE Bit Offset */
3695 #define FLCTL_IFG_AVPRE                          ((uint32_t)0x00000002)
3696 #define FLCTL_IFG_AVPST_OFS                      ( 2)                            /*!< AVPST Bit Offset */
3697 #define FLCTL_IFG_AVPST                          ((uint32_t)0x00000004)
3698 #define FLCTL_IFG_PRG_OFS                        ( 3)                            /*!< PRG Bit Offset */
3699 #define FLCTL_IFG_PRG                            ((uint32_t)0x00000008)
3700 #define FLCTL_IFG_PRGB_OFS                       ( 4)                            /*!< PRGB Bit Offset */
3701 #define FLCTL_IFG_PRGB                           ((uint32_t)0x00000010)
3702 #define FLCTL_IFG_ERASE_OFS                      ( 5)                            /*!< ERASE Bit Offset */
3703 #define FLCTL_IFG_ERASE                          ((uint32_t)0x00000020)
3704 #define FLCTL_IFG_BMRK_OFS                       ( 8)                            /*!< BMRK Bit Offset */
3705 #define FLCTL_IFG_BMRK                           ((uint32_t)0x00000100)
3706 #define FLCTL_IFG_PRG_ERR_OFS                    ( 9)                            /*!< PRG_ERR Bit Offset */
3707 #define FLCTL_IFG_PRG_ERR                        ((uint32_t)0x00000200)
3708 #define FLCTL_IE_RDBRST_OFS                      ( 0)                            /*!< RDBRST Bit Offset */
3709 #define FLCTL_IE_RDBRST                          ((uint32_t)0x00000001)
3710 #define FLCTL_IE_AVPRE_OFS                       ( 1)                            /*!< AVPRE Bit Offset */
3711 #define FLCTL_IE_AVPRE                           ((uint32_t)0x00000002)
3712 #define FLCTL_IE_AVPST_OFS                       ( 2)                            /*!< AVPST Bit Offset */
3713 #define FLCTL_IE_AVPST                           ((uint32_t)0x00000004)
3714 #define FLCTL_IE_PRG_OFS                         ( 3)                            /*!< PRG Bit Offset */
3715 #define FLCTL_IE_PRG                             ((uint32_t)0x00000008)
3716 #define FLCTL_IE_PRGB_OFS                        ( 4)                            /*!< PRGB Bit Offset */
3717 #define FLCTL_IE_PRGB                            ((uint32_t)0x00000010)
3718 #define FLCTL_IE_ERASE_OFS                       ( 5)                            /*!< ERASE Bit Offset */
3719 #define FLCTL_IE_ERASE                           ((uint32_t)0x00000020)
3720 #define FLCTL_IE_BMRK_OFS                        ( 8)                            /*!< BMRK Bit Offset */
3721 #define FLCTL_IE_BMRK                            ((uint32_t)0x00000100)
3722 #define FLCTL_IE_PRG_ERR_OFS                     ( 9)                            /*!< PRG_ERR Bit Offset */
3723 #define FLCTL_IE_PRG_ERR                         ((uint32_t)0x00000200)
3724 #define FLCTL_CLRIFG_RDBRST_OFS                  ( 0)                            /*!< RDBRST Bit Offset */
3725 #define FLCTL_CLRIFG_RDBRST                      ((uint32_t)0x00000001)
3726 #define FLCTL_CLRIFG_AVPRE_OFS                   ( 1)                            /*!< AVPRE Bit Offset */
3727 #define FLCTL_CLRIFG_AVPRE                       ((uint32_t)0x00000002)
3728 #define FLCTL_CLRIFG_AVPST_OFS                   ( 2)                            /*!< AVPST Bit Offset */
3729 #define FLCTL_CLRIFG_AVPST                       ((uint32_t)0x00000004)
3730 #define FLCTL_CLRIFG_PRG_OFS                     ( 3)                            /*!< PRG Bit Offset */
3731 #define FLCTL_CLRIFG_PRG                         ((uint32_t)0x00000008)
3732 #define FLCTL_CLRIFG_PRGB_OFS                    ( 4)                            /*!< PRGB Bit Offset */
3733 #define FLCTL_CLRIFG_PRGB                        ((uint32_t)0x00000010)
3734 #define FLCTL_CLRIFG_ERASE_OFS                   ( 5)                            /*!< ERASE Bit Offset */
3735 #define FLCTL_CLRIFG_ERASE                       ((uint32_t)0x00000020)
3736 #define FLCTL_CLRIFG_BMRK_OFS                    ( 8)                            /*!< BMRK Bit Offset */
3737 #define FLCTL_CLRIFG_BMRK                        ((uint32_t)0x00000100)
3738 #define FLCTL_CLRIFG_PRG_ERR_OFS                 ( 9)                            /*!< PRG_ERR Bit Offset */
3739 #define FLCTL_CLRIFG_PRG_ERR                     ((uint32_t)0x00000200)
3740 #define FLCTL_SETIFG_RDBRST_OFS                  ( 0)                            /*!< RDBRST Bit Offset */
3741 #define FLCTL_SETIFG_RDBRST                      ((uint32_t)0x00000001)
3742 #define FLCTL_SETIFG_AVPRE_OFS                   ( 1)                            /*!< AVPRE Bit Offset */
3743 #define FLCTL_SETIFG_AVPRE                       ((uint32_t)0x00000002)
3744 #define FLCTL_SETIFG_AVPST_OFS                   ( 2)                            /*!< AVPST Bit Offset */
3745 #define FLCTL_SETIFG_AVPST                       ((uint32_t)0x00000004)
3746 #define FLCTL_SETIFG_PRG_OFS                     ( 3)                            /*!< PRG Bit Offset */
3747 #define FLCTL_SETIFG_PRG                         ((uint32_t)0x00000008)
3748 #define FLCTL_SETIFG_PRGB_OFS                    ( 4)                            /*!< PRGB Bit Offset */
3749 #define FLCTL_SETIFG_PRGB                        ((uint32_t)0x00000010)
3750 #define FLCTL_SETIFG_ERASE_OFS                   ( 5)                            /*!< ERASE Bit Offset */
3751 #define FLCTL_SETIFG_ERASE                       ((uint32_t)0x00000020)
3752 #define FLCTL_SETIFG_BMRK_OFS                    ( 8)                            /*!< BMRK Bit Offset */
3753 #define FLCTL_SETIFG_BMRK                        ((uint32_t)0x00000100)
3754 #define FLCTL_SETIFG_PRG_ERR_OFS                 ( 9)                            /*!< PRG_ERR Bit Offset */
3755 #define FLCTL_SETIFG_PRG_ERR                     ((uint32_t)0x00000200)
3756 #define FLCTL_READ_TIMCTL_SETUP_OFS              ( 0)                            /*!< SETUP Bit Offset */
3757 #define FLCTL_READ_TIMCTL_SETUP_MASK             ((uint32_t)0x000000FF)          /*!< SETUP Bit Mask */
3758 #define FLCTL_READ_TIMCTL_IREF_BOOST1_OFS        (12)                            /*!< IREF_BOOST1 Bit Offset */
3759 #define FLCTL_READ_TIMCTL_IREF_BOOST1_MASK       ((uint32_t)0x0000F000)          /*!< IREF_BOOST1 Bit Mask */
3760 #define FLCTL_READ_TIMCTL_SETUP_LONG_OFS         (16)                            /*!< SETUP_LONG Bit Offset */
3761 #define FLCTL_READ_TIMCTL_SETUP_LONG_MASK        ((uint32_t)0x00FF0000)          /*!< SETUP_LONG Bit Mask */
3762 #define FLCTL_READMARGIN_TIMCTL_SETUP_OFS        ( 0)                            /*!< SETUP Bit Offset */
3763 #define FLCTL_READMARGIN_TIMCTL_SETUP_MASK       ((uint32_t)0x000000FF)          /*!< SETUP Bit Mask */
3764 #define FLCTL_PRGVER_TIMCTL_SETUP_OFS            ( 0)                            /*!< SETUP Bit Offset */
3765 #define FLCTL_PRGVER_TIMCTL_SETUP_MASK           ((uint32_t)0x000000FF)          /*!< SETUP Bit Mask */
3766 #define FLCTL_PRGVER_TIMCTL_ACTIVE_OFS           ( 8)                            /*!< ACTIVE Bit Offset */
3767 #define FLCTL_PRGVER_TIMCTL_ACTIVE_MASK          ((uint32_t)0x00000F00)          /*!< ACTIVE Bit Mask */
3768 #define FLCTL_PRGVER_TIMCTL_HOLD_OFS             (12)                            /*!< HOLD Bit Offset */
3769 #define FLCTL_PRGVER_TIMCTL_HOLD_MASK            ((uint32_t)0x0000F000)          /*!< HOLD Bit Mask */
3770 #define FLCTL_ERSVER_TIMCTL_SETUP_OFS            ( 0)                            /*!< SETUP Bit Offset */
3771 #define FLCTL_ERSVER_TIMCTL_SETUP_MASK           ((uint32_t)0x000000FF)          /*!< SETUP Bit Mask */
3772 #define FLCTL_LKGVER_TIMCTL_SETUP_OFS            ( 0)                            /*!< SETUP Bit Offset */
3773 #define FLCTL_LKGVER_TIMCTL_SETUP_MASK           ((uint32_t)0x000000FF)          /*!< SETUP Bit Mask */
3774 #define FLCTL_PROGRAM_TIMCTL_SETUP_OFS           ( 0)                            /*!< SETUP Bit Offset */
3775 #define FLCTL_PROGRAM_TIMCTL_SETUP_MASK          ((uint32_t)0x000000FF)          /*!< SETUP Bit Mask */
3776 #define FLCTL_PROGRAM_TIMCTL_ACTIVE_OFS          ( 8)                            /*!< ACTIVE Bit Offset */
3777 #define FLCTL_PROGRAM_TIMCTL_ACTIVE_MASK         ((uint32_t)0x0FFFFF00)          /*!< ACTIVE Bit Mask */
3778 #define FLCTL_PROGRAM_TIMCTL_HOLD_OFS            (28)                            /*!< HOLD Bit Offset */
3779 #define FLCTL_PROGRAM_TIMCTL_HOLD_MASK           ((uint32_t)0xF0000000)          /*!< HOLD Bit Mask */
3780 #define FLCTL_ERASE_TIMCTL_SETUP_OFS             ( 0)                            /*!< SETUP Bit Offset */
3781 #define FLCTL_ERASE_TIMCTL_SETUP_MASK            ((uint32_t)0x000000FF)          /*!< SETUP Bit Mask */
3782 #define FLCTL_ERASE_TIMCTL_ACTIVE_OFS            ( 8)                            /*!< ACTIVE Bit Offset */
3783 #define FLCTL_ERASE_TIMCTL_ACTIVE_MASK           ((uint32_t)0x0FFFFF00)          /*!< ACTIVE Bit Mask */
3784 #define FLCTL_ERASE_TIMCTL_HOLD_OFS              (28)                            /*!< HOLD Bit Offset */
3785 #define FLCTL_ERASE_TIMCTL_HOLD_MASK             ((uint32_t)0xF0000000)          /*!< HOLD Bit Mask */
3786 #define FLCTL_MASSERASE_TIMCTL_BOOST_ACTIVE_OFS  ( 0)                            /*!< BOOST_ACTIVE Bit Offset */
3787 #define FLCTL_MASSERASE_TIMCTL_BOOST_ACTIVE_MASK ((uint32_t)0x000000FF)          /*!< BOOST_ACTIVE Bit Mask */
3788 #define FLCTL_MASSERASE_TIMCTL_BOOST_HOLD_OFS    ( 8)                            /*!< BOOST_HOLD Bit Offset */
3789 #define FLCTL_MASSERASE_TIMCTL_BOOST_HOLD_MASK   ((uint32_t)0x0000FF00)          /*!< BOOST_HOLD Bit Mask */
3790 #define FLCTL_BURSTPRG_TIMCTL_ACTIVE_OFS         ( 8)                            /*!< ACTIVE Bit Offset */
3791 #define FLCTL_BURSTPRG_TIMCTL_ACTIVE_MASK        ((uint32_t)0x0FFFFF00)          /*!< ACTIVE Bit Mask */
3792 #define MPU_RASR_SIZE__32B                       ((uint32_t)0x00000008)          /*!< 32B */
3793 #define MPU_RASR_SIZE__64B                       ((uint32_t)0x0000000A)          /*!< 64B */
3794 #define MPU_RASR_SIZE__128B                      ((uint32_t)0x0000000C)          /*!< 128B */
3795 #define MPU_RASR_SIZE__256B                      ((uint32_t)0x0000000E)          /*!< 256B */
3796 #define MPU_RASR_SIZE__512B                      ((uint32_t)0x00000010)          /*!< 512B */
3797 #define MPU_RASR_SIZE__1K                        ((uint32_t)0x00000012)          /*!< 1KB */
3798 #define MPU_RASR_SIZE__2K                        ((uint32_t)0x00000014)          /*!< 2KB */
3799 #define MPU_RASR_SIZE__4K                        ((uint32_t)0x00000016)          /*!< 4KB */
3800 #define MPU_RASR_SIZE__8K                        ((uint32_t)0x00000018)          /*!< 8KB */
3801 #define MPU_RASR_SIZE__16K                       ((uint32_t)0x0000001A)          /*!< 16KB */
3802 #define MPU_RASR_SIZE__32K                       ((uint32_t)0x0000001C)          /*!< 32KB */
3803 #define MPU_RASR_SIZE__64K                       ((uint32_t)0x0000001E)          /*!< 64KB */
3804 #define MPU_RASR_SIZE__128K                      ((uint32_t)0x00000020)          /*!< 128KB */
3805 #define MPU_RASR_SIZE__256K                      ((uint32_t)0x00000022)          /*!< 256KB */
3806 #define MPU_RASR_SIZE__512K                      ((uint32_t)0x00000024)          /*!< 512KB */
3807 #define MPU_RASR_SIZE__1M                        ((uint32_t)0x00000026)          /*!< 1MB */
3808 #define MPU_RASR_SIZE__2M                        ((uint32_t)0x00000028)          /*!< 2MB */
3809 #define MPU_RASR_SIZE__4M                        ((uint32_t)0x0000002A)          /*!< 4MB */
3810 #define MPU_RASR_SIZE__8M                        ((uint32_t)0x0000002C)          /*!< 8MB */
3811 #define MPU_RASR_SIZE__16M                       ((uint32_t)0x0000002E)          /*!< 16MB */
3812 #define MPU_RASR_SIZE__32M                       ((uint32_t)0x00000030)          /*!< 32MB */
3813 #define MPU_RASR_SIZE__64M                       ((uint32_t)0x00000032)          /*!< 64MB */
3814 #define MPU_RASR_SIZE__128M                      ((uint32_t)0x00000034)          /*!< 128MB */
3815 #define MPU_RASR_SIZE__256M                      ((uint32_t)0x00000036)          /*!< 256MB */
3816 #define MPU_RASR_SIZE__512M                      ((uint32_t)0x00000038)          /*!< 512MB */
3817 #define MPU_RASR_SIZE__1G                        ((uint32_t)0x0000003A)          /*!< 1GB */
3818 #define MPU_RASR_SIZE__2G                        ((uint32_t)0x0000003C)          /*!< 2GB */
3819 #define MPU_RASR_SIZE__4G                        ((uint32_t)0x0000003E)          /*!< 4GB */
3820 #define MPU_RASR_AP_PRV_NO_USR_NO                ((uint32_t)0x00000000)          /*!< Privileged permissions: No access. User permissions: No access. */
3821 #define MPU_RASR_AP_PRV_RW_USR_NO                ((uint32_t)0x01000000)          /*!< Privileged permissions: Read-write. User permissions: No access. */
3822 #define MPU_RASR_AP_PRV_RW_USR_RO                ((uint32_t)0x02000000)          /*!< Privileged permissions: Read-write. User permissions: Read-only. */
3823 #define MPU_RASR_AP_PRV_RW_USR_RW                ((uint32_t)0x03000000)          /*!< Privileged permissions: Read-write. User permissions: Read-write. */
3824 #define MPU_RASR_AP_PRV_RO_USR_NO                ((uint32_t)0x05000000)          /*!< Privileged permissions: Read-only. User permissions: No access. */
3825 #define MPU_RASR_AP_PRV_RO_USR_RO                ((uint32_t)0x06000000)          /*!< Privileged permissions: Read-only. User permissions: Read-only. */
3826 #define MPU_RASR_AP_EXEC                         ((uint32_t)0x00000000)          /*!< Instruction access enabled */
3827 #define MPU_RASR_AP_NOEXEC                       ((uint32_t)0x10000000)          /*!< Instruction access disabled */
3828 #define NVIC_IPR0_PRI_0_OFS                      ( 0)                            /*!< PRI_0 Offset */
3829 #define NVIC_IPR0_PRI_0_M                        ((uint32_t)0x000000ff)          /*  */
3830 #define NVIC_IPR0_PRI_1_OFS                      ( 8)                            /*!< PRI_1 Offset */
3831 #define NVIC_IPR0_PRI_1_M                        ((uint32_t)0x0000ff00)          /*  */
3832 #define NVIC_IPR0_PRI_2_OFS                      (16)                            /*!< PRI_2 Offset */
3833 #define NVIC_IPR0_PRI_2_M                        ((uint32_t)0x00ff0000)          /*  */
3834 #define NVIC_IPR0_PRI_3_OFS                      (24)                            /*!< PRI_3 Offset */
3835 #define NVIC_IPR0_PRI_3_M                        ((uint32_t)0xff000000)          /*  */
3836 #define NVIC_IPR1_PRI_4_OFS                      ( 0)                            /*!< PRI_4 Offset */
3837 #define NVIC_IPR1_PRI_4_M                        ((uint32_t)0x000000ff)          /*  */
3838 #define NVIC_IPR1_PRI_5_OFS                      ( 8)                            /*!< PRI_5 Offset */
3839 #define NVIC_IPR1_PRI_5_M                        ((uint32_t)0x0000ff00)          /*  */
3840 #define NVIC_IPR1_PRI_6_OFS                      (16)                            /*!< PRI_6 Offset */
3841 #define NVIC_IPR1_PRI_6_M                        ((uint32_t)0x00ff0000)          /*  */
3842 #define NVIC_IPR1_PRI_7_OFS                      (24)                            /*!< PRI_7 Offset */
3843 #define NVIC_IPR1_PRI_7_M                        ((uint32_t)0xff000000)          /*  */
3844 #define NVIC_IPR2_PRI_8_OFS                      ( 0)                            /*!< PRI_8 Offset */
3845 #define NVIC_IPR2_PRI_8_M                        ((uint32_t)0x000000ff)          /*  */
3846 #define NVIC_IPR2_PRI_9_OFS                      ( 8)                            /*!< PRI_9 Offset */
3847 #define NVIC_IPR2_PRI_9_M                        ((uint32_t)0x0000ff00)          /*  */
3848 #define NVIC_IPR2_PRI_10_OFS                     (16)                            /*!< PRI_10 Offset */
3849 #define NVIC_IPR2_PRI_10_M                       ((uint32_t)0x00ff0000)          /*  */
3850 #define NVIC_IPR2_PRI_11_OFS                     (24)                            /*!< PRI_11 Offset */
3851 #define NVIC_IPR2_PRI_11_M                       ((uint32_t)0xff000000)          /*  */
3852 #define NVIC_IPR3_PRI_12_OFS                     ( 0)                            /*!< PRI_12 Offset */
3853 #define NVIC_IPR3_PRI_12_M                       ((uint32_t)0x000000ff)          /*  */
3854 #define NVIC_IPR3_PRI_13_OFS                     ( 8)                            /*!< PRI_13 Offset */
3855 #define NVIC_IPR3_PRI_13_M                       ((uint32_t)0x0000ff00)          /*  */
3856 #define NVIC_IPR3_PRI_14_OFS                     (16)                            /*!< PRI_14 Offset */
3857 #define NVIC_IPR3_PRI_14_M                       ((uint32_t)0x00ff0000)          /*  */
3858 #define NVIC_IPR3_PRI_15_OFS                     (24)                            /*!< PRI_15 Offset */
3859 #define NVIC_IPR3_PRI_15_M                       ((uint32_t)0xff000000)          /*  */
3860 #define NVIC_IPR4_PRI_16_OFS                     ( 0)                            /*!< PRI_16 Offset */
3861 #define NVIC_IPR4_PRI_16_M                       ((uint32_t)0x000000ff)          /*  */
3862 #define NVIC_IPR4_PRI_17_OFS                     ( 8)                            /*!< PRI_17 Offset */
3863 #define NVIC_IPR4_PRI_17_M                       ((uint32_t)0x0000ff00)          /*  */
3864 #define NVIC_IPR4_PRI_18_OFS                     (16)                            /*!< PRI_18 Offset */
3865 #define NVIC_IPR4_PRI_18_M                       ((uint32_t)0x00ff0000)          /*  */
3866 #define NVIC_IPR4_PRI_19_OFS                     (24)                            /*!< PRI_19 Offset */
3867 #define NVIC_IPR4_PRI_19_M                       ((uint32_t)0xff000000)          /*  */
3868 #define NVIC_IPR5_PRI_20_OFS                     ( 0)                            /*!< PRI_20 Offset */
3869 #define NVIC_IPR5_PRI_20_M                       ((uint32_t)0x000000ff)          /*  */
3870 #define NVIC_IPR5_PRI_21_OFS                     ( 8)                            /*!< PRI_21 Offset */
3871 #define NVIC_IPR5_PRI_21_M                       ((uint32_t)0x0000ff00)          /*  */
3872 #define NVIC_IPR5_PRI_22_OFS                     (16)                            /*!< PRI_22 Offset */
3873 #define NVIC_IPR5_PRI_22_M                       ((uint32_t)0x00ff0000)          /*  */
3874 #define NVIC_IPR5_PRI_23_OFS                     (24)                            /*!< PRI_23 Offset */
3875 #define NVIC_IPR5_PRI_23_M                       ((uint32_t)0xff000000)          /*  */
3876 #define NVIC_IPR6_PRI_24_OFS                     ( 0)                            /*!< PRI_24 Offset */
3877 #define NVIC_IPR6_PRI_24_M                       ((uint32_t)0x000000ff)          /*  */
3878 #define NVIC_IPR6_PRI_25_OFS                     ( 8)                            /*!< PRI_25 Offset */
3879 #define NVIC_IPR6_PRI_25_M                       ((uint32_t)0x0000ff00)          /*  */
3880 #define NVIC_IPR6_PRI_26_OFS                     (16)                            /*!< PRI_26 Offset */
3881 #define NVIC_IPR6_PRI_26_M                       ((uint32_t)0x00ff0000)          /*  */
3882 #define NVIC_IPR6_PRI_27_OFS                     (24)                            /*!< PRI_27 Offset */
3883 #define NVIC_IPR6_PRI_27_M                       ((uint32_t)0xff000000)          /*  */
3884 #define NVIC_IPR7_PRI_28_OFS                     ( 0)                            /*!< PRI_28 Offset */
3885 #define NVIC_IPR7_PRI_28_M                       ((uint32_t)0x000000ff)          /*  */
3886 #define NVIC_IPR7_PRI_29_OFS                     ( 8)                            /*!< PRI_29 Offset */
3887 #define NVIC_IPR7_PRI_29_M                       ((uint32_t)0x0000ff00)          /*  */
3888 #define NVIC_IPR7_PRI_30_OFS                     (16)                            /*!< PRI_30 Offset */
3889 #define NVIC_IPR7_PRI_30_M                       ((uint32_t)0x00ff0000)          /*  */
3890 #define NVIC_IPR7_PRI_31_OFS                     (24)                            /*!< PRI_31 Offset */
3891 #define NVIC_IPR7_PRI_31_M                       ((uint32_t)0xff000000)          /*  */
3892 #define NVIC_IPR8_PRI_32_OFS                     ( 0)                            /*!< PRI_32 Offset */
3893 #define NVIC_IPR8_PRI_32_M                       ((uint32_t)0x000000ff)          /*  */
3894 #define NVIC_IPR8_PRI_33_OFS                     ( 8)                            /*!< PRI_33 Offset */
3895 #define NVIC_IPR8_PRI_33_M                       ((uint32_t)0x0000ff00)          /*  */
3896 #define NVIC_IPR8_PRI_34_OFS                     (16)                            /*!< PRI_34 Offset */
3897 #define NVIC_IPR8_PRI_34_M                       ((uint32_t)0x00ff0000)          /*  */
3898 #define NVIC_IPR8_PRI_35_OFS                     (24)                            /*!< PRI_35 Offset */
3899 #define NVIC_IPR8_PRI_35_M                       ((uint32_t)0xff000000)          /*  */
3900 #define NVIC_IPR9_PRI_36_OFS                     ( 0)                            /*!< PRI_36 Offset */
3901 #define NVIC_IPR9_PRI_36_M                       ((uint32_t)0x000000ff)          /*  */
3902 #define NVIC_IPR9_PRI_37_OFS                     ( 8)                            /*!< PRI_37 Offset */
3903 #define NVIC_IPR9_PRI_37_M                       ((uint32_t)0x0000ff00)          /*  */
3904 #define NVIC_IPR9_PRI_38_OFS                     (16)                            /*!< PRI_38 Offset */
3905 #define NVIC_IPR9_PRI_38_M                       ((uint32_t)0x00ff0000)          /*  */
3906 #define NVIC_IPR9_PRI_39_OFS                     (24)                            /*!< PRI_39 Offset */
3907 #define NVIC_IPR9_PRI_39_M                       ((uint32_t)0xff000000)          /*  */
3908 #define NVIC_IPR10_PRI_40_OFS                    ( 0)                            /*!< PRI_40 Offset */
3909 #define NVIC_IPR10_PRI_40_M                      ((uint32_t)0x000000ff)          /*  */
3910 #define NVIC_IPR10_PRI_41_OFS                    ( 8)                            /*!< PRI_41 Offset */
3911 #define NVIC_IPR10_PRI_41_M                      ((uint32_t)0x0000ff00)          /*  */
3912 #define NVIC_IPR10_PRI_42_OFS                    (16)                            /*!< PRI_42 Offset */
3913 #define NVIC_IPR10_PRI_42_M                      ((uint32_t)0x00ff0000)          /*  */
3914 #define NVIC_IPR10_PRI_43_OFS                    (24)                            /*!< PRI_43 Offset */
3915 #define NVIC_IPR10_PRI_43_M                      ((uint32_t)0xff000000)          /*  */
3916 #define NVIC_IPR11_PRI_44_OFS                    ( 0)                            /*!< PRI_44 Offset */
3917 #define NVIC_IPR11_PRI_44_M                      ((uint32_t)0x000000ff)          /*  */
3918 #define NVIC_IPR11_PRI_45_OFS                    ( 8)                            /*!< PRI_45 Offset */
3919 #define NVIC_IPR11_PRI_45_M                      ((uint32_t)0x0000ff00)          /*  */
3920 #define NVIC_IPR11_PRI_46_OFS                    (16)                            /*!< PRI_46 Offset */
3921 #define NVIC_IPR11_PRI_46_M                      ((uint32_t)0x00ff0000)          /*  */
3922 #define NVIC_IPR11_PRI_47_OFS                    (24)                            /*!< PRI_47 Offset */
3923 #define NVIC_IPR11_PRI_47_M                      ((uint32_t)0xff000000)          /*  */
3924 #define NVIC_IPR12_PRI_48_OFS                    ( 0)                            /*!< PRI_48 Offset */
3925 #define NVIC_IPR12_PRI_48_M                      ((uint32_t)0x000000ff)          /*  */
3926 #define NVIC_IPR12_PRI_49_OFS                    ( 8)                            /*!< PRI_49 Offset */
3927 #define NVIC_IPR12_PRI_49_M                      ((uint32_t)0x0000ff00)          /*  */
3928 #define NVIC_IPR12_PRI_50_OFS                    (16)                            /*!< PRI_50 Offset */
3929 #define NVIC_IPR12_PRI_50_M                      ((uint32_t)0x00ff0000)          /*  */
3930 #define NVIC_IPR12_PRI_51_OFS                    (24)                            /*!< PRI_51 Offset */
3931 #define NVIC_IPR12_PRI_51_M                      ((uint32_t)0xff000000)          /*  */
3932 #define NVIC_IPR13_PRI_52_OFS                    ( 0)                            /*!< PRI_52 Offset */
3933 #define NVIC_IPR13_PRI_52_M                      ((uint32_t)0x000000ff)          /*  */
3934 #define NVIC_IPR13_PRI_53_OFS                    ( 8)                            /*!< PRI_53 Offset */
3935 #define NVIC_IPR13_PRI_53_M                      ((uint32_t)0x0000ff00)          /*  */
3936 #define NVIC_IPR13_PRI_54_OFS                    (16)                            /*!< PRI_54 Offset */
3937 #define NVIC_IPR13_PRI_54_M                      ((uint32_t)0x00ff0000)          /*  */
3938 #define NVIC_IPR13_PRI_55_OFS                    (24)                            /*!< PRI_55 Offset */
3939 #define NVIC_IPR13_PRI_55_M                      ((uint32_t)0xff000000)          /*  */
3940 #define NVIC_IPR14_PRI_56_OFS                    ( 0)                            /*!< PRI_56 Offset */
3941 #define NVIC_IPR14_PRI_56_M                      ((uint32_t)0x000000ff)          /*  */
3942 #define NVIC_IPR14_PRI_57_OFS                    ( 8)                            /*!< PRI_57 Offset */
3943 #define NVIC_IPR14_PRI_57_M                      ((uint32_t)0x0000ff00)          /*  */
3944 #define NVIC_IPR14_PRI_58_OFS                    (16)                            /*!< PRI_58 Offset */
3945 #define NVIC_IPR14_PRI_58_M                      ((uint32_t)0x00ff0000)          /*  */
3946 #define NVIC_IPR14_PRI_59_OFS                    (24)                            /*!< PRI_59 Offset */
3947 #define NVIC_IPR14_PRI_59_M                      ((uint32_t)0xff000000)          /*  */
3948 #define NVIC_IPR15_PRI_60_OFS                    ( 0)                            /*!< PRI_60 Offset */
3949 #define NVIC_IPR15_PRI_60_M                      ((uint32_t)0x000000ff)          /*  */
3950 #define NVIC_IPR15_PRI_61_OFS                    ( 8)                            /*!< PRI_61 Offset */
3951 #define NVIC_IPR15_PRI_61_M                      ((uint32_t)0x0000ff00)          /*  */
3952 #define NVIC_IPR15_PRI_62_OFS                    (16)                            /*!< PRI_62 Offset */
3953 #define NVIC_IPR15_PRI_62_M                      ((uint32_t)0x00ff0000)          /*  */
3954 #define NVIC_IPR15_PRI_63_OFS                    (24)                            /*!< PRI_63 Offset */
3955 #define NVIC_IPR15_PRI_63_M                      ((uint32_t)0xff000000)          /*  */
3956 #define PCM_CTL0_AMR_OFS                         ( 0)                            /*!< AMR Bit Offset */
3957 #define PCM_CTL0_AMR_MASK                        ((uint32_t)0x0000000F)          /*!< AMR Bit Mask */
3958 #define PCM_CTL0_AMR0                            ((uint32_t)0x00000001)          /*!< AMR Bit 0 */
3959 #define PCM_CTL0_AMR1                            ((uint32_t)0x00000002)          /*!< AMR Bit 1 */
3960 #define PCM_CTL0_AMR2                            ((uint32_t)0x00000004)          /*!< AMR Bit 2 */
3961 #define PCM_CTL0_AMR3                            ((uint32_t)0x00000008)          /*!< AMR Bit 3 */
3962 #define PCM_CTL0_AMR_0                           ((uint32_t)0x00000000)          /*!< LDO based Active Mode at Core voltage setting 0. */
3963 #define PCM_CTL0_AMR_1                           ((uint32_t)0x00000001)          /*!< LDO based Active Mode at Core voltage setting 1. */
3964 #define PCM_CTL0_AMR_4                           ((uint32_t)0x00000004)          /*!< DC-DC based Active Mode at Core voltage setting 0. */
3965 #define PCM_CTL0_AMR_5                           ((uint32_t)0x00000005)          /*!< DC-DC based Active Mode at Core voltage setting 1. */
3966 #define PCM_CTL0_AMR_8                           ((uint32_t)0x00000008)          /*!< Low-Frequency Active Mode at Core voltage setting 0. */
3967 #define PCM_CTL0_AMR_9                           ((uint32_t)0x00000009)          /*!< Low-Frequency Active Mode at Core voltage setting 1. */
3968 #define PCM_CTL0_AMR__AM_LDO_VCORE0              ((uint32_t)0x00000000)          /*!< LDO based Active Mode at Core voltage setting 0. */
3969 #define PCM_CTL0_AMR__AM_LDO_VCORE1              ((uint32_t)0x00000001)          /*!< LDO based Active Mode at Core voltage setting 1. */
3970 #define PCM_CTL0_AMR__AM_DCDC_VCORE0             ((uint32_t)0x00000004)          /*!< DC-DC based Active Mode at Core voltage setting 0. */
3971 #define PCM_CTL0_AMR__AM_DCDC_VCORE1             ((uint32_t)0x00000005)          /*!< DC-DC based Active Mode at Core voltage setting 1. */
3972 #define PCM_CTL0_AMR__AM_LF_VCORE0               ((uint32_t)0x00000008)          /*!< Low-Frequency Active Mode at Core voltage setting 0. */
3973 #define PCM_CTL0_AMR__AM_LF_VCORE1               ((uint32_t)0x00000009)          /*!< Low-Frequency Active Mode at Core voltage setting 1. */
3974 #define PCM_CTL0_LPMR_OFS                        ( 4)                            /*!< LPMR Bit Offset */
3975 #define PCM_CTL0_LPMR_MASK                       ((uint32_t)0x000000F0)          /*!< LPMR Bit Mask */
3976 #define PCM_CTL0_LPMR0                           ((uint32_t)0x00000010)          /*!< LPMR Bit 0 */
3977 #define PCM_CTL0_LPMR1                           ((uint32_t)0x00000020)          /*!< LPMR Bit 1 */
3978 #define PCM_CTL0_LPMR2                           ((uint32_t)0x00000040)          /*!< LPMR Bit 2 */
3979 #define PCM_CTL0_LPMR3                           ((uint32_t)0x00000080)          /*!< LPMR Bit 3 */
3980 #define PCM_CTL0_LPMR_0                          ((uint32_t)0x00000000)          /*!< LPM3. Core voltage setting is similar to the mode from which LPM3 is  */
3981 #define PCM_CTL0_LPMR_10                         ((uint32_t)0x000000A0)          /*!< LPM3.5. Core voltage setting 0. */
3982 #define PCM_CTL0_LPMR_12                         ((uint32_t)0x000000C0)          /*!< LPM4.5 */
3983 #define PCM_CTL0_LPMR__LPM3                      ((uint32_t)0x00000000)          /*!< LPM3. Core voltage setting is similar to the mode from which LPM3 is  */
3984 #define PCM_CTL0_LPMR__LPM35                     ((uint32_t)0x000000A0)          /*!< LPM3.5. Core voltage setting 0. */
3985 #define PCM_CTL0_LPMR__LPM45                     ((uint32_t)0x000000C0)          /*!< LPM4.5 */
3986 #define PCM_CTL0_CPM_OFS                         ( 8)                            /*!< CPM Bit Offset */
3987 #define PCM_CTL0_CPM_MASK                        ((uint32_t)0x00003F00)          /*!< CPM Bit Mask */
3988 #define PCM_CTL0_CPM0                            ((uint32_t)0x00000100)          /*!< CPM Bit 0 */
3989 #define PCM_CTL0_CPM1                            ((uint32_t)0x00000200)          /*!< CPM Bit 1 */
3990 #define PCM_CTL0_CPM2                            ((uint32_t)0x00000400)          /*!< CPM Bit 2 */
3991 #define PCM_CTL0_CPM3                            ((uint32_t)0x00000800)          /*!< CPM Bit 3 */
3992 #define PCM_CTL0_CPM4                            ((uint32_t)0x00001000)          /*!< CPM Bit 4 */
3993 #define PCM_CTL0_CPM5                            ((uint32_t)0x00002000)          /*!< CPM Bit 5 */
3994 #define PCM_CTL0_CPM_0                           ((uint32_t)0x00000000)          /*!< LDO based Active Mode at Core voltage setting 0. */
3995 #define PCM_CTL0_CPM_1                           ((uint32_t)0x00000100)          /*!< LDO based Active Mode at Core voltage setting 1. */
3996 #define PCM_CTL0_CPM_4                           ((uint32_t)0x00000400)          /*!< DC-DC based Active Mode at Core voltage setting 0. */
3997 #define PCM_CTL0_CPM_5                           ((uint32_t)0x00000500)          /*!< DC-DC based Active Mode at Core voltage setting 1. */
3998 #define PCM_CTL0_CPM_8                           ((uint32_t)0x00000800)          /*!< Low-Frequency Active Mode at Core voltage setting 0. */
3999 #define PCM_CTL0_CPM_9                           ((uint32_t)0x00000900)          /*!< Low-Frequency Active Mode at Core voltage setting 1. */
4000 #define PCM_CTL0_CPM_16                          ((uint32_t)0x00001000)          /*!< LDO based LPM0 at Core voltage setting 0. */
4001 #define PCM_CTL0_CPM_17                          ((uint32_t)0x00001100)          /*!< LDO based LPM0 at Core voltage setting 1. */
4002 #define PCM_CTL0_CPM_20                          ((uint32_t)0x00001400)          /*!< DC-DC based LPM0 at Core voltage setting 0. */
4003 #define PCM_CTL0_CPM_21                          ((uint32_t)0x00001500)          /*!< DC-DC based LPM0 at Core voltage setting 1. */
4004 #define PCM_CTL0_CPM_24                          ((uint32_t)0x00001800)          /*!< Low-Frequency LPM0 at Core voltage setting 0. */
4005 #define PCM_CTL0_CPM_25                          ((uint32_t)0x00001900)          /*!< Low-Frequency LPM0 at Core voltage setting 1. */
4006 #define PCM_CTL0_CPM_32                          ((uint32_t)0x00002000)          /*!< LPM3 */
4007 #define PCM_CTL0_CPM__AM_LDO_VCORE0              ((uint32_t)0x00000000)          /*!< LDO based Active Mode at Core voltage setting 0. */
4008 #define PCM_CTL0_CPM__AM_LDO_VCORE1              ((uint32_t)0x00000100)          /*!< LDO based Active Mode at Core voltage setting 1. */
4009 #define PCM_CTL0_CPM__AM_DCDC_VCORE0             ((uint32_t)0x00000400)          /*!< DC-DC based Active Mode at Core voltage setting 0. */
4010 #define PCM_CTL0_CPM__AM_DCDC_VCORE1             ((uint32_t)0x00000500)          /*!< DC-DC based Active Mode at Core voltage setting 1. */
4011 #define PCM_CTL0_CPM__AM_LF_VCORE0               ((uint32_t)0x00000800)          /*!< Low-Frequency Active Mode at Core voltage setting 0. */
4012 #define PCM_CTL0_CPM__AM_LF_VCORE1               ((uint32_t)0x00000900)          /*!< Low-Frequency Active Mode at Core voltage setting 1. */
4013 #define PCM_CTL0_CPM__LPM0_LDO_VCORE0            ((uint32_t)0x00001000)          /*!< LDO based LPM0 at Core voltage setting 0. */
4014 #define PCM_CTL0_CPM__LPM0_LDO_VCORE1            ((uint32_t)0x00001100)          /*!< LDO based LPM0 at Core voltage setting 1. */
4015 #define PCM_CTL0_CPM__LPM0_DCDC_VCORE0           ((uint32_t)0x00001400)          /*!< DC-DC based LPM0 at Core voltage setting 0. */
4016 #define PCM_CTL0_CPM__LPM0_DCDC_VCORE1           ((uint32_t)0x00001500)          /*!< DC-DC based LPM0 at Core voltage setting 1. */
4017 #define PCM_CTL0_CPM__LPM0_LF_VCORE0             ((uint32_t)0x00001800)          /*!< Low-Frequency LPM0 at Core voltage setting 0. */
4018 #define PCM_CTL0_CPM__LPM0_LF_VCORE1             ((uint32_t)0x00001900)          /*!< Low-Frequency LPM0 at Core voltage setting 1. */
4019 #define PCM_CTL0_CPM__LPM3                       ((uint32_t)0x00002000)          /*!< LPM3 */
4020 #define PCM_CTL0_KEY_OFS                         (16)                            /*!< PCMKEY Bit Offset */
4021 #define PCM_CTL0_KEY_MASK                        ((uint32_t)0xFFFF0000)          /*!< PCMKEY Bit Mask */
4022 #define PCM_CTL1_LOCKLPM5_OFS                    ( 0)                            /*!< LOCKLPM5 Bit Offset */
4023 #define PCM_CTL1_LOCKLPM5                        ((uint32_t)0x00000001)          /*!< Lock LPM5 */
4024 #define PCM_CTL1_LOCKBKUP_OFS                    ( 1)                            /*!< LOCKBKUP Bit Offset */
4025 #define PCM_CTL1_LOCKBKUP                        ((uint32_t)0x00000002)          /*!< Lock Backup */
4026 #define PCM_CTL1_FORCE_LPM_ENTRY_OFS             ( 2)                            /*!< FORCE_LPM_ENTRY Bit Offset */
4027 #define PCM_CTL1_FORCE_LPM_ENTRY                 ((uint32_t)0x00000004)          /*!< Force LPM entry */
4028 #define PCM_CTL1_PMR_BUSY_OFS                    ( 8)                            /*!< PMR_BUSY Bit Offset */
4029 #define PCM_CTL1_PMR_BUSY                        ((uint32_t)0x00000100)          /*!< Power mode request busy flag */
4030 #define PCM_CTL1_KEY_OFS                         (16)                            /*!< PCMKEY Bit Offset */
4031 #define PCM_CTL1_KEY_MASK                        ((uint32_t)0xFFFF0000)          /*!< PCMKEY Bit Mask */
4032 #define PCM_IE_LPM_INVALID_TR_IE_OFS             ( 0)                            /*!< LPM_INVALID_TR_IE Bit Offset */
4033 #define PCM_IE_LPM_INVALID_TR_IE                 ((uint32_t)0x00000001)          /*!< LPM invalid transition interrupt enable */
4034 #define PCM_IE_LPM_INVALID_CLK_IE_OFS            ( 1)                            /*!< LPM_INVALID_CLK_IE Bit Offset */
4035 #define PCM_IE_LPM_INVALID_CLK_IE                ((uint32_t)0x00000002)          /*!< LPM invalid clock interrupt enable */
4036 #define PCM_IE_AM_INVALID_TR_IE_OFS              ( 2)                            /*!< AM_INVALID_TR_IE Bit Offset */
4037 #define PCM_IE_AM_INVALID_TR_IE                  ((uint32_t)0x00000004)          /*!< Active mode invalid transition interrupt enable */
4038 #define PCM_IE_DCDC_ERROR_IE_OFS                 ( 6)                            /*!< DCDC_ERROR_IE Bit Offset */
4039 #define PCM_IE_DCDC_ERROR_IE                     ((uint32_t)0x00000040)          /*!< DC-DC error interrupt enable */
4040 #define PCM_IFG_LPM_INVALID_TR_IFG_OFS           ( 0)                            /*!< LPM_INVALID_TR_IFG Bit Offset */
4041 #define PCM_IFG_LPM_INVALID_TR_IFG               ((uint32_t)0x00000001)          /*!< LPM invalid transition flag */
4042 #define PCM_IFG_LPM_INVALID_CLK_IFG_OFS          ( 1)                            /*!< LPM_INVALID_CLK_IFG Bit Offset */
4043 #define PCM_IFG_LPM_INVALID_CLK_IFG              ((uint32_t)0x00000002)          /*!< LPM invalid clock flag */
4044 #define PCM_IFG_AM_INVALID_TR_IFG_OFS            ( 2)                            /*!< AM_INVALID_TR_IFG Bit Offset */
4045 #define PCM_IFG_AM_INVALID_TR_IFG                ((uint32_t)0x00000004)          /*!< Active mode invalid transition flag */
4046 #define PCM_IFG_DCDC_ERROR_IFG_OFS               ( 6)                            /*!< DCDC_ERROR_IFG Bit Offset */
4047 #define PCM_IFG_DCDC_ERROR_IFG                   ((uint32_t)0x00000040)          /*!< DC-DC error flag */
4048 #define PCM_CLRIFG_CLR_LPM_INVALID_TR_IFG_OFS    ( 0)                            /*!< CLR_LPM_INVALID_TR_IFG Bit Offset */
4049 #define PCM_CLRIFG_CLR_LPM_INVALID_TR_IFG        ((uint32_t)0x00000001)          /*!< Clear LPM invalid transition flag */
4050 #define PCM_CLRIFG_CLR_LPM_INVALID_CLK_IFG_OFS   ( 1)                            /*!< CLR_LPM_INVALID_CLK_IFG Bit Offset */
4051 #define PCM_CLRIFG_CLR_LPM_INVALID_CLK_IFG       ((uint32_t)0x00000002)          /*!< Clear LPM invalid clock flag */
4052 #define PCM_CLRIFG_CLR_AM_INVALID_TR_IFG_OFS     ( 2)                            /*!< CLR_AM_INVALID_TR_IFG Bit Offset */
4053 #define PCM_CLRIFG_CLR_AM_INVALID_TR_IFG         ((uint32_t)0x00000004)          /*!< Clear active mode invalid transition flag */
4054 #define PCM_CLRIFG_CLR_DCDC_ERROR_IFG_OFS        ( 6)                            /*!< CLR_DCDC_ERROR_IFG Bit Offset */
4055 #define PCM_CLRIFG_CLR_DCDC_ERROR_IFG            ((uint32_t)0x00000040)          /*!< Clear DC-DC error flag */
4056 #define PCM_CTL0_KEY_VAL                         ((uint32_t)0x695A0000)          /*!< PCM key value */
4057 #define PCM_CTL1_KEY_VAL                         ((uint32_t)0x695A0000)          /*!< PCM key value */
4058 #define PMAP_CTL_LOCKED_OFS                      ( 0)                            /*!< PMAPLOCKED Bit Offset */
4059 #define PMAP_CTL_LOCKED                          ((uint16_t)0x0001)              /*!< Port mapping lock bit */
4060 #define PMAP_CTL_PRECFG_OFS                      ( 1)                            /*!< PMAPRECFG Bit Offset */
4061 #define PMAP_CTL_PRECFG                          ((uint16_t)0x0002)              /*!< Port mapping reconfiguration control bit */
4062 #define PMAP_NONE                                            0
4063 #define PMAP_UCA0CLK                                         1
4064 #define PMAP_UCA0RXD                                         2
4065 #define PMAP_UCA0SOMI                                        2
4066 #define PMAP_UCA0TXD                                         3
4067 #define PMAP_UCA0SIMO                                        3
4068 #define PMAP_UCB0CLK                                         4
4069 #define PMAP_UCB0SDA                                         5
4070 #define PMAP_UCB0SIMO                                        5
4071 #define PMAP_UCB0SCL                                         6
4072 #define PMAP_UCB0SOMI                                        6
4073 #define PMAP_UCA1STE                                         7
4074 #define PMAP_UCA1CLK                                         8
4075 #define PMAP_UCA1RXD                                         9
4076 #define PMAP_UCA1SOMI                                        9
4077 #define PMAP_UCA1TXD                                         10
4078 #define PMAP_UCA1SIMO                                        10
4079 #define PMAP_UCA2STE                                         11
4080 #define PMAP_UCA2CLK                                         12
4081 #define PMAP_UCA2RXD                                         13
4082 #define PMAP_UCA2SOMI                                        13
4083 #define PMAP_UCA2TXD                                         14
4084 #define PMAP_UCA2SIMO                                        14
4085 #define PMAP_UCB2STE                                         15
4086 #define PMAP_UCB2CLK                                         16
4087 #define PMAP_UCB2SDA                                         17
4088 #define PMAP_UCB2SIMO                                        17
4089 #define PMAP_UCB2SCL                                         18
4090 #define PMAP_UCB2SOMI                                        18
4091 #define PMAP_TA0CCR0A                                        19
4092 #define PMAP_TA0CCR1A                                        20
4093 #define PMAP_TA0CCR2A                                        21
4094 #define PMAP_TA0CCR3A                                        22
4095 #define PMAP_TA0CCR4A                                        23
4096 #define PMAP_TA1CCR1A                                        24
4097 #define PMAP_TA1CCR2A                                        25
4098 #define PMAP_TA1CCR3A                                        26
4099 #define PMAP_TA1CCR4A                                        27
4100 #define PMAP_TA0CLK                                          28
4101 #define PMAP_CE0OUT                                          28
4102 #define PMAP_TA1CLK                                          29
4103 #define PMAP_CE1OUT                                          29
4104 #define PMAP_DMAE0                                           30
4105 #define PMAP_SMCLK                                           30
4106 #define PMAP_ANALOG                                          31
4107 #define PMAP_KEYID_VAL                           ((uint16_t)0x2D52)              /*!< Port Mapping Key */
4108 #define PSS_KEY_KEY_OFS                          ( 0)                            /*!< PSSKEY Bit Offset */
4109 #define PSS_KEY_KEY_MASK                         ((uint32_t)0x0000FFFF)          /*!< PSSKEY Bit Mask */
4110 #define PSS_CTL0_SVSMHOFF_OFS                    ( 0)                            /*!< SVSMHOFF Bit Offset */
4111 #define PSS_CTL0_SVSMHOFF                        ((uint32_t)0x00000001)          /*!< SVSM high-side off */
4112 #define PSS_CTL0_SVSMHLP_OFS                     ( 1)                            /*!< SVSMHLP Bit Offset */
4113 #define PSS_CTL0_SVSMHLP                         ((uint32_t)0x00000002)          /*!< SVSM high-side low power normal performance mode */
4114 #define PSS_CTL0_SVSMHS_OFS                      ( 2)                            /*!< SVSMHS Bit Offset */
4115 #define PSS_CTL0_SVSMHS                          ((uint32_t)0x00000004)          /*!< Supply supervisor or monitor selection for the high-side */
4116 #define PSS_CTL0_SVSMHTH_OFS                     ( 3)                            /*!< SVSMHTH Bit Offset */
4117 #define PSS_CTL0_SVSMHTH_MASK                    ((uint32_t)0x00000038)          /*!< SVSMHTH Bit Mask */
4118 #define PSS_CTL0_SVMHOE_OFS                      ( 6)                            /*!< SVMHOE Bit Offset */
4119 #define PSS_CTL0_SVMHOE                          ((uint32_t)0x00000040)          /*!< SVSM high-side output enable */
4120 #define PSS_CTL0_SVMHOUTPOLAL_OFS                ( 7)                            /*!< SVMHOUTPOLAL Bit Offset */
4121 #define PSS_CTL0_SVMHOUTPOLAL                    ((uint32_t)0x00000080)          /*!< SVMHOUT pin polarity active low */
4122 #define PSS_CTL0_DCDC_FORCE_OFS                  (10)                            /*!< DCDC_FORCE Bit Offset */
4123 #define PSS_CTL0_DCDC_FORCE                      ((uint32_t)0x00000400)          /*!< Force DC-DC regulator operation */
4124 #define PSS_CTL0_VCORETRAN_OFS                   (12)                            /*!< VCORETRAN Bit Offset */
4125 #define PSS_CTL0_VCORETRAN_MASK                  ((uint32_t)0x00003000)          /*!< VCORETRAN Bit Mask */
4126 #define PSS_CTL0_VCORETRAN0                      ((uint32_t)0x00001000)          /*!< VCORETRAN Bit 0 */
4127 #define PSS_CTL0_VCORETRAN1                      ((uint32_t)0x00002000)          /*!< VCORETRAN Bit 1 */
4128 #define PSS_CTL0_VCORETRAN_0                     ((uint32_t)0x00000000)          /*!< 32 s / 100 mV */
4129 #define PSS_CTL0_VCORETRAN_1                     ((uint32_t)0x00001000)          /*!< 64 s / 100 mV */
4130 #define PSS_CTL0_VCORETRAN_2                     ((uint32_t)0x00002000)          /*!< 128 s / 100 mV (default) */
4131 #define PSS_CTL0_VCORETRAN_3                     ((uint32_t)0x00003000)          /*!< 256 s / 100 mV */
4132 #define PSS_CTL0_VCORETRAN__32                   ((uint32_t)0x00000000)          /*!< 32 s / 100 mV */
4133 #define PSS_CTL0_VCORETRAN__64                   ((uint32_t)0x00001000)          /*!< 64 s / 100 mV */
4134 #define PSS_CTL0_VCORETRAN__128                  ((uint32_t)0x00002000)          /*!< 128 s / 100 mV (default) */
4135 #define PSS_CTL0_VCORETRAN__256                  ((uint32_t)0x00003000)          /*!< 256 s / 100 mV */
4136 #define PSS_IE_SVSMHIE_OFS                       ( 1)                            /*!< SVSMHIE Bit Offset */
4137 #define PSS_IE_SVSMHIE                           ((uint32_t)0x00000002)          /*!< High-side SVSM interrupt enable */
4138 #define PSS_IFG_SVSMHIFG_OFS                     ( 1)                            /*!< SVSMHIFG Bit Offset */
4139 #define PSS_IFG_SVSMHIFG                         ((uint32_t)0x00000002)          /*!< High-side SVSM interrupt flag */
4140 #define PSS_CLRIFG_CLRSVSMHIFG_OFS               ( 1)                            /*!< CLRSVSMHIFG Bit Offset */
4141 #define PSS_CLRIFG_CLRSVSMHIFG                   ((uint32_t)0x00000002)          /*!< SVSMH clear interrupt flag */
4142 #define PSS_KEY_KEY_VAL                           ((uint32_t)0x0000695A)          /*!< PSS control key value */
4143 #define REF_A_CTL0_ON_OFS                        ( 0)                            /*!< REFON Bit Offset */
4144 #define REF_A_CTL0_ON                            ((uint16_t)0x0001)              /*!< Reference enable */
4145 #define REF_A_CTL0_OUT_OFS                       ( 1)                            /*!< REFOUT Bit Offset */
4146 #define REF_A_CTL0_OUT                           ((uint16_t)0x0002)              /*!< Reference output buffer */
4147 #define REF_A_CTL0_TCOFF_OFS                     ( 3)                            /*!< REFTCOFF Bit Offset */
4148 #define REF_A_CTL0_TCOFF                         ((uint16_t)0x0008)              /*!< Temperature sensor disabled */
4149 #define REF_A_CTL0_VSEL_OFS                      ( 4)                            /*!< REFVSEL Bit Offset */
4150 #define REF_A_CTL0_VSEL_MASK                     ((uint16_t)0x0030)              /*!< REFVSEL Bit Mask */
4151 #define REF_A_CTL0_VSEL0                         ((uint16_t)0x0010)              /*!< VSEL Bit 0 */
4152 #define REF_A_CTL0_VSEL1                         ((uint16_t)0x0020)              /*!< VSEL Bit 1 */
4153 #define REF_A_CTL0_VSEL_0                        ((uint16_t)0x0000)              /*!< 1.2 V available when reference requested or REFON = 1 */
4154 #define REF_A_CTL0_VSEL_1                        ((uint16_t)0x0010)              /*!< 1.45 V available when reference requested or REFON = 1 */
4155 #define REF_A_CTL0_VSEL_3                        ((uint16_t)0x0030)              /*!< 2.5 V available when reference requested or REFON = 1 */
4156 #define REF_A_CTL0_GENOT_OFS                     ( 6)                            /*!< REFGENOT Bit Offset */
4157 #define REF_A_CTL0_GENOT                         ((uint16_t)0x0040)              /*!< Reference generator one-time trigger */
4158 #define REF_A_CTL0_BGOT_OFS                      ( 7)                            /*!< REFBGOT Bit Offset */
4159 #define REF_A_CTL0_BGOT                          ((uint16_t)0x0080)              /*!< Bandgap and bandgap buffer one-time trigger */
4160 #define REF_A_CTL0_GENACT_OFS                    ( 8)                            /*!< REFGENACT Bit Offset */
4161 #define REF_A_CTL0_GENACT                        ((uint16_t)0x0100)              /*!< Reference generator active */
4162 #define REF_A_CTL0_BGACT_OFS                     ( 9)                            /*!< REFBGACT Bit Offset */
4163 #define REF_A_CTL0_BGACT                         ((uint16_t)0x0200)              /*!< Reference bandgap active */
4164 #define REF_A_CTL0_GENBUSY_OFS                   (10)                            /*!< REFGENBUSY Bit Offset */
4165 #define REF_A_CTL0_GENBUSY                       ((uint16_t)0x0400)              /*!< Reference generator busy */
4166 #define REF_A_CTL0_BGMODE_OFS                    (11)                            /*!< BGMODE Bit Offset */
4167 #define REF_A_CTL0_BGMODE                        ((uint16_t)0x0800)              /*!< Bandgap mode */
4168 #define REF_A_CTL0_GENRDY_OFS                    (12)                            /*!< REFGENRDY Bit Offset */
4169 #define REF_A_CTL0_GENRDY                        ((uint16_t)0x1000)              /*!< Variable reference voltage ready status */
4170 #define REF_A_CTL0_BGRDY_OFS                     (13)                            /*!< REFBGRDY Bit Offset */
4171 #define REF_A_CTL0_BGRDY                         ((uint16_t)0x2000)              /*!< Buffered bandgap voltage ready status */
4172 #define RSTCTL_RESET_REQ_SOFT_REQ_OFS            ( 0)                            /*!< SOFT_REQ Bit Offset */
4173 #define RSTCTL_RESET_REQ_SOFT_REQ                ((uint32_t)0x00000001)          /*!< Soft Reset request */
4174 #define RSTCTL_RESET_REQ_HARD_REQ_OFS            ( 1)                            /*!< HARD_REQ Bit Offset */
4175 #define RSTCTL_RESET_REQ_HARD_REQ                ((uint32_t)0x00000002)          /*!< Hard Reset request */
4176 #define RSTCTL_RESET_REQ_RSTKEY_OFS              ( 8)                            /*!< RSTKEY Bit Offset */
4177 #define RSTCTL_RESET_REQ_RSTKEY_MASK             ((uint32_t)0x0000FF00)          /*!< RSTKEY Bit Mask */
4178 #define RSTCTL_HARDRESET_STAT_SRC0_OFS           ( 0)                            /*!< SRC0 Bit Offset */
4179 #define RSTCTL_HARDRESET_STAT_SRC0               ((uint32_t)0x00000001)          /*!< Indicates that SRC0 was the source of the Hard Reset */
4180 #define RSTCTL_HARDRESET_STAT_SRC1_OFS           ( 1)                            /*!< SRC1 Bit Offset */
4181 #define RSTCTL_HARDRESET_STAT_SRC1               ((uint32_t)0x00000002)          /*!< Indicates that SRC1 was the source of the Hard Reset */
4182 #define RSTCTL_HARDRESET_STAT_SRC2_OFS           ( 2)                            /*!< SRC2 Bit Offset */
4183 #define RSTCTL_HARDRESET_STAT_SRC2               ((uint32_t)0x00000004)          /*!< Indicates that SRC2 was the source of the Hard Reset */
4184 #define RSTCTL_HARDRESET_STAT_SRC3_OFS           ( 3)                            /*!< SRC3 Bit Offset */
4185 #define RSTCTL_HARDRESET_STAT_SRC3               ((uint32_t)0x00000008)          /*!< Indicates that SRC3 was the source of the Hard Reset */
4186 #define RSTCTL_HARDRESET_STAT_SRC4_OFS           ( 4)                            /*!< SRC4 Bit Offset */
4187 #define RSTCTL_HARDRESET_STAT_SRC4               ((uint32_t)0x00000010)          /*!< Indicates that SRC4 was the source of the Hard Reset */
4188 #define RSTCTL_HARDRESET_STAT_SRC5_OFS           ( 5)                            /*!< SRC5 Bit Offset */
4189 #define RSTCTL_HARDRESET_STAT_SRC5               ((uint32_t)0x00000020)          /*!< Indicates that SRC5 was the source of the Hard Reset */
4190 #define RSTCTL_HARDRESET_STAT_SRC6_OFS           ( 6)                            /*!< SRC6 Bit Offset */
4191 #define RSTCTL_HARDRESET_STAT_SRC6               ((uint32_t)0x00000040)          /*!< Indicates that SRC6 was the source of the Hard Reset */
4192 #define RSTCTL_HARDRESET_STAT_SRC7_OFS           ( 7)                            /*!< SRC7 Bit Offset */
4193 #define RSTCTL_HARDRESET_STAT_SRC7               ((uint32_t)0x00000080)          /*!< Indicates that SRC7 was the source of the Hard Reset */
4194 #define RSTCTL_HARDRESET_STAT_SRC8_OFS           ( 8)                            /*!< SRC8 Bit Offset */
4195 #define RSTCTL_HARDRESET_STAT_SRC8               ((uint32_t)0x00000100)          /*!< Indicates that SRC8 was the source of the Hard Reset */
4196 #define RSTCTL_HARDRESET_STAT_SRC9_OFS           ( 9)                            /*!< SRC9 Bit Offset */
4197 #define RSTCTL_HARDRESET_STAT_SRC9               ((uint32_t)0x00000200)          /*!< Indicates that SRC9 was the source of the Hard Reset */
4198 #define RSTCTL_HARDRESET_STAT_SRC10_OFS          (10)                            /*!< SRC10 Bit Offset */
4199 #define RSTCTL_HARDRESET_STAT_SRC10              ((uint32_t)0x00000400)          /*!< Indicates that SRC10 was the source of the Hard Reset */
4200 #define RSTCTL_HARDRESET_STAT_SRC11_OFS          (11)                            /*!< SRC11 Bit Offset */
4201 #define RSTCTL_HARDRESET_STAT_SRC11              ((uint32_t)0x00000800)          /*!< Indicates that SRC11 was the source of the Hard Reset */
4202 #define RSTCTL_HARDRESET_STAT_SRC12_OFS          (12)                            /*!< SRC12 Bit Offset */
4203 #define RSTCTL_HARDRESET_STAT_SRC12              ((uint32_t)0x00001000)          /*!< Indicates that SRC12 was the source of the Hard Reset */
4204 #define RSTCTL_HARDRESET_STAT_SRC13_OFS          (13)                            /*!< SRC13 Bit Offset */
4205 #define RSTCTL_HARDRESET_STAT_SRC13              ((uint32_t)0x00002000)          /*!< Indicates that SRC13 was the source of the Hard Reset */
4206 #define RSTCTL_HARDRESET_STAT_SRC14_OFS          (14)                            /*!< SRC14 Bit Offset */
4207 #define RSTCTL_HARDRESET_STAT_SRC14              ((uint32_t)0x00004000)          /*!< Indicates that SRC14 was the source of the Hard Reset */
4208 #define RSTCTL_HARDRESET_STAT_SRC15_OFS          (15)                            /*!< SRC15 Bit Offset */
4209 #define RSTCTL_HARDRESET_STAT_SRC15              ((uint32_t)0x00008000)          /*!< Indicates that SRC15 was the source of the Hard Reset */
4210 #define RSTCTL_HARDRESET_CLR_SRC0_OFS            ( 0)                            /*!< SRC0 Bit Offset */
4211 #define RSTCTL_HARDRESET_CLR_SRC0                ((uint32_t)0x00000001)          /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
4212 #define RSTCTL_HARDRESET_CLR_SRC1_OFS            ( 1)                            /*!< SRC1 Bit Offset */
4213 #define RSTCTL_HARDRESET_CLR_SRC1                ((uint32_t)0x00000002)          /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
4214 #define RSTCTL_HARDRESET_CLR_SRC2_OFS            ( 2)                            /*!< SRC2 Bit Offset */
4215 #define RSTCTL_HARDRESET_CLR_SRC2                ((uint32_t)0x00000004)          /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
4216 #define RSTCTL_HARDRESET_CLR_SRC3_OFS            ( 3)                            /*!< SRC3 Bit Offset */
4217 #define RSTCTL_HARDRESET_CLR_SRC3                ((uint32_t)0x00000008)          /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
4218 #define RSTCTL_HARDRESET_CLR_SRC4_OFS            ( 4)                            /*!< SRC4 Bit Offset */
4219 #define RSTCTL_HARDRESET_CLR_SRC4                ((uint32_t)0x00000010)          /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
4220 #define RSTCTL_HARDRESET_CLR_SRC5_OFS            ( 5)                            /*!< SRC5 Bit Offset */
4221 #define RSTCTL_HARDRESET_CLR_SRC5                ((uint32_t)0x00000020)          /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
4222 #define RSTCTL_HARDRESET_CLR_SRC6_OFS            ( 6)                            /*!< SRC6 Bit Offset */
4223 #define RSTCTL_HARDRESET_CLR_SRC6                ((uint32_t)0x00000040)          /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
4224 #define RSTCTL_HARDRESET_CLR_SRC7_OFS            ( 7)                            /*!< SRC7 Bit Offset */
4225 #define RSTCTL_HARDRESET_CLR_SRC7                ((uint32_t)0x00000080)          /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
4226 #define RSTCTL_HARDRESET_CLR_SRC8_OFS            ( 8)                            /*!< SRC8 Bit Offset */
4227 #define RSTCTL_HARDRESET_CLR_SRC8                ((uint32_t)0x00000100)          /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
4228 #define RSTCTL_HARDRESET_CLR_SRC9_OFS            ( 9)                            /*!< SRC9 Bit Offset */
4229 #define RSTCTL_HARDRESET_CLR_SRC9                ((uint32_t)0x00000200)          /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
4230 #define RSTCTL_HARDRESET_CLR_SRC10_OFS           (10)                            /*!< SRC10 Bit Offset */
4231 #define RSTCTL_HARDRESET_CLR_SRC10               ((uint32_t)0x00000400)          /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
4232 #define RSTCTL_HARDRESET_CLR_SRC11_OFS           (11)                            /*!< SRC11 Bit Offset */
4233 #define RSTCTL_HARDRESET_CLR_SRC11               ((uint32_t)0x00000800)          /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
4234 #define RSTCTL_HARDRESET_CLR_SRC12_OFS           (12)                            /*!< SRC12 Bit Offset */
4235 #define RSTCTL_HARDRESET_CLR_SRC12               ((uint32_t)0x00001000)          /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
4236 #define RSTCTL_HARDRESET_CLR_SRC13_OFS           (13)                            /*!< SRC13 Bit Offset */
4237 #define RSTCTL_HARDRESET_CLR_SRC13               ((uint32_t)0x00002000)          /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
4238 #define RSTCTL_HARDRESET_CLR_SRC14_OFS           (14)                            /*!< SRC14 Bit Offset */
4239 #define RSTCTL_HARDRESET_CLR_SRC14               ((uint32_t)0x00004000)          /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
4240 #define RSTCTL_HARDRESET_CLR_SRC15_OFS           (15)                            /*!< SRC15 Bit Offset */
4241 #define RSTCTL_HARDRESET_CLR_SRC15               ((uint32_t)0x00008000)          /*!< Write 1 clears the corresponding bit in the RSTCTL_HRDRESETSTAT_REG */
4242 #define RSTCTL_HARDRESET_SET_SRC0_OFS            ( 0)                            /*!< SRC0 Bit Offset */
4243 #define RSTCTL_HARDRESET_SET_SRC0                ((uint32_t)0x00000001)          /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and  */
4244 #define RSTCTL_HARDRESET_SET_SRC1_OFS            ( 1)                            /*!< SRC1 Bit Offset */
4245 #define RSTCTL_HARDRESET_SET_SRC1                ((uint32_t)0x00000002)          /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and  */
4246 #define RSTCTL_HARDRESET_SET_SRC2_OFS            ( 2)                            /*!< SRC2 Bit Offset */
4247 #define RSTCTL_HARDRESET_SET_SRC2                ((uint32_t)0x00000004)          /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and  */
4248 #define RSTCTL_HARDRESET_SET_SRC3_OFS            ( 3)                            /*!< SRC3 Bit Offset */
4249 #define RSTCTL_HARDRESET_SET_SRC3                ((uint32_t)0x00000008)          /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and  */
4250 #define RSTCTL_HARDRESET_SET_SRC4_OFS            ( 4)                            /*!< SRC4 Bit Offset */
4251 #define RSTCTL_HARDRESET_SET_SRC4                ((uint32_t)0x00000010)          /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and  */
4252 #define RSTCTL_HARDRESET_SET_SRC5_OFS            ( 5)                            /*!< SRC5 Bit Offset */
4253 #define RSTCTL_HARDRESET_SET_SRC5                ((uint32_t)0x00000020)          /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and  */
4254 #define RSTCTL_HARDRESET_SET_SRC6_OFS            ( 6)                            /*!< SRC6 Bit Offset */
4255 #define RSTCTL_HARDRESET_SET_SRC6                ((uint32_t)0x00000040)          /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and  */
4256 #define RSTCTL_HARDRESET_SET_SRC7_OFS            ( 7)                            /*!< SRC7 Bit Offset */
4257 #define RSTCTL_HARDRESET_SET_SRC7                ((uint32_t)0x00000080)          /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and  */
4258 #define RSTCTL_HARDRESET_SET_SRC8_OFS            ( 8)                            /*!< SRC8 Bit Offset */
4259 #define RSTCTL_HARDRESET_SET_SRC8                ((uint32_t)0x00000100)          /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and  */
4260 #define RSTCTL_HARDRESET_SET_SRC9_OFS            ( 9)                            /*!< SRC9 Bit Offset */
4261 #define RSTCTL_HARDRESET_SET_SRC9                ((uint32_t)0x00000200)          /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and  */
4262 #define RSTCTL_HARDRESET_SET_SRC10_OFS           (10)                            /*!< SRC10 Bit Offset */
4263 #define RSTCTL_HARDRESET_SET_SRC10               ((uint32_t)0x00000400)          /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and  */
4264 #define RSTCTL_HARDRESET_SET_SRC11_OFS           (11)                            /*!< SRC11 Bit Offset */
4265 #define RSTCTL_HARDRESET_SET_SRC11               ((uint32_t)0x00000800)          /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and  */
4266 #define RSTCTL_HARDRESET_SET_SRC12_OFS           (12)                            /*!< SRC12 Bit Offset */
4267 #define RSTCTL_HARDRESET_SET_SRC12               ((uint32_t)0x00001000)          /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and  */
4268 #define RSTCTL_HARDRESET_SET_SRC13_OFS           (13)                            /*!< SRC13 Bit Offset */
4269 #define RSTCTL_HARDRESET_SET_SRC13               ((uint32_t)0x00002000)          /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and  */
4270 #define RSTCTL_HARDRESET_SET_SRC14_OFS           (14)                            /*!< SRC14 Bit Offset */
4271 #define RSTCTL_HARDRESET_SET_SRC14               ((uint32_t)0x00004000)          /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and  */
4272 #define RSTCTL_HARDRESET_SET_SRC15_OFS           (15)                            /*!< SRC15 Bit Offset */
4273 #define RSTCTL_HARDRESET_SET_SRC15               ((uint32_t)0x00008000)          /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and  */
4274 #define RSTCTL_SOFTRESET_STAT_SRC0_OFS           ( 0)                            /*!< SRC0 Bit Offset */
4275 #define RSTCTL_SOFTRESET_STAT_SRC0               ((uint32_t)0x00000001)          /*!< If 1, indicates that SRC0 was the source of the Soft Reset */
4276 #define RSTCTL_SOFTRESET_STAT_SRC1_OFS           ( 1)                            /*!< SRC1 Bit Offset */
4277 #define RSTCTL_SOFTRESET_STAT_SRC1               ((uint32_t)0x00000002)          /*!< If 1, indicates that SRC1 was the source of the Soft Reset */
4278 #define RSTCTL_SOFTRESET_STAT_SRC2_OFS           ( 2)                            /*!< SRC2 Bit Offset */
4279 #define RSTCTL_SOFTRESET_STAT_SRC2               ((uint32_t)0x00000004)          /*!< If 1, indicates that SRC2 was the source of the Soft Reset */
4280 #define RSTCTL_SOFTRESET_STAT_SRC3_OFS           ( 3)                            /*!< SRC3 Bit Offset */
4281 #define RSTCTL_SOFTRESET_STAT_SRC3               ((uint32_t)0x00000008)          /*!< If 1, indicates that SRC3 was the source of the Soft Reset */
4282 #define RSTCTL_SOFTRESET_STAT_SRC4_OFS           ( 4)                            /*!< SRC4 Bit Offset */
4283 #define RSTCTL_SOFTRESET_STAT_SRC4               ((uint32_t)0x00000010)          /*!< If 1, indicates that SRC4 was the source of the Soft Reset */
4284 #define RSTCTL_SOFTRESET_STAT_SRC5_OFS           ( 5)                            /*!< SRC5 Bit Offset */
4285 #define RSTCTL_SOFTRESET_STAT_SRC5               ((uint32_t)0x00000020)          /*!< If 1, indicates that SRC5 was the source of the Soft Reset */
4286 #define RSTCTL_SOFTRESET_STAT_SRC6_OFS           ( 6)                            /*!< SRC6 Bit Offset */
4287 #define RSTCTL_SOFTRESET_STAT_SRC6               ((uint32_t)0x00000040)          /*!< If 1, indicates that SRC6 was the source of the Soft Reset */
4288 #define RSTCTL_SOFTRESET_STAT_SRC7_OFS           ( 7)                            /*!< SRC7 Bit Offset */
4289 #define RSTCTL_SOFTRESET_STAT_SRC7               ((uint32_t)0x00000080)          /*!< If 1, indicates that SRC7 was the source of the Soft Reset */
4290 #define RSTCTL_SOFTRESET_STAT_SRC8_OFS           ( 8)                            /*!< SRC8 Bit Offset */
4291 #define RSTCTL_SOFTRESET_STAT_SRC8               ((uint32_t)0x00000100)          /*!< If 1, indicates that SRC8 was the source of the Soft Reset */
4292 #define RSTCTL_SOFTRESET_STAT_SRC9_OFS           ( 9)                            /*!< SRC9 Bit Offset */
4293 #define RSTCTL_SOFTRESET_STAT_SRC9               ((uint32_t)0x00000200)          /*!< If 1, indicates that SRC9 was the source of the Soft Reset */
4294 #define RSTCTL_SOFTRESET_STAT_SRC10_OFS          (10)                            /*!< SRC10 Bit Offset */
4295 #define RSTCTL_SOFTRESET_STAT_SRC10              ((uint32_t)0x00000400)          /*!< If 1, indicates that SRC10 was the source of the Soft Reset */
4296 #define RSTCTL_SOFTRESET_STAT_SRC11_OFS          (11)                            /*!< SRC11 Bit Offset */
4297 #define RSTCTL_SOFTRESET_STAT_SRC11              ((uint32_t)0x00000800)          /*!< If 1, indicates that SRC11 was the source of the Soft Reset */
4298 #define RSTCTL_SOFTRESET_STAT_SRC12_OFS          (12)                            /*!< SRC12 Bit Offset */
4299 #define RSTCTL_SOFTRESET_STAT_SRC12              ((uint32_t)0x00001000)          /*!< If 1, indicates that SRC12 was the source of the Soft Reset */
4300 #define RSTCTL_SOFTRESET_STAT_SRC13_OFS          (13)                            /*!< SRC13 Bit Offset */
4301 #define RSTCTL_SOFTRESET_STAT_SRC13              ((uint32_t)0x00002000)          /*!< If 1, indicates that SRC13 was the source of the Soft Reset */
4302 #define RSTCTL_SOFTRESET_STAT_SRC14_OFS          (14)                            /*!< SRC14 Bit Offset */
4303 #define RSTCTL_SOFTRESET_STAT_SRC14              ((uint32_t)0x00004000)          /*!< If 1, indicates that SRC14 was the source of the Soft Reset */
4304 #define RSTCTL_SOFTRESET_STAT_SRC15_OFS          (15)                            /*!< SRC15 Bit Offset */
4305 #define RSTCTL_SOFTRESET_STAT_SRC15              ((uint32_t)0x00008000)          /*!< If 1, indicates that SRC15 was the source of the Soft Reset */
4306 #define RSTCTL_SOFTRESET_CLR_SRC0_OFS            ( 0)                            /*!< SRC0 Bit Offset */
4307 #define RSTCTL_SOFTRESET_CLR_SRC0                ((uint32_t)0x00000001)          /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
4308 #define RSTCTL_SOFTRESET_CLR_SRC1_OFS            ( 1)                            /*!< SRC1 Bit Offset */
4309 #define RSTCTL_SOFTRESET_CLR_SRC1                ((uint32_t)0x00000002)          /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
4310 #define RSTCTL_SOFTRESET_CLR_SRC2_OFS            ( 2)                            /*!< SRC2 Bit Offset */
4311 #define RSTCTL_SOFTRESET_CLR_SRC2                ((uint32_t)0x00000004)          /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
4312 #define RSTCTL_SOFTRESET_CLR_SRC3_OFS            ( 3)                            /*!< SRC3 Bit Offset */
4313 #define RSTCTL_SOFTRESET_CLR_SRC3                ((uint32_t)0x00000008)          /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
4314 #define RSTCTL_SOFTRESET_CLR_SRC4_OFS            ( 4)                            /*!< SRC4 Bit Offset */
4315 #define RSTCTL_SOFTRESET_CLR_SRC4                ((uint32_t)0x00000010)          /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
4316 #define RSTCTL_SOFTRESET_CLR_SRC5_OFS            ( 5)                            /*!< SRC5 Bit Offset */
4317 #define RSTCTL_SOFTRESET_CLR_SRC5                ((uint32_t)0x00000020)          /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
4318 #define RSTCTL_SOFTRESET_CLR_SRC6_OFS            ( 6)                            /*!< SRC6 Bit Offset */
4319 #define RSTCTL_SOFTRESET_CLR_SRC6                ((uint32_t)0x00000040)          /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
4320 #define RSTCTL_SOFTRESET_CLR_SRC7_OFS            ( 7)                            /*!< SRC7 Bit Offset */
4321 #define RSTCTL_SOFTRESET_CLR_SRC7                ((uint32_t)0x00000080)          /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
4322 #define RSTCTL_SOFTRESET_CLR_SRC8_OFS            ( 8)                            /*!< SRC8 Bit Offset */
4323 #define RSTCTL_SOFTRESET_CLR_SRC8                ((uint32_t)0x00000100)          /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
4324 #define RSTCTL_SOFTRESET_CLR_SRC9_OFS            ( 9)                            /*!< SRC9 Bit Offset */
4325 #define RSTCTL_SOFTRESET_CLR_SRC9                ((uint32_t)0x00000200)          /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
4326 #define RSTCTL_SOFTRESET_CLR_SRC10_OFS           (10)                            /*!< SRC10 Bit Offset */
4327 #define RSTCTL_SOFTRESET_CLR_SRC10               ((uint32_t)0x00000400)          /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
4328 #define RSTCTL_SOFTRESET_CLR_SRC11_OFS           (11)                            /*!< SRC11 Bit Offset */
4329 #define RSTCTL_SOFTRESET_CLR_SRC11               ((uint32_t)0x00000800)          /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
4330 #define RSTCTL_SOFTRESET_CLR_SRC12_OFS           (12)                            /*!< SRC12 Bit Offset */
4331 #define RSTCTL_SOFTRESET_CLR_SRC12               ((uint32_t)0x00001000)          /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
4332 #define RSTCTL_SOFTRESET_CLR_SRC13_OFS           (13)                            /*!< SRC13 Bit Offset */
4333 #define RSTCTL_SOFTRESET_CLR_SRC13               ((uint32_t)0x00002000)          /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
4334 #define RSTCTL_SOFTRESET_CLR_SRC14_OFS           (14)                            /*!< SRC14 Bit Offset */
4335 #define RSTCTL_SOFTRESET_CLR_SRC14               ((uint32_t)0x00004000)          /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
4336 #define RSTCTL_SOFTRESET_CLR_SRC15_OFS           (15)                            /*!< SRC15 Bit Offset */
4337 #define RSTCTL_SOFTRESET_CLR_SRC15               ((uint32_t)0x00008000)          /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
4338 #define RSTCTL_SOFTRESET_SET_SRC0_OFS            ( 0)                            /*!< SRC0 Bit Offset */
4339 #define RSTCTL_SOFTRESET_SET_SRC0                ((uint32_t)0x00000001)          /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and  */
4340 #define RSTCTL_SOFTRESET_SET_SRC1_OFS            ( 1)                            /*!< SRC1 Bit Offset */
4341 #define RSTCTL_SOFTRESET_SET_SRC1                ((uint32_t)0x00000002)          /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and  */
4342 #define RSTCTL_SOFTRESET_SET_SRC2_OFS            ( 2)                            /*!< SRC2 Bit Offset */
4343 #define RSTCTL_SOFTRESET_SET_SRC2                ((uint32_t)0x00000004)          /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and  */
4344 #define RSTCTL_SOFTRESET_SET_SRC3_OFS            ( 3)                            /*!< SRC3 Bit Offset */
4345 #define RSTCTL_SOFTRESET_SET_SRC3                ((uint32_t)0x00000008)          /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and  */
4346 #define RSTCTL_SOFTRESET_SET_SRC4_OFS            ( 4)                            /*!< SRC4 Bit Offset */
4347 #define RSTCTL_SOFTRESET_SET_SRC4                ((uint32_t)0x00000010)          /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and  */
4348 #define RSTCTL_SOFTRESET_SET_SRC5_OFS            ( 5)                            /*!< SRC5 Bit Offset */
4349 #define RSTCTL_SOFTRESET_SET_SRC5                ((uint32_t)0x00000020)          /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and  */
4350 #define RSTCTL_SOFTRESET_SET_SRC6_OFS            ( 6)                            /*!< SRC6 Bit Offset */
4351 #define RSTCTL_SOFTRESET_SET_SRC6                ((uint32_t)0x00000040)          /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and  */
4352 #define RSTCTL_SOFTRESET_SET_SRC7_OFS            ( 7)                            /*!< SRC7 Bit Offset */
4353 #define RSTCTL_SOFTRESET_SET_SRC7                ((uint32_t)0x00000080)          /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and  */
4354 #define RSTCTL_SOFTRESET_SET_SRC8_OFS            ( 8)                            /*!< SRC8 Bit Offset */
4355 #define RSTCTL_SOFTRESET_SET_SRC8                ((uint32_t)0x00000100)          /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and  */
4356 #define RSTCTL_SOFTRESET_SET_SRC9_OFS            ( 9)                            /*!< SRC9 Bit Offset */
4357 #define RSTCTL_SOFTRESET_SET_SRC9                ((uint32_t)0x00000200)          /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and  */
4358 #define RSTCTL_SOFTRESET_SET_SRC10_OFS           (10)                            /*!< SRC10 Bit Offset */
4359 #define RSTCTL_SOFTRESET_SET_SRC10               ((uint32_t)0x00000400)          /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and  */
4360 #define RSTCTL_SOFTRESET_SET_SRC11_OFS           (11)                            /*!< SRC11 Bit Offset */
4361 #define RSTCTL_SOFTRESET_SET_SRC11               ((uint32_t)0x00000800)          /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and  */
4362 #define RSTCTL_SOFTRESET_SET_SRC12_OFS           (12)                            /*!< SRC12 Bit Offset */
4363 #define RSTCTL_SOFTRESET_SET_SRC12               ((uint32_t)0x00001000)          /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and  */
4364 #define RSTCTL_SOFTRESET_SET_SRC13_OFS           (13)                            /*!< SRC13 Bit Offset */
4365 #define RSTCTL_SOFTRESET_SET_SRC13               ((uint32_t)0x00002000)          /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and  */
4366 #define RSTCTL_SOFTRESET_SET_SRC14_OFS           (14)                            /*!< SRC14 Bit Offset */
4367 #define RSTCTL_SOFTRESET_SET_SRC14               ((uint32_t)0x00004000)          /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and  */
4368 #define RSTCTL_SOFTRESET_SET_SRC15_OFS           (15)                            /*!< SRC15 Bit Offset */
4369 #define RSTCTL_SOFTRESET_SET_SRC15               ((uint32_t)0x00008000)          /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and  */
4370 #define RSTCTL_PSSRESET_STAT_SVSMH_OFS           ( 1)                            /*!< SVSMH Bit Offset */
4371 #define RSTCTL_PSSRESET_STAT_SVSMH               ((uint32_t)0x00000002)          /*!< Indicates if POR was caused by an SVSMH trip condition int the PSS */
4372 #define RSTCTL_PSSRESET_STAT_BGREF_OFS           ( 2)                            /*!< BGREF Bit Offset */
4373 #define RSTCTL_PSSRESET_STAT_BGREF               ((uint32_t)0x00000004)          /*!< Indicates if POR was caused by a BGREF not okay condition in the PSS */
4374 #define RSTCTL_PSSRESET_STAT_VCCDET_OFS          ( 3)                            /*!< VCCDET Bit Offset */
4375 #define RSTCTL_PSSRESET_STAT_VCCDET              ((uint32_t)0x00000008)          /*!< Indicates if POR was caused by a VCCDET trip condition in the PSS */
4376 #define RSTCTL_PSSRESET_CLR_CLR_OFS              ( 0)                            /*!< CLR Bit Offset */
4377 #define RSTCTL_PSSRESET_CLR_CLR                  ((uint32_t)0x00000001)          /*!< Write 1 clears all PSS Reset Flags in the RSTCTL_PSSRESET_STAT */
4378 #define RSTCTL_PCMRESET_STAT_LPM35_OFS           ( 0)                            /*!< LPM35 Bit Offset */
4379 #define RSTCTL_PCMRESET_STAT_LPM35               ((uint32_t)0x00000001)          /*!< Indicates if POR was caused by PCM due to an exit from LPM3.5 */
4380 #define RSTCTL_PCMRESET_STAT_LPM45_OFS           ( 1)                            /*!< LPM45 Bit Offset */
4381 #define RSTCTL_PCMRESET_STAT_LPM45               ((uint32_t)0x00000002)          /*!< Indicates if POR was caused by PCM due to an exit from LPM4.5 */
4382 #define RSTCTL_PCMRESET_CLR_CLR_OFS              ( 0)                            /*!< CLR Bit Offset */
4383 #define RSTCTL_PCMRESET_CLR_CLR                  ((uint32_t)0x00000001)          /*!< Write 1 clears all PCM Reset Flags in the RSTCTL_PCMRESET_STAT */
4384 #define RSTCTL_PINRESET_STAT_RSTNMI_OFS          ( 0)                            /*!< RSTNMI Bit Offset */
4385 #define RSTCTL_PINRESET_STAT_RSTNMI              ((uint32_t)0x00000001)          /*!< POR was caused by RSTn/NMI pin based reset event */
4386 #define RSTCTL_PINRESET_CLR_CLR_OFS              ( 0)                            /*!< CLR Bit Offset */
4387 #define RSTCTL_PINRESET_CLR_CLR                  ((uint32_t)0x00000001)          /*!< Write 1 clears the RSTn/NMI Pin Reset Flag in RSTCTL_PINRESET_STAT */
4388 #define RSTCTL_REBOOTRESET_STAT_REBOOT_OFS       ( 0)                            /*!< REBOOT Bit Offset */
4389 #define RSTCTL_REBOOTRESET_STAT_REBOOT           ((uint32_t)0x00000001)          /*!< Indicates if Reboot reset was caused by the SYSCTL module. */
4390 #define RSTCTL_REBOOTRESET_CLR_CLR_OFS           ( 0)                            /*!< CLR Bit Offset */
4391 #define RSTCTL_REBOOTRESET_CLR_CLR               ((uint32_t)0x00000001)          /*!< Write 1 clears the Reboot Reset Flag in RSTCTL_REBOOTRESET_STAT */
4392 #define RSTCTL_CSRESET_STAT_DCOR_SHT_OFS         ( 0)                            /*!< DCOR_SHT Bit Offset */
4393 #define RSTCTL_CSRESET_STAT_DCOR_SHT             ((uint32_t)0x00000001)          /*!< Indicates if POR was caused by DCO short circuit fault in the external  */
4394 #define RSTCTL_CSRESET_CLR_CLR_OFS               ( 0)                            /*!< CLR Bit Offset */
4395 #define RSTCTL_CSRESET_CLR_CLR                   ((uint32_t)0x00000001)          /*!< Write 1 clears the DCOR_SHT Flag in RSTCTL_CSRESET_STAT as well as  */
4396 #define RSTCTL_RESETREQ_RSTKEY_VAL                 ((uint32_t)0x00006900)          /*!< Key value to enable writes to bits 1-0 */
4397 #define RTC_C_CTL0_RDYIFG_OFS                    ( 0)                            /*!< RTCRDYIFG Bit Offset */
4398 #define RTC_C_CTL0_RDYIFG                        ((uint16_t)0x0001)              /*!< Real-time clock ready interrupt flag */
4399 #define RTC_C_CTL0_AIFG_OFS                      ( 1)                            /*!< RTCAIFG Bit Offset */
4400 #define RTC_C_CTL0_AIFG                          ((uint16_t)0x0002)              /*!< Real-time clock alarm interrupt flag */
4401 #define RTC_C_CTL0_TEVIFG_OFS                    ( 2)                            /*!< RTCTEVIFG Bit Offset */
4402 #define RTC_C_CTL0_TEVIFG                        ((uint16_t)0x0004)              /*!< Real-time clock time event interrupt flag */
4403 #define RTC_C_CTL0_OFIFG_OFS                     ( 3)                            /*!< RTCOFIFG Bit Offset */
4404 #define RTC_C_CTL0_OFIFG                         ((uint16_t)0x0008)              /*!< 32-kHz crystal oscillator fault interrupt flag */
4405 #define RTC_C_CTL0_RDYIE_OFS                     ( 4)                            /*!< RTCRDYIE Bit Offset */
4406 #define RTC_C_CTL0_RDYIE                         ((uint16_t)0x0010)              /*!< Real-time clock ready interrupt enable */
4407 #define RTC_C_CTL0_AIE_OFS                       ( 5)                            /*!< RTCAIE Bit Offset */
4408 #define RTC_C_CTL0_AIE                           ((uint16_t)0x0020)              /*!< Real-time clock alarm interrupt enable */
4409 #define RTC_C_CTL0_TEVIE_OFS                     ( 6)                            /*!< RTCTEVIE Bit Offset */
4410 #define RTC_C_CTL0_TEVIE                         ((uint16_t)0x0040)              /*!< Real-time clock time event interrupt enable */
4411 #define RTC_C_CTL0_OFIE_OFS                      ( 7)                            /*!< RTCOFIE Bit Offset */
4412 #define RTC_C_CTL0_OFIE                          ((uint16_t)0x0080)              /*!< 32-kHz crystal oscillator fault interrupt enable */
4413 #define RTC_C_CTL0_KEY_OFS                       ( 8)                            /*!< RTCKEY Bit Offset */
4414 #define RTC_C_CTL0_KEY_MASK                      ((uint16_t)0xFF00)              /*!< RTCKEY Bit Mask */
4415 #define RTC_C_CTL13_TEV_OFS                      ( 0)                            /*!< RTCTEV Bit Offset */
4416 #define RTC_C_CTL13_TEV_MASK                     ((uint16_t)0x0003)              /*!< RTCTEV Bit Mask */
4417 #define RTC_C_CTL13_TEV0                         ((uint16_t)0x0001)              /*!< TEV Bit 0 */
4418 #define RTC_C_CTL13_TEV1                         ((uint16_t)0x0002)              /*!< TEV Bit 1 */
4419 #define RTC_C_CTL13_TEV_0                        ((uint16_t)0x0000)              /*!< Minute changed */
4420 #define RTC_C_CTL13_TEV_1                        ((uint16_t)0x0001)              /*!< Hour changed */
4421 #define RTC_C_CTL13_TEV_2                        ((uint16_t)0x0002)              /*!< Every day at midnight (00:00) */
4422 #define RTC_C_CTL13_TEV_3                        ((uint16_t)0x0003)              /*!< Every day at noon (12:00) */
4423 #define RTC_C_CTL13_SSEL_OFS                     ( 2)                            /*!< RTCSSEL Bit Offset */
4424 #define RTC_C_CTL13_SSEL_MASK                    ((uint16_t)0x000C)              /*!< RTCSSEL Bit Mask */
4425 #define RTC_C_CTL13_SSEL0                        ((uint16_t)0x0004)              /*!< SSEL Bit 0 */
4426 #define RTC_C_CTL13_SSEL1                        ((uint16_t)0x0008)              /*!< SSEL Bit 1 */
4427 #define RTC_C_CTL13_SSEL_0                       ((uint16_t)0x0000)              /*!< BCLK */
4428 #define RTC_C_CTL13_SSEL__BCLK                   ((uint16_t)0x0000)              /*!< BCLK */
4429 #define RTC_C_CTL13_RDY_OFS                      ( 4)                            /*!< RTCRDY Bit Offset */
4430 #define RTC_C_CTL13_RDY                          ((uint16_t)0x0010)              /*!< Real-time clock ready */
4431 #define RTC_C_CTL13_MODE_OFS                     ( 5)                            /*!< RTCMODE Bit Offset */
4432 #define RTC_C_CTL13_MODE                         ((uint16_t)0x0020)
4433 #define RTC_C_CTL13_HOLD_OFS                     ( 6)                            /*!< RTCHOLD Bit Offset */
4434 #define RTC_C_CTL13_HOLD                         ((uint16_t)0x0040)              /*!< Real-time clock hold */
4435 #define RTC_C_CTL13_BCD_OFS                      ( 7)                            /*!< RTCBCD Bit Offset */
4436 #define RTC_C_CTL13_BCD                          ((uint16_t)0x0080)              /*!< Real-time clock BCD select */
4437 #define RTC_C_CTL13_CALF_OFS                     ( 8)                            /*!< RTCCALF Bit Offset */
4438 #define RTC_C_CTL13_CALF_MASK                    ((uint16_t)0x0300)              /*!< RTCCALF Bit Mask */
4439 #define RTC_C_CTL13_CALF0                        ((uint16_t)0x0100)              /*!< CALF Bit 0 */
4440 #define RTC_C_CTL13_CALF1                        ((uint16_t)0x0200)              /*!< CALF Bit 1 */
4441 #define RTC_C_CTL13_CALF_0                       ((uint16_t)0x0000)              /*!< No frequency output to RTCCLK pin */
4442 #define RTC_C_CTL13_CALF_1                       ((uint16_t)0x0100)              /*!< 512 Hz */
4443 #define RTC_C_CTL13_CALF_2                       ((uint16_t)0x0200)              /*!< 256 Hz */
4444 #define RTC_C_CTL13_CALF_3                       ((uint16_t)0x0300)              /*!< 1 Hz */
4445 #define RTC_C_CTL13_CALF__NONE                   ((uint16_t)0x0000)              /*!< No frequency output to RTCCLK pin */
4446 #define RTC_C_CTL13_CALF__512                    ((uint16_t)0x0100)              /*!< 512 Hz */
4447 #define RTC_C_CTL13_CALF__256                    ((uint16_t)0x0200)              /*!< 256 Hz */
4448 #define RTC_C_CTL13_CALF__1                      ((uint16_t)0x0300)              /*!< 1 Hz */
4449 #define RTC_C_OCAL_OCAL_OFS                      ( 0)                            /*!< RTCOCAL Bit Offset */
4450 #define RTC_C_OCAL_OCAL_MASK                     ((uint16_t)0x00FF)              /*!< RTCOCAL Bit Mask */
4451 #define RTC_C_OCAL_OCALS_OFS                     (15)                            /*!< RTCOCALS Bit Offset */
4452 #define RTC_C_OCAL_OCALS                         ((uint16_t)0x8000)              /*!< Real-time clock offset error calibration sign */
4453 #define RTC_C_TCMP_TCMPX_OFS                     ( 0)                            /*!< RTCTCMP Bit Offset */
4454 #define RTC_C_TCMP_TCMPX_MASK                    ((uint16_t)0x00FF)              /*!< RTCTCMP Bit Mask */
4455 #define RTC_C_TCMP_TCOK_OFS                      (13)                            /*!< RTCTCOK Bit Offset */
4456 #define RTC_C_TCMP_TCOK                          ((uint16_t)0x2000)              /*!< Real-time clock temperature compensation write OK */
4457 #define RTC_C_TCMP_TCRDY_OFS                     (14)                            /*!< RTCTCRDY Bit Offset */
4458 #define RTC_C_TCMP_TCRDY                         ((uint16_t)0x4000)              /*!< Real-time clock temperature compensation ready */
4459 #define RTC_C_TCMP_TCMPS_OFS                     (15)                            /*!< RTCTCMPS Bit Offset */
4460 #define RTC_C_TCMP_TCMPS                         ((uint16_t)0x8000)              /*!< Real-time clock temperature compensation sign */
4461 #define RTC_C_PS0CTL_RT0PSIFG_OFS                ( 0)                            /*!< RT0PSIFG Bit Offset */
4462 #define RTC_C_PS0CTL_RT0PSIFG                    ((uint16_t)0x0001)              /*!< Prescale timer 0 interrupt flag */
4463 #define RTC_C_PS0CTL_RT0PSIE_OFS                 ( 1)                            /*!< RT0PSIE Bit Offset */
4464 #define RTC_C_PS0CTL_RT0PSIE                     ((uint16_t)0x0002)              /*!< Prescale timer 0 interrupt enable */
4465 #define RTC_C_PS0CTL_RT0IP_OFS                   ( 2)                            /*!< RT0IP Bit Offset */
4466 #define RTC_C_PS0CTL_RT0IP_MASK                  ((uint16_t)0x001C)              /*!< RT0IP Bit Mask */
4467 #define RTC_C_PS0CTL_RT0IP0                      ((uint16_t)0x0004)              /*!< RT0IP Bit 0 */
4468 #define RTC_C_PS0CTL_RT0IP1                      ((uint16_t)0x0008)              /*!< RT0IP Bit 1 */
4469 #define RTC_C_PS0CTL_RT0IP2                      ((uint16_t)0x0010)              /*!< RT0IP Bit 2 */
4470 #define RTC_C_PS0CTL_RT0IP_0                     ((uint16_t)0x0000)              /*!< Divide by 2 */
4471 #define RTC_C_PS0CTL_RT0IP_1                     ((uint16_t)0x0004)              /*!< Divide by 4 */
4472 #define RTC_C_PS0CTL_RT0IP_2                     ((uint16_t)0x0008)              /*!< Divide by 8 */
4473 #define RTC_C_PS0CTL_RT0IP_3                     ((uint16_t)0x000C)              /*!< Divide by 16 */
4474 #define RTC_C_PS0CTL_RT0IP_4                     ((uint16_t)0x0010)              /*!< Divide by 32 */
4475 #define RTC_C_PS0CTL_RT0IP_5                     ((uint16_t)0x0014)              /*!< Divide by 64 */
4476 #define RTC_C_PS0CTL_RT0IP_6                     ((uint16_t)0x0018)              /*!< Divide by 128 */
4477 #define RTC_C_PS0CTL_RT0IP_7                     ((uint16_t)0x001C)              /*!< Divide by 256 */
4478 #define RTC_C_PS0CTL_RT0IP__2                    ((uint16_t)0x0000)              /*!< Divide by 2 */
4479 #define RTC_C_PS0CTL_RT0IP__4                    ((uint16_t)0x0004)              /*!< Divide by 4 */
4480 #define RTC_C_PS0CTL_RT0IP__8                    ((uint16_t)0x0008)              /*!< Divide by 8 */
4481 #define RTC_C_PS0CTL_RT0IP__16                   ((uint16_t)0x000C)              /*!< Divide by 16 */
4482 #define RTC_C_PS0CTL_RT0IP__32                   ((uint16_t)0x0010)              /*!< Divide by 32 */
4483 #define RTC_C_PS0CTL_RT0IP__64                   ((uint16_t)0x0014)              /*!< Divide by 64 */
4484 #define RTC_C_PS0CTL_RT0IP__128                  ((uint16_t)0x0018)              /*!< Divide by 128 */
4485 #define RTC_C_PS0CTL_RT0IP__256                  ((uint16_t)0x001C)              /*!< Divide by 256 */
4486 #define RTC_C_PS1CTL_RT1PSIFG_OFS                ( 0)                            /*!< RT1PSIFG Bit Offset */
4487 #define RTC_C_PS1CTL_RT1PSIFG                    ((uint16_t)0x0001)              /*!< Prescale timer 1 interrupt flag */
4488 #define RTC_C_PS1CTL_RT1PSIE_OFS                 ( 1)                            /*!< RT1PSIE Bit Offset */
4489 #define RTC_C_PS1CTL_RT1PSIE                     ((uint16_t)0x0002)              /*!< Prescale timer 1 interrupt enable */
4490 #define RTC_C_PS1CTL_RT1IP_OFS                   ( 2)                            /*!< RT1IP Bit Offset */
4491 #define RTC_C_PS1CTL_RT1IP_MASK                  ((uint16_t)0x001C)              /*!< RT1IP Bit Mask */
4492 #define RTC_C_PS1CTL_RT1IP0                      ((uint16_t)0x0004)              /*!< RT1IP Bit 0 */
4493 #define RTC_C_PS1CTL_RT1IP1                      ((uint16_t)0x0008)              /*!< RT1IP Bit 1 */
4494 #define RTC_C_PS1CTL_RT1IP2                      ((uint16_t)0x0010)              /*!< RT1IP Bit 2 */
4495 #define RTC_C_PS1CTL_RT1IP_0                     ((uint16_t)0x0000)              /*!< Divide by 2 */
4496 #define RTC_C_PS1CTL_RT1IP_1                     ((uint16_t)0x0004)              /*!< Divide by 4 */
4497 #define RTC_C_PS1CTL_RT1IP_2                     ((uint16_t)0x0008)              /*!< Divide by 8 */
4498 #define RTC_C_PS1CTL_RT1IP_3                     ((uint16_t)0x000C)              /*!< Divide by 16 */
4499 #define RTC_C_PS1CTL_RT1IP_4                     ((uint16_t)0x0010)              /*!< Divide by 32 */
4500 #define RTC_C_PS1CTL_RT1IP_5                     ((uint16_t)0x0014)              /*!< Divide by 64 */
4501 #define RTC_C_PS1CTL_RT1IP_6                     ((uint16_t)0x0018)              /*!< Divide by 128 */
4502 #define RTC_C_PS1CTL_RT1IP_7                     ((uint16_t)0x001C)              /*!< Divide by 256 */
4503 #define RTC_C_PS1CTL_RT1IP__2                    ((uint16_t)0x0000)              /*!< Divide by 2 */
4504 #define RTC_C_PS1CTL_RT1IP__4                    ((uint16_t)0x0004)              /*!< Divide by 4 */
4505 #define RTC_C_PS1CTL_RT1IP__8                    ((uint16_t)0x0008)              /*!< Divide by 8 */
4506 #define RTC_C_PS1CTL_RT1IP__16                   ((uint16_t)0x000C)              /*!< Divide by 16 */
4507 #define RTC_C_PS1CTL_RT1IP__32                   ((uint16_t)0x0010)              /*!< Divide by 32 */
4508 #define RTC_C_PS1CTL_RT1IP__64                   ((uint16_t)0x0014)              /*!< Divide by 64 */
4509 #define RTC_C_PS1CTL_RT1IP__128                  ((uint16_t)0x0018)              /*!< Divide by 128 */
4510 #define RTC_C_PS1CTL_RT1IP__256                  ((uint16_t)0x001C)              /*!< Divide by 256 */
4511 #define RTC_C_PS_RT0PS_OFS                       ( 0)                            /*!< RT0PS Bit Offset */
4512 #define RTC_C_PS_RT0PS_MASK                      ((uint16_t)0x00FF)              /*!< RT0PS Bit Mask */
4513 #define RTC_C_PS_RT1PS_OFS                       ( 8)                            /*!< RT1PS Bit Offset */
4514 #define RTC_C_PS_RT1PS_MASK                      ((uint16_t)0xFF00)              /*!< RT1PS Bit Mask */
4515 #define RTC_C_TIM0_SEC_OFS                       ( 0)                            /*!< Seconds Bit Offset */
4516 #define RTC_C_TIM0_SEC_MASK                      ((uint16_t)0x003F)              /*!< Seconds Bit Mask */
4517 #define RTC_C_TIM0_MIN_OFS                       ( 8)                            /*!< Minutes Bit Offset */
4518 #define RTC_C_TIM0_MIN_MASK                      ((uint16_t)0x3F00)              /*!< Minutes Bit Mask */
4519 #define RTC_C_TIM0_SEC_LD_OFS                    ( 0)                            /*!< SecondsLowDigit Bit Offset */
4520 #define RTC_C_TIM0_SEC_LD_MASK                   ((uint16_t)0x000F)              /*!< SecondsLowDigit Bit Mask */
4521 #define RTC_C_TIM0_SEC_HD_OFS                    ( 4)                            /*!< SecondsHighDigit Bit Offset */
4522 #define RTC_C_TIM0_SEC_HD_MASK                   ((uint16_t)0x0070)              /*!< SecondsHighDigit Bit Mask */
4523 #define RTC_C_TIM0_MIN_LD_OFS                    ( 8)                            /*!< MinutesLowDigit Bit Offset */
4524 #define RTC_C_TIM0_MIN_LD_MASK                   ((uint16_t)0x0F00)              /*!< MinutesLowDigit Bit Mask */
4525 #define RTC_C_TIM0_MIN_HD_OFS                    (12)                            /*!< MinutesHighDigit Bit Offset */
4526 #define RTC_C_TIM0_MIN_HD_MASK                   ((uint16_t)0x7000)              /*!< MinutesHighDigit Bit Mask */
4527 #define RTC_C_TIM1_HOUR_OFS                      ( 0)                            /*!< Hours Bit Offset */
4528 #define RTC_C_TIM1_HOUR_MASK                     ((uint16_t)0x001F)              /*!< Hours Bit Mask */
4529 #define RTC_C_TIM1_DOW_OFS                       ( 8)                            /*!< DayofWeek Bit Offset */
4530 #define RTC_C_TIM1_DOW_MASK                      ((uint16_t)0x0700)              /*!< DayofWeek Bit Mask */
4531 #define RTC_C_TIM1_HOUR_LD_OFS                   ( 0)                            /*!< HoursLowDigit Bit Offset */
4532 #define RTC_C_TIM1_HOUR_LD_MASK                  ((uint16_t)0x000F)              /*!< HoursLowDigit Bit Mask */
4533 #define RTC_C_TIM1_HOUR_HD_OFS                   ( 4)                            /*!< HoursHighDigit Bit Offset */
4534 #define RTC_C_TIM1_HOUR_HD_MASK                  ((uint16_t)0x0030)              /*!< HoursHighDigit Bit Mask */
4535 #define RTC_C_DATE_DAY_OFS                       ( 0)                            /*!< Day Bit Offset */
4536 #define RTC_C_DATE_DAY_MASK                      ((uint16_t)0x001F)              /*!< Day Bit Mask */
4537 #define RTC_C_DATE_MON_OFS                       ( 8)                            /*!< Month Bit Offset */
4538 #define RTC_C_DATE_MON_MASK                      ((uint16_t)0x0F00)              /*!< Month Bit Mask */
4539 #define RTC_C_DATE_DAY_LD_OFS                    ( 0)                            /*!< DayLowDigit Bit Offset */
4540 #define RTC_C_DATE_DAY_LD_MASK                   ((uint16_t)0x000F)              /*!< DayLowDigit Bit Mask */
4541 #define RTC_C_DATE_DAY_HD_OFS                    ( 4)                            /*!< DayHighDigit Bit Offset */
4542 #define RTC_C_DATE_DAY_HD_MASK                   ((uint16_t)0x0030)              /*!< DayHighDigit Bit Mask */
4543 #define RTC_C_DATE_MON_LD_OFS                    ( 8)                            /*!< MonthLowDigit Bit Offset */
4544 #define RTC_C_DATE_MON_LD_MASK                   ((uint16_t)0x0F00)              /*!< MonthLowDigit Bit Mask */
4545 #define RTC_C_DATE_MON_HD_OFS                    (12)                            /*!< MonthHighDigit Bit Offset */
4546 #define RTC_C_DATE_MON_HD                        ((uint16_t)0x1000)              /*!< Month  high digit (0 or 1) */
4547 #define RTC_C_YEAR_YEAR_LB_OFS                   ( 0)                            /*!< YearLowByte Bit Offset */
4548 #define RTC_C_YEAR_YEAR_LB_MASK                  ((uint16_t)0x00FF)              /*!< YearLowByte Bit Mask */
4549 #define RTC_C_YEAR_YEAR_HB_OFS                   ( 8)                            /*!< YearHighByte Bit Offset */
4550 #define RTC_C_YEAR_YEAR_HB_MASK                  ((uint16_t)0x0F00)              /*!< YearHighByte Bit Mask */
4551 #define RTC_C_YEAR_YEAR_OFS                      ( 0)                            /*!< Year Bit Offset */
4552 #define RTC_C_YEAR_YEAR_MASK                     ((uint16_t)0x000F)              /*!< Year Bit Mask */
4553 #define RTC_C_YEAR_DEC_OFS                       ( 4)                            /*!< Decade Bit Offset */
4554 #define RTC_C_YEAR_DEC_MASK                      ((uint16_t)0x00F0)              /*!< Decade Bit Mask */
4555 #define RTC_C_YEAR_CENT_LD_OFS                   ( 8)                            /*!< CenturyLowDigit Bit Offset */
4556 #define RTC_C_YEAR_CENT_LD_MASK                  ((uint16_t)0x0F00)              /*!< CenturyLowDigit Bit Mask */
4557 #define RTC_C_YEAR_CENT_HD_OFS                   (12)                            /*!< CenturyHighDigit Bit Offset */
4558 #define RTC_C_YEAR_CENT_HD_MASK                  ((uint16_t)0x7000)              /*!< CenturyHighDigit Bit Mask */
4559 #define RTC_C_AMINHR_MIN_OFS                     ( 0)                            /*!< Minutes Bit Offset */
4560 #define RTC_C_AMINHR_MIN_MASK                    ((uint16_t)0x003F)              /*!< Minutes Bit Mask */
4561 #define RTC_C_AMINHR_MINAE_OFS                   ( 7)                            /*!< MINAE Bit Offset */
4562 #define RTC_C_AMINHR_MINAE                       ((uint16_t)0x0080)              /*!< Alarm enable */
4563 #define RTC_C_AMINHR_HOUR_OFS                    ( 8)                            /*!< Hours Bit Offset */
4564 #define RTC_C_AMINHR_HOUR_MASK                   ((uint16_t)0x1F00)              /*!< Hours Bit Mask */
4565 #define RTC_C_AMINHR_HOURAE_OFS                  (15)                            /*!< HOURAE Bit Offset */
4566 #define RTC_C_AMINHR_HOURAE                      ((uint16_t)0x8000)              /*!< Alarm enable */
4567 #define RTC_C_AMINHR_MIN_LD_OFS                  ( 0)                            /*!< MinutesLowDigit Bit Offset */
4568 #define RTC_C_AMINHR_MIN_LD_MASK                 ((uint16_t)0x000F)              /*!< MinutesLowDigit Bit Mask */
4569 #define RTC_C_AMINHR_MIN_HD_OFS                  ( 4)                            /*!< MinutesHighDigit Bit Offset */
4570 #define RTC_C_AMINHR_MIN_HD_MASK                 ((uint16_t)0x0070)              /*!< MinutesHighDigit Bit Mask */
4571 #define RTC_C_AMINHR_HOUR_LD_OFS                 ( 8)                            /*!< HoursLowDigit Bit Offset */
4572 #define RTC_C_AMINHR_HOUR_LD_MASK                ((uint16_t)0x0F00)              /*!< HoursLowDigit Bit Mask */
4573 #define RTC_C_AMINHR_HOUR_HD_OFS                 (12)                            /*!< HoursHighDigit Bit Offset */
4574 #define RTC_C_AMINHR_HOUR_HD_MASK                ((uint16_t)0x3000)              /*!< HoursHighDigit Bit Mask */
4575 #define RTC_C_ADOWDAY_DOW_OFS                    ( 0)                            /*!< DayofWeek Bit Offset */
4576 #define RTC_C_ADOWDAY_DOW_MASK                   ((uint16_t)0x0007)              /*!< DayofWeek Bit Mask */
4577 #define RTC_C_ADOWDAY_DOWAE_OFS                  ( 7)                            /*!< DOWAE Bit Offset */
4578 #define RTC_C_ADOWDAY_DOWAE                      ((uint16_t)0x0080)              /*!< Alarm enable */
4579 #define RTC_C_ADOWDAY_DAY_OFS                    ( 8)                            /*!< DayofMonth Bit Offset */
4580 #define RTC_C_ADOWDAY_DAY_MASK                   ((uint16_t)0x1F00)              /*!< DayofMonth Bit Mask */
4581 #define RTC_C_ADOWDAY_DAYAE_OFS                  (15)                            /*!< DAYAE Bit Offset */
4582 #define RTC_C_ADOWDAY_DAYAE                      ((uint16_t)0x8000)              /*!< Alarm enable */
4583 #define RTC_C_ADOWDAY_DAY_LD_OFS                 ( 8)                            /*!< DayLowDigit Bit Offset */
4584 #define RTC_C_ADOWDAY_DAY_LD_MASK                ((uint16_t)0x0F00)              /*!< DayLowDigit Bit Mask */
4585 #define RTC_C_ADOWDAY_DAY_HD_OFS                 (12)                            /*!< DayHighDigit Bit Offset */
4586 #define RTC_C_ADOWDAY_DAY_HD_MASK                ((uint16_t)0x3000)              /*!< DayHighDigit Bit Mask */
4587 #define RTC_C_KEY                                 ((uint16_t)0xA500)              /*!< RTC_C Key Value for RTC_C write access */
4588 #define RTC_C_KEY_H                               ((uint16_t)0x00A5)              /*!< RTC_C Key Value for RTC_C write access */
4589 #define RTC_C_KEY_VAL                             ((uint16_t)0xA500)              /*!< RTC_C Key Value for RTC_C write access */
4590 #define SCB_PFR0_STATE0_OFS                      ( 0)                            /*!< STATE0 Bit Offset */
4591 #define SCB_PFR0_STATE0_MASK                     ((uint32_t)0x0000000F)          /*!< STATE0 Bit Mask */
4592 #define SCB_PFR0_STATE00                         ((uint32_t)0x00000001)          /*!< STATE0 Bit 0 */
4593 #define SCB_PFR0_STATE01                         ((uint32_t)0x00000002)          /*!< STATE0 Bit 1 */
4594 #define SCB_PFR0_STATE02                         ((uint32_t)0x00000004)          /*!< STATE0 Bit 2 */
4595 #define SCB_PFR0_STATE03                         ((uint32_t)0x00000008)          /*!< STATE0 Bit 3 */
4596 #define SCB_PFR0_STATE0_0                        ((uint32_t)0x00000000)          /*!< no ARM encoding */
4597 #define SCB_PFR0_STATE0_1                        ((uint32_t)0x00000001)          /*!< N/A */
4598 #define SCB_PFR0_STATE1_OFS                      ( 4)                            /*!< STATE1 Bit Offset */
4599 #define SCB_PFR0_STATE1_MASK                     ((uint32_t)0x000000F0)          /*!< STATE1 Bit Mask */
4600 #define SCB_PFR0_STATE10                         ((uint32_t)0x00000010)          /*!< STATE1 Bit 0 */
4601 #define SCB_PFR0_STATE11                         ((uint32_t)0x00000020)          /*!< STATE1 Bit 1 */
4602 #define SCB_PFR0_STATE12                         ((uint32_t)0x00000040)          /*!< STATE1 Bit 2 */
4603 #define SCB_PFR0_STATE13                         ((uint32_t)0x00000080)          /*!< STATE1 Bit 3 */
4604 #define SCB_PFR0_STATE1_0                        ((uint32_t)0x00000000)          /*!< N/A */
4605 #define SCB_PFR0_STATE1_1                        ((uint32_t)0x00000010)          /*!< N/A */
4606 #define SCB_PFR0_STATE1_2                        ((uint32_t)0x00000020)          /*!< Thumb-2 encoding with the 16-bit basic instructions plus 32-bit Buncond/BL  */
4607 #define SCB_PFR0_STATE1_3                        ((uint32_t)0x00000030)          /*!< Thumb-2 encoding with all Thumb-2 basic instructions */
4608 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_OFS ( 8)                            /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit Offset */
4609 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_MASK ((uint32_t)0x00000F00)          /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit Mask */
4610 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL0 ((uint32_t)0x00000100)          /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 0 */
4611 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL1 ((uint32_t)0x00000200)          /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 1 */
4612 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL2 ((uint32_t)0x00000400)          /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 2 */
4613 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL3 ((uint32_t)0x00000800)          /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 3 */
4614 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_0 ((uint32_t)0x00000000)          /*!< not supported */
4615 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_2 ((uint32_t)0x00000200)          /*!< two-stack support */
4616 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_OFS (20)                            /*!< MICROCONTROLLER_DEBUG_MODEL Bit Offset */
4617 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_MASK ((uint32_t)0x00F00000)          /*!< MICROCONTROLLER_DEBUG_MODEL Bit Mask */
4618 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL0    ((uint32_t)0x00100000)          /*!< MICROCONTROLLER_DEBUG_MODEL Bit 0 */
4619 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL1    ((uint32_t)0x00200000)          /*!< MICROCONTROLLER_DEBUG_MODEL Bit 1 */
4620 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL2    ((uint32_t)0x00400000)          /*!< MICROCONTROLLER_DEBUG_MODEL Bit 2 */
4621 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL3    ((uint32_t)0x00800000)          /*!< MICROCONTROLLER_DEBUG_MODEL Bit 3 */
4622 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_0   ((uint32_t)0x00000000)          /*!< not supported */
4623 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_1   ((uint32_t)0x00100000)          /*!< Microcontroller debug v1 (ITMv1, DWTv1, optional ETM) */
4624 #define SCB_MMFR0_PMSA_SUPPORT_OFS               ( 4)                            /*!< PMSA_SUPPORT Bit Offset */
4625 #define SCB_MMFR0_PMSA_SUPPORT_MASK              ((uint32_t)0x000000F0)          /*!< PMSA_SUPPORT Bit Mask */
4626 #define SCB_MMFR0_PMSA_SUPPORT0                  ((uint32_t)0x00000010)          /*!< PMSA_SUPPORT Bit 0 */
4627 #define SCB_MMFR0_PMSA_SUPPORT1                  ((uint32_t)0x00000020)          /*!< PMSA_SUPPORT Bit 1 */
4628 #define SCB_MMFR0_PMSA_SUPPORT2                  ((uint32_t)0x00000040)          /*!< PMSA_SUPPORT Bit 2 */
4629 #define SCB_MMFR0_PMSA_SUPPORT3                  ((uint32_t)0x00000080)          /*!< PMSA_SUPPORT Bit 3 */
4630 #define SCB_MMFR0_PMSA_SUPPORT_0                 ((uint32_t)0x00000000)          /*!< not supported */
4631 #define SCB_MMFR0_PMSA_SUPPORT_1                 ((uint32_t)0x00000010)          /*!< IMPLEMENTATION DEFINED (N/A) */
4632 #define SCB_MMFR0_PMSA_SUPPORT_2                 ((uint32_t)0x00000020)          /*!< PMSA base (features as defined for ARMv6) (N/A) */
4633 #define SCB_MMFR0_PMSA_SUPPORT_3                 ((uint32_t)0x00000030)          /*!< PMSAv7 (base plus subregion support) */
4634 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_OFS    ( 8)                            /*!< CACHE_COHERENCE_SUPPORT Bit Offset */
4635 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_MASK   ((uint32_t)0x00000F00)          /*!< CACHE_COHERENCE_SUPPORT Bit Mask */
4636 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT0       ((uint32_t)0x00000100)          /*!< CACHE_COHERENCE_SUPPORT Bit 0 */
4637 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT1       ((uint32_t)0x00000200)          /*!< CACHE_COHERENCE_SUPPORT Bit 1 */
4638 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT2       ((uint32_t)0x00000400)          /*!< CACHE_COHERENCE_SUPPORT Bit 2 */
4639 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT3       ((uint32_t)0x00000800)          /*!< CACHE_COHERENCE_SUPPORT Bit 3 */
4640 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_0      ((uint32_t)0x00000000)          /*!< no shared support */
4641 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_1      ((uint32_t)0x00000100)          /*!< partial-inner-shared coherency (coherency amongst some - but not all - of  */
4642 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_2      ((uint32_t)0x00000200)          /*!< full-inner-shared coherency (coherency amongst all of the entities within an  */
4643 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_3      ((uint32_t)0x00000300)          /*!< full coherency (coherency amongst all of the entities) */
4644 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_OFS (12)                            /*!< OUTER_NON_SHARABLE_SUPPORT Bit Offset */
4645 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_MASK ((uint32_t)0x0000F000)          /*!< OUTER_NON_SHARABLE_SUPPORT Bit Mask */
4646 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT0    ((uint32_t)0x00001000)          /*!< OUTER_NON_SHARABLE_SUPPORT Bit 0 */
4647 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT1    ((uint32_t)0x00002000)          /*!< OUTER_NON_SHARABLE_SUPPORT Bit 1 */
4648 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT2    ((uint32_t)0x00004000)          /*!< OUTER_NON_SHARABLE_SUPPORT Bit 2 */
4649 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT3    ((uint32_t)0x00008000)          /*!< OUTER_NON_SHARABLE_SUPPORT Bit 3 */
4650 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_0   ((uint32_t)0x00000000)          /*!< Outer non-sharable not supported */
4651 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_1   ((uint32_t)0x00001000)          /*!< Outer sharable supported */
4652 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_OFS  (20)                            /*!< AUXILIARY_REGISTER_SUPPORT Bit Offset */
4653 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_MASK ((uint32_t)0x00F00000)          /*!< AUXILIARY_REGISTER_SUPPORT Bit Mask */
4654 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT0     ((uint32_t)0x00100000)          /*!< AUILIARY_REGISTER_SUPPORT Bit 0 */
4655 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT1     ((uint32_t)0x00200000)          /*!< AUILIARY_REGISTER_SUPPORT Bit 1 */
4656 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT2     ((uint32_t)0x00400000)          /*!< AUILIARY_REGISTER_SUPPORT Bit 2 */
4657 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT3     ((uint32_t)0x00800000)          /*!< AUILIARY_REGISTER_SUPPORT Bit 3 */
4658 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_0    ((uint32_t)0x00000000)          /*!< not supported */
4659 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_1    ((uint32_t)0x00100000)          /*!< Auxiliary control register */
4660 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_OFS (24)                            /*!< WAIT_FOR_INTERRUPT_STALLING Bit Offset */
4661 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_MASK ((uint32_t)0x0F000000)          /*!< WAIT_FOR_INTERRUPT_STALLING Bit Mask */
4662 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING0   ((uint32_t)0x01000000)          /*!< WAIT_FOR_INTERRUPT_STALLING Bit 0 */
4663 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING1   ((uint32_t)0x02000000)          /*!< WAIT_FOR_INTERRUPT_STALLING Bit 1 */
4664 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING2   ((uint32_t)0x04000000)          /*!< WAIT_FOR_INTERRUPT_STALLING Bit 2 */
4665 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING3   ((uint32_t)0x08000000)          /*!< WAIT_FOR_INTERRUPT_STALLING Bit 3 */
4666 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_0  ((uint32_t)0x00000000)          /*!< not supported */
4667 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_1  ((uint32_t)0x01000000)          /*!< wait for interrupt supported */
4668 #define SCB_ISAR0_BITCOUNT_INSTRS_OFS            ( 4)                            /*!< BITCOUNT_INSTRS Bit Offset */
4669 #define SCB_ISAR0_BITCOUNT_INSTRS_MASK           ((uint32_t)0x000000F0)          /*!< BITCOUNT_INSTRS Bit Mask */
4670 #define SCB_ISAR0_BITCOUNT_INSTRS0               ((uint32_t)0x00000010)          /*!< BITCOUNT_INSTRS Bit 0 */
4671 #define SCB_ISAR0_BITCOUNT_INSTRS1               ((uint32_t)0x00000020)          /*!< BITCOUNT_INSTRS Bit 1 */
4672 #define SCB_ISAR0_BITCOUNT_INSTRS2               ((uint32_t)0x00000040)          /*!< BITCOUNT_INSTRS Bit 2 */
4673 #define SCB_ISAR0_BITCOUNT_INSTRS3               ((uint32_t)0x00000080)          /*!< BITCOUNT_INSTRS Bit 3 */
4674 #define SCB_ISAR0_BITCOUNT_INSTRS_0              ((uint32_t)0x00000000)          /*!< no bit-counting instructions present */
4675 #define SCB_ISAR0_BITCOUNT_INSTRS_1              ((uint32_t)0x00000010)          /*!< adds CLZ */
4676 #define SCB_ISAR0_BITFIELD_INSTRS_OFS            ( 8)                            /*!< BITFIELD_INSTRS Bit Offset */
4677 #define SCB_ISAR0_BITFIELD_INSTRS_MASK           ((uint32_t)0x00000F00)          /*!< BITFIELD_INSTRS Bit Mask */
4678 #define SCB_ISAR0_BITFIELD_INSTRS0               ((uint32_t)0x00000100)          /*!< BITFIELD_INSTRS Bit 0 */
4679 #define SCB_ISAR0_BITFIELD_INSTRS1               ((uint32_t)0x00000200)          /*!< BITFIELD_INSTRS Bit 1 */
4680 #define SCB_ISAR0_BITFIELD_INSTRS2               ((uint32_t)0x00000400)          /*!< BITFIELD_INSTRS Bit 2 */
4681 #define SCB_ISAR0_BITFIELD_INSTRS3               ((uint32_t)0x00000800)          /*!< BITFIELD_INSTRS Bit 3 */
4682 #define SCB_ISAR0_BITFIELD_INSTRS_0              ((uint32_t)0x00000000)          /*!< no bitfield instructions present */
4683 #define SCB_ISAR0_BITFIELD_INSTRS_1              ((uint32_t)0x00000100)          /*!< adds BFC, BFI, SBFX, UBFX */
4684 #define SCB_ISAR0_CMPBRANCH_INSTRS_OFS           (12)                            /*!< CMPBRANCH_INSTRS Bit Offset */
4685 #define SCB_ISAR0_CMPBRANCH_INSTRS_MASK          ((uint32_t)0x0000F000)          /*!< CMPBRANCH_INSTRS Bit Mask */
4686 #define SCB_ISAR0_CMPBRANCH_INSTRS0              ((uint32_t)0x00001000)          /*!< CMPBRANCH_INSTRS Bit 0 */
4687 #define SCB_ISAR0_CMPBRANCH_INSTRS1              ((uint32_t)0x00002000)          /*!< CMPBRANCH_INSTRS Bit 1 */
4688 #define SCB_ISAR0_CMPBRANCH_INSTRS2              ((uint32_t)0x00004000)          /*!< CMPBRANCH_INSTRS Bit 2 */
4689 #define SCB_ISAR0_CMPBRANCH_INSTRS3              ((uint32_t)0x00008000)          /*!< CMPBRANCH_INSTRS Bit 3 */
4690 #define SCB_ISAR0_CMPBRANCH_INSTRS_0             ((uint32_t)0x00000000)          /*!< no combined compare-and-branch instructions present */
4691 #define SCB_ISAR0_CMPBRANCH_INSTRS_1             ((uint32_t)0x00001000)          /*!< adds CB{N}Z */
4692 #define SCB_ISAR0_COPROC_INSTRS_OFS              (16)                            /*!< COPROC_INSTRS Bit Offset */
4693 #define SCB_ISAR0_COPROC_INSTRS_MASK             ((uint32_t)0x000F0000)          /*!< COPROC_INSTRS Bit Mask */
4694 #define SCB_ISAR0_COPROC_INSTRS0                 ((uint32_t)0x00010000)          /*!< COPROC_INSTRS Bit 0 */
4695 #define SCB_ISAR0_COPROC_INSTRS1                 ((uint32_t)0x00020000)          /*!< COPROC_INSTRS Bit 1 */
4696 #define SCB_ISAR0_COPROC_INSTRS2                 ((uint32_t)0x00040000)          /*!< COPROC_INSTRS Bit 2 */
4697 #define SCB_ISAR0_COPROC_INSTRS3                 ((uint32_t)0x00080000)          /*!< COPROC_INSTRS Bit 3 */
4698 #define SCB_ISAR0_COPROC_INSTRS_0                ((uint32_t)0x00000000)          /*!< no coprocessor support, other than for separately attributed architectures  */
4699 #define SCB_ISAR0_COPROC_INSTRS_1                ((uint32_t)0x00010000)          /*!< adds generic CDP, LDC, MCR, MRC, STC */
4700 #define SCB_ISAR0_COPROC_INSTRS_2                ((uint32_t)0x00020000)          /*!< adds generic CDP2, LDC2, MCR2, MRC2, STC2 */
4701 #define SCB_ISAR0_COPROC_INSTRS_3                ((uint32_t)0x00030000)          /*!< adds generic MCRR, MRRC */
4702 #define SCB_ISAR0_COPROC_INSTRS_4                ((uint32_t)0x00040000)          /*!< adds generic MCRR2, MRRC2 */
4703 #define SCB_ISAR0_DEBUG_INSTRS_OFS               (20)                            /*!< DEBUG_INSTRS Bit Offset */
4704 #define SCB_ISAR0_DEBUG_INSTRS_MASK              ((uint32_t)0x00F00000)          /*!< DEBUG_INSTRS Bit Mask */
4705 #define SCB_ISAR0_DEBUG_INSTRS0                  ((uint32_t)0x00100000)          /*!< DEBUG_INSTRS Bit 0 */
4706 #define SCB_ISAR0_DEBUG_INSTRS1                  ((uint32_t)0x00200000)          /*!< DEBUG_INSTRS Bit 1 */
4707 #define SCB_ISAR0_DEBUG_INSTRS2                  ((uint32_t)0x00400000)          /*!< DEBUG_INSTRS Bit 2 */
4708 #define SCB_ISAR0_DEBUG_INSTRS3                  ((uint32_t)0x00800000)          /*!< DEBUG_INSTRS Bit 3 */
4709 #define SCB_ISAR0_DEBUG_INSTRS_0                 ((uint32_t)0x00000000)          /*!< no debug instructions present */
4710 #define SCB_ISAR0_DEBUG_INSTRS_1                 ((uint32_t)0x00100000)          /*!< adds BKPT */
4711 #define SCB_ISAR0_DIVIDE_INSTRS_OFS              (24)                            /*!< DIVIDE_INSTRS Bit Offset */
4712 #define SCB_ISAR0_DIVIDE_INSTRS_MASK             ((uint32_t)0x0F000000)          /*!< DIVIDE_INSTRS Bit Mask */
4713 #define SCB_ISAR0_DIVIDE_INSTRS0                 ((uint32_t)0x01000000)          /*!< DIVIDE_INSTRS Bit 0 */
4714 #define SCB_ISAR0_DIVIDE_INSTRS1                 ((uint32_t)0x02000000)          /*!< DIVIDE_INSTRS Bit 1 */
4715 #define SCB_ISAR0_DIVIDE_INSTRS2                 ((uint32_t)0x04000000)          /*!< DIVIDE_INSTRS Bit 2 */
4716 #define SCB_ISAR0_DIVIDE_INSTRS3                 ((uint32_t)0x08000000)          /*!< DIVIDE_INSTRS Bit 3 */
4717 #define SCB_ISAR0_DIVIDE_INSTRS_0                ((uint32_t)0x00000000)          /*!< no divide instructions present */
4718 #define SCB_ISAR0_DIVIDE_INSTRS_1                ((uint32_t)0x01000000)          /*!< adds SDIV, UDIV (v1 quotient only result) */
4719 #define SCB_ISAR1_ETEND_INSRS_OFS                (12)                            /*!< EXTEND_INSRS Bit Offset */
4720 #define SCB_ISAR1_ETEND_INSRS_MASK               ((uint32_t)0x0000F000)          /*!< EXTEND_INSRS Bit Mask */
4721 #define SCB_ISAR1_ETEND_INSRS0                   ((uint32_t)0x00001000)          /*!< ETEND_INSRS Bit 0 */
4722 #define SCB_ISAR1_ETEND_INSRS1                   ((uint32_t)0x00002000)          /*!< ETEND_INSRS Bit 1 */
4723 #define SCB_ISAR1_ETEND_INSRS2                   ((uint32_t)0x00004000)          /*!< ETEND_INSRS Bit 2 */
4724 #define SCB_ISAR1_ETEND_INSRS3                   ((uint32_t)0x00008000)          /*!< ETEND_INSRS Bit 3 */
4725 #define SCB_ISAR1_ETEND_INSRS_0                  ((uint32_t)0x00000000)          /*!< no scalar (i.e. non-SIMD) sign/zero-extend instructions present */
4726 #define SCB_ISAR1_ETEND_INSRS_1                  ((uint32_t)0x00001000)          /*!< adds SXTB, SXTH, UXTB, UXTH */
4727 #define SCB_ISAR1_ETEND_INSRS_2                  ((uint32_t)0x00002000)          /*!< N/A */
4728 #define SCB_ISAR1_IFTHEN_INSTRS_OFS              (16)                            /*!< IFTHEN_INSTRS Bit Offset */
4729 #define SCB_ISAR1_IFTHEN_INSTRS_MASK             ((uint32_t)0x000F0000)          /*!< IFTHEN_INSTRS Bit Mask */
4730 #define SCB_ISAR1_IFTHEN_INSTRS0                 ((uint32_t)0x00010000)          /*!< IFTHEN_INSTRS Bit 0 */
4731 #define SCB_ISAR1_IFTHEN_INSTRS1                 ((uint32_t)0x00020000)          /*!< IFTHEN_INSTRS Bit 1 */
4732 #define SCB_ISAR1_IFTHEN_INSTRS2                 ((uint32_t)0x00040000)          /*!< IFTHEN_INSTRS Bit 2 */
4733 #define SCB_ISAR1_IFTHEN_INSTRS3                 ((uint32_t)0x00080000)          /*!< IFTHEN_INSTRS Bit 3 */
4734 #define SCB_ISAR1_IFTHEN_INSTRS_0                ((uint32_t)0x00000000)          /*!< IT instructions not present */
4735 #define SCB_ISAR1_IFTHEN_INSTRS_1                ((uint32_t)0x00010000)          /*!< adds IT instructions (and IT bits in PSRs) */
4736 #define SCB_ISAR1_IMMEDIATE_INSTRS_OFS           (20)                            /*!< IMMEDIATE_INSTRS Bit Offset */
4737 #define SCB_ISAR1_IMMEDIATE_INSTRS_MASK          ((uint32_t)0x00F00000)          /*!< IMMEDIATE_INSTRS Bit Mask */
4738 #define SCB_ISAR1_IMMEDIATE_INSTRS0              ((uint32_t)0x00100000)          /*!< IMMEDIATE_INSTRS Bit 0 */
4739 #define SCB_ISAR1_IMMEDIATE_INSTRS1              ((uint32_t)0x00200000)          /*!< IMMEDIATE_INSTRS Bit 1 */
4740 #define SCB_ISAR1_IMMEDIATE_INSTRS2              ((uint32_t)0x00400000)          /*!< IMMEDIATE_INSTRS Bit 2 */
4741 #define SCB_ISAR1_IMMEDIATE_INSTRS3              ((uint32_t)0x00800000)          /*!< IMMEDIATE_INSTRS Bit 3 */
4742 #define SCB_ISAR1_IMMEDIATE_INSTRS_0             ((uint32_t)0x00000000)          /*!< no special immediate-generating instructions present */
4743 #define SCB_ISAR1_IMMEDIATE_INSTRS_1             ((uint32_t)0x00100000)          /*!< adds ADDW, MOVW, MOVT, SUBW */
4744 #define SCB_ISAR1_INTERWORK_INSTRS_OFS           (24)                            /*!< INTERWORK_INSTRS Bit Offset */
4745 #define SCB_ISAR1_INTERWORK_INSTRS_MASK          ((uint32_t)0x0F000000)          /*!< INTERWORK_INSTRS Bit Mask */
4746 #define SCB_ISAR1_INTERWORK_INSTRS0              ((uint32_t)0x01000000)          /*!< INTERWORK_INSTRS Bit 0 */
4747 #define SCB_ISAR1_INTERWORK_INSTRS1              ((uint32_t)0x02000000)          /*!< INTERWORK_INSTRS Bit 1 */
4748 #define SCB_ISAR1_INTERWORK_INSTRS2              ((uint32_t)0x04000000)          /*!< INTERWORK_INSTRS Bit 2 */
4749 #define SCB_ISAR1_INTERWORK_INSTRS3              ((uint32_t)0x08000000)          /*!< INTERWORK_INSTRS Bit 3 */
4750 #define SCB_ISAR1_INTERWORK_INSTRS_0             ((uint32_t)0x00000000)          /*!< no interworking instructions supported */
4751 #define SCB_ISAR1_INTERWORK_INSTRS_1             ((uint32_t)0x01000000)          /*!< adds BX (and T bit in PSRs) */
4752 #define SCB_ISAR1_INTERWORK_INSTRS_2             ((uint32_t)0x02000000)          /*!< adds BLX, and PC loads have BX-like behavior */
4753 #define SCB_ISAR1_INTERWORK_INSTRS_3             ((uint32_t)0x03000000)          /*!< N/A */
4754 #define SCB_ISAR2_LOADSTORE_INSTRS_OFS           ( 0)                            /*!< LOADSTORE_INSTRS Bit Offset */
4755 #define SCB_ISAR2_LOADSTORE_INSTRS_MASK          ((uint32_t)0x0000000F)          /*!< LOADSTORE_INSTRS Bit Mask */
4756 #define SCB_ISAR2_LOADSTORE_INSTRS0              ((uint32_t)0x00000001)          /*!< LOADSTORE_INSTRS Bit 0 */
4757 #define SCB_ISAR2_LOADSTORE_INSTRS1              ((uint32_t)0x00000002)          /*!< LOADSTORE_INSTRS Bit 1 */
4758 #define SCB_ISAR2_LOADSTORE_INSTRS2              ((uint32_t)0x00000004)          /*!< LOADSTORE_INSTRS Bit 2 */
4759 #define SCB_ISAR2_LOADSTORE_INSTRS3              ((uint32_t)0x00000008)          /*!< LOADSTORE_INSTRS Bit 3 */
4760 #define SCB_ISAR2_LOADSTORE_INSTRS_0             ((uint32_t)0x00000000)          /*!< no additional normal load/store instructions present */
4761 #define SCB_ISAR2_LOADSTORE_INSTRS_1             ((uint32_t)0x00000001)          /*!< adds LDRD/STRD */
4762 #define SCB_ISAR2_MEMHINT_INSTRS_OFS             ( 4)                            /*!< MEMHINT_INSTRS Bit Offset */
4763 #define SCB_ISAR2_MEMHINT_INSTRS_MASK            ((uint32_t)0x000000F0)          /*!< MEMHINT_INSTRS Bit Mask */
4764 #define SCB_ISAR2_MEMHINT_INSTRS0                ((uint32_t)0x00000010)          /*!< MEMHINT_INSTRS Bit 0 */
4765 #define SCB_ISAR2_MEMHINT_INSTRS1                ((uint32_t)0x00000020)          /*!< MEMHINT_INSTRS Bit 1 */
4766 #define SCB_ISAR2_MEMHINT_INSTRS2                ((uint32_t)0x00000040)          /*!< MEMHINT_INSTRS Bit 2 */
4767 #define SCB_ISAR2_MEMHINT_INSTRS3                ((uint32_t)0x00000080)          /*!< MEMHINT_INSTRS Bit 3 */
4768 #define SCB_ISAR2_MEMHINT_INSTRS_0               ((uint32_t)0x00000000)          /*!< no memory hint instructions presen */
4769 #define SCB_ISAR2_MEMHINT_INSTRS_1               ((uint32_t)0x00000010)          /*!< adds PLD */
4770 #define SCB_ISAR2_MEMHINT_INSTRS_2               ((uint32_t)0x00000020)          /*!< adds PLD (ie a repeat on value 1) */
4771 #define SCB_ISAR2_MEMHINT_INSTRS_3               ((uint32_t)0x00000030)          /*!< adds PLI */
4772 #define SCB_ISAR2_MULTIACCESSINT_INSTRS_OFS      ( 8)                            /*!< MULTIACCESSINT_INSTRS Bit Offset */
4773 #define SCB_ISAR2_MULTIACCESSINT_INSTRS_MASK     ((uint32_t)0x00000F00)          /*!< MULTIACCESSINT_INSTRS Bit Mask */
4774 #define SCB_ISAR2_MULTIACCESSINT_INSTRS0         ((uint32_t)0x00000100)          /*!< MULTIACCESSINT_INSTRS Bit 0 */
4775 #define SCB_ISAR2_MULTIACCESSINT_INSTRS1         ((uint32_t)0x00000200)          /*!< MULTIACCESSINT_INSTRS Bit 1 */
4776 #define SCB_ISAR2_MULTIACCESSINT_INSTRS2         ((uint32_t)0x00000400)          /*!< MULTIACCESSINT_INSTRS Bit 2 */
4777 #define SCB_ISAR2_MULTIACCESSINT_INSTRS3         ((uint32_t)0x00000800)          /*!< MULTIACCESSINT_INSTRS Bit 3 */
4778 #define SCB_ISAR2_MULTIACCESSINT_INSTRS_0        ((uint32_t)0x00000000)          /*!< the (LDM/STM) instructions are non-interruptible */
4779 #define SCB_ISAR2_MULTIACCESSINT_INSTRS_1        ((uint32_t)0x00000100)          /*!< the (LDM/STM) instructions are restartable */
4780 #define SCB_ISAR2_MULTIACCESSINT_INSTRS_2        ((uint32_t)0x00000200)          /*!< the (LDM/STM) instructions are continuable */
4781 #define SCB_ISAR2_MULT_INSTRS_OFS                (12)                            /*!< MULT_INSTRS Bit Offset */
4782 #define SCB_ISAR2_MULT_INSTRS_MASK               ((uint32_t)0x0000F000)          /*!< MULT_INSTRS Bit Mask */
4783 #define SCB_ISAR2_MULT_INSTRS0                   ((uint32_t)0x00001000)          /*!< MULT_INSTRS Bit 0 */
4784 #define SCB_ISAR2_MULT_INSTRS1                   ((uint32_t)0x00002000)          /*!< MULT_INSTRS Bit 1 */
4785 #define SCB_ISAR2_MULT_INSTRS2                   ((uint32_t)0x00004000)          /*!< MULT_INSTRS Bit 2 */
4786 #define SCB_ISAR2_MULT_INSTRS3                   ((uint32_t)0x00008000)          /*!< MULT_INSTRS Bit 3 */
4787 #define SCB_ISAR2_MULT_INSTRS_0                  ((uint32_t)0x00000000)          /*!< only MUL present */
4788 #define SCB_ISAR2_MULT_INSTRS_1                  ((uint32_t)0x00001000)          /*!< adds MLA */
4789 #define SCB_ISAR2_MULT_INSTRS_2                  ((uint32_t)0x00002000)          /*!< adds MLS */
4790 #define SCB_ISAR2_MULTS_INSTRS_OFS               (16)                            /*!< MULTS_INSTRS Bit Offset */
4791 #define SCB_ISAR2_MULTS_INSTRS_MASK              ((uint32_t)0x000F0000)          /*!< MULTS_INSTRS Bit Mask */
4792 #define SCB_ISAR2_MULTS_INSTRS0                  ((uint32_t)0x00010000)          /*!< MULTS_INSTRS Bit 0 */
4793 #define SCB_ISAR2_MULTS_INSTRS1                  ((uint32_t)0x00020000)          /*!< MULTS_INSTRS Bit 1 */
4794 #define SCB_ISAR2_MULTS_INSTRS2                  ((uint32_t)0x00040000)          /*!< MULTS_INSTRS Bit 2 */
4795 #define SCB_ISAR2_MULTS_INSTRS3                  ((uint32_t)0x00080000)          /*!< MULTS_INSTRS Bit 3 */
4796 #define SCB_ISAR2_MULTS_INSTRS_0                 ((uint32_t)0x00000000)          /*!< no signed multiply instructions present */
4797 #define SCB_ISAR2_MULTS_INSTRS_1                 ((uint32_t)0x00010000)          /*!< adds SMULL, SMLAL */
4798 #define SCB_ISAR2_MULTS_INSTRS_2                 ((uint32_t)0x00020000)          /*!< N/A */
4799 #define SCB_ISAR2_MULTS_INSTRS_3                 ((uint32_t)0x00030000)          /*!< N/A */
4800 #define SCB_ISAR2_MULTU_INSTRS_OFS               (20)                            /*!< MULTU_INSTRS Bit Offset */
4801 #define SCB_ISAR2_MULTU_INSTRS_MASK              ((uint32_t)0x00F00000)          /*!< MULTU_INSTRS Bit Mask */
4802 #define SCB_ISAR2_MULTU_INSTRS0                  ((uint32_t)0x00100000)          /*!< MULTU_INSTRS Bit 0 */
4803 #define SCB_ISAR2_MULTU_INSTRS1                  ((uint32_t)0x00200000)          /*!< MULTU_INSTRS Bit 1 */
4804 #define SCB_ISAR2_MULTU_INSTRS2                  ((uint32_t)0x00400000)          /*!< MULTU_INSTRS Bit 2 */
4805 #define SCB_ISAR2_MULTU_INSTRS3                  ((uint32_t)0x00800000)          /*!< MULTU_INSTRS Bit 3 */
4806 #define SCB_ISAR2_MULTU_INSTRS_0                 ((uint32_t)0x00000000)          /*!< no unsigned multiply instructions present */
4807 #define SCB_ISAR2_MULTU_INSTRS_1                 ((uint32_t)0x00100000)          /*!< adds UMULL, UMLAL */
4808 #define SCB_ISAR2_MULTU_INSTRS_2                 ((uint32_t)0x00200000)          /*!< N/A */
4809 #define SCB_ISAR2_REVERSAL_INSTRS_OFS            (28)                            /*!< REVERSAL_INSTRS Bit Offset */
4810 #define SCB_ISAR2_REVERSAL_INSTRS_MASK           ((uint32_t)0xF0000000)          /*!< REVERSAL_INSTRS Bit Mask */
4811 #define SCB_ISAR2_REVERSAL_INSTRS0               ((uint32_t)0x10000000)          /*!< REVERSAL_INSTRS Bit 0 */
4812 #define SCB_ISAR2_REVERSAL_INSTRS1               ((uint32_t)0x20000000)          /*!< REVERSAL_INSTRS Bit 1 */
4813 #define SCB_ISAR2_REVERSAL_INSTRS2               ((uint32_t)0x40000000)          /*!< REVERSAL_INSTRS Bit 2 */
4814 #define SCB_ISAR2_REVERSAL_INSTRS3               ((uint32_t)0x80000000)          /*!< REVERSAL_INSTRS Bit 3 */
4815 #define SCB_ISAR2_REVERSAL_INSTRS_0              ((uint32_t)0x00000000)          /*!< no reversal instructions present */
4816 #define SCB_ISAR2_REVERSAL_INSTRS_1              ((uint32_t)0x10000000)          /*!< adds REV, REV16, REVSH */
4817 #define SCB_ISAR2_REVERSAL_INSTRS_2              ((uint32_t)0x20000000)          /*!< adds RBIT */
4818 #define SCB_ISAR3_SATRUATE_INSTRS_OFS            ( 0)                            /*!< SATRUATE_INSTRS Bit Offset */
4819 #define SCB_ISAR3_SATRUATE_INSTRS_MASK           ((uint32_t)0x0000000F)          /*!< SATRUATE_INSTRS Bit Mask */
4820 #define SCB_ISAR3_SATRUATE_INSTRS0               ((uint32_t)0x00000001)          /*!< SATRUATE_INSTRS Bit 0 */
4821 #define SCB_ISAR3_SATRUATE_INSTRS1               ((uint32_t)0x00000002)          /*!< SATRUATE_INSTRS Bit 1 */
4822 #define SCB_ISAR3_SATRUATE_INSTRS2               ((uint32_t)0x00000004)          /*!< SATRUATE_INSTRS Bit 2 */
4823 #define SCB_ISAR3_SATRUATE_INSTRS3               ((uint32_t)0x00000008)          /*!< SATRUATE_INSTRS Bit 3 */
4824 #define SCB_ISAR3_SATRUATE_INSTRS_0              ((uint32_t)0x00000000)          /*!< no non-SIMD saturate instructions present */
4825 #define SCB_ISAR3_SATRUATE_INSTRS_1              ((uint32_t)0x00000001)          /*!< N/A */
4826 #define SCB_ISAR3_SIMD_INSTRS_OFS                ( 4)                            /*!< SIMD_INSTRS Bit Offset */
4827 #define SCB_ISAR3_SIMD_INSTRS_MASK               ((uint32_t)0x000000F0)          /*!< SIMD_INSTRS Bit Mask */
4828 #define SCB_ISAR3_SIMD_INSTRS0                   ((uint32_t)0x00000010)          /*!< SIMD_INSTRS Bit 0 */
4829 #define SCB_ISAR3_SIMD_INSTRS1                   ((uint32_t)0x00000020)          /*!< SIMD_INSTRS Bit 1 */
4830 #define SCB_ISAR3_SIMD_INSTRS2                   ((uint32_t)0x00000040)          /*!< SIMD_INSTRS Bit 2 */
4831 #define SCB_ISAR3_SIMD_INSTRS3                   ((uint32_t)0x00000080)          /*!< SIMD_INSTRS Bit 3 */
4832 #define SCB_ISAR3_SIMD_INSTRS_0                  ((uint32_t)0x00000000)          /*!< no SIMD instructions present */
4833 #define SCB_ISAR3_SIMD_INSTRS_1                  ((uint32_t)0x00000010)          /*!< adds SSAT, USAT (and the Q flag in the PSRs) */
4834 #define SCB_ISAR3_SIMD_INSTRS_3                  ((uint32_t)0x00000030)          /*!< N/A */
4835 #define SCB_ISAR3_SVC_INSTRS_OFS                 ( 8)                            /*!< SVC_INSTRS Bit Offset */
4836 #define SCB_ISAR3_SVC_INSTRS_MASK                ((uint32_t)0x00000F00)          /*!< SVC_INSTRS Bit Mask */
4837 #define SCB_ISAR3_SVC_INSTRS0                    ((uint32_t)0x00000100)          /*!< SVC_INSTRS Bit 0 */
4838 #define SCB_ISAR3_SVC_INSTRS1                    ((uint32_t)0x00000200)          /*!< SVC_INSTRS Bit 1 */
4839 #define SCB_ISAR3_SVC_INSTRS2                    ((uint32_t)0x00000400)          /*!< SVC_INSTRS Bit 2 */
4840 #define SCB_ISAR3_SVC_INSTRS3                    ((uint32_t)0x00000800)          /*!< SVC_INSTRS Bit 3 */
4841 #define SCB_ISAR3_SVC_INSTRS_0                   ((uint32_t)0x00000000)          /*!< no SVC (SWI) instructions present */
4842 #define SCB_ISAR3_SVC_INSTRS_1                   ((uint32_t)0x00000100)          /*!< adds SVC (SWI) */
4843 #define SCB_ISAR3_SYNCPRIM_INSTRS_OFS            (12)                            /*!< SYNCPRIM_INSTRS Bit Offset */
4844 #define SCB_ISAR3_SYNCPRIM_INSTRS_MASK           ((uint32_t)0x0000F000)          /*!< SYNCPRIM_INSTRS Bit Mask */
4845 #define SCB_ISAR3_SYNCPRIM_INSTRS0               ((uint32_t)0x00001000)          /*!< SYNCPRIM_INSTRS Bit 0 */
4846 #define SCB_ISAR3_SYNCPRIM_INSTRS1               ((uint32_t)0x00002000)          /*!< SYNCPRIM_INSTRS Bit 1 */
4847 #define SCB_ISAR3_SYNCPRIM_INSTRS2               ((uint32_t)0x00004000)          /*!< SYNCPRIM_INSTRS Bit 2 */
4848 #define SCB_ISAR3_SYNCPRIM_INSTRS3               ((uint32_t)0x00008000)          /*!< SYNCPRIM_INSTRS Bit 3 */
4849 #define SCB_ISAR3_SYNCPRIM_INSTRS_0              ((uint32_t)0x00000000)          /*!< no synchronization primitives present */
4850 #define SCB_ISAR3_SYNCPRIM_INSTRS_1              ((uint32_t)0x00001000)          /*!< adds LDREX, STREX */
4851 #define SCB_ISAR3_SYNCPRIM_INSTRS_2              ((uint32_t)0x00002000)          /*!< adds LDREXB, LDREXH, LDREXD, STREXB, STREXH, STREXD, CLREX(N/A) */
4852 #define SCB_ISAR3_TABBRANCH_INSTRS_OFS           (16)                            /*!< TABBRANCH_INSTRS Bit Offset */
4853 #define SCB_ISAR3_TABBRANCH_INSTRS_MASK          ((uint32_t)0x000F0000)          /*!< TABBRANCH_INSTRS Bit Mask */
4854 #define SCB_ISAR3_TABBRANCH_INSTRS0              ((uint32_t)0x00010000)          /*!< TABBRANCH_INSTRS Bit 0 */
4855 #define SCB_ISAR3_TABBRANCH_INSTRS1              ((uint32_t)0x00020000)          /*!< TABBRANCH_INSTRS Bit 1 */
4856 #define SCB_ISAR3_TABBRANCH_INSTRS2              ((uint32_t)0x00040000)          /*!< TABBRANCH_INSTRS Bit 2 */
4857 #define SCB_ISAR3_TABBRANCH_INSTRS3              ((uint32_t)0x00080000)          /*!< TABBRANCH_INSTRS Bit 3 */
4858 #define SCB_ISAR3_TABBRANCH_INSTRS_0             ((uint32_t)0x00000000)          /*!< no table-branch instructions present */
4859 #define SCB_ISAR3_TABBRANCH_INSTRS_1             ((uint32_t)0x00010000)          /*!< adds TBB, TBH */
4860 #define SCB_ISAR3_THUMBCOPY_INSTRS_OFS           (20)                            /*!< THUMBCOPY_INSTRS Bit Offset */
4861 #define SCB_ISAR3_THUMBCOPY_INSTRS_MASK          ((uint32_t)0x00F00000)          /*!< THUMBCOPY_INSTRS Bit Mask */
4862 #define SCB_ISAR3_THUMBCOPY_INSTRS0              ((uint32_t)0x00100000)          /*!< THUMBCOPY_INSTRS Bit 0 */
4863 #define SCB_ISAR3_THUMBCOPY_INSTRS1              ((uint32_t)0x00200000)          /*!< THUMBCOPY_INSTRS Bit 1 */
4864 #define SCB_ISAR3_THUMBCOPY_INSTRS2              ((uint32_t)0x00400000)          /*!< THUMBCOPY_INSTRS Bit 2 */
4865 #define SCB_ISAR3_THUMBCOPY_INSTRS3              ((uint32_t)0x00800000)          /*!< THUMBCOPY_INSTRS Bit 3 */
4866 #define SCB_ISAR3_THUMBCOPY_INSTRS_0             ((uint32_t)0x00000000)          /*!< Thumb MOV(register) instruction does not allow low reg -> low reg */
4867 #define SCB_ISAR3_THUMBCOPY_INSTRS_1             ((uint32_t)0x00100000)          /*!< adds Thumb MOV(register) low reg -> low reg and the CPY alias */
4868 #define SCB_ISAR3_TRUENOP_INSTRS_OFS             (24)                            /*!< TRUENOP_INSTRS Bit Offset */
4869 #define SCB_ISAR3_TRUENOP_INSTRS_MASK            ((uint32_t)0x0F000000)          /*!< TRUENOP_INSTRS Bit Mask */
4870 #define SCB_ISAR3_TRUENOP_INSTRS0                ((uint32_t)0x01000000)          /*!< TRUENOP_INSTRS Bit 0 */
4871 #define SCB_ISAR3_TRUENOP_INSTRS1                ((uint32_t)0x02000000)          /*!< TRUENOP_INSTRS Bit 1 */
4872 #define SCB_ISAR3_TRUENOP_INSTRS2                ((uint32_t)0x04000000)          /*!< TRUENOP_INSTRS Bit 2 */
4873 #define SCB_ISAR3_TRUENOP_INSTRS3                ((uint32_t)0x08000000)          /*!< TRUENOP_INSTRS Bit 3 */
4874 #define SCB_ISAR3_TRUENOP_INSTRS_0               ((uint32_t)0x00000000)          /*!< true NOP instructions not present - that is, NOP instructions with no  */
4875 #define SCB_ISAR3_TRUENOP_INSTRS_1               ((uint32_t)0x01000000)          /*!< adds "true NOP", and the capability of additional "NOP compatible hints" */
4876 #define SCB_ISAR4_UNPRIV_INSTRS_OFS              ( 0)                            /*!< UNPRIV_INSTRS Bit Offset */
4877 #define SCB_ISAR4_UNPRIV_INSTRS_MASK             ((uint32_t)0x0000000F)          /*!< UNPRIV_INSTRS Bit Mask */
4878 #define SCB_ISAR4_UNPRIV_INSTRS0                 ((uint32_t)0x00000001)          /*!< UNPRIV_INSTRS Bit 0 */
4879 #define SCB_ISAR4_UNPRIV_INSTRS1                 ((uint32_t)0x00000002)          /*!< UNPRIV_INSTRS Bit 1 */
4880 #define SCB_ISAR4_UNPRIV_INSTRS2                 ((uint32_t)0x00000004)          /*!< UNPRIV_INSTRS Bit 2 */
4881 #define SCB_ISAR4_UNPRIV_INSTRS3                 ((uint32_t)0x00000008)          /*!< UNPRIV_INSTRS Bit 3 */
4882 #define SCB_ISAR4_UNPRIV_INSTRS_0                ((uint32_t)0x00000000)          /*!< no "T variant" instructions exist */
4883 #define SCB_ISAR4_UNPRIV_INSTRS_1                ((uint32_t)0x00000001)          /*!< adds LDRBT, LDRT, STRBT, STRT */
4884 #define SCB_ISAR4_UNPRIV_INSTRS_2                ((uint32_t)0x00000002)          /*!< adds LDRHT, LDRSBT, LDRSHT, STRHT */
4885 #define SCB_ISAR4_WITHSHIFTS_INSTRS_OFS          ( 4)                            /*!< WITHSHIFTS_INSTRS Bit Offset */
4886 #define SCB_ISAR4_WITHSHIFTS_INSTRS_MASK         ((uint32_t)0x000000F0)          /*!< WITHSHIFTS_INSTRS Bit Mask */
4887 #define SCB_ISAR4_WITHSHIFTS_INSTRS0             ((uint32_t)0x00000010)          /*!< WITHSHIFTS_INSTRS Bit 0 */
4888 #define SCB_ISAR4_WITHSHIFTS_INSTRS1             ((uint32_t)0x00000020)          /*!< WITHSHIFTS_INSTRS Bit 1 */
4889 #define SCB_ISAR4_WITHSHIFTS_INSTRS2             ((uint32_t)0x00000040)          /*!< WITHSHIFTS_INSTRS Bit 2 */
4890 #define SCB_ISAR4_WITHSHIFTS_INSTRS3             ((uint32_t)0x00000080)          /*!< WITHSHIFTS_INSTRS Bit 3 */
4891 #define SCB_ISAR4_WITHSHIFTS_INSTRS_0            ((uint32_t)0x00000000)          /*!< non-zero shifts only support MOV and shift instructions (see notes) */
4892 #define SCB_ISAR4_WITHSHIFTS_INSTRS_1            ((uint32_t)0x00000010)          /*!< shifts of loads/stores over the range LSL 0-3 */
4893 #define SCB_ISAR4_WITHSHIFTS_INSTRS_3            ((uint32_t)0x00000030)          /*!< adds other constant shift options. */
4894 #define SCB_ISAR4_WITHSHIFTS_INSTRS_4            ((uint32_t)0x00000040)          /*!< adds register-controlled shift options. */
4895 #define SCB_ISAR4_WRITEBACK_INSTRS_OFS           ( 8)                            /*!< WRITEBACK_INSTRS Bit Offset */
4896 #define SCB_ISAR4_WRITEBACK_INSTRS_MASK          ((uint32_t)0x00000F00)          /*!< WRITEBACK_INSTRS Bit Mask */
4897 #define SCB_ISAR4_WRITEBACK_INSTRS0              ((uint32_t)0x00000100)          /*!< WRITEBACK_INSTRS Bit 0 */
4898 #define SCB_ISAR4_WRITEBACK_INSTRS1              ((uint32_t)0x00000200)          /*!< WRITEBACK_INSTRS Bit 1 */
4899 #define SCB_ISAR4_WRITEBACK_INSTRS2              ((uint32_t)0x00000400)          /*!< WRITEBACK_INSTRS Bit 2 */
4900 #define SCB_ISAR4_WRITEBACK_INSTRS3              ((uint32_t)0x00000800)          /*!< WRITEBACK_INSTRS Bit 3 */
4901 #define SCB_ISAR4_WRITEBACK_INSTRS_0             ((uint32_t)0x00000000)          /*!< only non-writeback addressing modes present, except that  */
4902 #define SCB_ISAR4_WRITEBACK_INSTRS_1             ((uint32_t)0x00000100)          /*!< adds all currently-defined writeback addressing modes (ARMv7, Thumb-2) */
4903 #define SCB_ISAR4_BARRIER_INSTRS_OFS             (16)                            /*!< BARRIER_INSTRS Bit Offset */
4904 #define SCB_ISAR4_BARRIER_INSTRS_MASK            ((uint32_t)0x000F0000)          /*!< BARRIER_INSTRS Bit Mask */
4905 #define SCB_ISAR4_BARRIER_INSTRS0                ((uint32_t)0x00010000)          /*!< BARRIER_INSTRS Bit 0 */
4906 #define SCB_ISAR4_BARRIER_INSTRS1                ((uint32_t)0x00020000)          /*!< BARRIER_INSTRS Bit 1 */
4907 #define SCB_ISAR4_BARRIER_INSTRS2                ((uint32_t)0x00040000)          /*!< BARRIER_INSTRS Bit 2 */
4908 #define SCB_ISAR4_BARRIER_INSTRS3                ((uint32_t)0x00080000)          /*!< BARRIER_INSTRS Bit 3 */
4909 #define SCB_ISAR4_BARRIER_INSTRS_0               ((uint32_t)0x00000000)          /*!< no barrier instructions supported */
4910 #define SCB_ISAR4_BARRIER_INSTRS_1               ((uint32_t)0x00010000)          /*!< adds DMB, DSB, ISB barrier instructions */
4911 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_OFS       (20)                            /*!< SYNCPRIM_INSTRS_FRAC Bit Offset */
4912 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_MASK      ((uint32_t)0x00F00000)          /*!< SYNCPRIM_INSTRS_FRAC Bit Mask */
4913 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC0          ((uint32_t)0x00100000)          /*!< SYNCPRIM_INSTRS_FRAC Bit 0 */
4914 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC1          ((uint32_t)0x00200000)          /*!< SYNCPRIM_INSTRS_FRAC Bit 1 */
4915 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC2          ((uint32_t)0x00400000)          /*!< SYNCPRIM_INSTRS_FRAC Bit 2 */
4916 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC3          ((uint32_t)0x00800000)          /*!< SYNCPRIM_INSTRS_FRAC Bit 3 */
4917 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_0         ((uint32_t)0x00000000)          /*!< no additional support */
4918 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_3         ((uint32_t)0x00300000)          /*!< adds CLREX, LDREXB, STREXB, LDREXH, STREXH */
4919 #define SCB_ISAR4_PSR_M_INSTRS_OFS               (24)                            /*!< PSR_M_INSTRS Bit Offset */
4920 #define SCB_ISAR4_PSR_M_INSTRS_MASK              ((uint32_t)0x0F000000)          /*!< PSR_M_INSTRS Bit Mask */
4921 #define SCB_ISAR4_PSR_M_INSTRS0                  ((uint32_t)0x01000000)          /*!< PSR_M_INSTRS Bit 0 */
4922 #define SCB_ISAR4_PSR_M_INSTRS1                  ((uint32_t)0x02000000)          /*!< PSR_M_INSTRS Bit 1 */
4923 #define SCB_ISAR4_PSR_M_INSTRS2                  ((uint32_t)0x04000000)          /*!< PSR_M_INSTRS Bit 2 */
4924 #define SCB_ISAR4_PSR_M_INSTRS3                  ((uint32_t)0x08000000)          /*!< PSR_M_INSTRS Bit 3 */
4925 #define SCB_ISAR4_PSR_M_INSTRS_0                 ((uint32_t)0x00000000)          /*!< instructions not present */
4926 #define SCB_ISAR4_PSR_M_INSTRS_1                 ((uint32_t)0x01000000)          /*!< adds CPS, MRS, and MSR instructions (M-profile forms) */
4927 #define SCB_CPACR_CP11_OFS                       (22)                            /*!< CP11 Bit Offset */
4928 #define SCB_CPACR_CP11_MASK                      ((uint32_t)0x00C00000)          /*!< CP11 Bit Mask */
4929 #define SCB_CPACR_CP10_OFS                       (20)                            /*!< CP10 Bit Offset */
4930 #define SCB_CPACR_CP10_MASK                      ((uint32_t)0x00300000)          /*!< CP10 Bit Mask */
4931 #define SCB_SHPR1_PRI_4_OFS                      ( 0)                            /*!< PRI_4 Offset */
4932 #define SCB_SHPR1_PRI_4_M                        ((uint32_t)0x000000ff)          /*  */
4933 #define SCB_SHPR1_PRI_5_OFS                      ( 8)                            /*!< PRI_5 Offset */
4934 #define SCB_SHPR1_PRI_5_M                        ((uint32_t)0x0000ff00)          /*  */
4935 #define SCB_SHPR1_PRI_6_OFS                      (16)                            /*!< PRI_6 Offset */
4936 #define SCB_SHPR1_PRI_6_M                        ((uint32_t)0x00ff0000)          /*  */
4937 #define SCB_SHPR1_PRI_7_OFS                      (24)                            /*!< PRI_7 Offset */
4938 #define SCB_SHPR1_PRI_7_M                        ((uint32_t)0xff000000)          /*  */
4939 #define SCB_SHPR2_PRI_8_OFS                      ( 0)                            /*!< PRI_8 Offset */
4940 #define SCB_SHPR2_PRI_8_M                        ((uint32_t)0x000000ff)          /*  */
4941 #define SCB_SHPR2_PRI_9_OFS                      ( 8)                            /*!< PRI_9 Offset */
4942 #define SCB_SHPR2_PRI_9_M                        ((uint32_t)0x0000ff00)          /*  */
4943 #define SCB_SHPR2_PRI_10_OFS                     (16)                            /*!< PRI_10 Offset */
4944 #define SCB_SHPR2_PRI_10_M                       ((uint32_t)0x00ff0000)          /*  */
4945 #define SCB_SHPR2_PRI_11_OFS                     (24)                            /*!< PRI_11 Offset */
4946 #define SCB_SHPR2_PRI_11_M                       ((uint32_t)0xff000000)          /*  */
4947 #define SCB_SHPR3_PRI_12_OFS                     ( 0)                            /*!< PRI_12 Offset */
4948 #define SCB_SHPR3_PRI_12_M                       ((uint32_t)0x000000ff)          /*  */
4949 #define SCB_SHPR3_PRI_13_OFS                     ( 8)                            /*!< PRI_13 Offset */
4950 #define SCB_SHPR3_PRI_13_M                       ((uint32_t)0x0000ff00)          /*  */
4951 #define SCB_SHPR3_PRI_14_OFS                     (16)                            /*!< PRI_14 Offset */
4952 #define SCB_SHPR3_PRI_14_M                       ((uint32_t)0x00ff0000)          /*  */
4953 #define SCB_SHPR3_PRI_15_OFS                     (24)                            /*!< PRI_15 Offset */
4954 #define SCB_SHPR3_PRI_15_M                       ((uint32_t)0xff000000)          /*  */
4955 #define SCB_CFSR_IACCVIOL_OFS                    ( 0)                            /*!< IACCVIOL Offset */
4956 #define SCB_CFSR_IACCVIOL                        ((uint32_t)0x00000001)          /*  */
4957 #define SCB_CFSR_DACCVIOL_OFS                    ( 1)                            /*!< DACCVIOL Offset */
4958 #define SCB_CFSR_DACCVIOL                        ((uint32_t)0x00000002)          /*  */
4959 #define SCB_CFSR_MUNSTKERR_OFS                   ( 3)                            /*!< MUNSTKERR Offset */
4960 #define SCB_CFSR_MUNSTKERR                       ((uint32_t)0x00000008)          /*  */
4961 #define SCB_CFSR_MSTKERR_OFS                     ( 4)                            /*!< MSTKERR Offset */
4962 #define SCB_CFSR_MSTKERR                         ((uint32_t)0x00000010)          /*  */
4963 #define SCB_CFSR_MMARVALID_OFS                   ( 7)                            /*!< MMARVALID Offset */
4964 #define SCB_CFSR_MMARVALID                       ((uint32_t)0x00000080)          /*  */
4965 #define SCB_CFSR_IBUSERR_OFS                     ( 8)                            /*!< IBUSERR Offset */
4966 #define SCB_CFSR_IBUSERR                         ((uint32_t)0x00000100)          /*  */
4967 #define SCB_CFSR_PRECISERR_OFS                   ( 9)                            /*!< PRECISERR Offset */
4968 #define SCB_CFSR_PRECISERR                       ((uint32_t)0x00000200)          /*  */
4969 #define SCB_CFSR_IMPRECISERR_OFS                 (10)                            /*!< IMPRECISERR Offset */
4970 #define SCB_CFSR_IMPRECISERR                     ((uint32_t)0x00000400)          /*  */
4971 #define SCB_CFSR_UNSTKERR_OFS                    (11)                            /*!< UNSTKERR Offset */
4972 #define SCB_CFSR_UNSTKERR                        ((uint32_t)0x00000800)          /*  */
4973 #define SCB_CFSR_STKERR_OFS                      (12)                            /*!< STKERR Offset */
4974 #define SCB_CFSR_STKERR                          ((uint32_t)0x00001000)          /*  */
4975 #define SCB_CFSR_BFARVALID_OFS                   (15)                            /*!< BFARVALID Offset */
4976 #define SCB_CFSR_BFARVALID                       ((uint32_t)0x00008000)          /*  */
4977 #define SCB_CFSR_UNDEFINSTR_OFS                  (16)                            /*!< UNDEFINSTR Offset */
4978 #define SCB_CFSR_UNDEFINSTR                      ((uint32_t)0x00010000)          /*  */
4979 #define SCB_CFSR_INVSTATE_OFS                    (17)                            /*!< INVSTATE Offset */
4980 #define SCB_CFSR_INVSTATE                        ((uint32_t)0x00020000)          /*  */
4981 #define SCB_CFSR_INVPC_OFS                       (18)                            /*!< INVPC Offset */
4982 #define SCB_CFSR_INVPC                           ((uint32_t)0x00040000)          /*  */
4983 #define SCB_CFSR_NOCP_OFS                        (19)                            /*!< NOCP Offset */
4984 #define SCB_CFSR_NOCP                            ((uint32_t)0x00080000)          /*  */
4985 #define SCB_CFSR_UNALIGNED_OFS                   (24)                            /*!< UNALIGNED Offset */
4986 #define SCB_CFSR_UNALIGNED                       ((uint32_t)0x01000000)          /*  */
4987 #define SCB_CFSR_DIVBYZERO_OFS                   (25)                            /*!< DIVBYZERO Offset */
4988 #define SCB_CFSR_DIVBYZERO                       ((uint32_t)0x02000000)          /*  */
4989 #define SCB_CFSR_MLSPERR_OFS                     ( 5)                            /*!< MLSPERR Offset */
4990 #define SCB_CFSR_MLSPERR                         ((uint32_t)0x00000020)          /*  */
4991 #define SCB_CFSR_LSPERR_OFS                      (13)                            /*!< LSPERR Offset */
4992 #define SCB_CFSR_LSPERR                          ((uint32_t)0x00002000)          /*  */
4993 #define SYSCTL_REBOOT_CTL_REBOOT_OFS             ( 0)                            /*!< REBOOT Bit Offset */
4994 #define SYSCTL_REBOOT_CTL_REBOOT                 ((uint32_t)0x00000001)          /*!< Write 1 initiates a Reboot of the device */
4995 #define SYSCTL_REBOOT_CTL_WKEY_OFS               ( 8)                            /*!< WKEY Bit Offset */
4996 #define SYSCTL_REBOOT_CTL_WKEY_MASK              ((uint32_t)0x0000FF00)          /*!< WKEY Bit Mask */
4997 #define SYSCTL_NMI_CTLSTAT_CS_SRC_OFS            ( 0)                            /*!< CS_SRC Bit Offset */
4998 #define SYSCTL_NMI_CTLSTAT_CS_SRC                ((uint32_t)0x00000001)          /*!< CS interrupt as a source of NMI */
4999 #define SYSCTL_NMI_CTLSTAT_PSS_SRC_OFS           ( 1)                            /*!< PSS_SRC Bit Offset */
5000 #define SYSCTL_NMI_CTLSTAT_PSS_SRC               ((uint32_t)0x00000002)          /*!< PSS interrupt as a source of NMI */
5001 #define SYSCTL_NMI_CTLSTAT_PCM_SRC_OFS           ( 2)                            /*!< PCM_SRC Bit Offset */
5002 #define SYSCTL_NMI_CTLSTAT_PCM_SRC               ((uint32_t)0x00000004)          /*!< PCM interrupt as a source of NMI */
5003 #define SYSCTL_NMI_CTLSTAT_PIN_SRC_OFS           ( 3)                            /*!< PIN_SRC Bit Offset */
5004 #define SYSCTL_NMI_CTLSTAT_PIN_SRC               ((uint32_t)0x00000008)
5005 #define SYSCTL_NMI_CTLSTAT_CS_FLG_OFS            (16)                            /*!< CS_FLG Bit Offset */
5006 #define SYSCTL_NMI_CTLSTAT_CS_FLG                ((uint32_t)0x00010000)          /*!< CS interrupt was the source of NMI */
5007 #define SYSCTL_NMI_CTLSTAT_PSS_FLG_OFS           (17)                            /*!< PSS_FLG Bit Offset */
5008 #define SYSCTL_NMI_CTLSTAT_PSS_FLG               ((uint32_t)0x00020000)          /*!< PSS interrupt was the source of NMI */
5009 #define SYSCTL_NMI_CTLSTAT_PCM_FLG_OFS           (18)                            /*!< PCM_FLG Bit Offset */
5010 #define SYSCTL_NMI_CTLSTAT_PCM_FLG               ((uint32_t)0x00040000)          /*!< PCM interrupt was the source of NMI */
5011 #define SYSCTL_NMI_CTLSTAT_PIN_FLG_OFS           (19)                            /*!< PIN_FLG Bit Offset */
5012 #define SYSCTL_NMI_CTLSTAT_PIN_FLG               ((uint32_t)0x00080000)          /*!< RSTn/NMI pin was the source of NMI */
5013 #define SYSCTL_WDTRESET_CTL_TIMEOUT_OFS          ( 0)                            /*!< TIMEOUT Bit Offset */
5014 #define SYSCTL_WDTRESET_CTL_TIMEOUT              ((uint32_t)0x00000001)          /*!< WDT timeout reset type */
5015 #define SYSCTL_WDTRESET_CTL_VIOLATION_OFS        ( 1)                            /*!< VIOLATION Bit Offset */
5016 #define SYSCTL_WDTRESET_CTL_VIOLATION            ((uint32_t)0x00000002)          /*!< WDT password violation reset type */
5017 #define SYSCTL_PERIHALT_CTL_HALT_T16_0_OFS       ( 0)                            /*!< HALT_T16_0 Bit Offset */
5018 #define SYSCTL_PERIHALT_CTL_HALT_T16_0           ((uint32_t)0x00000001)          /*!< Freezes IP operation when CPU is halted */
5019 #define SYSCTL_PERIHALT_CTL_HALT_T16_1_OFS       ( 1)                            /*!< HALT_T16_1 Bit Offset */
5020 #define SYSCTL_PERIHALT_CTL_HALT_T16_1           ((uint32_t)0x00000002)          /*!< Freezes IP operation when CPU is halted */
5021 #define SYSCTL_PERIHALT_CTL_HALT_T16_2_OFS       ( 2)                            /*!< HALT_T16_2 Bit Offset */
5022 #define SYSCTL_PERIHALT_CTL_HALT_T16_2           ((uint32_t)0x00000004)          /*!< Freezes IP operation when CPU is halted */
5023 #define SYSCTL_PERIHALT_CTL_HALT_T16_3_OFS       ( 3)                            /*!< HALT_T16_3 Bit Offset */
5024 #define SYSCTL_PERIHALT_CTL_HALT_T16_3           ((uint32_t)0x00000008)          /*!< Freezes IP operation when CPU is halted */
5025 #define SYSCTL_PERIHALT_CTL_HALT_T32_0_OFS       ( 4)                            /*!< HALT_T32_0 Bit Offset */
5026 #define SYSCTL_PERIHALT_CTL_HALT_T32_0           ((uint32_t)0x00000010)          /*!< Freezes IP operation when CPU is halted */
5027 #define SYSCTL_PERIHALT_CTL_HALT_EUA0_OFS        ( 5)                            /*!< HALT_eUA0 Bit Offset */
5028 #define SYSCTL_PERIHALT_CTL_HALT_EUA0            ((uint32_t)0x00000020)          /*!< Freezes IP operation when CPU is halted */
5029 #define SYSCTL_PERIHALT_CTL_HALT_EUA1_OFS        ( 6)                            /*!< HALT_eUA1 Bit Offset */
5030 #define SYSCTL_PERIHALT_CTL_HALT_EUA1            ((uint32_t)0x00000040)          /*!< Freezes IP operation when CPU is halted */
5031 #define SYSCTL_PERIHALT_CTL_HALT_EUA2_OFS        ( 7)                            /*!< HALT_eUA2 Bit Offset */
5032 #define SYSCTL_PERIHALT_CTL_HALT_EUA2            ((uint32_t)0x00000080)          /*!< Freezes IP operation when CPU is halted */
5033 #define SYSCTL_PERIHALT_CTL_HALT_EUA3_OFS        ( 8)                            /*!< HALT_eUA3 Bit Offset */
5034 #define SYSCTL_PERIHALT_CTL_HALT_EUA3            ((uint32_t)0x00000100)          /*!< Freezes IP operation when CPU is halted */
5035 #define SYSCTL_PERIHALT_CTL_HALT_EUB0_OFS        ( 9)                            /*!< HALT_eUB0 Bit Offset */
5036 #define SYSCTL_PERIHALT_CTL_HALT_EUB0            ((uint32_t)0x00000200)          /*!< Freezes IP operation when CPU is halted */
5037 #define SYSCTL_PERIHALT_CTL_HALT_EUB1_OFS        (10)                            /*!< HALT_eUB1 Bit Offset */
5038 #define SYSCTL_PERIHALT_CTL_HALT_EUB1            ((uint32_t)0x00000400)          /*!< Freezes IP operation when CPU is halted */
5039 #define SYSCTL_PERIHALT_CTL_HALT_EUB2_OFS        (11)                            /*!< HALT_eUB2 Bit Offset */
5040 #define SYSCTL_PERIHALT_CTL_HALT_EUB2            ((uint32_t)0x00000800)          /*!< Freezes IP operation when CPU is halted */
5041 #define SYSCTL_PERIHALT_CTL_HALT_EUB3_OFS        (12)                            /*!< HALT_eUB3 Bit Offset */
5042 #define SYSCTL_PERIHALT_CTL_HALT_EUB3            ((uint32_t)0x00001000)          /*!< Freezes IP operation when CPU is halted */
5043 #define SYSCTL_PERIHALT_CTL_HALT_ADC_OFS         (13)                            /*!< HALT_ADC Bit Offset */
5044 #define SYSCTL_PERIHALT_CTL_HALT_ADC             ((uint32_t)0x00002000)          /*!< Freezes IP operation when CPU is halted */
5045 #define SYSCTL_PERIHALT_CTL_HALT_WDT_OFS         (14)                            /*!< HALT_WDT Bit Offset */
5046 #define SYSCTL_PERIHALT_CTL_HALT_WDT             ((uint32_t)0x00004000)          /*!< Freezes IP operation when CPU is halted */
5047 #define SYSCTL_PERIHALT_CTL_HALT_DMA_OFS         (15)                            /*!< HALT_DMA Bit Offset */
5048 #define SYSCTL_PERIHALT_CTL_HALT_DMA             ((uint32_t)0x00008000)          /*!< Freezes IP operation when CPU is halted */
5049 #define SYSCTL_SRAM_BANKEN_BNK0_EN_OFS           ( 0)                            /*!< BNK0_EN Bit Offset */
5050 #define SYSCTL_SRAM_BANKEN_BNK0_EN               ((uint32_t)0x00000001)          /*!< SRAM Bank0 enable */
5051 #define SYSCTL_SRAM_BANKEN_BNK1_EN_OFS           ( 1)                            /*!< BNK1_EN Bit Offset */
5052 #define SYSCTL_SRAM_BANKEN_BNK1_EN               ((uint32_t)0x00000002)          /*!< SRAM Bank1 enable */
5053 #define SYSCTL_SRAM_BANKEN_BNK2_EN_OFS           ( 2)                            /*!< BNK2_EN Bit Offset */
5054 #define SYSCTL_SRAM_BANKEN_BNK2_EN               ((uint32_t)0x00000004)          /*!< SRAM Bank1 enable */
5055 #define SYSCTL_SRAM_BANKEN_BNK3_EN_OFS           ( 3)                            /*!< BNK3_EN Bit Offset */
5056 #define SYSCTL_SRAM_BANKEN_BNK3_EN               ((uint32_t)0x00000008)          /*!< SRAM Bank1 enable */
5057 #define SYSCTL_SRAM_BANKEN_BNK4_EN_OFS           ( 4)                            /*!< BNK4_EN Bit Offset */
5058 #define SYSCTL_SRAM_BANKEN_BNK4_EN               ((uint32_t)0x00000010)          /*!< SRAM Bank1 enable */
5059 #define SYSCTL_SRAM_BANKEN_BNK5_EN_OFS           ( 5)                            /*!< BNK5_EN Bit Offset */
5060 #define SYSCTL_SRAM_BANKEN_BNK5_EN               ((uint32_t)0x00000020)          /*!< SRAM Bank1 enable */
5061 #define SYSCTL_SRAM_BANKEN_BNK6_EN_OFS           ( 6)                            /*!< BNK6_EN Bit Offset */
5062 #define SYSCTL_SRAM_BANKEN_BNK6_EN               ((uint32_t)0x00000040)          /*!< SRAM Bank1 enable */
5063 #define SYSCTL_SRAM_BANKEN_BNK7_EN_OFS           ( 7)                            /*!< BNK7_EN Bit Offset */
5064 #define SYSCTL_SRAM_BANKEN_BNK7_EN               ((uint32_t)0x00000080)          /*!< SRAM Bank1 enable */
5065 #define SYSCTL_SRAM_BANKEN_SRAM_RDY_OFS          (16)                            /*!< SRAM_RDY Bit Offset */
5066 #define SYSCTL_SRAM_BANKEN_SRAM_RDY              ((uint32_t)0x00010000)          /*!< SRAM ready */
5067 #define SYSCTL_SRAM_BANKRET_BNK0_RET_OFS         ( 0)                            /*!< BNK0_RET Bit Offset */
5068 #define SYSCTL_SRAM_BANKRET_BNK0_RET             ((uint32_t)0x00000001)          /*!< Bank0 retention */
5069 #define SYSCTL_SRAM_BANKRET_BNK1_RET_OFS         ( 1)                            /*!< BNK1_RET Bit Offset */
5070 #define SYSCTL_SRAM_BANKRET_BNK1_RET             ((uint32_t)0x00000002)          /*!< Bank1 retention */
5071 #define SYSCTL_SRAM_BANKRET_BNK2_RET_OFS         ( 2)                            /*!< BNK2_RET Bit Offset */
5072 #define SYSCTL_SRAM_BANKRET_BNK2_RET             ((uint32_t)0x00000004)          /*!< Bank2 retention */
5073 #define SYSCTL_SRAM_BANKRET_BNK3_RET_OFS         ( 3)                            /*!< BNK3_RET Bit Offset */
5074 #define SYSCTL_SRAM_BANKRET_BNK3_RET             ((uint32_t)0x00000008)          /*!< Bank3 retention */
5075 #define SYSCTL_SRAM_BANKRET_BNK4_RET_OFS         ( 4)                            /*!< BNK4_RET Bit Offset */
5076 #define SYSCTL_SRAM_BANKRET_BNK4_RET             ((uint32_t)0x00000010)          /*!< Bank4 retention */
5077 #define SYSCTL_SRAM_BANKRET_BNK5_RET_OFS         ( 5)                            /*!< BNK5_RET Bit Offset */
5078 #define SYSCTL_SRAM_BANKRET_BNK5_RET             ((uint32_t)0x00000020)          /*!< Bank5 retention */
5079 #define SYSCTL_SRAM_BANKRET_BNK6_RET_OFS         ( 6)                            /*!< BNK6_RET Bit Offset */
5080 #define SYSCTL_SRAM_BANKRET_BNK6_RET             ((uint32_t)0x00000040)          /*!< Bank6 retention */
5081 #define SYSCTL_SRAM_BANKRET_BNK7_RET_OFS         ( 7)                            /*!< BNK7_RET Bit Offset */
5082 #define SYSCTL_SRAM_BANKRET_BNK7_RET             ((uint32_t)0x00000080)          /*!< Bank7 retention */
5083 #define SYSCTL_SRAM_BANKRET_SRAM_RDY_OFS         (16)                            /*!< SRAM_RDY Bit Offset */
5084 #define SYSCTL_SRAM_BANKRET_SRAM_RDY             ((uint32_t)0x00010000)          /*!< SRAM ready */
5085 #define SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN_OFS       ( 0)                            /*!< GLTCH_EN Bit Offset */
5086 #define SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN           ((uint32_t)0x00000001)          /*!< Glitch filter enable */
5087 #define SYSCTL_SECDATA_UNLOCK_UNLKEY_OFS         ( 0)                            /*!< UNLKEY Bit Offset */
5088 #define SYSCTL_SECDATA_UNLOCK_UNLKEY_MASK        ((uint32_t)0x0000FFFF)          /*!< UNLKEY Bit Mask */
5089 #define SYSCTL_MASTER_UNLOCK_UNLKEY_OFS          ( 0)                            /*!< UNLKEY Bit Offset */
5090 #define SYSCTL_MASTER_UNLOCK_UNLKEY_MASK         ((uint32_t)0x0000FFFF)          /*!< UNLKEY Bit Mask */
5091 #define SYSCTL_RESET_REQ_POR_OFS                 ( 0)                            /*!< POR Bit Offset */
5092 #define SYSCTL_RESET_REQ_POR                     ((uint32_t)0x00000001)          /*!< Generate POR */
5093 #define SYSCTL_RESET_REQ_REBOOT_OFS              ( 1)                            /*!< REBOOT Bit Offset */
5094 #define SYSCTL_RESET_REQ_REBOOT                  ((uint32_t)0x00000002)          /*!< Generate Reboot_Reset */
5095 #define SYSCTL_RESET_REQ_WKEY_OFS                ( 8)                            /*!< WKEY Bit Offset */
5096 #define SYSCTL_RESET_REQ_WKEY_MASK               ((uint32_t)0x0000FF00)          /*!< WKEY Bit Mask */
5097 #define SYSCTL_RESET_STATOVER_SOFT_OFS           ( 0)                            /*!< SOFT Bit Offset */
5098 #define SYSCTL_RESET_STATOVER_SOFT               ((uint32_t)0x00000001)          /*!< Indicates if SOFT Reset is active */
5099 #define SYSCTL_RESET_STATOVER_HARD_OFS           ( 1)                            /*!< HARD Bit Offset */
5100 #define SYSCTL_RESET_STATOVER_HARD               ((uint32_t)0x00000002)          /*!< Indicates if HARD Reset is active */
5101 #define SYSCTL_RESET_STATOVER_REBOOT_OFS         ( 2)                            /*!< REBOOT Bit Offset */
5102 #define SYSCTL_RESET_STATOVER_REBOOT             ((uint32_t)0x00000004)          /*!< Indicates if Reboot Reset is active */
5103 #define SYSCTL_RESET_STATOVER_SOFT_OVER_OFS      ( 8)                            /*!< SOFT_OVER Bit Offset */
5104 #define SYSCTL_RESET_STATOVER_SOFT_OVER          ((uint32_t)0x00000100)          /*!< SOFT_Reset overwrite request */
5105 #define SYSCTL_RESET_STATOVER_HARD_OVER_OFS      ( 9)                            /*!< HARD_OVER Bit Offset */
5106 #define SYSCTL_RESET_STATOVER_HARD_OVER          ((uint32_t)0x00000200)          /*!< HARD_Reset overwrite request */
5107 #define SYSCTL_RESET_STATOVER_RBT_OVER_OFS       (10)                            /*!< RBT_OVER Bit Offset */
5108 #define SYSCTL_RESET_STATOVER_RBT_OVER           ((uint32_t)0x00000400)          /*!< Reboot Reset overwrite request */
5109 #define SYSCTL_REBOOT_CTL_WKEY_VAL              ((uint32_t)0x00006900)          /*!< Key value to enable writes to bit 0 */
5110 #define TIMER32_CONTROL_ONESHOT_OFS              ( 0)                            /*!< ONESHOT Bit Offset */
5111 #define TIMER32_CONTROL_ONESHOT                  ((uint32_t)0x00000001)          /*!< Selects one-shot or wrapping counter mode */
5112 #define TIMER32_CONTROL_SIZE_OFS                 ( 1)                            /*!< SIZE Bit Offset */
5113 #define TIMER32_CONTROL_SIZE                     ((uint32_t)0x00000002)          /*!< Selects 16 or 32 bit counter operation */
5114 #define TIMER32_CONTROL_PRESCALE_OFS             ( 2)                            /*!< PRESCALE Bit Offset */
5115 #define TIMER32_CONTROL_PRESCALE_MASK            ((uint32_t)0x0000000C)          /*!< PRESCALE Bit Mask */
5116 #define TIMER32_CONTROL_PRESCALE0                ((uint32_t)0x00000004)          /*!< PRESCALE Bit 0 */
5117 #define TIMER32_CONTROL_PRESCALE1                ((uint32_t)0x00000008)          /*!< PRESCALE Bit 1 */
5118 #define TIMER32_CONTROL_PRESCALE_0               ((uint32_t)0x00000000)          /*!< 0 stages of prescale, clock is divided by 1 */
5119 #define TIMER32_CONTROL_PRESCALE_1               ((uint32_t)0x00000004)          /*!< 4 stages of prescale, clock is divided by 16 */
5120 #define TIMER32_CONTROL_PRESCALE_2               ((uint32_t)0x00000008)          /*!< 8 stages of prescale, clock is divided by 256 */
5121 #define TIMER32_CONTROL_IE_OFS                   ( 5)                            /*!< IE Bit Offset */
5122 #define TIMER32_CONTROL_IE                       ((uint32_t)0x00000020)          /*!< Interrupt enable bit */
5123 #define TIMER32_CONTROL_MODE_OFS                 ( 6)                            /*!< MODE Bit Offset */
5124 #define TIMER32_CONTROL_MODE                     ((uint32_t)0x00000040)          /*!< Mode bit */
5125 #define TIMER32_CONTROL_ENABLE_OFS               ( 7)                            /*!< ENABLE Bit Offset */
5126 #define TIMER32_CONTROL_ENABLE                   ((uint32_t)0x00000080)
5127 #define TIMER32_RIS_RAW_IFG_OFS                  ( 0)                            /*!< RAW_IFG Bit Offset */
5128 #define TIMER32_RIS_RAW_IFG                      ((uint32_t)0x00000001)          /*!< Raw interrupt status */
5129 #define TIMER32_MIS_IFG_OFS                      ( 0)                            /*!< IFG Bit Offset */
5130 #define TIMER32_MIS_IFG                          ((uint32_t)0x00000001)          /*!< Enabled interrupt status */
5131 #define TIMER_A_CTL_IFG_OFS                      ( 0)                            /*!< TAIFG Bit Offset */
5132 #define TIMER_A_CTL_IFG                          ((uint16_t)0x0001)              /*!< TimerA interrupt flag */
5133 #define TIMER_A_CTL_IE_OFS                       ( 1)                            /*!< TAIE Bit Offset */
5134 #define TIMER_A_CTL_IE                           ((uint16_t)0x0002)              /*!< TimerA interrupt enable */
5135 #define TIMER_A_CTL_CLR_OFS                      ( 2)                            /*!< TACLR Bit Offset */
5136 #define TIMER_A_CTL_CLR                          ((uint16_t)0x0004)              /*!< TimerA clear */
5137 #define TIMER_A_CTL_MC_OFS                       ( 4)                            /*!< MC Bit Offset */
5138 #define TIMER_A_CTL_MC_MASK                      ((uint16_t)0x0030)              /*!< MC Bit Mask */
5139 #define TIMER_A_CTL_MC0                          ((uint16_t)0x0010)              /*!< MC Bit 0 */
5140 #define TIMER_A_CTL_MC1                          ((uint16_t)0x0020)              /*!< MC Bit 1 */
5141 #define TIMER_A_CTL_MC_0                         ((uint16_t)0x0000)              /*!< Stop mode: Timer is halted */
5142 #define TIMER_A_CTL_MC_1                         ((uint16_t)0x0010)              /*!< Up mode: Timer counts up to TAxCCR0 */
5143 #define TIMER_A_CTL_MC_2                         ((uint16_t)0x0020)              /*!< Continuous mode: Timer counts up to 0FFFFh */
5144 #define TIMER_A_CTL_MC_3                         ((uint16_t)0x0030)              /*!< Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */
5145 #define TIMER_A_CTL_MC__STOP                     ((uint16_t)0x0000)              /*!< Stop mode: Timer is halted */
5146 #define TIMER_A_CTL_MC__UP                       ((uint16_t)0x0010)              /*!< Up mode: Timer counts up to TAxCCR0 */
5147 #define TIMER_A_CTL_MC__CONTINUOUS               ((uint16_t)0x0020)              /*!< Continuous mode: Timer counts up to 0FFFFh */
5148 #define TIMER_A_CTL_MC__UPDOWN                   ((uint16_t)0x0030)              /*!< Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */
5149 #define TIMER_A_CTL_ID_OFS                       ( 6)                            /*!< ID Bit Offset */
5150 #define TIMER_A_CTL_ID_MASK                      ((uint16_t)0x00C0)              /*!< ID Bit Mask */
5151 #define TIMER_A_CTL_ID0                          ((uint16_t)0x0040)              /*!< ID Bit 0 */
5152 #define TIMER_A_CTL_ID1                          ((uint16_t)0x0080)              /*!< ID Bit 1 */
5153 #define TIMER_A_CTL_ID_0                         ((uint16_t)0x0000)              /*!< /1 */
5154 #define TIMER_A_CTL_ID_1                         ((uint16_t)0x0040)              /*!< /2 */
5155 #define TIMER_A_CTL_ID_2                         ((uint16_t)0x0080)              /*!< /4 */
5156 #define TIMER_A_CTL_ID_3                         ((uint16_t)0x00C0)              /*!< /8 */
5157 #define TIMER_A_CTL_ID__1                        ((uint16_t)0x0000)              /*!< /1 */
5158 #define TIMER_A_CTL_ID__2                        ((uint16_t)0x0040)              /*!< /2 */
5159 #define TIMER_A_CTL_ID__4                        ((uint16_t)0x0080)              /*!< /4 */
5160 #define TIMER_A_CTL_ID__8                        ((uint16_t)0x00C0)              /*!< /8 */
5161 #define TIMER_A_CTL_SSEL_OFS                     ( 8)                            /*!< TASSEL Bit Offset */
5162 #define TIMER_A_CTL_SSEL_MASK                    ((uint16_t)0x0300)              /*!< TASSEL Bit Mask */
5163 #define TIMER_A_CTL_SSEL0                        ((uint16_t)0x0100)              /*!< SSEL Bit 0 */
5164 #define TIMER_A_CTL_SSEL1                        ((uint16_t)0x0200)              /*!< SSEL Bit 1 */
5165 #define TIMER_A_CTL_TASSEL_0                     ((uint16_t)0x0000)              /*!< TAxCLK */
5166 #define TIMER_A_CTL_TASSEL_1                     ((uint16_t)0x0100)              /*!< ACLK */
5167 #define TIMER_A_CTL_TASSEL_2                     ((uint16_t)0x0200)              /*!< SMCLK */
5168 #define TIMER_A_CTL_TASSEL_3                     ((uint16_t)0x0300)              /*!< INCLK */
5169 #define TIMER_A_CTL_SSEL__TACLK                  ((uint16_t)0x0000)              /*!< TAxCLK */
5170 #define TIMER_A_CTL_SSEL__ACLK                   ((uint16_t)0x0100)              /*!< ACLK */
5171 #define TIMER_A_CTL_SSEL__SMCLK                  ((uint16_t)0x0200)              /*!< SMCLK */
5172 #define TIMER_A_CTL_SSEL__INCLK                  ((uint16_t)0x0300)              /*!< INCLK */
5173 #define TIMER_A_CCTLN_CCIFG_OFS                  ( 0)                            /*!< CCIFG Bit Offset */
5174 #define TIMER_A_CCTLN_CCIFG                      ((uint16_t)0x0001)              /*!< Capture/compare interrupt flag */
5175 #define TIMER_A_CCTLN_COV_OFS                    ( 1)                            /*!< COV Bit Offset */
5176 #define TIMER_A_CCTLN_COV                        ((uint16_t)0x0002)              /*!< Capture overflow */
5177 #define TIMER_A_CCTLN_OUT_OFS                    ( 2)                            /*!< OUT Bit Offset */
5178 #define TIMER_A_CCTLN_OUT                        ((uint16_t)0x0004)              /*!< Output */
5179 #define TIMER_A_CCTLN_CCI_OFS                    ( 3)                            /*!< CCI Bit Offset */
5180 #define TIMER_A_CCTLN_CCI                        ((uint16_t)0x0008)              /*!< Capture/compare input */
5181 #define TIMER_A_CCTLN_CCIE_OFS                   ( 4)                            /*!< CCIE Bit Offset */
5182 #define TIMER_A_CCTLN_CCIE                       ((uint16_t)0x0010)              /*!< Capture/compare interrupt enable */
5183 #define TIMER_A_CCTLN_OUTMOD_OFS                 ( 5)                            /*!< OUTMOD Bit Offset */
5184 #define TIMER_A_CCTLN_OUTMOD_MASK                ((uint16_t)0x00E0)              /*!< OUTMOD Bit Mask */
5185 #define TIMER_A_CCTLN_OUTMOD0                    ((uint16_t)0x0020)              /*!< OUTMOD Bit 0 */
5186 #define TIMER_A_CCTLN_OUTMOD1                    ((uint16_t)0x0040)              /*!< OUTMOD Bit 1 */
5187 #define TIMER_A_CCTLN_OUTMOD2                    ((uint16_t)0x0080)              /*!< OUTMOD Bit 2 */
5188 #define TIMER_A_CCTLN_OUTMOD_0                   ((uint16_t)0x0000)              /*!< OUT bit value */
5189 #define TIMER_A_CCTLN_OUTMOD_1                   ((uint16_t)0x0020)              /*!< Set */
5190 #define TIMER_A_CCTLN_OUTMOD_2                   ((uint16_t)0x0040)              /*!< Toggle/reset */
5191 #define TIMER_A_CCTLN_OUTMOD_3                   ((uint16_t)0x0060)              /*!< Set/reset */
5192 #define TIMER_A_CCTLN_OUTMOD_4                   ((uint16_t)0x0080)              /*!< Toggle */
5193 #define TIMER_A_CCTLN_OUTMOD_5                   ((uint16_t)0x00A0)              /*!< Reset */
5194 #define TIMER_A_CCTLN_OUTMOD_6                   ((uint16_t)0x00C0)              /*!< Toggle/set */
5195 #define TIMER_A_CCTLN_OUTMOD_7                   ((uint16_t)0x00E0)              /*!< Reset/set */
5196 #define TIMER_A_CCTLN_CAP_OFS                    ( 8)                            /*!< CAP Bit Offset */
5197 #define TIMER_A_CCTLN_CAP                        ((uint16_t)0x0100)              /*!< Capture mode */
5198 #define TIMER_A_CCTLN_SCCI_OFS                   (10)                            /*!< SCCI Bit Offset */
5199 #define TIMER_A_CCTLN_SCCI                       ((uint16_t)0x0400)              /*!< Synchronized capture/compare input */
5200 #define TIMER_A_CCTLN_SCS_OFS                    (11)                            /*!< SCS Bit Offset */
5201 #define TIMER_A_CCTLN_SCS                        ((uint16_t)0x0800)              /*!< Synchronize capture source */
5202 #define TIMER_A_CCTLN_CCIS_OFS                   (12)                            /*!< CCIS Bit Offset */
5203 #define TIMER_A_CCTLN_CCIS_MASK                  ((uint16_t)0x3000)              /*!< CCIS Bit Mask */
5204 #define TIMER_A_CCTLN_CCIS0                      ((uint16_t)0x1000)              /*!< CCIS Bit 0 */
5205 #define TIMER_A_CCTLN_CCIS1                      ((uint16_t)0x2000)              /*!< CCIS Bit 1 */
5206 #define TIMER_A_CCTLN_CCIS_0                     ((uint16_t)0x0000)              /*!< CCIxA */
5207 #define TIMER_A_CCTLN_CCIS_1                     ((uint16_t)0x1000)              /*!< CCIxB */
5208 #define TIMER_A_CCTLN_CCIS_2                     ((uint16_t)0x2000)              /*!< GND */
5209 #define TIMER_A_CCTLN_CCIS_3                     ((uint16_t)0x3000)              /*!< VCC */
5210 #define TIMER_A_CCTLN_CCIS__CCIA                 ((uint16_t)0x0000)              /*!< CCIxA */
5211 #define TIMER_A_CCTLN_CCIS__CCIB                 ((uint16_t)0x1000)              /*!< CCIxB */
5212 #define TIMER_A_CCTLN_CCIS__GND                  ((uint16_t)0x2000)              /*!< GND */
5213 #define TIMER_A_CCTLN_CCIS__VCC                  ((uint16_t)0x3000)              /*!< VCC */
5214 #define TIMER_A_CCTLN_CM_OFS                     (14)                            /*!< CM Bit Offset */
5215 #define TIMER_A_CCTLN_CM_MASK                    ((uint16_t)0xC000)              /*!< CM Bit Mask */
5216 #define TIMER_A_CCTLN_CM0                        ((uint16_t)0x4000)              /*!< CM Bit 0 */
5217 #define TIMER_A_CCTLN_CM1                        ((uint16_t)0x8000)              /*!< CM Bit 1 */
5218 #define TIMER_A_CCTLN_CM_0                       ((uint16_t)0x0000)              /*!< No capture */
5219 #define TIMER_A_CCTLN_CM_1                       ((uint16_t)0x4000)              /*!< Capture on rising edge */
5220 #define TIMER_A_CCTLN_CM_2                       ((uint16_t)0x8000)              /*!< Capture on falling edge */
5221 #define TIMER_A_CCTLN_CM_3                       ((uint16_t)0xC000)              /*!< Capture on both rising and falling edges */
5222 #define TIMER_A_CCTLN_CM__NONE                   ((uint16_t)0x0000)              /*!< No capture */
5223 #define TIMER_A_CCTLN_CM__RISING                 ((uint16_t)0x4000)              /*!< Capture on rising edge */
5224 #define TIMER_A_CCTLN_CM__FALLING                ((uint16_t)0x8000)              /*!< Capture on falling edge */
5225 #define TIMER_A_CCTLN_CM__BOTH                   ((uint16_t)0xC000)              /*!< Capture on both rising and falling edges */
5226 #define TIMER_A_EX0_IDEX_OFS                     ( 0)                            /*!< TAIDEX Bit Offset */
5227 #define TIMER_A_EX0_IDEX_MASK                    ((uint16_t)0x0007)              /*!< TAIDEX Bit Mask */
5228 #define TIMER_A_EX0_IDEX0                        ((uint16_t)0x0001)              /*!< IDEX Bit 0 */
5229 #define TIMER_A_EX0_IDEX1                        ((uint16_t)0x0002)              /*!< IDEX Bit 1 */
5230 #define TIMER_A_EX0_IDEX2                        ((uint16_t)0x0004)              /*!< IDEX Bit 2 */
5231 #define TIMER_A_EX0_TAIDEX_0                     ((uint16_t)0x0000)              /*!< Divide by 1 */
5232 #define TIMER_A_EX0_TAIDEX_1                     ((uint16_t)0x0001)              /*!< Divide by 2 */
5233 #define TIMER_A_EX0_TAIDEX_2                     ((uint16_t)0x0002)              /*!< Divide by 3 */
5234 #define TIMER_A_EX0_TAIDEX_3                     ((uint16_t)0x0003)              /*!< Divide by 4 */
5235 #define TIMER_A_EX0_TAIDEX_4                     ((uint16_t)0x0004)              /*!< Divide by 5 */
5236 #define TIMER_A_EX0_TAIDEX_5                     ((uint16_t)0x0005)              /*!< Divide by 6 */
5237 #define TIMER_A_EX0_TAIDEX_6                     ((uint16_t)0x0006)              /*!< Divide by 7 */
5238 #define TIMER_A_EX0_TAIDEX_7                     ((uint16_t)0x0007)              /*!< Divide by 8 */
5239 #define TIMER_A_EX0_IDEX__1                      ((uint16_t)0x0000)              /*!< Divide by 1 */
5240 #define TIMER_A_EX0_IDEX__2                      ((uint16_t)0x0001)              /*!< Divide by 2 */
5241 #define TIMER_A_EX0_IDEX__3                      ((uint16_t)0x0002)              /*!< Divide by 3 */
5242 #define TIMER_A_EX0_IDEX__4                      ((uint16_t)0x0003)              /*!< Divide by 4 */
5243 #define TIMER_A_EX0_IDEX__5                      ((uint16_t)0x0004)              /*!< Divide by 5 */
5244 #define TIMER_A_EX0_IDEX__6                      ((uint16_t)0x0005)              /*!< Divide by 6 */
5245 #define TIMER_A_EX0_IDEX__7                      ((uint16_t)0x0006)              /*!< Divide by 7 */
5246 #define TIMER_A_EX0_IDEX__8                      ((uint16_t)0x0007)              /*!< Divide by 8 */
5247 #define TLV_TAG_RESERVED1                                   1
5248 #define TLV_TAG_RESERVED2                                   2
5249 #define TLV_TAG_CS                                          3
5250 #define TLV_TAG_FLASHCTL                                    4
5251 #define TLV_TAG_ADC14                                       5
5252 #define TLV_TAG_RESERVED6                                   6
5253 #define TLV_TAG_RESERVED7                                   7
5254 #define TLV_TAG_REF                                         8
5255 #define TLV_TAG_RESERVED9                                   9
5256 #define TLV_TAG_RESERVED10                                 10
5257 #define TLV_TAG_DEVINFO                                    11
5258 #define TLV_TAG_DIEREC                                     12
5259 #define TLV_TAG_RANDNUM                                    13
5260 #define TLV_TAG_RESERVED14                                 14
5261 #define TLV_TAG_BSL                                        15
5262 #define TLV_TAG_END                                        (0x0BD0E11D)
5263 #define WDT_A_CTL_IS_OFS                         ( 0)                            /*!< WDTIS Bit Offset */
5264 #define WDT_A_CTL_IS_MASK                        ((uint16_t)0x0007)              /*!< WDTIS Bit Mask */
5265 #define WDT_A_CTL_IS0                            ((uint16_t)0x0001)              /*!< IS Bit 0 */
5266 #define WDT_A_CTL_IS1                            ((uint16_t)0x0002)              /*!< IS Bit 1 */
5267 #define WDT_A_CTL_IS2                            ((uint16_t)0x0004)              /*!< IS Bit 2 */
5268 #define WDT_A_CTL_IS_0                           ((uint16_t)0x0000)              /*!< Watchdog clock source / (2^(31)) (18:12:16 at 32.768 kHz) */
5269 #define WDT_A_CTL_IS_1                           ((uint16_t)0x0001)              /*!< Watchdog clock source /(2^(27)) (01:08:16 at 32.768 kHz) */
5270 #define WDT_A_CTL_IS_2                           ((uint16_t)0x0002)              /*!< Watchdog clock source /(2^(23)) (00:04:16 at 32.768 kHz) */
5271 #define WDT_A_CTL_IS_3                           ((uint16_t)0x0003)              /*!< Watchdog clock source /(2^(19)) (00:00:16 at 32.768 kHz) */
5272 #define WDT_A_CTL_IS_4                           ((uint16_t)0x0004)              /*!< Watchdog clock source /(2^(15)) (1 s at 32.768 kHz) */
5273 #define WDT_A_CTL_IS_5                           ((uint16_t)0x0005)              /*!< Watchdog clock source / (2^(13)) (250 ms at 32.768 kHz) */
5274 #define WDT_A_CTL_IS_6                           ((uint16_t)0x0006)              /*!< Watchdog clock source / (2^(9)) (15.625 ms at 32.768 kHz) */
5275 #define WDT_A_CTL_IS_7                           ((uint16_t)0x0007)              /*!< Watchdog clock source / (2^(6)) (1.95 ms at 32.768 kHz) */
5276 #define WDT_A_CTL_CNTCL_OFS                      ( 3)                            /*!< WDTCNTCL Bit Offset */
5277 #define WDT_A_CTL_CNTCL                          ((uint16_t)0x0008)              /*!< Watchdog timer counter clear */
5278 #define WDT_A_CTL_TMSEL_OFS                      ( 4)                            /*!< WDTTMSEL Bit Offset */
5279 #define WDT_A_CTL_TMSEL                          ((uint16_t)0x0010)              /*!< Watchdog timer mode select */
5280 #define WDT_A_CTL_SSEL_OFS                       ( 5)                            /*!< WDTSSEL Bit Offset */
5281 #define WDT_A_CTL_SSEL_MASK                      ((uint16_t)0x0060)              /*!< WDTSSEL Bit Mask */
5282 #define WDT_A_CTL_SSEL0                          ((uint16_t)0x0020)              /*!< SSEL Bit 0 */
5283 #define WDT_A_CTL_SSEL1                          ((uint16_t)0x0040)              /*!< SSEL Bit 1 */
5284 #define WDT_A_CTL_SSEL_0                         ((uint16_t)0x0000)              /*!< SMCLK */
5285 #define WDT_A_CTL_SSEL_1                         ((uint16_t)0x0020)              /*!< ACLK */
5286 #define WDT_A_CTL_SSEL_2                         ((uint16_t)0x0040)              /*!< VLOCLK */
5287 #define WDT_A_CTL_SSEL_3                         ((uint16_t)0x0060)              /*!< BCLK */
5288 #define WDT_A_CTL_SSEL__SMCLK                    ((uint16_t)0x0000)              /*!< SMCLK */
5289 #define WDT_A_CTL_SSEL__ACLK                     ((uint16_t)0x0020)              /*!< ACLK */
5290 #define WDT_A_CTL_SSEL__VLOCLK                   ((uint16_t)0x0040)              /*!< VLOCLK */
5291 #define WDT_A_CTL_SSEL__BCLK                     ((uint16_t)0x0060)              /*!< BCLK */
5292 #define WDT_A_CTL_HOLD_OFS                       ( 7)                            /*!< WDTHOLD Bit Offset */
5293 #define WDT_A_CTL_HOLD                           ((uint16_t)0x0080)              /*!< Watchdog timer hold */
5294 #define WDT_A_CTL_PW_OFS                         ( 8)                            /*!< WDTPW Bit Offset */
5295 #define WDT_A_CTL_PW_MASK                        ((uint16_t)0xFF00)              /*!< WDTPW Bit Mask */
5296 #define WDT_A_CTL_PW                              ((uint16_t)0x5A00)              /*!< WDT Key Value for WDT write access */
5297 #define FLCTL_A_POWER_STAT_PSTAT_OFS             ( 0)                            /*!< PSTAT Bit Offset */
5298 #define FLCTL_A_POWER_STAT_PSTAT_MASK            ((uint32_t)0x00000007)          /*!< PSTAT Bit Mask */
5299 #define FLCTL_A_POWER_STAT_PSTAT0                ((uint32_t)0x00000001)          /*!< PSTAT Bit 0 */
5300 #define FLCTL_A_POWER_STAT_PSTAT1                ((uint32_t)0x00000002)          /*!< PSTAT Bit 1 */
5301 #define FLCTL_A_POWER_STAT_PSTAT2                ((uint32_t)0x00000004)          /*!< PSTAT Bit 2 */
5302 #define FLCTL_A_POWER_STAT_PSTAT_0               ((uint32_t)0x00000000)          /*!< Flash IP in power-down mode */
5303 #define FLCTL_A_POWER_STAT_PSTAT_1               ((uint32_t)0x00000001)          /*!< Flash IP Vdd domain power-up in progress */
5304 #define FLCTL_A_POWER_STAT_PSTAT_2               ((uint32_t)0x00000002)          /*!< PSS LDO_GOOD, IREF_OK and VREF_OK check in progress */
5305 #define FLCTL_A_POWER_STAT_PSTAT_3               ((uint32_t)0x00000003)          /*!< Flash IP SAFE_LV check in progress */
5306 #define FLCTL_A_POWER_STAT_PSTAT_4               ((uint32_t)0x00000004)          /*!< Flash IP Active */
5307 #define FLCTL_A_POWER_STAT_PSTAT_5               ((uint32_t)0x00000005)          /*!< Flash IP Active in Low-Frequency Active and Low-Frequency LPM0 modes. */
5308 #define FLCTL_A_POWER_STAT_PSTAT_6               ((uint32_t)0x00000006)          /*!< Flash IP in Standby mode */
5309 #define FLCTL_A_POWER_STAT_PSTAT_7               ((uint32_t)0x00000007)          /*!< Flash IP in Current mirror boost state */
5310 #define FLCTL_A_POWER_STAT_LDOSTAT_OFS           ( 3)                            /*!< LDOSTAT Bit Offset */
5311 #define FLCTL_A_POWER_STAT_LDOSTAT               ((uint32_t)0x00000008)          /*!< PSS FLDO GOOD status */
5312 #define FLCTL_A_POWER_STAT_VREFSTAT_OFS          ( 4)                            /*!< VREFSTAT Bit Offset */
5313 #define FLCTL_A_POWER_STAT_VREFSTAT              ((uint32_t)0x00000010)          /*!< PSS VREF stable status */
5314 #define FLCTL_A_POWER_STAT_IREFSTAT_OFS          ( 5)                            /*!< IREFSTAT Bit Offset */
5315 #define FLCTL_A_POWER_STAT_IREFSTAT              ((uint32_t)0x00000020)          /*!< PSS IREF stable status */
5316 #define FLCTL_A_POWER_STAT_TRIMSTAT_OFS          ( 6)                            /*!< TRIMSTAT Bit Offset */
5317 #define FLCTL_A_POWER_STAT_TRIMSTAT              ((uint32_t)0x00000040)          /*!< PSS trim done status */
5318 #define FLCTL_A_POWER_STAT_RD_2T_OFS             ( 7)                            /*!< RD_2T Bit Offset */
5319 #define FLCTL_A_POWER_STAT_RD_2T                 ((uint32_t)0x00000080)          /*!< Indicates if Flash is being accessed in 2T mode */
5320 #define FLCTL_A_BANK0_RDCTL_RD_MODE_OFS          ( 0)                            /*!< RD_MODE Bit Offset */
5321 #define FLCTL_A_BANK0_RDCTL_RD_MODE_MASK         ((uint32_t)0x0000000F)          /*!< RD_MODE Bit Mask */
5322 #define FLCTL_A_BANK0_RDCTL_RD_MODE0             ((uint32_t)0x00000001)          /*!< RD_MODE Bit 0 */
5323 #define FLCTL_A_BANK0_RDCTL_RD_MODE1             ((uint32_t)0x00000002)          /*!< RD_MODE Bit 1 */
5324 #define FLCTL_A_BANK0_RDCTL_RD_MODE2             ((uint32_t)0x00000004)          /*!< RD_MODE Bit 2 */
5325 #define FLCTL_A_BANK0_RDCTL_RD_MODE3             ((uint32_t)0x00000008)          /*!< RD_MODE Bit 3 */
5326 #define FLCTL_A_BANK0_RDCTL_RD_MODE_0            ((uint32_t)0x00000000)          /*!< Normal read mode */
5327 #define FLCTL_A_BANK0_RDCTL_RD_MODE_1            ((uint32_t)0x00000001)          /*!< Read Margin 0 */
5328 #define FLCTL_A_BANK0_RDCTL_RD_MODE_2            ((uint32_t)0x00000002)          /*!< Read Margin 1 */
5329 #define FLCTL_A_BANK0_RDCTL_RD_MODE_3            ((uint32_t)0x00000003)          /*!< Program Verify */
5330 #define FLCTL_A_BANK0_RDCTL_RD_MODE_4            ((uint32_t)0x00000004)          /*!< Erase Verify */
5331 #define FLCTL_A_BANK0_RDCTL_RD_MODE_5            ((uint32_t)0x00000005)          /*!< Leakage Verify */
5332 #define FLCTL_A_BANK0_RDCTL_RD_MODE_9            ((uint32_t)0x00000009)          /*!< Read Margin 0B */
5333 #define FLCTL_A_BANK0_RDCTL_RD_MODE_10           ((uint32_t)0x0000000A)          /*!< Read Margin 1B */
5334 #define FLCTL_A_BANK0_RDCTL_BUFI_OFS             ( 4)                            /*!< BUFI Bit Offset */
5335 #define FLCTL_A_BANK0_RDCTL_BUFI                 ((uint32_t)0x00000010)          /*!< Enables read buffering feature for instruction fetches to this Bank */
5336 #define FLCTL_A_BANK0_RDCTL_BUFD_OFS             ( 5)                            /*!< BUFD Bit Offset */
5337 #define FLCTL_A_BANK0_RDCTL_BUFD                 ((uint32_t)0x00000020)          /*!< Enables read buffering feature for data reads to this Bank */
5338 #define FLCTL_A_BANK0_RDCTL_WAIT_OFS             (12)                            /*!< WAIT Bit Offset */
5339 #define FLCTL_A_BANK0_RDCTL_WAIT_MASK            ((uint32_t)0x0000F000)          /*!< WAIT Bit Mask */
5340 #define FLCTL_A_BANK0_RDCTL_WAIT0                ((uint32_t)0x00001000)          /*!< WAIT Bit 0 */
5341 #define FLCTL_A_BANK0_RDCTL_WAIT1                ((uint32_t)0x00002000)          /*!< WAIT Bit 1 */
5342 #define FLCTL_A_BANK0_RDCTL_WAIT2                ((uint32_t)0x00004000)          /*!< WAIT Bit 2 */
5343 #define FLCTL_A_BANK0_RDCTL_WAIT3                ((uint32_t)0x00008000)          /*!< WAIT Bit 3 */
5344 #define FLCTL_A_BANK0_RDCTL_WAIT_0               ((uint32_t)0x00000000)          /*!< 0 wait states */
5345 #define FLCTL_A_BANK0_RDCTL_WAIT_1               ((uint32_t)0x00001000)          /*!< 1 wait states */
5346 #define FLCTL_A_BANK0_RDCTL_WAIT_2               ((uint32_t)0x00002000)          /*!< 2 wait states */
5347 #define FLCTL_A_BANK0_RDCTL_WAIT_3               ((uint32_t)0x00003000)          /*!< 3 wait states */
5348 #define FLCTL_A_BANK0_RDCTL_WAIT_4               ((uint32_t)0x00004000)          /*!< 4 wait states */
5349 #define FLCTL_A_BANK0_RDCTL_WAIT_5               ((uint32_t)0x00005000)          /*!< 5 wait states */
5350 #define FLCTL_A_BANK0_RDCTL_WAIT_6               ((uint32_t)0x00006000)          /*!< 6 wait states */
5351 #define FLCTL_A_BANK0_RDCTL_WAIT_7               ((uint32_t)0x00007000)          /*!< 7 wait states */
5352 #define FLCTL_A_BANK0_RDCTL_WAIT_8               ((uint32_t)0x00008000)          /*!< 8 wait states */
5353 #define FLCTL_A_BANK0_RDCTL_WAIT_9               ((uint32_t)0x00009000)          /*!< 9 wait states */
5354 #define FLCTL_A_BANK0_RDCTL_WAIT_10              ((uint32_t)0x0000A000)          /*!< 10 wait states */
5355 #define FLCTL_A_BANK0_RDCTL_WAIT_11              ((uint32_t)0x0000B000)          /*!< 11 wait states */
5356 #define FLCTL_A_BANK0_RDCTL_WAIT_12              ((uint32_t)0x0000C000)          /*!< 12 wait states */
5357 #define FLCTL_A_BANK0_RDCTL_WAIT_13              ((uint32_t)0x0000D000)          /*!< 13 wait states */
5358 #define FLCTL_A_BANK0_RDCTL_WAIT_14              ((uint32_t)0x0000E000)          /*!< 14 wait states */
5359 #define FLCTL_A_BANK0_RDCTL_WAIT_15              ((uint32_t)0x0000F000)          /*!< 15 wait states */
5360 #define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_OFS   (16)                            /*!< RD_MODE_STATUS Bit Offset */
5361 #define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_MASK  ((uint32_t)0x000F0000)          /*!< RD_MODE_STATUS Bit Mask */
5362 #define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS0      ((uint32_t)0x00010000)          /*!< RD_MODE_STATUS Bit 0 */
5363 #define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS1      ((uint32_t)0x00020000)          /*!< RD_MODE_STATUS Bit 1 */
5364 #define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS2      ((uint32_t)0x00040000)          /*!< RD_MODE_STATUS Bit 2 */
5365 #define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS3      ((uint32_t)0x00080000)          /*!< RD_MODE_STATUS Bit 3 */
5366 #define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_0     ((uint32_t)0x00000000)          /*!< Normal read mode */
5367 #define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_1     ((uint32_t)0x00010000)          /*!< Read Margin 0 */
5368 #define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_2     ((uint32_t)0x00020000)          /*!< Read Margin 1 */
5369 #define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_3     ((uint32_t)0x00030000)          /*!< Program Verify */
5370 #define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_4     ((uint32_t)0x00040000)          /*!< Erase Verify */
5371 #define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_5     ((uint32_t)0x00050000)          /*!< Leakage Verify */
5372 #define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_9     ((uint32_t)0x00090000)          /*!< Read Margin 0B */
5373 #define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_10    ((uint32_t)0x000A0000)          /*!< Read Margin 1B */
5374 #define FLCTL_A_BANK1_RDCTL_RD_MODE_OFS          ( 0)                            /*!< RD_MODE Bit Offset */
5375 #define FLCTL_A_BANK1_RDCTL_RD_MODE_MASK         ((uint32_t)0x0000000F)          /*!< RD_MODE Bit Mask */
5376 #define FLCTL_A_BANK1_RDCTL_RD_MODE0             ((uint32_t)0x00000001)          /*!< RD_MODE Bit 0 */
5377 #define FLCTL_A_BANK1_RDCTL_RD_MODE1             ((uint32_t)0x00000002)          /*!< RD_MODE Bit 1 */
5378 #define FLCTL_A_BANK1_RDCTL_RD_MODE2             ((uint32_t)0x00000004)          /*!< RD_MODE Bit 2 */
5379 #define FLCTL_A_BANK1_RDCTL_RD_MODE3             ((uint32_t)0x00000008)          /*!< RD_MODE Bit 3 */
5380 #define FLCTL_A_BANK1_RDCTL_RD_MODE_0            ((uint32_t)0x00000000)          /*!< Normal read mode */
5381 #define FLCTL_A_BANK1_RDCTL_RD_MODE_1            ((uint32_t)0x00000001)          /*!< Read Margin 0 */
5382 #define FLCTL_A_BANK1_RDCTL_RD_MODE_2            ((uint32_t)0x00000002)          /*!< Read Margin 1 */
5383 #define FLCTL_A_BANK1_RDCTL_RD_MODE_3            ((uint32_t)0x00000003)          /*!< Program Verify */
5384 #define FLCTL_A_BANK1_RDCTL_RD_MODE_4            ((uint32_t)0x00000004)          /*!< Erase Verify */
5385 #define FLCTL_A_BANK1_RDCTL_RD_MODE_5            ((uint32_t)0x00000005)          /*!< Leakage Verify */
5386 #define FLCTL_A_BANK1_RDCTL_RD_MODE_9            ((uint32_t)0x00000009)          /*!< Read Margin 0B */
5387 #define FLCTL_A_BANK1_RDCTL_RD_MODE_10           ((uint32_t)0x0000000A)          /*!< Read Margin 1B */
5388 #define FLCTL_A_BANK1_RDCTL_BUFI_OFS             ( 4)                            /*!< BUFI Bit Offset */
5389 #define FLCTL_A_BANK1_RDCTL_BUFI                 ((uint32_t)0x00000010)          /*!< Enables read buffering feature for instruction fetches to this Bank */
5390 #define FLCTL_A_BANK1_RDCTL_BUFD_OFS             ( 5)                            /*!< BUFD Bit Offset */
5391 #define FLCTL_A_BANK1_RDCTL_BUFD                 ((uint32_t)0x00000020)          /*!< Enables read buffering feature for data reads to this Bank */
5392 #define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_OFS   (16)                            /*!< RD_MODE_STATUS Bit Offset */
5393 #define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_MASK  ((uint32_t)0x000F0000)          /*!< RD_MODE_STATUS Bit Mask */
5394 #define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS0      ((uint32_t)0x00010000)          /*!< RD_MODE_STATUS Bit 0 */
5395 #define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS1      ((uint32_t)0x00020000)          /*!< RD_MODE_STATUS Bit 1 */
5396 #define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS2      ((uint32_t)0x00040000)          /*!< RD_MODE_STATUS Bit 2 */
5397 #define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS3      ((uint32_t)0x00080000)          /*!< RD_MODE_STATUS Bit 3 */
5398 #define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_0     ((uint32_t)0x00000000)          /*!< Normal read mode */
5399 #define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_1     ((uint32_t)0x00010000)          /*!< Read Margin 0 */
5400 #define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_2     ((uint32_t)0x00020000)          /*!< Read Margin 1 */
5401 #define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_3     ((uint32_t)0x00030000)          /*!< Program Verify */
5402 #define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_4     ((uint32_t)0x00040000)          /*!< Erase Verify */
5403 #define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_5     ((uint32_t)0x00050000)          /*!< Leakage Verify */
5404 #define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_9     ((uint32_t)0x00090000)          /*!< Read Margin 0B */
5405 #define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_10    ((uint32_t)0x000A0000)          /*!< Read Margin 1B */
5406 #define FLCTL_A_BANK1_RDCTL_WAIT_OFS             (12)                            /*!< WAIT Bit Offset */
5407 #define FLCTL_A_BANK1_RDCTL_WAIT_MASK            ((uint32_t)0x0000F000)          /*!< WAIT Bit Mask */
5408 #define FLCTL_A_BANK1_RDCTL_WAIT0                ((uint32_t)0x00001000)          /*!< WAIT Bit 0 */
5409 #define FLCTL_A_BANK1_RDCTL_WAIT1                ((uint32_t)0x00002000)          /*!< WAIT Bit 1 */
5410 #define FLCTL_A_BANK1_RDCTL_WAIT2                ((uint32_t)0x00004000)          /*!< WAIT Bit 2 */
5411 #define FLCTL_A_BANK1_RDCTL_WAIT3                ((uint32_t)0x00008000)          /*!< WAIT Bit 3 */
5412 #define FLCTL_A_BANK1_RDCTL_WAIT_0               ((uint32_t)0x00000000)          /*!< 0 wait states */
5413 #define FLCTL_A_BANK1_RDCTL_WAIT_1               ((uint32_t)0x00001000)          /*!< 1 wait states */
5414 #define FLCTL_A_BANK1_RDCTL_WAIT_2               ((uint32_t)0x00002000)          /*!< 2 wait states */
5415 #define FLCTL_A_BANK1_RDCTL_WAIT_3               ((uint32_t)0x00003000)          /*!< 3 wait states */
5416 #define FLCTL_A_BANK1_RDCTL_WAIT_4               ((uint32_t)0x00004000)          /*!< 4 wait states */
5417 #define FLCTL_A_BANK1_RDCTL_WAIT_5               ((uint32_t)0x00005000)          /*!< 5 wait states */
5418 #define FLCTL_A_BANK1_RDCTL_WAIT_6               ((uint32_t)0x00006000)          /*!< 6 wait states */
5419 #define FLCTL_A_BANK1_RDCTL_WAIT_7               ((uint32_t)0x00007000)          /*!< 7 wait states */
5420 #define FLCTL_A_BANK1_RDCTL_WAIT_8               ((uint32_t)0x00008000)          /*!< 8 wait states */
5421 #define FLCTL_A_BANK1_RDCTL_WAIT_9               ((uint32_t)0x00009000)          /*!< 9 wait states */
5422 #define FLCTL_A_BANK1_RDCTL_WAIT_10              ((uint32_t)0x0000A000)          /*!< 10 wait states */
5423 #define FLCTL_A_BANK1_RDCTL_WAIT_11              ((uint32_t)0x0000B000)          /*!< 11 wait states */
5424 #define FLCTL_A_BANK1_RDCTL_WAIT_12              ((uint32_t)0x0000C000)          /*!< 12 wait states */
5425 #define FLCTL_A_BANK1_RDCTL_WAIT_13              ((uint32_t)0x0000D000)          /*!< 13 wait states */
5426 #define FLCTL_A_BANK1_RDCTL_WAIT_14              ((uint32_t)0x0000E000)          /*!< 14 wait states */
5427 #define FLCTL_A_BANK1_RDCTL_WAIT_15              ((uint32_t)0x0000F000)          /*!< 15 wait states */
5428 #define FLCTL_A_RDBRST_CTLSTAT_START_OFS         ( 0)                            /*!< START Bit Offset */
5429 #define FLCTL_A_RDBRST_CTLSTAT_START             ((uint32_t)0x00000001)          /*!< Start of burst/compare operation */
5430 #define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE_OFS      ( 1)                            /*!< MEM_TYPE Bit Offset */
5431 #define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE_MASK     ((uint32_t)0x00000006)          /*!< MEM_TYPE Bit Mask */
5432 #define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE0         ((uint32_t)0x00000002)          /*!< MEM_TYPE Bit 0 */
5433 #define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE1         ((uint32_t)0x00000004)          /*!< MEM_TYPE Bit 1 */
5434 #define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE_0        ((uint32_t)0x00000000)          /*!< Main Memory */
5435 #define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE_1        ((uint32_t)0x00000002)          /*!< Information Memory */
5436 #define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE_2        ((uint32_t)0x00000004)          /*!< Reserved */
5437 #define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE_3        ((uint32_t)0x00000006)          /*!< Engineering Memory */
5438 #define FLCTL_A_RDBRST_CTLSTAT_STOP_FAIL_OFS     ( 3)                            /*!< STOP_FAIL Bit Offset */
5439 #define FLCTL_A_RDBRST_CTLSTAT_STOP_FAIL         ((uint32_t)0x00000008)          /*!< Terminate burst/compare operation */
5440 #define FLCTL_A_RDBRST_CTLSTAT_DATA_CMP_OFS      ( 4)                            /*!< DATA_CMP Bit Offset */
5441 #define FLCTL_A_RDBRST_CTLSTAT_DATA_CMP          ((uint32_t)0x00000010)          /*!< Data pattern used for comparison against memory read data */
5442 #define FLCTL_A_RDBRST_CTLSTAT_TEST_EN_OFS       ( 6)                            /*!< TEST_EN Bit Offset */
5443 #define FLCTL_A_RDBRST_CTLSTAT_TEST_EN           ((uint32_t)0x00000040)          /*!< Enable comparison against test data compare registers */
5444 #define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT_OFS     (16)                            /*!< BRST_STAT Bit Offset */
5445 #define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT_MASK    ((uint32_t)0x00030000)          /*!< BRST_STAT Bit Mask */
5446 #define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT0        ((uint32_t)0x00010000)          /*!< BRST_STAT Bit 0 */
5447 #define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT1        ((uint32_t)0x00020000)          /*!< BRST_STAT Bit 1 */
5448 #define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT_0       ((uint32_t)0x00000000)          /*!< Idle */
5449 #define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT_1       ((uint32_t)0x00010000)          /*!< Burst/Compare START bit written, but operation pending */
5450 #define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT_2       ((uint32_t)0x00020000)          /*!< Burst/Compare in progress */
5451 #define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT_3       ((uint32_t)0x00030000)          /*!< Burst complete (status of completed burst remains in this state unless  */
5452 #define FLCTL_A_RDBRST_CTLSTAT_CMP_ERR_OFS       (18)                            /*!< CMP_ERR Bit Offset */
5453 #define FLCTL_A_RDBRST_CTLSTAT_CMP_ERR           ((uint32_t)0x00040000)          /*!< Burst/Compare Operation encountered atleast one data */
5454 #define FLCTL_A_RDBRST_CTLSTAT_ADDR_ERR_OFS      (19)                            /*!< ADDR_ERR Bit Offset */
5455 #define FLCTL_A_RDBRST_CTLSTAT_ADDR_ERR          ((uint32_t)0x00080000)          /*!< Burst/Compare Operation was terminated due to access to */
5456 #define FLCTL_A_RDBRST_CTLSTAT_CLR_STAT_OFS      (23)                            /*!< CLR_STAT Bit Offset */
5457 #define FLCTL_A_RDBRST_CTLSTAT_CLR_STAT          ((uint32_t)0x00800000)          /*!< Clear status bits 19-16 of this register */
5458 #define FLCTL_A_RDBRST_STARTADDR_START_ADDRESS_OFS ( 0)                            /*!< START_ADDRESS Bit Offset */
5459 #define FLCTL_A_RDBRST_STARTADDR_START_ADDRESS_MASK ((uint32_t)0x001FFFFF)          /*!< START_ADDRESS Bit Mask */
5460 #define FLCTL_A_RDBRST_LEN_BURST_LENGTH_OFS      ( 0)                            /*!< BURST_LENGTH Bit Offset */
5461 #define FLCTL_A_RDBRST_LEN_BURST_LENGTH_MASK     ((uint32_t)0x001FFFFF)          /*!< BURST_LENGTH Bit Mask */
5462 #define FLCTL_A_RDBRST_FAILADDR_FAIL_ADDRESS_OFS ( 0)                            /*!< FAIL_ADDRESS Bit Offset */
5463 #define FLCTL_A_RDBRST_FAILADDR_FAIL_ADDRESS_MASK ((uint32_t)0x001FFFFF)          /*!< FAIL_ADDRESS Bit Mask */
5464 #define FLCTL_A_RDBRST_FAILCNT_FAIL_COUNT_OFS    ( 0)                            /*!< FAIL_COUNT Bit Offset */
5465 #define FLCTL_A_RDBRST_FAILCNT_FAIL_COUNT_MASK   ((uint32_t)0x0001FFFF)          /*!< FAIL_COUNT Bit Mask */
5466 #define FLCTL_A_PRG_CTLSTAT_ENABLE_OFS           ( 0)                            /*!< ENABLE Bit Offset */
5467 #define FLCTL_A_PRG_CTLSTAT_ENABLE               ((uint32_t)0x00000001)          /*!< Master control for all word program operations */
5468 #define FLCTL_A_PRG_CTLSTAT_MODE_OFS             ( 1)                            /*!< MODE Bit Offset */
5469 #define FLCTL_A_PRG_CTLSTAT_MODE                 ((uint32_t)0x00000002)          /*!< Write mode */
5470 #define FLCTL_A_PRG_CTLSTAT_VER_PRE_OFS          ( 2)                            /*!< VER_PRE Bit Offset */
5471 #define FLCTL_A_PRG_CTLSTAT_VER_PRE              ((uint32_t)0x00000004)          /*!< Controls automatic pre program verify operations */
5472 #define FLCTL_A_PRG_CTLSTAT_VER_PST_OFS          ( 3)                            /*!< VER_PST Bit Offset */
5473 #define FLCTL_A_PRG_CTLSTAT_VER_PST              ((uint32_t)0x00000008)          /*!< Controls automatic post program verify operations */
5474 #define FLCTL_A_PRG_CTLSTAT_STATUS_OFS           (16)                            /*!< STATUS Bit Offset */
5475 #define FLCTL_A_PRG_CTLSTAT_STATUS_MASK          ((uint32_t)0x00030000)          /*!< STATUS Bit Mask */
5476 #define FLCTL_A_PRG_CTLSTAT_STATUS0              ((uint32_t)0x00010000)          /*!< STATUS Bit 0 */
5477 #define FLCTL_A_PRG_CTLSTAT_STATUS1              ((uint32_t)0x00020000)          /*!< STATUS Bit 1 */
5478 #define FLCTL_A_PRG_CTLSTAT_STATUS_0             ((uint32_t)0x00000000)          /*!< Idle (no program operation currently active) */
5479 #define FLCTL_A_PRG_CTLSTAT_STATUS_1             ((uint32_t)0x00010000)          /*!< Single word program operation triggered, but pending */
5480 #define FLCTL_A_PRG_CTLSTAT_STATUS_2             ((uint32_t)0x00020000)          /*!< Single word program in progress */
5481 #define FLCTL_A_PRG_CTLSTAT_STATUS_3             ((uint32_t)0x00030000)          /*!< Reserved (Idle) */
5482 #define FLCTL_A_PRG_CTLSTAT_BNK_ACT_OFS          (18)                            /*!< BNK_ACT Bit Offset */
5483 #define FLCTL_A_PRG_CTLSTAT_BNK_ACT              ((uint32_t)0x00040000)          /*!< Bank active */
5484 #define FLCTL_A_PRGBRST_CTLSTAT_START_OFS        ( 0)                            /*!< START Bit Offset */
5485 #define FLCTL_A_PRGBRST_CTLSTAT_START            ((uint32_t)0x00000001)          /*!< Trigger start of burst program operation */
5486 #define FLCTL_A_PRGBRST_CTLSTAT_TYPE_OFS         ( 1)                            /*!< TYPE Bit Offset */
5487 #define FLCTL_A_PRGBRST_CTLSTAT_TYPE_MASK        ((uint32_t)0x00000006)          /*!< TYPE Bit Mask */
5488 #define FLCTL_A_PRGBRST_CTLSTAT_TYPE0            ((uint32_t)0x00000002)          /*!< TYPE Bit 0 */
5489 #define FLCTL_A_PRGBRST_CTLSTAT_TYPE1            ((uint32_t)0x00000004)          /*!< TYPE Bit 1 */
5490 #define FLCTL_A_PRGBRST_CTLSTAT_TYPE_0           ((uint32_t)0x00000000)          /*!< Main Memory */
5491 #define FLCTL_A_PRGBRST_CTLSTAT_TYPE_1           ((uint32_t)0x00000002)          /*!< Information Memory */
5492 #define FLCTL_A_PRGBRST_CTLSTAT_TYPE_2           ((uint32_t)0x00000004)          /*!< Reserved */
5493 #define FLCTL_A_PRGBRST_CTLSTAT_TYPE_3           ((uint32_t)0x00000006)          /*!< Engineering Memory */
5494 #define FLCTL_A_PRGBRST_CTLSTAT_LEN_OFS          ( 3)                            /*!< LEN Bit Offset */
5495 #define FLCTL_A_PRGBRST_CTLSTAT_LEN_MASK         ((uint32_t)0x00000038)          /*!< LEN Bit Mask */
5496 #define FLCTL_A_PRGBRST_CTLSTAT_LEN0             ((uint32_t)0x00000008)          /*!< LEN Bit 0 */
5497 #define FLCTL_A_PRGBRST_CTLSTAT_LEN1             ((uint32_t)0x00000010)          /*!< LEN Bit 1 */
5498 #define FLCTL_A_PRGBRST_CTLSTAT_LEN2             ((uint32_t)0x00000020)          /*!< LEN Bit 2 */
5499 #define FLCTL_A_PRGBRST_CTLSTAT_LEN_0            ((uint32_t)0x00000000)          /*!< No burst operation */
5500 #define FLCTL_A_PRGBRST_CTLSTAT_LEN_1            ((uint32_t)0x00000008)          /*!< 1 word burst of 128 bits, starting with address in the  */
5501 #define FLCTL_A_PRGBRST_CTLSTAT_LEN_2            ((uint32_t)0x00000010)          /*!< 2*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR  */
5502 #define FLCTL_A_PRGBRST_CTLSTAT_LEN_3            ((uint32_t)0x00000018)          /*!< 3*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR  */
5503 #define FLCTL_A_PRGBRST_CTLSTAT_LEN_4            ((uint32_t)0x00000020)          /*!< 4*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR  */
5504 #define FLCTL_A_PRGBRST_CTLSTAT_AUTO_PRE_OFS     ( 6)                            /*!< AUTO_PRE Bit Offset */
5505 #define FLCTL_A_PRGBRST_CTLSTAT_AUTO_PRE         ((uint32_t)0x00000040)          /*!< Auto-Verify operation before the Burst Program */
5506 #define FLCTL_A_PRGBRST_CTLSTAT_AUTO_PST_OFS     ( 7)                            /*!< AUTO_PST Bit Offset */
5507 #define FLCTL_A_PRGBRST_CTLSTAT_AUTO_PST         ((uint32_t)0x00000080)          /*!< Auto-Verify operation after the Burst Program */
5508 #define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_OFS (16)                            /*!< BURST_STATUS Bit Offset */
5509 #define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_MASK ((uint32_t)0x00070000)          /*!< BURST_STATUS Bit Mask */
5510 #define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS0    ((uint32_t)0x00010000)          /*!< BURST_STATUS Bit 0 */
5511 #define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS1    ((uint32_t)0x00020000)          /*!< BURST_STATUS Bit 1 */
5512 #define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS2    ((uint32_t)0x00040000)          /*!< BURST_STATUS Bit 2 */
5513 #define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_0   ((uint32_t)0x00000000)          /*!< Idle (Burst not active) */
5514 #define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_1   ((uint32_t)0x00010000)          /*!< Burst program started but pending */
5515 #define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_2   ((uint32_t)0x00020000)          /*!< Burst active, with 1st 128 bit word being written into Flash */
5516 #define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_3   ((uint32_t)0x00030000)          /*!< Burst active, with 2nd 128 bit word being written into Flash */
5517 #define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_4   ((uint32_t)0x00040000)          /*!< Burst active, with 3rd 128 bit word being written into Flash */
5518 #define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_5   ((uint32_t)0x00050000)          /*!< Burst active, with 4th 128 bit word being written into Flash */
5519 #define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_6   ((uint32_t)0x00060000)          /*!< Reserved (Idle) */
5520 #define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_7   ((uint32_t)0x00070000)          /*!< Burst Complete (status of completed burst remains in this state unless  */
5521 #define FLCTL_A_PRGBRST_CTLSTAT_PRE_ERR_OFS      (19)                            /*!< PRE_ERR Bit Offset */
5522 #define FLCTL_A_PRGBRST_CTLSTAT_PRE_ERR          ((uint32_t)0x00080000)          /*!< Burst Operation encountered preprogram auto-verify errors */
5523 #define FLCTL_A_PRGBRST_CTLSTAT_PST_ERR_OFS      (20)                            /*!< PST_ERR Bit Offset */
5524 #define FLCTL_A_PRGBRST_CTLSTAT_PST_ERR          ((uint32_t)0x00100000)          /*!< Burst Operation encountered postprogram auto-verify errors */
5525 #define FLCTL_A_PRGBRST_CTLSTAT_ADDR_ERR_OFS     (21)                            /*!< ADDR_ERR Bit Offset */
5526 #define FLCTL_A_PRGBRST_CTLSTAT_ADDR_ERR         ((uint32_t)0x00200000)          /*!< Burst Operation was terminated due to attempted program of reserved memory */
5527 #define FLCTL_A_PRGBRST_CTLSTAT_CLR_STAT_OFS     (23)                            /*!< CLR_STAT Bit Offset */
5528 #define FLCTL_A_PRGBRST_CTLSTAT_CLR_STAT         ((uint32_t)0x00800000)          /*!< Clear status bits 21-16 of this register */
5529 #define FLCTL_A_PRGBRST_STARTADDR_START_ADDRESS_OFS ( 0)                            /*!< START_ADDRESS Bit Offset */
5530 #define FLCTL_A_PRGBRST_STARTADDR_START_ADDRESS_MASK ((uint32_t)0x003FFFFF)          /*!< START_ADDRESS Bit Mask */
5531 #define FLCTL_A_ERASE_CTLSTAT_START_OFS          ( 0)                            /*!< START Bit Offset */
5532 #define FLCTL_A_ERASE_CTLSTAT_START              ((uint32_t)0x00000001)          /*!< Start of Erase operation */
5533 #define FLCTL_A_ERASE_CTLSTAT_MODE_OFS           ( 1)                            /*!< MODE Bit Offset */
5534 #define FLCTL_A_ERASE_CTLSTAT_MODE               ((uint32_t)0x00000002)          /*!< Erase mode selected by application */
5535 #define FLCTL_A_ERASE_CTLSTAT_TYPE_OFS           ( 2)                            /*!< TYPE Bit Offset */
5536 #define FLCTL_A_ERASE_CTLSTAT_TYPE_MASK          ((uint32_t)0x0000000C)          /*!< TYPE Bit Mask */
5537 #define FLCTL_A_ERASE_CTLSTAT_TYPE0              ((uint32_t)0x00000004)          /*!< TYPE Bit 0 */
5538 #define FLCTL_A_ERASE_CTLSTAT_TYPE1              ((uint32_t)0x00000008)          /*!< TYPE Bit 1 */
5539 #define FLCTL_A_ERASE_CTLSTAT_TYPE_0             ((uint32_t)0x00000000)          /*!< Main Memory */
5540 #define FLCTL_A_ERASE_CTLSTAT_TYPE_1             ((uint32_t)0x00000004)          /*!< Information Memory */
5541 #define FLCTL_A_ERASE_CTLSTAT_TYPE_2             ((uint32_t)0x00000008)          /*!< Reserved */
5542 #define FLCTL_A_ERASE_CTLSTAT_TYPE_3             ((uint32_t)0x0000000C)          /*!< Engineering Memory */
5543 #define FLCTL_A_ERASE_CTLSTAT_STATUS_OFS         (16)                            /*!< STATUS Bit Offset */
5544 #define FLCTL_A_ERASE_CTLSTAT_STATUS_MASK        ((uint32_t)0x00030000)          /*!< STATUS Bit Mask */
5545 #define FLCTL_A_ERASE_CTLSTAT_STATUS0            ((uint32_t)0x00010000)          /*!< STATUS Bit 0 */
5546 #define FLCTL_A_ERASE_CTLSTAT_STATUS1            ((uint32_t)0x00020000)          /*!< STATUS Bit 1 */
5547 #define FLCTL_A_ERASE_CTLSTAT_STATUS_0           ((uint32_t)0x00000000)          /*!< Idle (no program operation currently active) */
5548 #define FLCTL_A_ERASE_CTLSTAT_STATUS_1           ((uint32_t)0x00010000)          /*!< Erase operation triggered to START but pending */
5549 #define FLCTL_A_ERASE_CTLSTAT_STATUS_2           ((uint32_t)0x00020000)          /*!< Erase operation in progress */
5550 #define FLCTL_A_ERASE_CTLSTAT_STATUS_3           ((uint32_t)0x00030000)          /*!< Erase operation completed (status of completed erase remains in this state  */
5551 #define FLCTL_A_ERASE_CTLSTAT_ADDR_ERR_OFS       (18)                            /*!< ADDR_ERR Bit Offset */
5552 #define FLCTL_A_ERASE_CTLSTAT_ADDR_ERR           ((uint32_t)0x00040000)          /*!< Erase Operation was terminated due to attempted erase of reserved memory  */
5553 #define FLCTL_A_ERASE_CTLSTAT_CLR_STAT_OFS       (19)                            /*!< CLR_STAT Bit Offset */
5554 #define FLCTL_A_ERASE_CTLSTAT_CLR_STAT           ((uint32_t)0x00080000)          /*!< Clear status bits 18-16 of this register */
5555 #define FLCTL_A_ERASE_SECTADDR_SECT_ADDRESS_OFS  ( 0)                            /*!< SECT_ADDRESS Bit Offset */
5556 #define FLCTL_A_ERASE_SECTADDR_SECT_ADDRESS_MASK ((uint32_t)0x003FFFFF)          /*!< SECT_ADDRESS Bit Mask */
5557 #define FLCTL_A_BANK0_INFO_WEPROT_PROT0_OFS      ( 0)                            /*!< PROT0 Bit Offset */
5558 #define FLCTL_A_BANK0_INFO_WEPROT_PROT0          ((uint32_t)0x00000001)          /*!< Protects Sector 0 from program or erase */
5559 #define FLCTL_A_BANK0_INFO_WEPROT_PROT1_OFS      ( 1)                            /*!< PROT1 Bit Offset */
5560 #define FLCTL_A_BANK0_INFO_WEPROT_PROT1          ((uint32_t)0x00000002)          /*!< Protects Sector 1 from program or erase */
5561 #define FLCTL_A_BANK0_INFO_WEPROT_PROT2_OFS      ( 2)                            /*!< PROT2 Bit Offset */
5562 #define FLCTL_A_BANK0_INFO_WEPROT_PROT2          ((uint32_t)0x00000004)          /*!< Protects Sector 2 from program or erase */
5563 #define FLCTL_A_BANK0_INFO_WEPROT_PROT3_OFS      ( 3)                            /*!< PROT3 Bit Offset */
5564 #define FLCTL_A_BANK0_INFO_WEPROT_PROT3          ((uint32_t)0x00000008)          /*!< Protects Sector 3 from program or erase */
5565 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT0_OFS      ( 0)                            /*!< PROT0 Bit Offset */
5566 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT0          ((uint32_t)0x00000001)          /*!< Protects Sector 0 from program or erase */
5567 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT1_OFS      ( 1)                            /*!< PROT1 Bit Offset */
5568 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT1          ((uint32_t)0x00000002)          /*!< Protects Sector 1 from program or erase */
5569 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT2_OFS      ( 2)                            /*!< PROT2 Bit Offset */
5570 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT2          ((uint32_t)0x00000004)          /*!< Protects Sector 2 from program or erase */
5571 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT3_OFS      ( 3)                            /*!< PROT3 Bit Offset */
5572 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT3          ((uint32_t)0x00000008)          /*!< Protects Sector 3 from program or erase */
5573 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT4_OFS      ( 4)                            /*!< PROT4 Bit Offset */
5574 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT4          ((uint32_t)0x00000010)          /*!< Protects Sector 4 from program or erase */
5575 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT5_OFS      ( 5)                            /*!< PROT5 Bit Offset */
5576 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT5          ((uint32_t)0x00000020)          /*!< Protects Sector 5 from program or erase */
5577 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT6_OFS      ( 6)                            /*!< PROT6 Bit Offset */
5578 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT6          ((uint32_t)0x00000040)          /*!< Protects Sector 6 from program or erase */
5579 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT7_OFS      ( 7)                            /*!< PROT7 Bit Offset */
5580 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT7          ((uint32_t)0x00000080)          /*!< Protects Sector 7 from program or erase */
5581 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT8_OFS      ( 8)                            /*!< PROT8 Bit Offset */
5582 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT8          ((uint32_t)0x00000100)          /*!< Protects Sector 8 from program or erase */
5583 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT9_OFS      ( 9)                            /*!< PROT9 Bit Offset */
5584 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT9          ((uint32_t)0x00000200)          /*!< Protects Sector 9 from program or erase */
5585 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT10_OFS     (10)                            /*!< PROT10 Bit Offset */
5586 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT10         ((uint32_t)0x00000400)          /*!< Protects Sector 10 from program or erase */
5587 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT11_OFS     (11)                            /*!< PROT11 Bit Offset */
5588 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT11         ((uint32_t)0x00000800)          /*!< Protects Sector 11 from program or erase */
5589 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT12_OFS     (12)                            /*!< PROT12 Bit Offset */
5590 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT12         ((uint32_t)0x00001000)          /*!< Protects Sector 12 from program or erase */
5591 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT13_OFS     (13)                            /*!< PROT13 Bit Offset */
5592 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT13         ((uint32_t)0x00002000)          /*!< Protects Sector 13 from program or erase */
5593 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT14_OFS     (14)                            /*!< PROT14 Bit Offset */
5594 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT14         ((uint32_t)0x00004000)          /*!< Protects Sector 14 from program or erase */
5595 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT15_OFS     (15)                            /*!< PROT15 Bit Offset */
5596 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT15         ((uint32_t)0x00008000)          /*!< Protects Sector 15 from program or erase */
5597 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT16_OFS     (16)                            /*!< PROT16 Bit Offset */
5598 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT16         ((uint32_t)0x00010000)          /*!< Protects Sector 16 from program or erase */
5599 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT17_OFS     (17)                            /*!< PROT17 Bit Offset */
5600 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT17         ((uint32_t)0x00020000)          /*!< Protects Sector 17 from program or erase */
5601 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT18_OFS     (18)                            /*!< PROT18 Bit Offset */
5602 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT18         ((uint32_t)0x00040000)          /*!< Protects Sector 18 from program or erase */
5603 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT19_OFS     (19)                            /*!< PROT19 Bit Offset */
5604 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT19         ((uint32_t)0x00080000)          /*!< Protects Sector 19 from program or erase */
5605 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT20_OFS     (20)                            /*!< PROT20 Bit Offset */
5606 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT20         ((uint32_t)0x00100000)          /*!< Protects Sector 20 from program or erase */
5607 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT21_OFS     (21)                            /*!< PROT21 Bit Offset */
5608 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT21         ((uint32_t)0x00200000)          /*!< Protects Sector 21 from program or erase */
5609 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT22_OFS     (22)                            /*!< PROT22 Bit Offset */
5610 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT22         ((uint32_t)0x00400000)          /*!< Protects Sector 22 from program or erase */
5611 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT23_OFS     (23)                            /*!< PROT23 Bit Offset */
5612 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT23         ((uint32_t)0x00800000)          /*!< Protects Sector 23 from program or erase */
5613 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT24_OFS     (24)                            /*!< PROT24 Bit Offset */
5614 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT24         ((uint32_t)0x01000000)          /*!< Protects Sector 24 from program or erase */
5615 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT25_OFS     (25)                            /*!< PROT25 Bit Offset */
5616 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT25         ((uint32_t)0x02000000)          /*!< Protects Sector 25 from program or erase */
5617 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT26_OFS     (26)                            /*!< PROT26 Bit Offset */
5618 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT26         ((uint32_t)0x04000000)          /*!< Protects Sector 26 from program or erase */
5619 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT27_OFS     (27)                            /*!< PROT27 Bit Offset */
5620 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT27         ((uint32_t)0x08000000)          /*!< Protects Sector 27 from program or erase */
5621 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT28_OFS     (28)                            /*!< PROT28 Bit Offset */
5622 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT28         ((uint32_t)0x10000000)          /*!< Protects Sector 28 from program or erase */
5623 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT29_OFS     (29)                            /*!< PROT29 Bit Offset */
5624 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT29         ((uint32_t)0x20000000)          /*!< Protects Sector 29 from program or erase */
5625 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT30_OFS     (30)                            /*!< PROT30 Bit Offset */
5626 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT30         ((uint32_t)0x40000000)          /*!< Protects Sector 30 from program or erase */
5627 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT31_OFS     (31)                            /*!< PROT31 Bit Offset */
5628 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT31         ((uint32_t)0x80000000)          /*!< Protects Sector 31 from program or erase */
5629 #define FLCTL_A_BANK1_INFO_WEPROT_PROT0_OFS      ( 0)                            /*!< PROT0 Bit Offset */
5630 #define FLCTL_A_BANK1_INFO_WEPROT_PROT0          ((uint32_t)0x00000001)          /*!< Protects Sector 0 from program or erase operations */
5631 #define FLCTL_A_BANK1_INFO_WEPROT_PROT1_OFS      ( 1)                            /*!< PROT1 Bit Offset */
5632 #define FLCTL_A_BANK1_INFO_WEPROT_PROT1          ((uint32_t)0x00000002)          /*!< Protects Sector 1 from program or erase operations */
5633 #define FLCTL_A_BANK1_INFO_WEPROT_PROT2_OFS      ( 2)                            /*!< PROT2 Bit Offset */
5634 #define FLCTL_A_BANK1_INFO_WEPROT_PROT2          ((uint32_t)0x00000004)          /*!< Protects Sector 2 from program or erase */
5635 #define FLCTL_A_BANK1_INFO_WEPROT_PROT3_OFS      ( 3)                            /*!< PROT3 Bit Offset */
5636 #define FLCTL_A_BANK1_INFO_WEPROT_PROT3          ((uint32_t)0x00000008)          /*!< Protects Sector 3 from program or erase */
5637 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT0_OFS      ( 0)                            /*!< PROT0 Bit Offset */
5638 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT0          ((uint32_t)0x00000001)          /*!< Protects Sector 0 from program or erase operations */
5639 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT1_OFS      ( 1)                            /*!< PROT1 Bit Offset */
5640 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT1          ((uint32_t)0x00000002)          /*!< Protects Sector 1 from program or erase operations */
5641 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT2_OFS      ( 2)                            /*!< PROT2 Bit Offset */
5642 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT2          ((uint32_t)0x00000004)          /*!< Protects Sector 2 from program or erase operations */
5643 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT3_OFS      ( 3)                            /*!< PROT3 Bit Offset */
5644 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT3          ((uint32_t)0x00000008)          /*!< Protects Sector 3 from program or erase operations */
5645 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT4_OFS      ( 4)                            /*!< PROT4 Bit Offset */
5646 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT4          ((uint32_t)0x00000010)          /*!< Protects Sector 4 from program or erase operations */
5647 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT5_OFS      ( 5)                            /*!< PROT5 Bit Offset */
5648 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT5          ((uint32_t)0x00000020)          /*!< Protects Sector 5 from program or erase operations */
5649 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT6_OFS      ( 6)                            /*!< PROT6 Bit Offset */
5650 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT6          ((uint32_t)0x00000040)          /*!< Protects Sector 6 from program or erase operations */
5651 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT7_OFS      ( 7)                            /*!< PROT7 Bit Offset */
5652 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT7          ((uint32_t)0x00000080)          /*!< Protects Sector 7 from program or erase operations */
5653 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT8_OFS      ( 8)                            /*!< PROT8 Bit Offset */
5654 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT8          ((uint32_t)0x00000100)          /*!< Protects Sector 8 from program or erase operations */
5655 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT9_OFS      ( 9)                            /*!< PROT9 Bit Offset */
5656 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT9          ((uint32_t)0x00000200)          /*!< Protects Sector 9 from program or erase operations */
5657 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT10_OFS     (10)                            /*!< PROT10 Bit Offset */
5658 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT10         ((uint32_t)0x00000400)          /*!< Protects Sector 10 from program or erase operations */
5659 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT11_OFS     (11)                            /*!< PROT11 Bit Offset */
5660 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT11         ((uint32_t)0x00000800)          /*!< Protects Sector 11 from program or erase operations */
5661 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT12_OFS     (12)                            /*!< PROT12 Bit Offset */
5662 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT12         ((uint32_t)0x00001000)          /*!< Protects Sector 12 from program or erase operations */
5663 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT13_OFS     (13)                            /*!< PROT13 Bit Offset */
5664 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT13         ((uint32_t)0x00002000)          /*!< Protects Sector 13 from program or erase operations */
5665 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT14_OFS     (14)                            /*!< PROT14 Bit Offset */
5666 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT14         ((uint32_t)0x00004000)          /*!< Protects Sector 14 from program or erase operations */
5667 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT15_OFS     (15)                            /*!< PROT15 Bit Offset */
5668 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT15         ((uint32_t)0x00008000)          /*!< Protects Sector 15 from program or erase operations */
5669 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT16_OFS     (16)                            /*!< PROT16 Bit Offset */
5670 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT16         ((uint32_t)0x00010000)          /*!< Protects Sector 16 from program or erase operations */
5671 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT17_OFS     (17)                            /*!< PROT17 Bit Offset */
5672 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT17         ((uint32_t)0x00020000)          /*!< Protects Sector 17 from program or erase operations */
5673 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT18_OFS     (18)                            /*!< PROT18 Bit Offset */
5674 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT18         ((uint32_t)0x00040000)          /*!< Protects Sector 18 from program or erase operations */
5675 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT19_OFS     (19)                            /*!< PROT19 Bit Offset */
5676 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT19         ((uint32_t)0x00080000)          /*!< Protects Sector 19 from program or erase operations */
5677 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT20_OFS     (20)                            /*!< PROT20 Bit Offset */
5678 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT20         ((uint32_t)0x00100000)          /*!< Protects Sector 20 from program or erase operations */
5679 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT21_OFS     (21)                            /*!< PROT21 Bit Offset */
5680 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT21         ((uint32_t)0x00200000)          /*!< Protects Sector 21 from program or erase operations */
5681 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT22_OFS     (22)                            /*!< PROT22 Bit Offset */
5682 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT22         ((uint32_t)0x00400000)          /*!< Protects Sector 22 from program or erase operations */
5683 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT23_OFS     (23)                            /*!< PROT23 Bit Offset */
5684 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT23         ((uint32_t)0x00800000)          /*!< Protects Sector 23 from program or erase operations */
5685 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT24_OFS     (24)                            /*!< PROT24 Bit Offset */
5686 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT24         ((uint32_t)0x01000000)          /*!< Protects Sector 24 from program or erase operations */
5687 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT25_OFS     (25)                            /*!< PROT25 Bit Offset */
5688 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT25         ((uint32_t)0x02000000)          /*!< Protects Sector 25 from program or erase operations */
5689 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT26_OFS     (26)                            /*!< PROT26 Bit Offset */
5690 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT26         ((uint32_t)0x04000000)          /*!< Protects Sector 26 from program or erase operations */
5691 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT27_OFS     (27)                            /*!< PROT27 Bit Offset */
5692 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT27         ((uint32_t)0x08000000)          /*!< Protects Sector 27 from program or erase operations */
5693 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT28_OFS     (28)                            /*!< PROT28 Bit Offset */
5694 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT28         ((uint32_t)0x10000000)          /*!< Protects Sector 28 from program or erase operations */
5695 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT29_OFS     (29)                            /*!< PROT29 Bit Offset */
5696 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT29         ((uint32_t)0x20000000)          /*!< Protects Sector 29 from program or erase operations */
5697 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT30_OFS     (30)                            /*!< PROT30 Bit Offset */
5698 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT30         ((uint32_t)0x40000000)          /*!< Protects Sector 30 from program or erase operations */
5699 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT31_OFS     (31)                            /*!< PROT31 Bit Offset */
5700 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT31         ((uint32_t)0x80000000)          /*!< Protects Sector 31 from program or erase operations */
5701 #define FLCTL_A_BMRK_CTLSTAT_I_BMRK_OFS          ( 0)                            /*!< I_BMRK Bit Offset */
5702 #define FLCTL_A_BMRK_CTLSTAT_I_BMRK              ((uint32_t)0x00000001)
5703 #define FLCTL_A_BMRK_CTLSTAT_D_BMRK_OFS          ( 1)                            /*!< D_BMRK Bit Offset */
5704 #define FLCTL_A_BMRK_CTLSTAT_D_BMRK              ((uint32_t)0x00000002)
5705 #define FLCTL_A_BMRK_CTLSTAT_CMP_EN_OFS          ( 2)                            /*!< CMP_EN Bit Offset */
5706 #define FLCTL_A_BMRK_CTLSTAT_CMP_EN              ((uint32_t)0x00000004)
5707 #define FLCTL_A_BMRK_CTLSTAT_CMP_SEL_OFS         ( 3)                            /*!< CMP_SEL Bit Offset */
5708 #define FLCTL_A_BMRK_CTLSTAT_CMP_SEL             ((uint32_t)0x00000008)
5709 #define FLCTL_A_IFG_RDBRST_OFS                   ( 0)                            /*!< RDBRST Bit Offset */
5710 #define FLCTL_A_IFG_RDBRST                       ((uint32_t)0x00000001)
5711 #define FLCTL_A_IFG_AVPRE_OFS                    ( 1)                            /*!< AVPRE Bit Offset */
5712 #define FLCTL_A_IFG_AVPRE                        ((uint32_t)0x00000002)
5713 #define FLCTL_A_IFG_AVPST_OFS                    ( 2)                            /*!< AVPST Bit Offset */
5714 #define FLCTL_A_IFG_AVPST                        ((uint32_t)0x00000004)
5715 #define FLCTL_A_IFG_PRG_OFS                      ( 3)                            /*!< PRG Bit Offset */
5716 #define FLCTL_A_IFG_PRG                          ((uint32_t)0x00000008)
5717 #define FLCTL_A_IFG_PRGB_OFS                     ( 4)                            /*!< PRGB Bit Offset */
5718 #define FLCTL_A_IFG_PRGB                         ((uint32_t)0x00000010)
5719 #define FLCTL_A_IFG_ERASE_OFS                    ( 5)                            /*!< ERASE Bit Offset */
5720 #define FLCTL_A_IFG_ERASE                        ((uint32_t)0x00000020)
5721 #define FLCTL_A_IFG_BMRK_OFS                     ( 8)                            /*!< BMRK Bit Offset */
5722 #define FLCTL_A_IFG_BMRK                         ((uint32_t)0x00000100)
5723 #define FLCTL_A_IFG_PRG_ERR_OFS                  ( 9)                            /*!< PRG_ERR Bit Offset */
5724 #define FLCTL_A_IFG_PRG_ERR                      ((uint32_t)0x00000200)
5725 #define FLCTL_A_IE_RDBRST_OFS                    ( 0)                            /*!< RDBRST Bit Offset */
5726 #define FLCTL_A_IE_RDBRST                        ((uint32_t)0x00000001)
5727 #define FLCTL_A_IE_AVPRE_OFS                     ( 1)                            /*!< AVPRE Bit Offset */
5728 #define FLCTL_A_IE_AVPRE                         ((uint32_t)0x00000002)
5729 #define FLCTL_A_IE_AVPST_OFS                     ( 2)                            /*!< AVPST Bit Offset */
5730 #define FLCTL_A_IE_AVPST                         ((uint32_t)0x00000004)
5731 #define FLCTL_A_IE_PRG_OFS                       ( 3)                            /*!< PRG Bit Offset */
5732 #define FLCTL_A_IE_PRG                           ((uint32_t)0x00000008)
5733 #define FLCTL_A_IE_PRGB_OFS                      ( 4)                            /*!< PRGB Bit Offset */
5734 #define FLCTL_A_IE_PRGB                          ((uint32_t)0x00000010)
5735 #define FLCTL_A_IE_ERASE_OFS                     ( 5)                            /*!< ERASE Bit Offset */
5736 #define FLCTL_A_IE_ERASE                         ((uint32_t)0x00000020)
5737 #define FLCTL_A_IE_BMRK_OFS                      ( 8)                            /*!< BMRK Bit Offset */
5738 #define FLCTL_A_IE_BMRK                          ((uint32_t)0x00000100)
5739 #define FLCTL_A_IE_PRG_ERR_OFS                   ( 9)                            /*!< PRG_ERR Bit Offset */
5740 #define FLCTL_A_IE_PRG_ERR                       ((uint32_t)0x00000200)
5741 #define FLCTL_A_CLRIFG_RDBRST_OFS                ( 0)                            /*!< RDBRST Bit Offset */
5742 #define FLCTL_A_CLRIFG_RDBRST                    ((uint32_t)0x00000001)
5743 #define FLCTL_A_CLRIFG_AVPRE_OFS                 ( 1)                            /*!< AVPRE Bit Offset */
5744 #define FLCTL_A_CLRIFG_AVPRE                     ((uint32_t)0x00000002)
5745 #define FLCTL_A_CLRIFG_AVPST_OFS                 ( 2)                            /*!< AVPST Bit Offset */
5746 #define FLCTL_A_CLRIFG_AVPST                     ((uint32_t)0x00000004)
5747 #define FLCTL_A_CLRIFG_PRG_OFS                   ( 3)                            /*!< PRG Bit Offset */
5748 #define FLCTL_A_CLRIFG_PRG                       ((uint32_t)0x00000008)
5749 #define FLCTL_A_CLRIFG_PRGB_OFS                  ( 4)                            /*!< PRGB Bit Offset */
5750 #define FLCTL_A_CLRIFG_PRGB                      ((uint32_t)0x00000010)
5751 #define FLCTL_A_CLRIFG_ERASE_OFS                 ( 5)                            /*!< ERASE Bit Offset */
5752 #define FLCTL_A_CLRIFG_ERASE                     ((uint32_t)0x00000020)
5753 #define FLCTL_A_CLRIFG_BMRK_OFS                  ( 8)                            /*!< BMRK Bit Offset */
5754 #define FLCTL_A_CLRIFG_BMRK                      ((uint32_t)0x00000100)
5755 #define FLCTL_A_CLRIFG_PRG_ERR_OFS               ( 9)                            /*!< PRG_ERR Bit Offset */
5756 #define FLCTL_A_CLRIFG_PRG_ERR                   ((uint32_t)0x00000200)
5757 #define FLCTL_A_SETIFG_RDBRST_OFS                ( 0)                            /*!< RDBRST Bit Offset */
5758 #define FLCTL_A_SETIFG_RDBRST                    ((uint32_t)0x00000001)
5759 #define FLCTL_A_SETIFG_AVPRE_OFS                 ( 1)                            /*!< AVPRE Bit Offset */
5760 #define FLCTL_A_SETIFG_AVPRE                     ((uint32_t)0x00000002)
5761 #define FLCTL_A_SETIFG_AVPST_OFS                 ( 2)                            /*!< AVPST Bit Offset */
5762 #define FLCTL_A_SETIFG_AVPST                     ((uint32_t)0x00000004)
5763 #define FLCTL_A_SETIFG_PRG_OFS                   ( 3)                            /*!< PRG Bit Offset */
5764 #define FLCTL_A_SETIFG_PRG                       ((uint32_t)0x00000008)
5765 #define FLCTL_A_SETIFG_PRGB_OFS                  ( 4)                            /*!< PRGB Bit Offset */
5766 #define FLCTL_A_SETIFG_PRGB                      ((uint32_t)0x00000010)
5767 #define FLCTL_A_SETIFG_ERASE_OFS                 ( 5)                            /*!< ERASE Bit Offset */
5768 #define FLCTL_A_SETIFG_ERASE                     ((uint32_t)0x00000020)
5769 #define FLCTL_A_SETIFG_BMRK_OFS                  ( 8)                            /*!< BMRK Bit Offset */
5770 #define FLCTL_A_SETIFG_BMRK                      ((uint32_t)0x00000100)
5771 #define FLCTL_A_SETIFG_PRG_ERR_OFS               ( 9)                            /*!< PRG_ERR Bit Offset */
5772 #define FLCTL_A_SETIFG_PRG_ERR                   ((uint32_t)0x00000200)
5773 #define FLCTL_A_READ_TIMCTL_SETUP_OFS            ( 0)                            /*!< SETUP Bit Offset */
5774 #define FLCTL_A_READ_TIMCTL_SETUP_MASK           ((uint32_t)0x000000FF)          /*!< SETUP Bit Mask */
5775 #define FLCTL_A_READ_TIMCTL_IREF_BOOST1_OFS      (12)                            /*!< IREF_BOOST1 Bit Offset */
5776 #define FLCTL_A_READ_TIMCTL_IREF_BOOST1_MASK     ((uint32_t)0x0000F000)          /*!< IREF_BOOST1 Bit Mask */
5777 #define FLCTL_A_READ_TIMCTL_SETUP_LONG_OFS       (16)                            /*!< SETUP_LONG Bit Offset */
5778 #define FLCTL_A_READ_TIMCTL_SETUP_LONG_MASK      ((uint32_t)0x00FF0000)          /*!< SETUP_LONG Bit Mask */
5779 #define FLCTL_A_READMARGIN_TIMCTL_SETUP_OFS      ( 0)                            /*!< SETUP Bit Offset */
5780 #define FLCTL_A_READMARGIN_TIMCTL_SETUP_MASK     ((uint32_t)0x000000FF)          /*!< SETUP Bit Mask */
5781 #define FLCTL_A_PRGVER_TIMCTL_SETUP_OFS          ( 0)                            /*!< SETUP Bit Offset */
5782 #define FLCTL_A_PRGVER_TIMCTL_SETUP_MASK         ((uint32_t)0x000000FF)          /*!< SETUP Bit Mask */
5783 #define FLCTL_A_PRGVER_TIMCTL_ACTIVE_OFS         ( 8)                            /*!< ACTIVE Bit Offset */
5784 #define FLCTL_A_PRGVER_TIMCTL_ACTIVE_MASK        ((uint32_t)0x00000F00)          /*!< ACTIVE Bit Mask */
5785 #define FLCTL_A_PRGVER_TIMCTL_HOLD_OFS           (12)                            /*!< HOLD Bit Offset */
5786 #define FLCTL_A_PRGVER_TIMCTL_HOLD_MASK          ((uint32_t)0x0000F000)          /*!< HOLD Bit Mask */
5787 #define FLCTL_A_ERSVER_TIMCTL_SETUP_OFS          ( 0)                            /*!< SETUP Bit Offset */
5788 #define FLCTL_A_ERSVER_TIMCTL_SETUP_MASK         ((uint32_t)0x000000FF)          /*!< SETUP Bit Mask */
5789 #define FLCTL_A_LKGVER_TIMCTL_SETUP_OFS          ( 0)                            /*!< SETUP Bit Offset */
5790 #define FLCTL_A_LKGVER_TIMCTL_SETUP_MASK         ((uint32_t)0x000000FF)          /*!< SETUP Bit Mask */
5791 #define FLCTL_A_PROGRAM_TIMCTL_SETUP_OFS         ( 0)                            /*!< SETUP Bit Offset */
5792 #define FLCTL_A_PROGRAM_TIMCTL_SETUP_MASK        ((uint32_t)0x000000FF)          /*!< SETUP Bit Mask */
5793 #define FLCTL_A_PROGRAM_TIMCTL_ACTIVE_OFS        ( 8)                            /*!< ACTIVE Bit Offset */
5794 #define FLCTL_A_PROGRAM_TIMCTL_ACTIVE_MASK       ((uint32_t)0x0FFFFF00)          /*!< ACTIVE Bit Mask */
5795 #define FLCTL_A_PROGRAM_TIMCTL_HOLD_OFS          (28)                            /*!< HOLD Bit Offset */
5796 #define FLCTL_A_PROGRAM_TIMCTL_HOLD_MASK         ((uint32_t)0xF0000000)          /*!< HOLD Bit Mask */
5797 #define FLCTL_A_ERASE_TIMCTL_SETUP_OFS           ( 0)                            /*!< SETUP Bit Offset */
5798 #define FLCTL_A_ERASE_TIMCTL_SETUP_MASK          ((uint32_t)0x000000FF)          /*!< SETUP Bit Mask */
5799 #define FLCTL_A_ERASE_TIMCTL_ACTIVE_OFS          ( 8)                            /*!< ACTIVE Bit Offset */
5800 #define FLCTL_A_ERASE_TIMCTL_ACTIVE_MASK         ((uint32_t)0x0FFFFF00)          /*!< ACTIVE Bit Mask */
5801 #define FLCTL_A_ERASE_TIMCTL_HOLD_OFS            (28)                            /*!< HOLD Bit Offset */
5802 #define FLCTL_A_ERASE_TIMCTL_HOLD_MASK           ((uint32_t)0xF0000000)          /*!< HOLD Bit Mask */
5803 #define FLCTL_A_MASSERASE_TIMCTL_BOOST_ACTIVE_OFS ( 0)                            /*!< BOOST_ACTIVE Bit Offset */
5804 #define FLCTL_A_MASSERASE_TIMCTL_BOOST_ACTIVE_MASK ((uint32_t)0x000000FF)          /*!< BOOST_ACTIVE Bit Mask */
5805 #define FLCTL_A_MASSERASE_TIMCTL_BOOST_HOLD_OFS  ( 8)                            /*!< BOOST_HOLD Bit Offset */
5806 #define FLCTL_A_MASSERASE_TIMCTL_BOOST_HOLD_MASK ((uint32_t)0x0000FF00)          /*!< BOOST_HOLD Bit Mask */
5807 #define FLCTL_A_BURSTPRG_TIMCTL_ACTIVE_OFS       ( 8)                            /*!< ACTIVE Bit Offset */
5808 #define FLCTL_A_BURSTPRG_TIMCTL_ACTIVE_MASK      ((uint32_t)0x0FFFFF00)          /*!< ACTIVE Bit Mask */
5809 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT0_OFS     ( 0)                            /*!< PROT0 Bit Offset */
5810 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT0         ((uint32_t)0x00000001)          /*!< Protects Sector 0 from program or erase */
5811 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT1_OFS     ( 1)                            /*!< PROT1 Bit Offset */
5812 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT1         ((uint32_t)0x00000002)          /*!< Protects Sector 1 from program or erase */
5813 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT2_OFS     ( 2)                            /*!< PROT2 Bit Offset */
5814 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT2         ((uint32_t)0x00000004)          /*!< Protects Sector 2 from program or erase */
5815 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT3_OFS     ( 3)                            /*!< PROT3 Bit Offset */
5816 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT3         ((uint32_t)0x00000008)          /*!< Protects Sector 3 from program or erase */
5817 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT4_OFS     ( 4)                            /*!< PROT4 Bit Offset */
5818 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT4         ((uint32_t)0x00000010)          /*!< Protects Sector 4 from program or erase */
5819 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT5_OFS     ( 5)                            /*!< PROT5 Bit Offset */
5820 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT5         ((uint32_t)0x00000020)          /*!< Protects Sector 5 from program or erase */
5821 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT6_OFS     ( 6)                            /*!< PROT6 Bit Offset */
5822 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT6         ((uint32_t)0x00000040)          /*!< Protects Sector 6 from program or erase */
5823 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT7_OFS     ( 7)                            /*!< PROT7 Bit Offset */
5824 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT7         ((uint32_t)0x00000080)          /*!< Protects Sector 7 from program or erase */
5825 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT8_OFS     ( 8)                            /*!< PROT8 Bit Offset */
5826 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT8         ((uint32_t)0x00000100)          /*!< Protects Sector 8 from program or erase */
5827 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT9_OFS     ( 9)                            /*!< PROT9 Bit Offset */
5828 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT9         ((uint32_t)0x00000200)          /*!< Protects Sector 9 from program or erase */
5829 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT10_OFS    (10)                            /*!< PROT10 Bit Offset */
5830 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT10        ((uint32_t)0x00000400)          /*!< Protects Sector 10 from program or erase */
5831 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT11_OFS    (11)                            /*!< PROT11 Bit Offset */
5832 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT11        ((uint32_t)0x00000800)          /*!< Protects Sector 11 from program or erase */
5833 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT12_OFS    (12)                            /*!< PROT12 Bit Offset */
5834 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT12        ((uint32_t)0x00001000)          /*!< Protects Sector 12 from program or erase */
5835 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT13_OFS    (13)                            /*!< PROT13 Bit Offset */
5836 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT13        ((uint32_t)0x00002000)          /*!< Protects Sector 13 from program or erase */
5837 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT14_OFS    (14)                            /*!< PROT14 Bit Offset */
5838 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT14        ((uint32_t)0x00004000)          /*!< Protects Sector 14 from program or erase */
5839 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT15_OFS    (15)                            /*!< PROT15 Bit Offset */
5840 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT15        ((uint32_t)0x00008000)          /*!< Protects Sector 15 from program or erase */
5841 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT16_OFS    (16)                            /*!< PROT16 Bit Offset */
5842 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT16        ((uint32_t)0x00010000)          /*!< Protects Sector 16 from program or erase */
5843 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT17_OFS    (17)                            /*!< PROT17 Bit Offset */
5844 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT17        ((uint32_t)0x00020000)          /*!< Protects Sector 17 from program or erase */
5845 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT18_OFS    (18)                            /*!< PROT18 Bit Offset */
5846 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT18        ((uint32_t)0x00040000)          /*!< Protects Sector 18 from program or erase */
5847 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT19_OFS    (19)                            /*!< PROT19 Bit Offset */
5848 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT19        ((uint32_t)0x00080000)          /*!< Protects Sector 19 from program or erase */
5849 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT20_OFS    (20)                            /*!< PROT20 Bit Offset */
5850 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT20        ((uint32_t)0x00100000)          /*!< Protects Sector 20 from program or erase */
5851 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT21_OFS    (21)                            /*!< PROT21 Bit Offset */
5852 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT21        ((uint32_t)0x00200000)          /*!< Protects Sector 21 from program or erase */
5853 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT22_OFS    (22)                            /*!< PROT22 Bit Offset */
5854 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT22        ((uint32_t)0x00400000)          /*!< Protects Sector 22 from program or erase */
5855 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT23_OFS    (23)                            /*!< PROT23 Bit Offset */
5856 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT23        ((uint32_t)0x00800000)          /*!< Protects Sector 23 from program or erase */
5857 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT24_OFS    (24)                            /*!< PROT24 Bit Offset */
5858 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT24        ((uint32_t)0x01000000)          /*!< Protects Sector 24 from program or erase */
5859 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT25_OFS    (25)                            /*!< PROT25 Bit Offset */
5860 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT25        ((uint32_t)0x02000000)          /*!< Protects Sector 25 from program or erase */
5861 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT26_OFS    (26)                            /*!< PROT26 Bit Offset */
5862 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT26        ((uint32_t)0x04000000)          /*!< Protects Sector 26 from program or erase */
5863 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT27_OFS    (27)                            /*!< PROT27 Bit Offset */
5864 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT27        ((uint32_t)0x08000000)          /*!< Protects Sector 27 from program or erase */
5865 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT28_OFS    (28)                            /*!< PROT28 Bit Offset */
5866 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT28        ((uint32_t)0x10000000)          /*!< Protects Sector 28 from program or erase */
5867 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT29_OFS    (29)                            /*!< PROT29 Bit Offset */
5868 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT29        ((uint32_t)0x20000000)          /*!< Protects Sector 29 from program or erase */
5869 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT30_OFS    (30)                            /*!< PROT30 Bit Offset */
5870 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT30        ((uint32_t)0x40000000)          /*!< Protects Sector 30 from program or erase */
5871 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT31_OFS    (31)                            /*!< PROT31 Bit Offset */
5872 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT31        ((uint32_t)0x80000000)          /*!< Protects Sector 31 from program or erase */
5873 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT32_OFS    ( 0)                            /*!< PROT32 Bit Offset */
5874 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT32        ((uint32_t)0x00000001)          /*!< Protects Sector 32 from program or erase */
5875 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT33_OFS    ( 1)                            /*!< PROT33 Bit Offset */
5876 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT33        ((uint32_t)0x00000002)          /*!< Protects Sector 33 from program or erase */
5877 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT34_OFS    ( 2)                            /*!< PROT34 Bit Offset */
5878 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT34        ((uint32_t)0x00000004)          /*!< Protects Sector 34 from program or erase */
5879 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT35_OFS    ( 3)                            /*!< PROT35 Bit Offset */
5880 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT35        ((uint32_t)0x00000008)          /*!< Protects Sector 35 from program or erase */
5881 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT36_OFS    ( 4)                            /*!< PROT36 Bit Offset */
5882 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT36        ((uint32_t)0x00000010)          /*!< Protects Sector 36 from program or erase */
5883 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT37_OFS    ( 5)                            /*!< PROT37 Bit Offset */
5884 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT37        ((uint32_t)0x00000020)          /*!< Protects Sector 37 from program or erase */
5885 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT38_OFS    ( 6)                            /*!< PROT38 Bit Offset */
5886 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT38        ((uint32_t)0x00000040)          /*!< Protects Sector 38 from program or erase */
5887 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT39_OFS    ( 7)                            /*!< PROT39 Bit Offset */
5888 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT39        ((uint32_t)0x00000080)          /*!< Protects Sector 39 from program or erase */
5889 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT40_OFS    ( 8)                            /*!< PROT40 Bit Offset */
5890 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT40        ((uint32_t)0x00000100)          /*!< Protects Sector 40 from program or erase */
5891 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT41_OFS    ( 9)                            /*!< PROT41 Bit Offset */
5892 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT41        ((uint32_t)0x00000200)          /*!< Protects Sector 41 from program or erase */
5893 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT42_OFS    (10)                            /*!< PROT42 Bit Offset */
5894 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT42        ((uint32_t)0x00000400)          /*!< Protects Sector 42 from program or erase */
5895 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT43_OFS    (11)                            /*!< PROT43 Bit Offset */
5896 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT43        ((uint32_t)0x00000800)          /*!< Protects Sector 43 from program or erase */
5897 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT44_OFS    (12)                            /*!< PROT44 Bit Offset */
5898 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT44        ((uint32_t)0x00001000)          /*!< Protects Sector 44 from program or erase */
5899 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT45_OFS    (13)                            /*!< PROT45 Bit Offset */
5900 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT45        ((uint32_t)0x00002000)          /*!< Protects Sector 45 from program or erase */
5901 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT46_OFS    (14)                            /*!< PROT46 Bit Offset */
5902 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT46        ((uint32_t)0x00004000)          /*!< Protects Sector 46 from program or erase */
5903 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT47_OFS    (15)                            /*!< PROT47 Bit Offset */
5904 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT47        ((uint32_t)0x00008000)          /*!< Protects Sector 47 from program or erase */
5905 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT48_OFS    (16)                            /*!< PROT48 Bit Offset */
5906 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT48        ((uint32_t)0x00010000)          /*!< Protects Sector 48 from program or erase */
5907 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT49_OFS    (17)                            /*!< PROT49 Bit Offset */
5908 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT49        ((uint32_t)0x00020000)          /*!< Protects Sector 49 from program or erase */
5909 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT50_OFS    (18)                            /*!< PROT50 Bit Offset */
5910 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT50        ((uint32_t)0x00040000)          /*!< Protects Sector 50 from program or erase */
5911 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT51_OFS    (19)                            /*!< PROT51 Bit Offset */
5912 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT51        ((uint32_t)0x00080000)          /*!< Protects Sector 51 from program or erase */
5913 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT52_OFS    (20)                            /*!< PROT52 Bit Offset */
5914 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT52        ((uint32_t)0x00100000)          /*!< Protects Sector 52 from program or erase */
5915 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT53_OFS    (21)                            /*!< PROT53 Bit Offset */
5916 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT53        ((uint32_t)0x00200000)          /*!< Protects Sector 53 from program or erase */
5917 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT54_OFS    (22)                            /*!< PROT54 Bit Offset */
5918 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT54        ((uint32_t)0x00400000)          /*!< Protects Sector 54 from program or erase */
5919 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT55_OFS    (23)                            /*!< PROT55 Bit Offset */
5920 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT55        ((uint32_t)0x00800000)          /*!< Protects Sector 55 from program or erase */
5921 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT56_OFS    (24)                            /*!< PROT56 Bit Offset */
5922 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT56        ((uint32_t)0x01000000)          /*!< Protects Sector 56 from program or erase */
5923 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT57_OFS    (25)                            /*!< PROT57 Bit Offset */
5924 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT57        ((uint32_t)0x02000000)          /*!< Protects Sector 57 from program or erase */
5925 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT58_OFS    (26)                            /*!< PROT58 Bit Offset */
5926 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT58        ((uint32_t)0x04000000)          /*!< Protects Sector 58 from program or erase */
5927 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT59_OFS    (27)                            /*!< PROT59 Bit Offset */
5928 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT59        ((uint32_t)0x08000000)          /*!< Protects Sector 59 from program or erase */
5929 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT60_OFS    (28)                            /*!< PROT60 Bit Offset */
5930 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT60        ((uint32_t)0x10000000)          /*!< Protects Sector 60 from program or erase */
5931 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT61_OFS    (29)                            /*!< PROT61 Bit Offset */
5932 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT61        ((uint32_t)0x20000000)          /*!< Protects Sector 61 from program or erase */
5933 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT62_OFS    (30)                            /*!< PROT62 Bit Offset */
5934 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT62        ((uint32_t)0x40000000)          /*!< Protects Sector 62 from program or erase */
5935 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT63_OFS    (31)                            /*!< PROT63 Bit Offset */
5936 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT63        ((uint32_t)0x80000000)          /*!< Protects Sector 63 from program or erase */
5937 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT64_OFS    ( 0)                            /*!< PROT64 Bit Offset */
5938 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT64        ((uint32_t)0x00000001)          /*!< Protects Sector 64 from program or erase */
5939 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT65_OFS    ( 1)                            /*!< PROT65 Bit Offset */
5940 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT65        ((uint32_t)0x00000002)          /*!< Protects Sector 65 from program or erase */
5941 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT66_OFS    ( 2)                            /*!< PROT66 Bit Offset */
5942 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT66        ((uint32_t)0x00000004)          /*!< Protects Sector 66 from program or erase */
5943 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT67_OFS    ( 3)                            /*!< PROT67 Bit Offset */
5944 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT67        ((uint32_t)0x00000008)          /*!< Protects Sector 67 from program or erase */
5945 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT68_OFS    ( 4)                            /*!< PROT68 Bit Offset */
5946 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT68        ((uint32_t)0x00000010)          /*!< Protects Sector 68 from program or erase */
5947 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT69_OFS    ( 5)                            /*!< PROT69 Bit Offset */
5948 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT69        ((uint32_t)0x00000020)          /*!< Protects Sector 69 from program or erase */
5949 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT70_OFS    ( 6)                            /*!< PROT70 Bit Offset */
5950 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT70        ((uint32_t)0x00000040)          /*!< Protects Sector 70 from program or erase */
5951 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT71_OFS    ( 7)                            /*!< PROT71 Bit Offset */
5952 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT71        ((uint32_t)0x00000080)          /*!< Protects Sector 71 from program or erase */
5953 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT72_OFS    ( 8)                            /*!< PROT72 Bit Offset */
5954 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT72        ((uint32_t)0x00000100)          /*!< Protects Sector 72 from program or erase */
5955 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT73_OFS    ( 9)                            /*!< PROT73 Bit Offset */
5956 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT73        ((uint32_t)0x00000200)          /*!< Protects Sector 73 from program or erase */
5957 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT74_OFS    (10)                            /*!< PROT74 Bit Offset */
5958 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT74        ((uint32_t)0x00000400)          /*!< Protects Sector 74 from program or erase */
5959 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT75_OFS    (11)                            /*!< PROT75 Bit Offset */
5960 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT75        ((uint32_t)0x00000800)          /*!< Protects Sector 75 from program or erase */
5961 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT76_OFS    (12)                            /*!< PROT76 Bit Offset */
5962 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT76        ((uint32_t)0x00001000)          /*!< Protects Sector 76 from program or erase */
5963 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT77_OFS    (13)                            /*!< PROT77 Bit Offset */
5964 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT77        ((uint32_t)0x00002000)          /*!< Protects Sector 77 from program or erase */
5965 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT78_OFS    (14)                            /*!< PROT78 Bit Offset */
5966 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT78        ((uint32_t)0x00004000)          /*!< Protects Sector 78 from program or erase */
5967 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT79_OFS    (15)                            /*!< PROT79 Bit Offset */
5968 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT79        ((uint32_t)0x00008000)          /*!< Protects Sector 79 from program or erase */
5969 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT80_OFS    (16)                            /*!< PROT80 Bit Offset */
5970 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT80        ((uint32_t)0x00010000)          /*!< Protects Sector 80 from program or erase */
5971 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT81_OFS    (17)                            /*!< PROT81 Bit Offset */
5972 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT81        ((uint32_t)0x00020000)          /*!< Protects Sector 81 from program or erase */
5973 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT82_OFS    (18)                            /*!< PROT82 Bit Offset */
5974 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT82        ((uint32_t)0x00040000)          /*!< Protects Sector 82 from program or erase */
5975 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT83_OFS    (19)                            /*!< PROT83 Bit Offset */
5976 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT83        ((uint32_t)0x00080000)          /*!< Protects Sector 83 from program or erase */
5977 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT84_OFS    (20)                            /*!< PROT84 Bit Offset */
5978 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT84        ((uint32_t)0x00100000)          /*!< Protects Sector 84 from program or erase */
5979 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT85_OFS    (21)                            /*!< PROT85 Bit Offset */
5980 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT85        ((uint32_t)0x00200000)          /*!< Protects Sector 85 from program or erase */
5981 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT86_OFS    (22)                            /*!< PROT86 Bit Offset */
5982 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT86        ((uint32_t)0x00400000)          /*!< Protects Sector 86 from program or erase */
5983 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT87_OFS    (23)                            /*!< PROT87 Bit Offset */
5984 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT87        ((uint32_t)0x00800000)          /*!< Protects Sector 87 from program or erase */
5985 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT88_OFS    (24)                            /*!< PROT88 Bit Offset */
5986 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT88        ((uint32_t)0x01000000)          /*!< Protects Sector 88 from program or erase */
5987 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT89_OFS    (25)                            /*!< PROT89 Bit Offset */
5988 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT89        ((uint32_t)0x02000000)          /*!< Protects Sector 89 from program or erase */
5989 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT90_OFS    (26)                            /*!< PROT90 Bit Offset */
5990 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT90        ((uint32_t)0x04000000)          /*!< Protects Sector 90 from program or erase */
5991 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT91_OFS    (27)                            /*!< PROT91 Bit Offset */
5992 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT91        ((uint32_t)0x08000000)          /*!< Protects Sector 91 from program or erase */
5993 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT92_OFS    (28)                            /*!< PROT92 Bit Offset */
5994 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT92        ((uint32_t)0x10000000)          /*!< Protects Sector 92 from program or erase */
5995 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT93_OFS    (29)                            /*!< PROT93 Bit Offset */
5996 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT93        ((uint32_t)0x20000000)          /*!< Protects Sector 93 from program or erase */
5997 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT94_OFS    (30)                            /*!< PROT94 Bit Offset */
5998 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT94        ((uint32_t)0x40000000)          /*!< Protects Sector 94 from program or erase */
5999 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT95_OFS    (31)                            /*!< PROT95 Bit Offset */
6000 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT95        ((uint32_t)0x80000000)          /*!< Protects Sector 95 from program or erase */
6001 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT96_OFS    ( 0)                            /*!< PROT96 Bit Offset */
6002 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT96        ((uint32_t)0x00000001)          /*!< Protects Sector 96 from program or erase */
6003 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT97_OFS    ( 1)                            /*!< PROT97 Bit Offset */
6004 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT97        ((uint32_t)0x00000002)          /*!< Protects Sector 97 from program or erase */
6005 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT98_OFS    ( 2)                            /*!< PROT98 Bit Offset */
6006 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT98        ((uint32_t)0x00000004)          /*!< Protects Sector 98 from program or erase */
6007 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT99_OFS    ( 3)                            /*!< PROT99 Bit Offset */
6008 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT99        ((uint32_t)0x00000008)          /*!< Protects Sector 99 from program or erase */
6009 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT100_OFS   ( 4)                            /*!< PROT100 Bit Offset */
6010 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT100       ((uint32_t)0x00000010)          /*!< Protects Sector 100 from program or erase */
6011 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT101_OFS   ( 5)                            /*!< PROT101 Bit Offset */
6012 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT101       ((uint32_t)0x00000020)          /*!< Protects Sector 101 from program or erase */
6013 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT102_OFS   ( 6)                            /*!< PROT102 Bit Offset */
6014 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT102       ((uint32_t)0x00000040)          /*!< Protects Sector 102 from program or erase */
6015 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT103_OFS   ( 7)                            /*!< PROT103 Bit Offset */
6016 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT103       ((uint32_t)0x00000080)          /*!< Protects Sector 103 from program or erase */
6017 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT104_OFS   ( 8)                            /*!< PROT104 Bit Offset */
6018 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT104       ((uint32_t)0x00000100)          /*!< Protects Sector 104 from program or erase */
6019 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT105_OFS   ( 9)                            /*!< PROT105 Bit Offset */
6020 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT105       ((uint32_t)0x00000200)          /*!< Protects Sector 105 from program or erase */
6021 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT106_OFS   (10)                            /*!< PROT106 Bit Offset */
6022 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT106       ((uint32_t)0x00000400)          /*!< Protects Sector 106 from program or erase */
6023 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT107_OFS   (11)                            /*!< PROT107 Bit Offset */
6024 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT107       ((uint32_t)0x00000800)          /*!< Protects Sector 107 from program or erase */
6025 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT108_OFS   (12)                            /*!< PROT108 Bit Offset */
6026 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT108       ((uint32_t)0x00001000)          /*!< Protects Sector 108 from program or erase */
6027 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT109_OFS   (13)                            /*!< PROT109 Bit Offset */
6028 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT109       ((uint32_t)0x00002000)          /*!< Protects Sector 109 from program or erase */
6029 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT110_OFS   (14)                            /*!< PROT110 Bit Offset */
6030 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT110       ((uint32_t)0x00004000)          /*!< Protects Sector 110 from program or erase */
6031 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT111_OFS   (15)                            /*!< PROT111 Bit Offset */
6032 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT111       ((uint32_t)0x00008000)          /*!< Protects Sector 111 from program or erase */
6033 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT112_OFS   (16)                            /*!< PROT112 Bit Offset */
6034 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT112       ((uint32_t)0x00010000)          /*!< Protects Sector 112 from program or erase */
6035 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT113_OFS   (17)                            /*!< PROT113 Bit Offset */
6036 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT113       ((uint32_t)0x00020000)          /*!< Protects Sector 113 from program or erase */
6037 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT114_OFS   (18)                            /*!< PROT114 Bit Offset */
6038 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT114       ((uint32_t)0x00040000)          /*!< Protects Sector 114 from program or erase */
6039 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT115_OFS   (19)                            /*!< PROT115 Bit Offset */
6040 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT115       ((uint32_t)0x00080000)          /*!< Protects Sector 115 from program or erase */
6041 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT116_OFS   (20)                            /*!< PROT116 Bit Offset */
6042 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT116       ((uint32_t)0x00100000)          /*!< Protects Sector 116 from program or erase */
6043 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT117_OFS   (21)                            /*!< PROT117 Bit Offset */
6044 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT117       ((uint32_t)0x00200000)          /*!< Protects Sector 117 from program or erase */
6045 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT118_OFS   (22)                            /*!< PROT118 Bit Offset */
6046 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT118       ((uint32_t)0x00400000)          /*!< Protects Sector 118 from program or erase */
6047 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT119_OFS   (23)                            /*!< PROT119 Bit Offset */
6048 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT119       ((uint32_t)0x00800000)          /*!< Protects Sector 119 from program or erase */
6049 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT120_OFS   (24)                            /*!< PROT120 Bit Offset */
6050 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT120       ((uint32_t)0x01000000)          /*!< Protects Sector 120 from program or erase */
6051 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT121_OFS   (25)                            /*!< PROT121 Bit Offset */
6052 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT121       ((uint32_t)0x02000000)          /*!< Protects Sector 121 from program or erase */
6053 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT122_OFS   (26)                            /*!< PROT122 Bit Offset */
6054 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT122       ((uint32_t)0x04000000)          /*!< Protects Sector 122 from program or erase */
6055 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT123_OFS   (27)                            /*!< PROT123 Bit Offset */
6056 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT123       ((uint32_t)0x08000000)          /*!< Protects Sector 123 from program or erase */
6057 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT124_OFS   (28)                            /*!< PROT124 Bit Offset */
6058 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT124       ((uint32_t)0x10000000)          /*!< Protects Sector 124 from program or erase */
6059 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT125_OFS   (29)                            /*!< PROT125 Bit Offset */
6060 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT125       ((uint32_t)0x20000000)          /*!< Protects Sector 125 from program or erase */
6061 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT126_OFS   (30)                            /*!< PROT126 Bit Offset */
6062 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT126       ((uint32_t)0x40000000)          /*!< Protects Sector 126 from program or erase */
6063 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT127_OFS   (31)                            /*!< PROT127 Bit Offset */
6064 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT127       ((uint32_t)0x80000000)          /*!< Protects Sector 127 from program or erase */
6065 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT128_OFS   ( 0)                            /*!< PROT128 Bit Offset */
6066 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT128       ((uint32_t)0x00000001)          /*!< Protects Sector 128 from program or erase */
6067 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT129_OFS   ( 1)                            /*!< PROT129 Bit Offset */
6068 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT129       ((uint32_t)0x00000002)          /*!< Protects Sector 129 from program or erase */
6069 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT130_OFS   ( 2)                            /*!< PROT130 Bit Offset */
6070 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT130       ((uint32_t)0x00000004)          /*!< Protects Sector 130 from program or erase */
6071 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT131_OFS   ( 3)                            /*!< PROT131 Bit Offset */
6072 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT131       ((uint32_t)0x00000008)          /*!< Protects Sector 131 from program or erase */
6073 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT132_OFS   ( 4)                            /*!< PROT132 Bit Offset */
6074 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT132       ((uint32_t)0x00000010)          /*!< Protects Sector 132 from program or erase */
6075 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT133_OFS   ( 5)                            /*!< PROT133 Bit Offset */
6076 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT133       ((uint32_t)0x00000020)          /*!< Protects Sector 133 from program or erase */
6077 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT134_OFS   ( 6)                            /*!< PROT134 Bit Offset */
6078 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT134       ((uint32_t)0x00000040)          /*!< Protects Sector 134 from program or erase */
6079 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT135_OFS   ( 7)                            /*!< PROT135 Bit Offset */
6080 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT135       ((uint32_t)0x00000080)          /*!< Protects Sector 135 from program or erase */
6081 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT136_OFS   ( 8)                            /*!< PROT136 Bit Offset */
6082 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT136       ((uint32_t)0x00000100)          /*!< Protects Sector 136 from program or erase */
6083 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT137_OFS   ( 9)                            /*!< PROT137 Bit Offset */
6084 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT137       ((uint32_t)0x00000200)          /*!< Protects Sector 137 from program or erase */
6085 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT138_OFS   (10)                            /*!< PROT138 Bit Offset */
6086 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT138       ((uint32_t)0x00000400)          /*!< Protects Sector 138 from program or erase */
6087 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT139_OFS   (11)                            /*!< PROT139 Bit Offset */
6088 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT139       ((uint32_t)0x00000800)          /*!< Protects Sector 139 from program or erase */
6089 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT140_OFS   (12)                            /*!< PROT140 Bit Offset */
6090 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT140       ((uint32_t)0x00001000)          /*!< Protects Sector 140 from program or erase */
6091 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT141_OFS   (13)                            /*!< PROT141 Bit Offset */
6092 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT141       ((uint32_t)0x00002000)          /*!< Protects Sector 141 from program or erase */
6093 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT142_OFS   (14)                            /*!< PROT142 Bit Offset */
6094 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT142       ((uint32_t)0x00004000)          /*!< Protects Sector 142 from program or erase */
6095 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT143_OFS   (15)                            /*!< PROT143 Bit Offset */
6096 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT143       ((uint32_t)0x00008000)          /*!< Protects Sector 143 from program or erase */
6097 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT144_OFS   (16)                            /*!< PROT144 Bit Offset */
6098 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT144       ((uint32_t)0x00010000)          /*!< Protects Sector 144 from program or erase */
6099 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT145_OFS   (17)                            /*!< PROT145 Bit Offset */
6100 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT145       ((uint32_t)0x00020000)          /*!< Protects Sector 145 from program or erase */
6101 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT146_OFS   (18)                            /*!< PROT146 Bit Offset */
6102 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT146       ((uint32_t)0x00040000)          /*!< Protects Sector 146 from program or erase */
6103 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT147_OFS   (19)                            /*!< PROT147 Bit Offset */
6104 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT147       ((uint32_t)0x00080000)          /*!< Protects Sector 147 from program or erase */
6105 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT148_OFS   (20)                            /*!< PROT148 Bit Offset */
6106 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT148       ((uint32_t)0x00100000)          /*!< Protects Sector 148 from program or erase */
6107 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT149_OFS   (21)                            /*!< PROT149 Bit Offset */
6108 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT149       ((uint32_t)0x00200000)          /*!< Protects Sector 149 from program or erase */
6109 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT150_OFS   (22)                            /*!< PROT150 Bit Offset */
6110 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT150       ((uint32_t)0x00400000)          /*!< Protects Sector 150 from program or erase */
6111 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT151_OFS   (23)                            /*!< PROT151 Bit Offset */
6112 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT151       ((uint32_t)0x00800000)          /*!< Protects Sector 151 from program or erase */
6113 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT152_OFS   (24)                            /*!< PROT152 Bit Offset */
6114 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT152       ((uint32_t)0x01000000)          /*!< Protects Sector 152 from program or erase */
6115 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT153_OFS   (25)                            /*!< PROT153 Bit Offset */
6116 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT153       ((uint32_t)0x02000000)          /*!< Protects Sector 153 from program or erase */
6117 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT154_OFS   (26)                            /*!< PROT154 Bit Offset */
6118 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT154       ((uint32_t)0x04000000)          /*!< Protects Sector 154 from program or erase */
6119 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT155_OFS   (27)                            /*!< PROT155 Bit Offset */
6120 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT155       ((uint32_t)0x08000000)          /*!< Protects Sector 155 from program or erase */
6121 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT156_OFS   (28)                            /*!< PROT156 Bit Offset */
6122 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT156       ((uint32_t)0x10000000)          /*!< Protects Sector 156 from program or erase */
6123 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT157_OFS   (29)                            /*!< PROT157 Bit Offset */
6124 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT157       ((uint32_t)0x20000000)          /*!< Protects Sector 157 from program or erase */
6125 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT158_OFS   (30)                            /*!< PROT158 Bit Offset */
6126 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT158       ((uint32_t)0x40000000)          /*!< Protects Sector 158 from program or erase */
6127 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT159_OFS   (31)                            /*!< PROT159 Bit Offset */
6128 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT159       ((uint32_t)0x80000000)          /*!< Protects Sector 159 from program or erase */
6129 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT160_OFS   ( 0)                            /*!< PROT160 Bit Offset */
6130 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT160       ((uint32_t)0x00000001)          /*!< Protects Sector 160 from program or erase */
6131 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT161_OFS   ( 1)                            /*!< PROT161 Bit Offset */
6132 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT161       ((uint32_t)0x00000002)          /*!< Protects Sector 161 from program or erase */
6133 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT162_OFS   ( 2)                            /*!< PROT162 Bit Offset */
6134 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT162       ((uint32_t)0x00000004)          /*!< Protects Sector 162 from program or erase */
6135 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT163_OFS   ( 3)                            /*!< PROT163 Bit Offset */
6136 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT163       ((uint32_t)0x00000008)          /*!< Protects Sector 163 from program or erase */
6137 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT164_OFS   ( 4)                            /*!< PROT164 Bit Offset */
6138 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT164       ((uint32_t)0x00000010)          /*!< Protects Sector 164 from program or erase */
6139 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT165_OFS   ( 5)                            /*!< PROT165 Bit Offset */
6140 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT165       ((uint32_t)0x00000020)          /*!< Protects Sector 165 from program or erase */
6141 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT166_OFS   ( 6)                            /*!< PROT166 Bit Offset */
6142 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT166       ((uint32_t)0x00000040)          /*!< Protects Sector 166 from program or erase */
6143 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT167_OFS   ( 7)                            /*!< PROT167 Bit Offset */
6144 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT167       ((uint32_t)0x00000080)          /*!< Protects Sector 167 from program or erase */
6145 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT168_OFS   ( 8)                            /*!< PROT168 Bit Offset */
6146 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT168       ((uint32_t)0x00000100)          /*!< Protects Sector 168 from program or erase */
6147 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT169_OFS   ( 9)                            /*!< PROT169 Bit Offset */
6148 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT169       ((uint32_t)0x00000200)          /*!< Protects Sector 169 from program or erase */
6149 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT170_OFS   (10)                            /*!< PROT170 Bit Offset */
6150 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT170       ((uint32_t)0x00000400)          /*!< Protects Sector 170 from program or erase */
6151 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT171_OFS   (11)                            /*!< PROT171 Bit Offset */
6152 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT171       ((uint32_t)0x00000800)          /*!< Protects Sector 171 from program or erase */
6153 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT172_OFS   (12)                            /*!< PROT172 Bit Offset */
6154 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT172       ((uint32_t)0x00001000)          /*!< Protects Sector 172 from program or erase */
6155 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT173_OFS   (13)                            /*!< PROT173 Bit Offset */
6156 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT173       ((uint32_t)0x00002000)          /*!< Protects Sector 173 from program or erase */
6157 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT174_OFS   (14)                            /*!< PROT174 Bit Offset */
6158 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT174       ((uint32_t)0x00004000)          /*!< Protects Sector 174 from program or erase */
6159 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT175_OFS   (15)                            /*!< PROT175 Bit Offset */
6160 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT175       ((uint32_t)0x00008000)          /*!< Protects Sector 175 from program or erase */
6161 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT176_OFS   (16)                            /*!< PROT176 Bit Offset */
6162 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT176       ((uint32_t)0x00010000)          /*!< Protects Sector 176 from program or erase */
6163 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT177_OFS   (17)                            /*!< PROT177 Bit Offset */
6164 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT177       ((uint32_t)0x00020000)          /*!< Protects Sector 177 from program or erase */
6165 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT178_OFS   (18)                            /*!< PROT178 Bit Offset */
6166 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT178       ((uint32_t)0x00040000)          /*!< Protects Sector 178 from program or erase */
6167 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT179_OFS   (19)                            /*!< PROT179 Bit Offset */
6168 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT179       ((uint32_t)0x00080000)          /*!< Protects Sector 179 from program or erase */
6169 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT180_OFS   (20)                            /*!< PROT180 Bit Offset */
6170 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT180       ((uint32_t)0x00100000)          /*!< Protects Sector 180 from program or erase */
6171 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT181_OFS   (21)                            /*!< PROT181 Bit Offset */
6172 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT181       ((uint32_t)0x00200000)          /*!< Protects Sector 181 from program or erase */
6173 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT182_OFS   (22)                            /*!< PROT182 Bit Offset */
6174 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT182       ((uint32_t)0x00400000)          /*!< Protects Sector 182 from program or erase */
6175 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT183_OFS   (23)                            /*!< PROT183 Bit Offset */
6176 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT183       ((uint32_t)0x00800000)          /*!< Protects Sector 183 from program or erase */
6177 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT184_OFS   (24)                            /*!< PROT184 Bit Offset */
6178 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT184       ((uint32_t)0x01000000)          /*!< Protects Sector 184 from program or erase */
6179 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT185_OFS   (25)                            /*!< PROT185 Bit Offset */
6180 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT185       ((uint32_t)0x02000000)          /*!< Protects Sector 185 from program or erase */
6181 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT186_OFS   (26)                            /*!< PROT186 Bit Offset */
6182 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT186       ((uint32_t)0x04000000)          /*!< Protects Sector 186 from program or erase */
6183 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT187_OFS   (27)                            /*!< PROT187 Bit Offset */
6184 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT187       ((uint32_t)0x08000000)          /*!< Protects Sector 187 from program or erase */
6185 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT188_OFS   (28)                            /*!< PROT188 Bit Offset */
6186 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT188       ((uint32_t)0x10000000)          /*!< Protects Sector 188 from program or erase */
6187 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT189_OFS   (29)                            /*!< PROT189 Bit Offset */
6188 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT189       ((uint32_t)0x20000000)          /*!< Protects Sector 189 from program or erase */
6189 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT190_OFS   (30)                            /*!< PROT190 Bit Offset */
6190 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT190       ((uint32_t)0x40000000)          /*!< Protects Sector 190 from program or erase */
6191 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT191_OFS   (31)                            /*!< PROT191 Bit Offset */
6192 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT191       ((uint32_t)0x80000000)          /*!< Protects Sector 191 from program or erase */
6193 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT192_OFS   ( 0)                            /*!< PROT192 Bit Offset */
6194 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT192       ((uint32_t)0x00000001)          /*!< Protects Sector 192 from program or erase */
6195 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT193_OFS   ( 1)                            /*!< PROT193 Bit Offset */
6196 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT193       ((uint32_t)0x00000002)          /*!< Protects Sector 193 from program or erase */
6197 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT194_OFS   ( 2)                            /*!< PROT194 Bit Offset */
6198 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT194       ((uint32_t)0x00000004)          /*!< Protects Sector 194 from program or erase */
6199 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT195_OFS   ( 3)                            /*!< PROT195 Bit Offset */
6200 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT195       ((uint32_t)0x00000008)          /*!< Protects Sector 195 from program or erase */
6201 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT196_OFS   ( 4)                            /*!< PROT196 Bit Offset */
6202 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT196       ((uint32_t)0x00000010)          /*!< Protects Sector 196 from program or erase */
6203 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT197_OFS   ( 5)                            /*!< PROT197 Bit Offset */
6204 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT197       ((uint32_t)0x00000020)          /*!< Protects Sector 197 from program or erase */
6205 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT198_OFS   ( 6)                            /*!< PROT198 Bit Offset */
6206 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT198       ((uint32_t)0x00000040)          /*!< Protects Sector 198 from program or erase */
6207 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT199_OFS   ( 7)                            /*!< PROT199 Bit Offset */
6208 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT199       ((uint32_t)0x00000080)          /*!< Protects Sector 199 from program or erase */
6209 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT200_OFS   ( 8)                            /*!< PROT200 Bit Offset */
6210 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT200       ((uint32_t)0x00000100)          /*!< Protects Sector 200 from program or erase */
6211 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT201_OFS   ( 9)                            /*!< PROT201 Bit Offset */
6212 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT201       ((uint32_t)0x00000200)          /*!< Protects Sector 201 from program or erase */
6213 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT202_OFS   (10)                            /*!< PROT202 Bit Offset */
6214 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT202       ((uint32_t)0x00000400)          /*!< Protects Sector 202 from program or erase */
6215 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT203_OFS   (11)                            /*!< PROT203 Bit Offset */
6216 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT203       ((uint32_t)0x00000800)          /*!< Protects Sector 203 from program or erase */
6217 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT204_OFS   (12)                            /*!< PROT204 Bit Offset */
6218 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT204       ((uint32_t)0x00001000)          /*!< Protects Sector 204 from program or erase */
6219 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT205_OFS   (13)                            /*!< PROT205 Bit Offset */
6220 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT205       ((uint32_t)0x00002000)          /*!< Protects Sector 205 from program or erase */
6221 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT206_OFS   (14)                            /*!< PROT206 Bit Offset */
6222 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT206       ((uint32_t)0x00004000)          /*!< Protects Sector 206 from program or erase */
6223 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT207_OFS   (15)                            /*!< PROT207 Bit Offset */
6224 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT207       ((uint32_t)0x00008000)          /*!< Protects Sector 207 from program or erase */
6225 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT208_OFS   (16)                            /*!< PROT208 Bit Offset */
6226 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT208       ((uint32_t)0x00010000)          /*!< Protects Sector 208 from program or erase */
6227 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT209_OFS   (17)                            /*!< PROT209 Bit Offset */
6228 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT209       ((uint32_t)0x00020000)          /*!< Protects Sector 209 from program or erase */
6229 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT210_OFS   (18)                            /*!< PROT210 Bit Offset */
6230 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT210       ((uint32_t)0x00040000)          /*!< Protects Sector 210 from program or erase */
6231 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT211_OFS   (19)                            /*!< PROT211 Bit Offset */
6232 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT211       ((uint32_t)0x00080000)          /*!< Protects Sector 211 from program or erase */
6233 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT212_OFS   (20)                            /*!< PROT212 Bit Offset */
6234 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT212       ((uint32_t)0x00100000)          /*!< Protects Sector 212 from program or erase */
6235 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT213_OFS   (21)                            /*!< PROT213 Bit Offset */
6236 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT213       ((uint32_t)0x00200000)          /*!< Protects Sector 213 from program or erase */
6237 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT214_OFS   (22)                            /*!< PROT214 Bit Offset */
6238 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT214       ((uint32_t)0x00400000)          /*!< Protects Sector 214 from program or erase */
6239 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT215_OFS   (23)                            /*!< PROT215 Bit Offset */
6240 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT215       ((uint32_t)0x00800000)          /*!< Protects Sector 215 from program or erase */
6241 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT216_OFS   (24)                            /*!< PROT216 Bit Offset */
6242 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT216       ((uint32_t)0x01000000)          /*!< Protects Sector 216 from program or erase */
6243 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT217_OFS   (25)                            /*!< PROT217 Bit Offset */
6244 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT217       ((uint32_t)0x02000000)          /*!< Protects Sector 217 from program or erase */
6245 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT218_OFS   (26)                            /*!< PROT218 Bit Offset */
6246 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT218       ((uint32_t)0x04000000)          /*!< Protects Sector 218 from program or erase */
6247 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT219_OFS   (27)                            /*!< PROT219 Bit Offset */
6248 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT219       ((uint32_t)0x08000000)          /*!< Protects Sector 219 from program or erase */
6249 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT220_OFS   (28)                            /*!< PROT220 Bit Offset */
6250 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT220       ((uint32_t)0x10000000)          /*!< Protects Sector 220 from program or erase */
6251 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT221_OFS   (29)                            /*!< PROT221 Bit Offset */
6252 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT221       ((uint32_t)0x20000000)          /*!< Protects Sector 221 from program or erase */
6253 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT222_OFS   (30)                            /*!< PROT222 Bit Offset */
6254 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT222       ((uint32_t)0x40000000)          /*!< Protects Sector 222 from program or erase */
6255 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT223_OFS   (31)                            /*!< PROT223 Bit Offset */
6256 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT223       ((uint32_t)0x80000000)          /*!< Protects Sector 223 from program or erase */
6257 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT224_OFS   ( 0)                            /*!< PROT224 Bit Offset */
6258 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT224       ((uint32_t)0x00000001)          /*!< Protects Sector 224 from program or erase */
6259 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT225_OFS   ( 1)                            /*!< PROT225 Bit Offset */
6260 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT225       ((uint32_t)0x00000002)          /*!< Protects Sector 225 from program or erase */
6261 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT226_OFS   ( 2)                            /*!< PROT226 Bit Offset */
6262 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT226       ((uint32_t)0x00000004)          /*!< Protects Sector 226 from program or erase */
6263 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT227_OFS   ( 3)                            /*!< PROT227 Bit Offset */
6264 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT227       ((uint32_t)0x00000008)          /*!< Protects Sector 227 from program or erase */
6265 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT228_OFS   ( 4)                            /*!< PROT228 Bit Offset */
6266 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT228       ((uint32_t)0x00000010)          /*!< Protects Sector 228 from program or erase */
6267 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT229_OFS   ( 5)                            /*!< PROT229 Bit Offset */
6268 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT229       ((uint32_t)0x00000020)          /*!< Protects Sector 229 from program or erase */
6269 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT230_OFS   ( 6)                            /*!< PROT230 Bit Offset */
6270 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT230       ((uint32_t)0x00000040)          /*!< Protects Sector 230 from program or erase */
6271 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT231_OFS   ( 7)                            /*!< PROT231 Bit Offset */
6272 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT231       ((uint32_t)0x00000080)          /*!< Protects Sector 231 from program or erase */
6273 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT232_OFS   ( 8)                            /*!< PROT232 Bit Offset */
6274 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT232       ((uint32_t)0x00000100)          /*!< Protects Sector 232 from program or erase */
6275 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT233_OFS   ( 9)                            /*!< PROT233 Bit Offset */
6276 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT233       ((uint32_t)0x00000200)          /*!< Protects Sector 233 from program or erase */
6277 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT234_OFS   (10)                            /*!< PROT234 Bit Offset */
6278 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT234       ((uint32_t)0x00000400)          /*!< Protects Sector 234 from program or erase */
6279 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT235_OFS   (11)                            /*!< PROT235 Bit Offset */
6280 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT235       ((uint32_t)0x00000800)          /*!< Protects Sector 235 from program or erase */
6281 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT236_OFS   (12)                            /*!< PROT236 Bit Offset */
6282 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT236       ((uint32_t)0x00001000)          /*!< Protects Sector 236 from program or erase */
6283 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT237_OFS   (13)                            /*!< PROT237 Bit Offset */
6284 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT237       ((uint32_t)0x00002000)          /*!< Protects Sector 237 from program or erase */
6285 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT238_OFS   (14)                            /*!< PROT238 Bit Offset */
6286 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT238       ((uint32_t)0x00004000)          /*!< Protects Sector 238 from program or erase */
6287 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT239_OFS   (15)                            /*!< PROT239 Bit Offset */
6288 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT239       ((uint32_t)0x00008000)          /*!< Protects Sector 239 from program or erase */
6289 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT240_OFS   (16)                            /*!< PROT240 Bit Offset */
6290 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT240       ((uint32_t)0x00010000)          /*!< Protects Sector 240 from program or erase */
6291 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT241_OFS   (17)                            /*!< PROT241 Bit Offset */
6292 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT241       ((uint32_t)0x00020000)          /*!< Protects Sector 241 from program or erase */
6293 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT242_OFS   (18)                            /*!< PROT242 Bit Offset */
6294 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT242       ((uint32_t)0x00040000)          /*!< Protects Sector 242 from program or erase */
6295 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT243_OFS   (19)                            /*!< PROT243 Bit Offset */
6296 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT243       ((uint32_t)0x00080000)          /*!< Protects Sector 243 from program or erase */
6297 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT244_OFS   (20)                            /*!< PROT244 Bit Offset */
6298 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT244       ((uint32_t)0x00100000)          /*!< Protects Sector 244 from program or erase */
6299 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT245_OFS   (21)                            /*!< PROT245 Bit Offset */
6300 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT245       ((uint32_t)0x00200000)          /*!< Protects Sector 245 from program or erase */
6301 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT246_OFS   (22)                            /*!< PROT246 Bit Offset */
6302 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT246       ((uint32_t)0x00400000)          /*!< Protects Sector 246 from program or erase */
6303 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT247_OFS   (23)                            /*!< PROT247 Bit Offset */
6304 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT247       ((uint32_t)0x00800000)          /*!< Protects Sector 247 from program or erase */
6305 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT248_OFS   (24)                            /*!< PROT248 Bit Offset */
6306 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT248       ((uint32_t)0x01000000)          /*!< Protects Sector 248 from program or erase */
6307 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT249_OFS   (25)                            /*!< PROT249 Bit Offset */
6308 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT249       ((uint32_t)0x02000000)          /*!< Protects Sector 249 from program or erase */
6309 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT250_OFS   (26)                            /*!< PROT250 Bit Offset */
6310 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT250       ((uint32_t)0x04000000)          /*!< Protects Sector 250 from program or erase */
6311 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT251_OFS   (27)                            /*!< PROT251 Bit Offset */
6312 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT251       ((uint32_t)0x08000000)          /*!< Protects Sector 251 from program or erase */
6313 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT252_OFS   (28)                            /*!< PROT252 Bit Offset */
6314 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT252       ((uint32_t)0x10000000)          /*!< Protects Sector 252 from program or erase */
6315 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT253_OFS   (29)                            /*!< PROT253 Bit Offset */
6316 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT253       ((uint32_t)0x20000000)          /*!< Protects Sector 253 from program or erase */
6317 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT254_OFS   (30)                            /*!< PROT254 Bit Offset */
6318 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT254       ((uint32_t)0x40000000)          /*!< Protects Sector 254 from program or erase */
6319 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT255_OFS   (31)                            /*!< PROT255 Bit Offset */
6320 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT255       ((uint32_t)0x80000000)          /*!< Protects Sector 255 from program or erase */
6321 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT0_OFS     ( 0)                            /*!< PROT0 Bit Offset */
6322 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT0         ((uint32_t)0x00000001)          /*!< Protects Sector 0 from program or erase */
6323 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT1_OFS     ( 1)                            /*!< PROT1 Bit Offset */
6324 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT1         ((uint32_t)0x00000002)          /*!< Protects Sector 1 from program or erase */
6325 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT2_OFS     ( 2)                            /*!< PROT2 Bit Offset */
6326 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT2         ((uint32_t)0x00000004)          /*!< Protects Sector 2 from program or erase */
6327 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT3_OFS     ( 3)                            /*!< PROT3 Bit Offset */
6328 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT3         ((uint32_t)0x00000008)          /*!< Protects Sector 3 from program or erase */
6329 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT4_OFS     ( 4)                            /*!< PROT4 Bit Offset */
6330 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT4         ((uint32_t)0x00000010)          /*!< Protects Sector 4 from program or erase */
6331 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT5_OFS     ( 5)                            /*!< PROT5 Bit Offset */
6332 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT5         ((uint32_t)0x00000020)          /*!< Protects Sector 5 from program or erase */
6333 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT6_OFS     ( 6)                            /*!< PROT6 Bit Offset */
6334 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT6         ((uint32_t)0x00000040)          /*!< Protects Sector 6 from program or erase */
6335 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT7_OFS     ( 7)                            /*!< PROT7 Bit Offset */
6336 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT7         ((uint32_t)0x00000080)          /*!< Protects Sector 7 from program or erase */
6337 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT8_OFS     ( 8)                            /*!< PROT8 Bit Offset */
6338 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT8         ((uint32_t)0x00000100)          /*!< Protects Sector 8 from program or erase */
6339 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT9_OFS     ( 9)                            /*!< PROT9 Bit Offset */
6340 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT9         ((uint32_t)0x00000200)          /*!< Protects Sector 9 from program or erase */
6341 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT10_OFS    (10)                            /*!< PROT10 Bit Offset */
6342 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT10        ((uint32_t)0x00000400)          /*!< Protects Sector 10 from program or erase */
6343 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT11_OFS    (11)                            /*!< PROT11 Bit Offset */
6344 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT11        ((uint32_t)0x00000800)          /*!< Protects Sector 11 from program or erase */
6345 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT12_OFS    (12)                            /*!< PROT12 Bit Offset */
6346 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT12        ((uint32_t)0x00001000)          /*!< Protects Sector 12 from program or erase */
6347 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT13_OFS    (13)                            /*!< PROT13 Bit Offset */
6348 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT13        ((uint32_t)0x00002000)          /*!< Protects Sector 13 from program or erase */
6349 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT14_OFS    (14)                            /*!< PROT14 Bit Offset */
6350 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT14        ((uint32_t)0x00004000)          /*!< Protects Sector 14 from program or erase */
6351 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT15_OFS    (15)                            /*!< PROT15 Bit Offset */
6352 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT15        ((uint32_t)0x00008000)          /*!< Protects Sector 15 from program or erase */
6353 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT16_OFS    (16)                            /*!< PROT16 Bit Offset */
6354 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT16        ((uint32_t)0x00010000)          /*!< Protects Sector 16 from program or erase */
6355 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT17_OFS    (17)                            /*!< PROT17 Bit Offset */
6356 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT17        ((uint32_t)0x00020000)          /*!< Protects Sector 17 from program or erase */
6357 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT18_OFS    (18)                            /*!< PROT18 Bit Offset */
6358 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT18        ((uint32_t)0x00040000)          /*!< Protects Sector 18 from program or erase */
6359 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT19_OFS    (19)                            /*!< PROT19 Bit Offset */
6360 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT19        ((uint32_t)0x00080000)          /*!< Protects Sector 19 from program or erase */
6361 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT20_OFS    (20)                            /*!< PROT20 Bit Offset */
6362 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT20        ((uint32_t)0x00100000)          /*!< Protects Sector 20 from program or erase */
6363 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT21_OFS    (21)                            /*!< PROT21 Bit Offset */
6364 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT21        ((uint32_t)0x00200000)          /*!< Protects Sector 21 from program or erase */
6365 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT22_OFS    (22)                            /*!< PROT22 Bit Offset */
6366 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT22        ((uint32_t)0x00400000)          /*!< Protects Sector 22 from program or erase */
6367 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT23_OFS    (23)                            /*!< PROT23 Bit Offset */
6368 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT23        ((uint32_t)0x00800000)          /*!< Protects Sector 23 from program or erase */
6369 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT24_OFS    (24)                            /*!< PROT24 Bit Offset */
6370 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT24        ((uint32_t)0x01000000)          /*!< Protects Sector 24 from program or erase */
6371 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT25_OFS    (25)                            /*!< PROT25 Bit Offset */
6372 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT25        ((uint32_t)0x02000000)          /*!< Protects Sector 25 from program or erase */
6373 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT26_OFS    (26)                            /*!< PROT26 Bit Offset */
6374 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT26        ((uint32_t)0x04000000)          /*!< Protects Sector 26 from program or erase */
6375 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT27_OFS    (27)                            /*!< PROT27 Bit Offset */
6376 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT27        ((uint32_t)0x08000000)          /*!< Protects Sector 27 from program or erase */
6377 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT28_OFS    (28)                            /*!< PROT28 Bit Offset */
6378 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT28        ((uint32_t)0x10000000)          /*!< Protects Sector 28 from program or erase */
6379 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT29_OFS    (29)                            /*!< PROT29 Bit Offset */
6380 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT29        ((uint32_t)0x20000000)          /*!< Protects Sector 29 from program or erase */
6381 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT30_OFS    (30)                            /*!< PROT30 Bit Offset */
6382 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT30        ((uint32_t)0x40000000)          /*!< Protects Sector 30 from program or erase */
6383 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT31_OFS    (31)                            /*!< PROT31 Bit Offset */
6384 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT31        ((uint32_t)0x80000000)          /*!< Protects Sector 31 from program or erase */
6385 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT32_OFS    ( 0)                            /*!< PROT32 Bit Offset */
6386 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT32        ((uint32_t)0x00000001)          /*!< Protects Sector 32 from program or erase */
6387 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT33_OFS    ( 1)                            /*!< PROT33 Bit Offset */
6388 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT33        ((uint32_t)0x00000002)          /*!< Protects Sector 33 from program or erase */
6389 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT34_OFS    ( 2)                            /*!< PROT34 Bit Offset */
6390 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT34        ((uint32_t)0x00000004)          /*!< Protects Sector 34 from program or erase */
6391 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT35_OFS    ( 3)                            /*!< PROT35 Bit Offset */
6392 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT35        ((uint32_t)0x00000008)          /*!< Protects Sector 35 from program or erase */
6393 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT36_OFS    ( 4)                            /*!< PROT36 Bit Offset */
6394 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT36        ((uint32_t)0x00000010)          /*!< Protects Sector 36 from program or erase */
6395 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT37_OFS    ( 5)                            /*!< PROT37 Bit Offset */
6396 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT37        ((uint32_t)0x00000020)          /*!< Protects Sector 37 from program or erase */
6397 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT38_OFS    ( 6)                            /*!< PROT38 Bit Offset */
6398 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT38        ((uint32_t)0x00000040)          /*!< Protects Sector 38 from program or erase */
6399 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT39_OFS    ( 7)                            /*!< PROT39 Bit Offset */
6400 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT39        ((uint32_t)0x00000080)          /*!< Protects Sector 39 from program or erase */
6401 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT40_OFS    ( 8)                            /*!< PROT40 Bit Offset */
6402 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT40        ((uint32_t)0x00000100)          /*!< Protects Sector 40 from program or erase */
6403 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT41_OFS    ( 9)                            /*!< PROT41 Bit Offset */
6404 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT41        ((uint32_t)0x00000200)          /*!< Protects Sector 41 from program or erase */
6405 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT42_OFS    (10)                            /*!< PROT42 Bit Offset */
6406 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT42        ((uint32_t)0x00000400)          /*!< Protects Sector 42 from program or erase */
6407 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT43_OFS    (11)                            /*!< PROT43 Bit Offset */
6408 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT43        ((uint32_t)0x00000800)          /*!< Protects Sector 43 from program or erase */
6409 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT44_OFS    (12)                            /*!< PROT44 Bit Offset */
6410 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT44        ((uint32_t)0x00001000)          /*!< Protects Sector 44 from program or erase */
6411 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT45_OFS    (13)                            /*!< PROT45 Bit Offset */
6412 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT45        ((uint32_t)0x00002000)          /*!< Protects Sector 45 from program or erase */
6413 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT46_OFS    (14)                            /*!< PROT46 Bit Offset */
6414 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT46        ((uint32_t)0x00004000)          /*!< Protects Sector 46 from program or erase */
6415 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT47_OFS    (15)                            /*!< PROT47 Bit Offset */
6416 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT47        ((uint32_t)0x00008000)          /*!< Protects Sector 47 from program or erase */
6417 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT48_OFS    (16)                            /*!< PROT48 Bit Offset */
6418 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT48        ((uint32_t)0x00010000)          /*!< Protects Sector 48 from program or erase */
6419 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT49_OFS    (17)                            /*!< PROT49 Bit Offset */
6420 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT49        ((uint32_t)0x00020000)          /*!< Protects Sector 49 from program or erase */
6421 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT50_OFS    (18)                            /*!< PROT50 Bit Offset */
6422 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT50        ((uint32_t)0x00040000)          /*!< Protects Sector 50 from program or erase */
6423 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT51_OFS    (19)                            /*!< PROT51 Bit Offset */
6424 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT51        ((uint32_t)0x00080000)          /*!< Protects Sector 51 from program or erase */
6425 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT52_OFS    (20)                            /*!< PROT52 Bit Offset */
6426 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT52        ((uint32_t)0x00100000)          /*!< Protects Sector 52 from program or erase */
6427 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT53_OFS    (21)                            /*!< PROT53 Bit Offset */
6428 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT53        ((uint32_t)0x00200000)          /*!< Protects Sector 53 from program or erase */
6429 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT54_OFS    (22)                            /*!< PROT54 Bit Offset */
6430 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT54        ((uint32_t)0x00400000)          /*!< Protects Sector 54 from program or erase */
6431 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT55_OFS    (23)                            /*!< PROT55 Bit Offset */
6432 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT55        ((uint32_t)0x00800000)          /*!< Protects Sector 55 from program or erase */
6433 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT56_OFS    (24)                            /*!< PROT56 Bit Offset */
6434 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT56        ((uint32_t)0x01000000)          /*!< Protects Sector 56 from program or erase */
6435 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT57_OFS    (25)                            /*!< PROT57 Bit Offset */
6436 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT57        ((uint32_t)0x02000000)          /*!< Protects Sector 57 from program or erase */
6437 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT58_OFS    (26)                            /*!< PROT58 Bit Offset */
6438 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT58        ((uint32_t)0x04000000)          /*!< Protects Sector 58 from program or erase */
6439 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT59_OFS    (27)                            /*!< PROT59 Bit Offset */
6440 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT59        ((uint32_t)0x08000000)          /*!< Protects Sector 59 from program or erase */
6441 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT60_OFS    (28)                            /*!< PROT60 Bit Offset */
6442 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT60        ((uint32_t)0x10000000)          /*!< Protects Sector 60 from program or erase */
6443 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT61_OFS    (29)                            /*!< PROT61 Bit Offset */
6444 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT61        ((uint32_t)0x20000000)          /*!< Protects Sector 61 from program or erase */
6445 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT62_OFS    (30)                            /*!< PROT62 Bit Offset */
6446 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT62        ((uint32_t)0x40000000)          /*!< Protects Sector 62 from program or erase */
6447 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT63_OFS    (31)                            /*!< PROT63 Bit Offset */
6448 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT63        ((uint32_t)0x80000000)          /*!< Protects Sector 63 from program or erase */
6449 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT64_OFS    ( 0)                            /*!< PROT64 Bit Offset */
6450 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT64        ((uint32_t)0x00000001)          /*!< Protects Sector 64 from program or erase */
6451 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT65_OFS    ( 1)                            /*!< PROT65 Bit Offset */
6452 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT65        ((uint32_t)0x00000002)          /*!< Protects Sector 65 from program or erase */
6453 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT66_OFS    ( 2)                            /*!< PROT66 Bit Offset */
6454 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT66        ((uint32_t)0x00000004)          /*!< Protects Sector 66 from program or erase */
6455 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT67_OFS    ( 3)                            /*!< PROT67 Bit Offset */
6456 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT67        ((uint32_t)0x00000008)          /*!< Protects Sector 67 from program or erase */
6457 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT68_OFS    ( 4)                            /*!< PROT68 Bit Offset */
6458 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT68        ((uint32_t)0x00000010)          /*!< Protects Sector 68 from program or erase */
6459 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT69_OFS    ( 5)                            /*!< PROT69 Bit Offset */
6460 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT69        ((uint32_t)0x00000020)          /*!< Protects Sector 69 from program or erase */
6461 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT70_OFS    ( 6)                            /*!< PROT70 Bit Offset */
6462 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT70        ((uint32_t)0x00000040)          /*!< Protects Sector 70 from program or erase */
6463 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT71_OFS    ( 7)                            /*!< PROT71 Bit Offset */
6464 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT71        ((uint32_t)0x00000080)          /*!< Protects Sector 71 from program or erase */
6465 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT72_OFS    ( 8)                            /*!< PROT72 Bit Offset */
6466 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT72        ((uint32_t)0x00000100)          /*!< Protects Sector 72 from program or erase */
6467 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT73_OFS    ( 9)                            /*!< PROT73 Bit Offset */
6468 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT73        ((uint32_t)0x00000200)          /*!< Protects Sector 73 from program or erase */
6469 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT74_OFS    (10)                            /*!< PROT74 Bit Offset */
6470 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT74        ((uint32_t)0x00000400)          /*!< Protects Sector 74 from program or erase */
6471 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT75_OFS    (11)                            /*!< PROT75 Bit Offset */
6472 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT75        ((uint32_t)0x00000800)          /*!< Protects Sector 75 from program or erase */
6473 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT76_OFS    (12)                            /*!< PROT76 Bit Offset */
6474 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT76        ((uint32_t)0x00001000)          /*!< Protects Sector 76 from program or erase */
6475 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT77_OFS    (13)                            /*!< PROT77 Bit Offset */
6476 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT77        ((uint32_t)0x00002000)          /*!< Protects Sector 77 from program or erase */
6477 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT78_OFS    (14)                            /*!< PROT78 Bit Offset */
6478 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT78        ((uint32_t)0x00004000)          /*!< Protects Sector 78 from program or erase */
6479 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT79_OFS    (15)                            /*!< PROT79 Bit Offset */
6480 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT79        ((uint32_t)0x00008000)          /*!< Protects Sector 79 from program or erase */
6481 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT80_OFS    (16)                            /*!< PROT80 Bit Offset */
6482 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT80        ((uint32_t)0x00010000)          /*!< Protects Sector 80 from program or erase */
6483 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT81_OFS    (17)                            /*!< PROT81 Bit Offset */
6484 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT81        ((uint32_t)0x00020000)          /*!< Protects Sector 81 from program or erase */
6485 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT82_OFS    (18)                            /*!< PROT82 Bit Offset */
6486 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT82        ((uint32_t)0x00040000)          /*!< Protects Sector 82 from program or erase */
6487 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT83_OFS    (19)                            /*!< PROT83 Bit Offset */
6488 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT83        ((uint32_t)0x00080000)          /*!< Protects Sector 83 from program or erase */
6489 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT84_OFS    (20)                            /*!< PROT84 Bit Offset */
6490 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT84        ((uint32_t)0x00100000)          /*!< Protects Sector 84 from program or erase */
6491 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT85_OFS    (21)                            /*!< PROT85 Bit Offset */
6492 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT85        ((uint32_t)0x00200000)          /*!< Protects Sector 85 from program or erase */
6493 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT86_OFS    (22)                            /*!< PROT86 Bit Offset */
6494 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT86        ((uint32_t)0x00400000)          /*!< Protects Sector 86 from program or erase */
6495 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT87_OFS    (23)                            /*!< PROT87 Bit Offset */
6496 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT87        ((uint32_t)0x00800000)          /*!< Protects Sector 87 from program or erase */
6497 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT88_OFS    (24)                            /*!< PROT88 Bit Offset */
6498 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT88        ((uint32_t)0x01000000)          /*!< Protects Sector 88 from program or erase */
6499 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT89_OFS    (25)                            /*!< PROT89 Bit Offset */
6500 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT89        ((uint32_t)0x02000000)          /*!< Protects Sector 89 from program or erase */
6501 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT90_OFS    (26)                            /*!< PROT90 Bit Offset */
6502 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT90        ((uint32_t)0x04000000)          /*!< Protects Sector 90 from program or erase */
6503 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT91_OFS    (27)                            /*!< PROT91 Bit Offset */
6504 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT91        ((uint32_t)0x08000000)          /*!< Protects Sector 91 from program or erase */
6505 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT92_OFS    (28)                            /*!< PROT92 Bit Offset */
6506 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT92        ((uint32_t)0x10000000)          /*!< Protects Sector 92 from program or erase */
6507 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT93_OFS    (29)                            /*!< PROT93 Bit Offset */
6508 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT93        ((uint32_t)0x20000000)          /*!< Protects Sector 93 from program or erase */
6509 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT94_OFS    (30)                            /*!< PROT94 Bit Offset */
6510 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT94        ((uint32_t)0x40000000)          /*!< Protects Sector 94 from program or erase */
6511 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT95_OFS    (31)                            /*!< PROT95 Bit Offset */
6512 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT95        ((uint32_t)0x80000000)          /*!< Protects Sector 95 from program or erase */
6513 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT96_OFS    ( 0)                            /*!< PROT96 Bit Offset */
6514 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT96        ((uint32_t)0x00000001)          /*!< Protects Sector 96 from program or erase */
6515 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT97_OFS    ( 1)                            /*!< PROT97 Bit Offset */
6516 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT97        ((uint32_t)0x00000002)          /*!< Protects Sector 97 from program or erase */
6517 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT98_OFS    ( 2)                            /*!< PROT98 Bit Offset */
6518 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT98        ((uint32_t)0x00000004)          /*!< Protects Sector 98 from program or erase */
6519 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT99_OFS    ( 3)                            /*!< PROT99 Bit Offset */
6520 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT99        ((uint32_t)0x00000008)          /*!< Protects Sector 99 from program or erase */
6521 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT100_OFS   ( 4)                            /*!< PROT100 Bit Offset */
6522 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT100       ((uint32_t)0x00000010)          /*!< Protects Sector 100 from program or erase */
6523 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT101_OFS   ( 5)                            /*!< PROT101 Bit Offset */
6524 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT101       ((uint32_t)0x00000020)          /*!< Protects Sector 101 from program or erase */
6525 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT102_OFS   ( 6)                            /*!< PROT102 Bit Offset */
6526 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT102       ((uint32_t)0x00000040)          /*!< Protects Sector 102 from program or erase */
6527 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT103_OFS   ( 7)                            /*!< PROT103 Bit Offset */
6528 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT103       ((uint32_t)0x00000080)          /*!< Protects Sector 103 from program or erase */
6529 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT104_OFS   ( 8)                            /*!< PROT104 Bit Offset */
6530 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT104       ((uint32_t)0x00000100)          /*!< Protects Sector 104 from program or erase */
6531 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT105_OFS   ( 9)                            /*!< PROT105 Bit Offset */
6532 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT105       ((uint32_t)0x00000200)          /*!< Protects Sector 105 from program or erase */
6533 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT106_OFS   (10)                            /*!< PROT106 Bit Offset */
6534 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT106       ((uint32_t)0x00000400)          /*!< Protects Sector 106 from program or erase */
6535 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT107_OFS   (11)                            /*!< PROT107 Bit Offset */
6536 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT107       ((uint32_t)0x00000800)          /*!< Protects Sector 107 from program or erase */
6537 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT108_OFS   (12)                            /*!< PROT108 Bit Offset */
6538 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT108       ((uint32_t)0x00001000)          /*!< Protects Sector 108 from program or erase */
6539 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT109_OFS   (13)                            /*!< PROT109 Bit Offset */
6540 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT109       ((uint32_t)0x00002000)          /*!< Protects Sector 109 from program or erase */
6541 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT110_OFS   (14)                            /*!< PROT110 Bit Offset */
6542 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT110       ((uint32_t)0x00004000)          /*!< Protects Sector 110 from program or erase */
6543 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT111_OFS   (15)                            /*!< PROT111 Bit Offset */
6544 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT111       ((uint32_t)0x00008000)          /*!< Protects Sector 111 from program or erase */
6545 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT112_OFS   (16)                            /*!< PROT112 Bit Offset */
6546 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT112       ((uint32_t)0x00010000)          /*!< Protects Sector 112 from program or erase */
6547 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT113_OFS   (17)                            /*!< PROT113 Bit Offset */
6548 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT113       ((uint32_t)0x00020000)          /*!< Protects Sector 113 from program or erase */
6549 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT114_OFS   (18)                            /*!< PROT114 Bit Offset */
6550 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT114       ((uint32_t)0x00040000)          /*!< Protects Sector 114 from program or erase */
6551 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT115_OFS   (19)                            /*!< PROT115 Bit Offset */
6552 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT115       ((uint32_t)0x00080000)          /*!< Protects Sector 115 from program or erase */
6553 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT116_OFS   (20)                            /*!< PROT116 Bit Offset */
6554 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT116       ((uint32_t)0x00100000)          /*!< Protects Sector 116 from program or erase */
6555 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT117_OFS   (21)                            /*!< PROT117 Bit Offset */
6556 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT117       ((uint32_t)0x00200000)          /*!< Protects Sector 117 from program or erase */
6557 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT118_OFS   (22)                            /*!< PROT118 Bit Offset */
6558 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT118       ((uint32_t)0x00400000)          /*!< Protects Sector 118 from program or erase */
6559 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT119_OFS   (23)                            /*!< PROT119 Bit Offset */
6560 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT119       ((uint32_t)0x00800000)          /*!< Protects Sector 119 from program or erase */
6561 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT120_OFS   (24)                            /*!< PROT120 Bit Offset */
6562 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT120       ((uint32_t)0x01000000)          /*!< Protects Sector 120 from program or erase */
6563 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT121_OFS   (25)                            /*!< PROT121 Bit Offset */
6564 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT121       ((uint32_t)0x02000000)          /*!< Protects Sector 121 from program or erase */
6565 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT122_OFS   (26)                            /*!< PROT122 Bit Offset */
6566 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT122       ((uint32_t)0x04000000)          /*!< Protects Sector 122 from program or erase */
6567 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT123_OFS   (27)                            /*!< PROT123 Bit Offset */
6568 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT123       ((uint32_t)0x08000000)          /*!< Protects Sector 123 from program or erase */
6569 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT124_OFS   (28)                            /*!< PROT124 Bit Offset */
6570 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT124       ((uint32_t)0x10000000)          /*!< Protects Sector 124 from program or erase */
6571 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT125_OFS   (29)                            /*!< PROT125 Bit Offset */
6572 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT125       ((uint32_t)0x20000000)          /*!< Protects Sector 125 from program or erase */
6573 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT126_OFS   (30)                            /*!< PROT126 Bit Offset */
6574 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT126       ((uint32_t)0x40000000)          /*!< Protects Sector 126 from program or erase */
6575 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT127_OFS   (31)                            /*!< PROT127 Bit Offset */
6576 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT127       ((uint32_t)0x80000000)          /*!< Protects Sector 127 from program or erase */
6577 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT128_OFS   ( 0)                            /*!< PROT128 Bit Offset */
6578 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT128       ((uint32_t)0x00000001)          /*!< Protects Sector 128 from program or erase */
6579 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT129_OFS   ( 1)                            /*!< PROT129 Bit Offset */
6580 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT129       ((uint32_t)0x00000002)          /*!< Protects Sector 129 from program or erase */
6581 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT130_OFS   ( 2)                            /*!< PROT130 Bit Offset */
6582 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT130       ((uint32_t)0x00000004)          /*!< Protects Sector 130 from program or erase */
6583 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT131_OFS   ( 3)                            /*!< PROT131 Bit Offset */
6584 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT131       ((uint32_t)0x00000008)          /*!< Protects Sector 131 from program or erase */
6585 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT132_OFS   ( 4)                            /*!< PROT132 Bit Offset */
6586 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT132       ((uint32_t)0x00000010)          /*!< Protects Sector 132 from program or erase */
6587 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT133_OFS   ( 5)                            /*!< PROT133 Bit Offset */
6588 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT133       ((uint32_t)0x00000020)          /*!< Protects Sector 133 from program or erase */
6589 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT134_OFS   ( 6)                            /*!< PROT134 Bit Offset */
6590 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT134       ((uint32_t)0x00000040)          /*!< Protects Sector 134 from program or erase */
6591 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT135_OFS   ( 7)                            /*!< PROT135 Bit Offset */
6592 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT135       ((uint32_t)0x00000080)          /*!< Protects Sector 135 from program or erase */
6593 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT136_OFS   ( 8)                            /*!< PROT136 Bit Offset */
6594 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT136       ((uint32_t)0x00000100)          /*!< Protects Sector 136 from program or erase */
6595 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT137_OFS   ( 9)                            /*!< PROT137 Bit Offset */
6596 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT137       ((uint32_t)0x00000200)          /*!< Protects Sector 137 from program or erase */
6597 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT138_OFS   (10)                            /*!< PROT138 Bit Offset */
6598 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT138       ((uint32_t)0x00000400)          /*!< Protects Sector 138 from program or erase */
6599 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT139_OFS   (11)                            /*!< PROT139 Bit Offset */
6600 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT139       ((uint32_t)0x00000800)          /*!< Protects Sector 139 from program or erase */
6601 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT140_OFS   (12)                            /*!< PROT140 Bit Offset */
6602 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT140       ((uint32_t)0x00001000)          /*!< Protects Sector 140 from program or erase */
6603 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT141_OFS   (13)                            /*!< PROT141 Bit Offset */
6604 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT141       ((uint32_t)0x00002000)          /*!< Protects Sector 141 from program or erase */
6605 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT142_OFS   (14)                            /*!< PROT142 Bit Offset */
6606 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT142       ((uint32_t)0x00004000)          /*!< Protects Sector 142 from program or erase */
6607 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT143_OFS   (15)                            /*!< PROT143 Bit Offset */
6608 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT143       ((uint32_t)0x00008000)          /*!< Protects Sector 143 from program or erase */
6609 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT144_OFS   (16)                            /*!< PROT144 Bit Offset */
6610 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT144       ((uint32_t)0x00010000)          /*!< Protects Sector 144 from program or erase */
6611 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT145_OFS   (17)                            /*!< PROT145 Bit Offset */
6612 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT145       ((uint32_t)0x00020000)          /*!< Protects Sector 145 from program or erase */
6613 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT146_OFS   (18)                            /*!< PROT146 Bit Offset */
6614 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT146       ((uint32_t)0x00040000)          /*!< Protects Sector 146 from program or erase */
6615 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT147_OFS   (19)                            /*!< PROT147 Bit Offset */
6616 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT147       ((uint32_t)0x00080000)          /*!< Protects Sector 147 from program or erase */
6617 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT148_OFS   (20)                            /*!< PROT148 Bit Offset */
6618 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT148       ((uint32_t)0x00100000)          /*!< Protects Sector 148 from program or erase */
6619 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT149_OFS   (21)                            /*!< PROT149 Bit Offset */
6620 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT149       ((uint32_t)0x00200000)          /*!< Protects Sector 149 from program or erase */
6621 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT150_OFS   (22)                            /*!< PROT150 Bit Offset */
6622 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT150       ((uint32_t)0x00400000)          /*!< Protects Sector 150 from program or erase */
6623 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT151_OFS   (23)                            /*!< PROT151 Bit Offset */
6624 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT151       ((uint32_t)0x00800000)          /*!< Protects Sector 151 from program or erase */
6625 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT152_OFS   (24)                            /*!< PROT152 Bit Offset */
6626 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT152       ((uint32_t)0x01000000)          /*!< Protects Sector 152 from program or erase */
6627 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT153_OFS   (25)                            /*!< PROT153 Bit Offset */
6628 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT153       ((uint32_t)0x02000000)          /*!< Protects Sector 153 from program or erase */
6629 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT154_OFS   (26)                            /*!< PROT154 Bit Offset */
6630 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT154       ((uint32_t)0x04000000)          /*!< Protects Sector 154 from program or erase */
6631 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT155_OFS   (27)                            /*!< PROT155 Bit Offset */
6632 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT155       ((uint32_t)0x08000000)          /*!< Protects Sector 155 from program or erase */
6633 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT156_OFS   (28)                            /*!< PROT156 Bit Offset */
6634 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT156       ((uint32_t)0x10000000)          /*!< Protects Sector 156 from program or erase */
6635 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT157_OFS   (29)                            /*!< PROT157 Bit Offset */
6636 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT157       ((uint32_t)0x20000000)          /*!< Protects Sector 157 from program or erase */
6637 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT158_OFS   (30)                            /*!< PROT158 Bit Offset */
6638 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT158       ((uint32_t)0x40000000)          /*!< Protects Sector 158 from program or erase */
6639 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT159_OFS   (31)                            /*!< PROT159 Bit Offset */
6640 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT159       ((uint32_t)0x80000000)          /*!< Protects Sector 159 from program or erase */
6641 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT160_OFS   ( 0)                            /*!< PROT160 Bit Offset */
6642 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT160       ((uint32_t)0x00000001)          /*!< Protects Sector 160 from program or erase */
6643 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT161_OFS   ( 1)                            /*!< PROT161 Bit Offset */
6644 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT161       ((uint32_t)0x00000002)          /*!< Protects Sector 161 from program or erase */
6645 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT162_OFS   ( 2)                            /*!< PROT162 Bit Offset */
6646 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT162       ((uint32_t)0x00000004)          /*!< Protects Sector 162 from program or erase */
6647 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT163_OFS   ( 3)                            /*!< PROT163 Bit Offset */
6648 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT163       ((uint32_t)0x00000008)          /*!< Protects Sector 163 from program or erase */
6649 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT164_OFS   ( 4)                            /*!< PROT164 Bit Offset */
6650 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT164       ((uint32_t)0x00000010)          /*!< Protects Sector 164 from program or erase */
6651 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT165_OFS   ( 5)                            /*!< PROT165 Bit Offset */
6652 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT165       ((uint32_t)0x00000020)          /*!< Protects Sector 165 from program or erase */
6653 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT166_OFS   ( 6)                            /*!< PROT166 Bit Offset */
6654 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT166       ((uint32_t)0x00000040)          /*!< Protects Sector 166 from program or erase */
6655 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT167_OFS   ( 7)                            /*!< PROT167 Bit Offset */
6656 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT167       ((uint32_t)0x00000080)          /*!< Protects Sector 167 from program or erase */
6657 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT168_OFS   ( 8)                            /*!< PROT168 Bit Offset */
6658 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT168       ((uint32_t)0x00000100)          /*!< Protects Sector 168 from program or erase */
6659 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT169_OFS   ( 9)                            /*!< PROT169 Bit Offset */
6660 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT169       ((uint32_t)0x00000200)          /*!< Protects Sector 169 from program or erase */
6661 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT170_OFS   (10)                            /*!< PROT170 Bit Offset */
6662 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT170       ((uint32_t)0x00000400)          /*!< Protects Sector 170 from program or erase */
6663 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT171_OFS   (11)                            /*!< PROT171 Bit Offset */
6664 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT171       ((uint32_t)0x00000800)          /*!< Protects Sector 171 from program or erase */
6665 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT172_OFS   (12)                            /*!< PROT172 Bit Offset */
6666 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT172       ((uint32_t)0x00001000)          /*!< Protects Sector 172 from program or erase */
6667 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT173_OFS   (13)                            /*!< PROT173 Bit Offset */
6668 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT173       ((uint32_t)0x00002000)          /*!< Protects Sector 173 from program or erase */
6669 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT174_OFS   (14)                            /*!< PROT174 Bit Offset */
6670 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT174       ((uint32_t)0x00004000)          /*!< Protects Sector 174 from program or erase */
6671 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT175_OFS   (15)                            /*!< PROT175 Bit Offset */
6672 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT175       ((uint32_t)0x00008000)          /*!< Protects Sector 175 from program or erase */
6673 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT176_OFS   (16)                            /*!< PROT176 Bit Offset */
6674 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT176       ((uint32_t)0x00010000)          /*!< Protects Sector 176 from program or erase */
6675 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT177_OFS   (17)                            /*!< PROT177 Bit Offset */
6676 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT177       ((uint32_t)0x00020000)          /*!< Protects Sector 177 from program or erase */
6677 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT178_OFS   (18)                            /*!< PROT178 Bit Offset */
6678 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT178       ((uint32_t)0x00040000)          /*!< Protects Sector 178 from program or erase */
6679 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT179_OFS   (19)                            /*!< PROT179 Bit Offset */
6680 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT179       ((uint32_t)0x00080000)          /*!< Protects Sector 179 from program or erase */
6681 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT180_OFS   (20)                            /*!< PROT180 Bit Offset */
6682 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT180       ((uint32_t)0x00100000)          /*!< Protects Sector 180 from program or erase */
6683 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT181_OFS   (21)                            /*!< PROT181 Bit Offset */
6684 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT181       ((uint32_t)0x00200000)          /*!< Protects Sector 181 from program or erase */
6685 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT182_OFS   (22)                            /*!< PROT182 Bit Offset */
6686 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT182       ((uint32_t)0x00400000)          /*!< Protects Sector 182 from program or erase */
6687 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT183_OFS   (23)                            /*!< PROT183 Bit Offset */
6688 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT183       ((uint32_t)0x00800000)          /*!< Protects Sector 183 from program or erase */
6689 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT184_OFS   (24)                            /*!< PROT184 Bit Offset */
6690 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT184       ((uint32_t)0x01000000)          /*!< Protects Sector 184 from program or erase */
6691 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT185_OFS   (25)                            /*!< PROT185 Bit Offset */
6692 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT185       ((uint32_t)0x02000000)          /*!< Protects Sector 185 from program or erase */
6693 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT186_OFS   (26)                            /*!< PROT186 Bit Offset */
6694 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT186       ((uint32_t)0x04000000)          /*!< Protects Sector 186 from program or erase */
6695 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT187_OFS   (27)                            /*!< PROT187 Bit Offset */
6696 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT187       ((uint32_t)0x08000000)          /*!< Protects Sector 187 from program or erase */
6697 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT188_OFS   (28)                            /*!< PROT188 Bit Offset */
6698 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT188       ((uint32_t)0x10000000)          /*!< Protects Sector 188 from program or erase */
6699 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT189_OFS   (29)                            /*!< PROT189 Bit Offset */
6700 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT189       ((uint32_t)0x20000000)          /*!< Protects Sector 189 from program or erase */
6701 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT190_OFS   (30)                            /*!< PROT190 Bit Offset */
6702 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT190       ((uint32_t)0x40000000)          /*!< Protects Sector 190 from program or erase */
6703 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT191_OFS   (31)                            /*!< PROT191 Bit Offset */
6704 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT191       ((uint32_t)0x80000000)          /*!< Protects Sector 191 from program or erase */
6705 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT192_OFS   ( 0)                            /*!< PROT192 Bit Offset */
6706 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT192       ((uint32_t)0x00000001)          /*!< Protects Sector 192 from program or erase */
6707 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT193_OFS   ( 1)                            /*!< PROT193 Bit Offset */
6708 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT193       ((uint32_t)0x00000002)          /*!< Protects Sector 193 from program or erase */
6709 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT194_OFS   ( 2)                            /*!< PROT194 Bit Offset */
6710 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT194       ((uint32_t)0x00000004)          /*!< Protects Sector 194 from program or erase */
6711 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT195_OFS   ( 3)                            /*!< PROT195 Bit Offset */
6712 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT195       ((uint32_t)0x00000008)          /*!< Protects Sector 195 from program or erase */
6713 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT196_OFS   ( 4)                            /*!< PROT196 Bit Offset */
6714 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT196       ((uint32_t)0x00000010)          /*!< Protects Sector 196 from program or erase */
6715 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT197_OFS   ( 5)                            /*!< PROT197 Bit Offset */
6716 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT197       ((uint32_t)0x00000020)          /*!< Protects Sector 197 from program or erase */
6717 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT198_OFS   ( 6)                            /*!< PROT198 Bit Offset */
6718 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT198       ((uint32_t)0x00000040)          /*!< Protects Sector 198 from program or erase */
6719 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT199_OFS   ( 7)                            /*!< PROT199 Bit Offset */
6720 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT199       ((uint32_t)0x00000080)          /*!< Protects Sector 199 from program or erase */
6721 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT200_OFS   ( 8)                            /*!< PROT200 Bit Offset */
6722 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT200       ((uint32_t)0x00000100)          /*!< Protects Sector 200 from program or erase */
6723 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT201_OFS   ( 9)                            /*!< PROT201 Bit Offset */
6724 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT201       ((uint32_t)0x00000200)          /*!< Protects Sector 201 from program or erase */
6725 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT202_OFS   (10)                            /*!< PROT202 Bit Offset */
6726 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT202       ((uint32_t)0x00000400)          /*!< Protects Sector 202 from program or erase */
6727 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT203_OFS   (11)                            /*!< PROT203 Bit Offset */
6728 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT203       ((uint32_t)0x00000800)          /*!< Protects Sector 203 from program or erase */
6729 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT204_OFS   (12)                            /*!< PROT204 Bit Offset */
6730 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT204       ((uint32_t)0x00001000)          /*!< Protects Sector 204 from program or erase */
6731 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT205_OFS   (13)                            /*!< PROT205 Bit Offset */
6732 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT205       ((uint32_t)0x00002000)          /*!< Protects Sector 205 from program or erase */
6733 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT206_OFS   (14)                            /*!< PROT206 Bit Offset */
6734 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT206       ((uint32_t)0x00004000)          /*!< Protects Sector 206 from program or erase */
6735 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT207_OFS   (15)                            /*!< PROT207 Bit Offset */
6736 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT207       ((uint32_t)0x00008000)          /*!< Protects Sector 207 from program or erase */
6737 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT208_OFS   (16)                            /*!< PROT208 Bit Offset */
6738 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT208       ((uint32_t)0x00010000)          /*!< Protects Sector 208 from program or erase */
6739 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT209_OFS   (17)                            /*!< PROT209 Bit Offset */
6740 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT209       ((uint32_t)0x00020000)          /*!< Protects Sector 209 from program or erase */
6741 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT210_OFS   (18)                            /*!< PROT210 Bit Offset */
6742 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT210       ((uint32_t)0x00040000)          /*!< Protects Sector 210 from program or erase */
6743 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT211_OFS   (19)                            /*!< PROT211 Bit Offset */
6744 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT211       ((uint32_t)0x00080000)          /*!< Protects Sector 211 from program or erase */
6745 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT212_OFS   (20)                            /*!< PROT212 Bit Offset */
6746 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT212       ((uint32_t)0x00100000)          /*!< Protects Sector 212 from program or erase */
6747 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT213_OFS   (21)                            /*!< PROT213 Bit Offset */
6748 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT213       ((uint32_t)0x00200000)          /*!< Protects Sector 213 from program or erase */
6749 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT214_OFS   (22)                            /*!< PROT214 Bit Offset */
6750 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT214       ((uint32_t)0x00400000)          /*!< Protects Sector 214 from program or erase */
6751 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT215_OFS   (23)                            /*!< PROT215 Bit Offset */
6752 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT215       ((uint32_t)0x00800000)          /*!< Protects Sector 215 from program or erase */
6753 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT216_OFS   (24)                            /*!< PROT216 Bit Offset */
6754 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT216       ((uint32_t)0x01000000)          /*!< Protects Sector 216 from program or erase */
6755 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT217_OFS   (25)                            /*!< PROT217 Bit Offset */
6756 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT217       ((uint32_t)0x02000000)          /*!< Protects Sector 217 from program or erase */
6757 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT218_OFS   (26)                            /*!< PROT218 Bit Offset */
6758 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT218       ((uint32_t)0x04000000)          /*!< Protects Sector 218 from program or erase */
6759 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT219_OFS   (27)                            /*!< PROT219 Bit Offset */
6760 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT219       ((uint32_t)0x08000000)          /*!< Protects Sector 219 from program or erase */
6761 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT220_OFS   (28)                            /*!< PROT220 Bit Offset */
6762 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT220       ((uint32_t)0x10000000)          /*!< Protects Sector 220 from program or erase */
6763 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT221_OFS   (29)                            /*!< PROT221 Bit Offset */
6764 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT221       ((uint32_t)0x20000000)          /*!< Protects Sector 221 from program or erase */
6765 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT222_OFS   (30)                            /*!< PROT222 Bit Offset */
6766 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT222       ((uint32_t)0x40000000)          /*!< Protects Sector 222 from program or erase */
6767 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT223_OFS   (31)                            /*!< PROT223 Bit Offset */
6768 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT223       ((uint32_t)0x80000000)          /*!< Protects Sector 223 from program or erase */
6769 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT224_OFS   ( 0)                            /*!< PROT224 Bit Offset */
6770 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT224       ((uint32_t)0x00000001)          /*!< Protects Sector 224 from program or erase */
6771 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT225_OFS   ( 1)                            /*!< PROT225 Bit Offset */
6772 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT225       ((uint32_t)0x00000002)          /*!< Protects Sector 225 from program or erase */
6773 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT226_OFS   ( 2)                            /*!< PROT226 Bit Offset */
6774 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT226       ((uint32_t)0x00000004)          /*!< Protects Sector 226 from program or erase */
6775 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT227_OFS   ( 3)                            /*!< PROT227 Bit Offset */
6776 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT227       ((uint32_t)0x00000008)          /*!< Protects Sector 227 from program or erase */
6777 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT228_OFS   ( 4)                            /*!< PROT228 Bit Offset */
6778 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT228       ((uint32_t)0x00000010)          /*!< Protects Sector 228 from program or erase */
6779 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT229_OFS   ( 5)                            /*!< PROT229 Bit Offset */
6780 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT229       ((uint32_t)0x00000020)          /*!< Protects Sector 229 from program or erase */
6781 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT230_OFS   ( 6)                            /*!< PROT230 Bit Offset */
6782 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT230       ((uint32_t)0x00000040)          /*!< Protects Sector 230 from program or erase */
6783 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT231_OFS   ( 7)                            /*!< PROT231 Bit Offset */
6784 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT231       ((uint32_t)0x00000080)          /*!< Protects Sector 231 from program or erase */
6785 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT232_OFS   ( 8)                            /*!< PROT232 Bit Offset */
6786 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT232       ((uint32_t)0x00000100)          /*!< Protects Sector 232 from program or erase */
6787 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT233_OFS   ( 9)                            /*!< PROT233 Bit Offset */
6788 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT233       ((uint32_t)0x00000200)          /*!< Protects Sector 233 from program or erase */
6789 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT234_OFS   (10)                            /*!< PROT234 Bit Offset */
6790 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT234       ((uint32_t)0x00000400)          /*!< Protects Sector 234 from program or erase */
6791 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT235_OFS   (11)                            /*!< PROT235 Bit Offset */
6792 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT235       ((uint32_t)0x00000800)          /*!< Protects Sector 235 from program or erase */
6793 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT236_OFS   (12)                            /*!< PROT236 Bit Offset */
6794 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT236       ((uint32_t)0x00001000)          /*!< Protects Sector 236 from program or erase */
6795 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT237_OFS   (13)                            /*!< PROT237 Bit Offset */
6796 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT237       ((uint32_t)0x00002000)          /*!< Protects Sector 237 from program or erase */
6797 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT238_OFS   (14)                            /*!< PROT238 Bit Offset */
6798 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT238       ((uint32_t)0x00004000)          /*!< Protects Sector 238 from program or erase */
6799 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT239_OFS   (15)                            /*!< PROT239 Bit Offset */
6800 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT239       ((uint32_t)0x00008000)          /*!< Protects Sector 239 from program or erase */
6801 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT240_OFS   (16)                            /*!< PROT240 Bit Offset */
6802 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT240       ((uint32_t)0x00010000)          /*!< Protects Sector 240 from program or erase */
6803 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT241_OFS   (17)                            /*!< PROT241 Bit Offset */
6804 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT241       ((uint32_t)0x00020000)          /*!< Protects Sector 241 from program or erase */
6805 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT242_OFS   (18)                            /*!< PROT242 Bit Offset */
6806 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT242       ((uint32_t)0x00040000)          /*!< Protects Sector 242 from program or erase */
6807 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT243_OFS   (19)                            /*!< PROT243 Bit Offset */
6808 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT243       ((uint32_t)0x00080000)          /*!< Protects Sector 243 from program or erase */
6809 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT244_OFS   (20)                            /*!< PROT244 Bit Offset */
6810 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT244       ((uint32_t)0x00100000)          /*!< Protects Sector 244 from program or erase */
6811 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT245_OFS   (21)                            /*!< PROT245 Bit Offset */
6812 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT245       ((uint32_t)0x00200000)          /*!< Protects Sector 245 from program or erase */
6813 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT246_OFS   (22)                            /*!< PROT246 Bit Offset */
6814 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT246       ((uint32_t)0x00400000)          /*!< Protects Sector 246 from program or erase */
6815 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT247_OFS   (23)                            /*!< PROT247 Bit Offset */
6816 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT247       ((uint32_t)0x00800000)          /*!< Protects Sector 247 from program or erase */
6817 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT248_OFS   (24)                            /*!< PROT248 Bit Offset */
6818 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT248       ((uint32_t)0x01000000)          /*!< Protects Sector 248 from program or erase */
6819 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT249_OFS   (25)                            /*!< PROT249 Bit Offset */
6820 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT249       ((uint32_t)0x02000000)          /*!< Protects Sector 249 from program or erase */
6821 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT250_OFS   (26)                            /*!< PROT250 Bit Offset */
6822 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT250       ((uint32_t)0x04000000)          /*!< Protects Sector 250 from program or erase */
6823 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT251_OFS   (27)                            /*!< PROT251 Bit Offset */
6824 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT251       ((uint32_t)0x08000000)          /*!< Protects Sector 251 from program or erase */
6825 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT252_OFS   (28)                            /*!< PROT252 Bit Offset */
6826 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT252       ((uint32_t)0x10000000)          /*!< Protects Sector 252 from program or erase */
6827 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT253_OFS   (29)                            /*!< PROT253 Bit Offset */
6828 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT253       ((uint32_t)0x20000000)          /*!< Protects Sector 253 from program or erase */
6829 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT254_OFS   (30)                            /*!< PROT254 Bit Offset */
6830 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT254       ((uint32_t)0x40000000)          /*!< Protects Sector 254 from program or erase */
6831 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT255_OFS   (31)                            /*!< PROT255 Bit Offset */
6832 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT255       ((uint32_t)0x80000000)          /*!< Protects Sector 255 from program or erase */
6833 #define LCD_F_CTL_ON_OFS                         ( 0)                            /*!< LCDON Bit Offset */
6834 #define LCD_F_CTL_ON                             ((uint32_t)0x00000001)          /*!< LCD on */
6835 #define LCD_F_CTL_LP_OFS                         ( 1)                            /*!< LCDLP Bit Offset */
6836 #define LCD_F_CTL_LP                             ((uint32_t)0x00000002)          /*!< LCD Low-power Waveform */
6837 #define LCD_F_CTL_SON_OFS                        ( 2)                            /*!< LCDSON Bit Offset */
6838 #define LCD_F_CTL_SON                            ((uint32_t)0x00000004)          /*!< LCD segments on */
6839 #define LCD_F_CTL_MX_OFS                         ( 3)                            /*!< LCDMXx Bit Offset */
6840 #define LCD_F_CTL_MX_MASK                        ((uint32_t)0x00000038)          /*!< LCDMXx Bit Mask */
6841 #define LCD_F_CTL_MX0                            ((uint32_t)0x00000008)          /*!< MX Bit 0 */
6842 #define LCD_F_CTL_MX1                            ((uint32_t)0x00000010)          /*!< MX Bit 1 */
6843 #define LCD_F_CTL_MX2                            ((uint32_t)0x00000020)          /*!< MX Bit 2 */
6844 #define LCD_F_CTL_MX_0                           ((uint32_t)0x00000000)          /*!< Static */
6845 #define LCD_F_CTL_MX_1                           ((uint32_t)0x00000008)          /*!< 2-mux */
6846 #define LCD_F_CTL_MX_2                           ((uint32_t)0x00000010)          /*!< 3-mux */
6847 #define LCD_F_CTL_MX_3                           ((uint32_t)0x00000018)          /*!< 4-mux */
6848 #define LCD_F_CTL_MX_4                           ((uint32_t)0x00000020)          /*!< 5-mux */
6849 #define LCD_F_CTL_MX_5                           ((uint32_t)0x00000028)          /*!< 6-mux */
6850 #define LCD_F_CTL_MX_6                           ((uint32_t)0x00000030)          /*!< 7-mux */
6851 #define LCD_F_CTL_MX_7                           ((uint32_t)0x00000038)          /*!< 8-mux */
6852 #define LCD_F_CTL_PRE_OFS                        ( 8)                            /*!< LCDPREx Bit Offset */
6853 #define LCD_F_CTL_PRE_MASK                       ((uint32_t)0x00000700)          /*!< LCDPREx Bit Mask */
6854 #define LCD_F_CTL_PRE0                           ((uint32_t)0x00000100)          /*!< PRE Bit 0 */
6855 #define LCD_F_CTL_PRE1                           ((uint32_t)0x00000200)          /*!< PRE Bit 1 */
6856 #define LCD_F_CTL_PRE2                           ((uint32_t)0x00000400)          /*!< PRE Bit 2 */
6857 #define LCD_F_CTL_PRE_0                          ((uint32_t)0x00000000)          /*!< Divide by 1 */
6858 #define LCD_F_CTL_PRE_1                          ((uint32_t)0x00000100)          /*!< Divide by 2 */
6859 #define LCD_F_CTL_PRE_2                          ((uint32_t)0x00000200)          /*!< Divide by 4 */
6860 #define LCD_F_CTL_PRE_3                          ((uint32_t)0x00000300)          /*!< Divide by 8 */
6861 #define LCD_F_CTL_PRE_4                          ((uint32_t)0x00000400)          /*!< Divide by 16 */
6862 #define LCD_F_CTL_PRE_5                          ((uint32_t)0x00000500)          /*!< Divide by 32 */
6863 #define LCD_F_CTL_PRE_6                          ((uint32_t)0x00000600)          /*!< Reserved (defaults to divide by 32) */
6864 #define LCD_F_CTL_PRE_7                          ((uint32_t)0x00000700)          /*!< Reserved (defaults to divide by 32) */
6865 #define LCD_F_CTL_DIV_OFS                        (11)                            /*!< LCDDIVx Bit Offset */
6866 #define LCD_F_CTL_DIV_MASK                       ((uint32_t)0x0000F800)          /*!< LCDDIVx Bit Mask */
6867 #define LCD_F_CTL_DIV0                           ((uint32_t)0x00000800)          /*!< DIV Bit 0 */
6868 #define LCD_F_CTL_DIV1                           ((uint32_t)0x00001000)          /*!< DIV Bit 1 */
6869 #define LCD_F_CTL_DIV2                           ((uint32_t)0x00002000)          /*!< DIV Bit 2 */
6870 #define LCD_F_CTL_DIV3                           ((uint32_t)0x00004000)          /*!< DIV Bit 3 */
6871 #define LCD_F_CTL_DIV4                           ((uint32_t)0x00008000)          /*!< DIV Bit 4 */
6872 #define LCD_F_CTL_DIV_0                          ((uint32_t)0x00000000)          /*!< Divide by 1 */
6873 #define LCD_F_CTL_DIV_1                          ((uint32_t)0x00000800)          /*!< Divide by 2 */
6874 #define LCD_F_CTL_DIV_2                          ((uint32_t)0x00001000)          /*!< Divide by 3 */
6875 #define LCD_F_CTL_DIV_3                          ((uint32_t)0x00001800)          /*!< Divide by 4 */
6876 #define LCD_F_CTL_DIV_4                          ((uint32_t)0x00002000)          /*!< Divide by 5 */
6877 #define LCD_F_CTL_DIV_5                          ((uint32_t)0x00002800)          /*!< Divide by 6 */
6878 #define LCD_F_CTL_DIV_6                          ((uint32_t)0x00003000)          /*!< Divide by 7 */
6879 #define LCD_F_CTL_DIV_7                          ((uint32_t)0x00003800)          /*!< Divide by 8 */
6880 #define LCD_F_CTL_DIV_8                          ((uint32_t)0x00004000)          /*!< Divide by 9 */
6881 #define LCD_F_CTL_DIV_9                          ((uint32_t)0x00004800)          /*!< Divide by 10 */
6882 #define LCD_F_CTL_DIV_10                         ((uint32_t)0x00005000)          /*!< Divide by 11 */
6883 #define LCD_F_CTL_DIV_11                         ((uint32_t)0x00005800)          /*!< Divide by 12 */
6884 #define LCD_F_CTL_DIV_12                         ((uint32_t)0x00006000)          /*!< Divide by 13 */
6885 #define LCD_F_CTL_DIV_13                         ((uint32_t)0x00006800)          /*!< Divide by 14 */
6886 #define LCD_F_CTL_DIV_14                         ((uint32_t)0x00007000)          /*!< Divide by 15 */
6887 #define LCD_F_CTL_DIV_15                         ((uint32_t)0x00007800)          /*!< Divide by 16 */
6888 #define LCD_F_CTL_DIV_16                         ((uint32_t)0x00008000)          /*!< Divide by 17 */
6889 #define LCD_F_CTL_DIV_17                         ((uint32_t)0x00008800)          /*!< Divide by 18 */
6890 #define LCD_F_CTL_DIV_18                         ((uint32_t)0x00009000)          /*!< Divide by 19 */
6891 #define LCD_F_CTL_DIV_19                         ((uint32_t)0x00009800)          /*!< Divide by 20 */
6892 #define LCD_F_CTL_DIV_20                         ((uint32_t)0x0000A000)          /*!< Divide by 21 */
6893 #define LCD_F_CTL_DIV_21                         ((uint32_t)0x0000A800)          /*!< Divide by 22 */
6894 #define LCD_F_CTL_DIV_22                         ((uint32_t)0x0000B000)          /*!< Divide by 23 */
6895 #define LCD_F_CTL_DIV_23                         ((uint32_t)0x0000B800)          /*!< Divide by 24 */
6896 #define LCD_F_CTL_DIV_24                         ((uint32_t)0x0000C000)          /*!< Divide by 25 */
6897 #define LCD_F_CTL_DIV_25                         ((uint32_t)0x0000C800)          /*!< Divide by 26 */
6898 #define LCD_F_CTL_DIV_26                         ((uint32_t)0x0000D000)          /*!< Divide by 27 */
6899 #define LCD_F_CTL_DIV_27                         ((uint32_t)0x0000D800)          /*!< Divide by 28 */
6900 #define LCD_F_CTL_DIV_28                         ((uint32_t)0x0000E000)          /*!< Divide by 29 */
6901 #define LCD_F_CTL_DIV_29                         ((uint32_t)0x0000E800)          /*!< Divide by 30 */
6902 #define LCD_F_CTL_DIV_30                         ((uint32_t)0x0000F000)          /*!< Divide by 31 */
6903 #define LCD_F_CTL_DIV_31                         ((uint32_t)0x0000F800)          /*!< Divide by 32 */
6904 #define LCD_F_CTL_SSEL_OFS                       (16)                            /*!< LCDSSEL Bit Offset */
6905 #define LCD_F_CTL_SSEL_MASK                      ((uint32_t)0x00030000)          /*!< LCDSSEL Bit Mask */
6906 #define LCD_F_CTL_SSEL0                          ((uint32_t)0x00010000)          /*!< SSEL Bit 0 */
6907 #define LCD_F_CTL_SSEL1                          ((uint32_t)0x00020000)          /*!< SSEL Bit 1 */
6908 #define LCD_F_CTL_SSEL_0                         ((uint32_t)0x00000000)          /*!< ACLK */
6909 #define LCD_F_CTL_SSEL_1                         ((uint32_t)0x00010000)          /*!< VLOCLK */
6910 #define LCD_F_CTL_SSEL_2                         ((uint32_t)0x00020000)          /*!< REFOCLK */
6911 #define LCD_F_CTL_SSEL_3                         ((uint32_t)0x00030000)          /*!< LFXTCLK */
6912 #define LCD_F_BMCTL_BLKMOD_OFS                   ( 0)                            /*!< LCDBLKMODx Bit Offset */
6913 #define LCD_F_BMCTL_BLKMOD_MASK                  ((uint32_t)0x00000003)          /*!< LCDBLKMODx Bit Mask */
6914 #define LCD_F_BMCTL_BLKMOD0                      ((uint32_t)0x00000001)          /*!< BLKMOD Bit 0 */
6915 #define LCD_F_BMCTL_BLKMOD1                      ((uint32_t)0x00000002)          /*!< BLKMOD Bit 1 */
6916 #define LCD_F_BMCTL_BLKMOD_0                     ((uint32_t)0x00000000)          /*!< Blinking disabled */
6917 #define LCD_F_BMCTL_BLKMOD_1                     ((uint32_t)0x00000001)          /*!< Blinking of individual segments as enabled in blinking memory register  */
6918 #define LCD_F_BMCTL_BLKMOD_2                     ((uint32_t)0x00000002)          /*!< Blinking of all segments */
6919 #define LCD_F_BMCTL_BLKMOD_3                     ((uint32_t)0x00000003)          /*!< Switching between display contents as stored in LCDMx and LCDBMx memory  */
6920 #define LCD_F_BMCTL_BLKPRE_OFS                   ( 2)                            /*!< LCDBLKPREx Bit Offset */
6921 #define LCD_F_BMCTL_BLKPRE_MASK                  ((uint32_t)0x0000001C)          /*!< LCDBLKPREx Bit Mask */
6922 #define LCD_F_BMCTL_BLKPRE0                      ((uint32_t)0x00000004)          /*!< BLKPRE Bit 0 */
6923 #define LCD_F_BMCTL_BLKPRE1                      ((uint32_t)0x00000008)          /*!< BLKPRE Bit 1 */
6924 #define LCD_F_BMCTL_BLKPRE2                      ((uint32_t)0x00000010)          /*!< BLKPRE Bit 2 */
6925 #define LCD_F_BMCTL_BLKPRE_0                     ((uint32_t)0x00000000)          /*!< Divide by 512 */
6926 #define LCD_F_BMCTL_BLKPRE_1                     ((uint32_t)0x00000004)          /*!< Divide by 1024 */
6927 #define LCD_F_BMCTL_BLKPRE_2                     ((uint32_t)0x00000008)          /*!< Divide by 2048 */
6928 #define LCD_F_BMCTL_BLKPRE_3                     ((uint32_t)0x0000000C)          /*!< Divide by 4096 */
6929 #define LCD_F_BMCTL_BLKPRE_4                     ((uint32_t)0x00000010)          /*!< Divide by 8162 */
6930 #define LCD_F_BMCTL_BLKPRE_5                     ((uint32_t)0x00000014)          /*!< Divide by 16384 */
6931 #define LCD_F_BMCTL_BLKPRE_6                     ((uint32_t)0x00000018)          /*!< Divide by 32768 */
6932 #define LCD_F_BMCTL_BLKPRE_7                     ((uint32_t)0x0000001C)          /*!< Divide by 65536 */
6933 #define LCD_F_BMCTL_BLKDIV_OFS                   ( 5)                            /*!< LCDBLKDIVx Bit Offset */
6934 #define LCD_F_BMCTL_BLKDIV_MASK                  ((uint32_t)0x000000E0)          /*!< LCDBLKDIVx Bit Mask */
6935 #define LCD_F_BMCTL_BLKDIV0                      ((uint32_t)0x00000020)          /*!< BLKDIV Bit 0 */
6936 #define LCD_F_BMCTL_BLKDIV1                      ((uint32_t)0x00000040)          /*!< BLKDIV Bit 1 */
6937 #define LCD_F_BMCTL_BLKDIV2                      ((uint32_t)0x00000080)          /*!< BLKDIV Bit 2 */
6938 #define LCD_F_BMCTL_BLKDIV_0                     ((uint32_t)0x00000000)          /*!< Divide by 1 */
6939 #define LCD_F_BMCTL_BLKDIV_1                     ((uint32_t)0x00000020)          /*!< Divide by 2 */
6940 #define LCD_F_BMCTL_BLKDIV_2                     ((uint32_t)0x00000040)          /*!< Divide by 3 */
6941 #define LCD_F_BMCTL_BLKDIV_3                     ((uint32_t)0x00000060)          /*!< Divide by 4 */
6942 #define LCD_F_BMCTL_BLKDIV_4                     ((uint32_t)0x00000080)          /*!< Divide by 5 */
6943 #define LCD_F_BMCTL_BLKDIV_5                     ((uint32_t)0x000000A0)          /*!< Divide by 6 */
6944 #define LCD_F_BMCTL_BLKDIV_6                     ((uint32_t)0x000000C0)          /*!< Divide by 7 */
6945 #define LCD_F_BMCTL_BLKDIV_7                     ((uint32_t)0x000000E0)          /*!< Divide by 8 */
6946 #define LCD_F_BMCTL_DISP_OFS                     (16)                            /*!< LCDDISP Bit Offset */
6947 #define LCD_F_BMCTL_DISP                         ((uint32_t)0x00010000)          /*!< Select LCD memory registers for display */
6948 #define LCD_F_BMCTL_CLRM_OFS                     (17)                            /*!< LCDCLRM Bit Offset */
6949 #define LCD_F_BMCTL_CLRM                         ((uint32_t)0x00020000)          /*!< Clear LCD memory */
6950 #define LCD_F_BMCTL_CLRBM_OFS                    (18)                            /*!< LCDCLRBM Bit Offset */
6951 #define LCD_F_BMCTL_CLRBM                        ((uint32_t)0x00040000)          /*!< Clear LCD blinking memory */
6952 #define LCD_F_VCTL_LCD2B_OFS                     ( 0)                            /*!< LCD2B Bit Offset */
6953 #define LCD_F_VCTL_LCD2B                         ((uint32_t)0x00000001)          /*!< Bias select. */
6954 #define LCD_F_VCTL_EXTBIAS_OFS                   ( 5)                            /*!< LCDEXTBIAS Bit Offset */
6955 #define LCD_F_VCTL_EXTBIAS                       ((uint32_t)0x00000020)          /*!< V2 to V4 voltage select */
6956 #define LCD_F_VCTL_R03EXT_OFS                    ( 6)                            /*!< R03EXT Bit Offset */
6957 #define LCD_F_VCTL_R03EXT                        ((uint32_t)0x00000040)          /*!< V5 voltage select */
6958 #define LCD_F_VCTL_REXT_OFS                      ( 7)                            /*!< LCDREXT Bit Offset */
6959 #define LCD_F_VCTL_REXT                          ((uint32_t)0x00000080)          /*!< V2 to V4 voltage on external Rx3 pins */
6960 #define LCD_F_PCTL0_S0_OFS                       ( 0)                            /*!< LCDS0 Bit Offset */
6961 #define LCD_F_PCTL0_S0                           ((uint32_t)0x00000001)          /*!< LCD pin 0 enable */
6962 #define LCD_F_PCTL0_S1_OFS                       ( 1)                            /*!< LCDS1 Bit Offset */
6963 #define LCD_F_PCTL0_S1                           ((uint32_t)0x00000002)          /*!< LCD pin 1 enable */
6964 #define LCD_F_PCTL0_S2_OFS                       ( 2)                            /*!< LCDS2 Bit Offset */
6965 #define LCD_F_PCTL0_S2                           ((uint32_t)0x00000004)          /*!< LCD pin 2 enable */
6966 #define LCD_F_PCTL0_S3_OFS                       ( 3)                            /*!< LCDS3 Bit Offset */
6967 #define LCD_F_PCTL0_S3                           ((uint32_t)0x00000008)          /*!< LCD pin 3 enable */
6968 #define LCD_F_PCTL0_S4_OFS                       ( 4)                            /*!< LCDS4 Bit Offset */
6969 #define LCD_F_PCTL0_S4                           ((uint32_t)0x00000010)          /*!< LCD pin 4 enable */
6970 #define LCD_F_PCTL0_S5_OFS                       ( 5)                            /*!< LCDS5 Bit Offset */
6971 #define LCD_F_PCTL0_S5                           ((uint32_t)0x00000020)          /*!< LCD pin 5 enable */
6972 #define LCD_F_PCTL0_S6_OFS                       ( 6)                            /*!< LCDS6 Bit Offset */
6973 #define LCD_F_PCTL0_S6                           ((uint32_t)0x00000040)          /*!< LCD pin 6 enable */
6974 #define LCD_F_PCTL0_S7_OFS                       ( 7)                            /*!< LCDS7 Bit Offset */
6975 #define LCD_F_PCTL0_S7                           ((uint32_t)0x00000080)          /*!< LCD pin 7 enable */
6976 #define LCD_F_PCTL0_S8_OFS                       ( 8)                            /*!< LCDS8 Bit Offset */
6977 #define LCD_F_PCTL0_S8                           ((uint32_t)0x00000100)          /*!< LCD pin 8 enable */
6978 #define LCD_F_PCTL0_S9_OFS                       ( 9)                            /*!< LCDS9 Bit Offset */
6979 #define LCD_F_PCTL0_S9                           ((uint32_t)0x00000200)          /*!< LCD pin 9 enable */
6980 #define LCD_F_PCTL0_S10_OFS                      (10)                            /*!< LCDS10 Bit Offset */
6981 #define LCD_F_PCTL0_S10                          ((uint32_t)0x00000400)          /*!< LCD pin 10 enable */
6982 #define LCD_F_PCTL0_S11_OFS                      (11)                            /*!< LCDS11 Bit Offset */
6983 #define LCD_F_PCTL0_S11                          ((uint32_t)0x00000800)          /*!< LCD pin 11 enable */
6984 #define LCD_F_PCTL0_S12_OFS                      (12)                            /*!< LCDS12 Bit Offset */
6985 #define LCD_F_PCTL0_S12                          ((uint32_t)0x00001000)          /*!< LCD pin 12 enable */
6986 #define LCD_F_PCTL0_S13_OFS                      (13)                            /*!< LCDS13 Bit Offset */
6987 #define LCD_F_PCTL0_S13                          ((uint32_t)0x00002000)          /*!< LCD pin 13 enable */
6988 #define LCD_F_PCTL0_S14_OFS                      (14)                            /*!< LCDS14 Bit Offset */
6989 #define LCD_F_PCTL0_S14                          ((uint32_t)0x00004000)          /*!< LCD pin 14 enable */
6990 #define LCD_F_PCTL0_S15_OFS                      (15)                            /*!< LCDS15 Bit Offset */
6991 #define LCD_F_PCTL0_S15                          ((uint32_t)0x00008000)          /*!< LCD pin 15 enable */
6992 #define LCD_F_PCTL0_S16_OFS                      (16)                            /*!< LCDS16 Bit Offset */
6993 #define LCD_F_PCTL0_S16                          ((uint32_t)0x00010000)          /*!< LCD pin 16 enable */
6994 #define LCD_F_PCTL0_S17_OFS                      (17)                            /*!< LCDS17 Bit Offset */
6995 #define LCD_F_PCTL0_S17                          ((uint32_t)0x00020000)          /*!< LCD pin 17 enable */
6996 #define LCD_F_PCTL0_S18_OFS                      (18)                            /*!< LCDS18 Bit Offset */
6997 #define LCD_F_PCTL0_S18                          ((uint32_t)0x00040000)          /*!< LCD pin 18 enable */
6998 #define LCD_F_PCTL0_S19_OFS                      (19)                            /*!< LCDS19 Bit Offset */
6999 #define LCD_F_PCTL0_S19                          ((uint32_t)0x00080000)          /*!< LCD pin 19 enable */
7000 #define LCD_F_PCTL0_S20_OFS                      (20)                            /*!< LCDS20 Bit Offset */
7001 #define LCD_F_PCTL0_S20                          ((uint32_t)0x00100000)          /*!< LCD pin 20 enable */
7002 #define LCD_F_PCTL0_S21_OFS                      (21)                            /*!< LCDS21 Bit Offset */
7003 #define LCD_F_PCTL0_S21                          ((uint32_t)0x00200000)          /*!< LCD pin 21 enable */
7004 #define LCD_F_PCTL0_S22_OFS                      (22)                            /*!< LCDS22 Bit Offset */
7005 #define LCD_F_PCTL0_S22                          ((uint32_t)0x00400000)          /*!< LCD pin 22 enable */
7006 #define LCD_F_PCTL0_S23_OFS                      (23)                            /*!< LCDS23 Bit Offset */
7007 #define LCD_F_PCTL0_S23                          ((uint32_t)0x00800000)          /*!< LCD pin 23 enable */
7008 #define LCD_F_PCTL0_S24_OFS                      (24)                            /*!< LCDS24 Bit Offset */
7009 #define LCD_F_PCTL0_S24                          ((uint32_t)0x01000000)          /*!< LCD pin 24 enable */
7010 #define LCD_F_PCTL0_S25_OFS                      (25)                            /*!< LCDS25 Bit Offset */
7011 #define LCD_F_PCTL0_S25                          ((uint32_t)0x02000000)          /*!< LCD pin 25 enable */
7012 #define LCD_F_PCTL0_S26_OFS                      (26)                            /*!< LCDS26 Bit Offset */
7013 #define LCD_F_PCTL0_S26                          ((uint32_t)0x04000000)          /*!< LCD pin 26 enable */
7014 #define LCD_F_PCTL0_S27_OFS                      (27)                            /*!< LCDS27 Bit Offset */
7015 #define LCD_F_PCTL0_S27                          ((uint32_t)0x08000000)          /*!< LCD pin 27 enable */
7016 #define LCD_F_PCTL0_S28_OFS                      (28)                            /*!< LCDS28 Bit Offset */
7017 #define LCD_F_PCTL0_S28                          ((uint32_t)0x10000000)          /*!< LCD pin 28 enable */
7018 #define LCD_F_PCTL0_S29_OFS                      (29)                            /*!< LCDS29 Bit Offset */
7019 #define LCD_F_PCTL0_S29                          ((uint32_t)0x20000000)          /*!< LCD pin 29 enable */
7020 #define LCD_F_PCTL0_S30_OFS                      (30)                            /*!< LCDS30 Bit Offset */
7021 #define LCD_F_PCTL0_S30                          ((uint32_t)0x40000000)          /*!< LCD pin 30 enable */
7022 #define LCD_F_PCTL0_S31_OFS                      (31)                            /*!< LCDS31 Bit Offset */
7023 #define LCD_F_PCTL0_S31                          ((uint32_t)0x80000000)          /*!< LCD pin 31 enable */
7024 #define LCD_F_PCTL1_S32_OFS                      ( 0)                            /*!< LCDS32 Bit Offset */
7025 #define LCD_F_PCTL1_S32                          ((uint32_t)0x00000001)          /*!< LCD pin 32 enable */
7026 #define LCD_F_PCTL1_S33_OFS                      ( 1)                            /*!< LCDS33 Bit Offset */
7027 #define LCD_F_PCTL1_S33                          ((uint32_t)0x00000002)          /*!< LCD pin 33 enable */
7028 #define LCD_F_PCTL1_S34_OFS                      ( 2)                            /*!< LCDS34 Bit Offset */
7029 #define LCD_F_PCTL1_S34                          ((uint32_t)0x00000004)          /*!< LCD pin 34 enable */
7030 #define LCD_F_PCTL1_S35_OFS                      ( 3)                            /*!< LCDS35 Bit Offset */
7031 #define LCD_F_PCTL1_S35                          ((uint32_t)0x00000008)          /*!< LCD pin 35 enable */
7032 #define LCD_F_PCTL1_S36_OFS                      ( 4)                            /*!< LCDS36 Bit Offset */
7033 #define LCD_F_PCTL1_S36                          ((uint32_t)0x00000010)          /*!< LCD pin 36 enable */
7034 #define LCD_F_PCTL1_S37_OFS                      ( 5)                            /*!< LCDS37 Bit Offset */
7035 #define LCD_F_PCTL1_S37                          ((uint32_t)0x00000020)          /*!< LCD pin 37 enable */
7036 #define LCD_F_PCTL1_S38_OFS                      ( 6)                            /*!< LCDS38 Bit Offset */
7037 #define LCD_F_PCTL1_S38                          ((uint32_t)0x00000040)          /*!< LCD pin 38 enable */
7038 #define LCD_F_PCTL1_S39_OFS                      ( 7)                            /*!< LCDS39 Bit Offset */
7039 #define LCD_F_PCTL1_S39                          ((uint32_t)0x00000080)          /*!< LCD pin 39 enable */
7040 #define LCD_F_PCTL1_S40_OFS                      ( 8)                            /*!< LCDS40 Bit Offset */
7041 #define LCD_F_PCTL1_S40                          ((uint32_t)0x00000100)          /*!< LCD pin 40 enable */
7042 #define LCD_F_PCTL1_S41_OFS                      ( 9)                            /*!< LCDS41 Bit Offset */
7043 #define LCD_F_PCTL1_S41                          ((uint32_t)0x00000200)          /*!< LCD pin 41 enable */
7044 #define LCD_F_PCTL1_S42_OFS                      (10)                            /*!< LCDS42 Bit Offset */
7045 #define LCD_F_PCTL1_S42                          ((uint32_t)0x00000400)          /*!< LCD pin 42 enable */
7046 #define LCD_F_PCTL1_S43_OFS                      (11)                            /*!< LCDS43 Bit Offset */
7047 #define LCD_F_PCTL1_S43                          ((uint32_t)0x00000800)          /*!< LCD pin 43 enable */
7048 #define LCD_F_PCTL1_S44_OFS                      (12)                            /*!< LCDS44 Bit Offset */
7049 #define LCD_F_PCTL1_S44                          ((uint32_t)0x00001000)          /*!< LCD pin 44 enable */
7050 #define LCD_F_PCTL1_S45_OFS                      (13)                            /*!< LCDS45 Bit Offset */
7051 #define LCD_F_PCTL1_S45                          ((uint32_t)0x00002000)          /*!< LCD pin 45 enable */
7052 #define LCD_F_PCTL1_S46_OFS                      (14)                            /*!< LCDS46 Bit Offset */
7053 #define LCD_F_PCTL1_S46                          ((uint32_t)0x00004000)          /*!< LCD pin 46 enable */
7054 #define LCD_F_PCTL1_S47_OFS                      (15)                            /*!< LCDS47 Bit Offset */
7055 #define LCD_F_PCTL1_S47                          ((uint32_t)0x00008000)          /*!< LCD pin 47 enable */
7056 #define LCD_F_PCTL1_S48_OFS                      (16)                            /*!< LCDS48 Bit Offset */
7057 #define LCD_F_PCTL1_S48                          ((uint32_t)0x00010000)          /*!< LCD pin 48 enable */
7058 #define LCD_F_PCTL1_S49_OFS                      (17)                            /*!< LCDS49 Bit Offset */
7059 #define LCD_F_PCTL1_S49                          ((uint32_t)0x00020000)          /*!< LCD pin 49 enable */
7060 #define LCD_F_PCTL1_S50_OFS                      (18)                            /*!< LCDS50 Bit Offset */
7061 #define LCD_F_PCTL1_S50                          ((uint32_t)0x00040000)          /*!< LCD pin 50 enable */
7062 #define LCD_F_PCTL1_S51_OFS                      (19)                            /*!< LCDS51 Bit Offset */
7063 #define LCD_F_PCTL1_S51                          ((uint32_t)0x00080000)          /*!< LCD pin 51 enable */
7064 #define LCD_F_PCTL1_S52_OFS                      (20)                            /*!< LCDS52 Bit Offset */
7065 #define LCD_F_PCTL1_S52                          ((uint32_t)0x00100000)          /*!< LCD pin 52 enable */
7066 #define LCD_F_PCTL1_S53_OFS                      (21)                            /*!< LCDS53 Bit Offset */
7067 #define LCD_F_PCTL1_S53                          ((uint32_t)0x00200000)          /*!< LCD pin 53 enable */
7068 #define LCD_F_PCTL1_S54_OFS                      (22)                            /*!< LCDS54 Bit Offset */
7069 #define LCD_F_PCTL1_S54                          ((uint32_t)0x00400000)          /*!< LCD pin 54 enable */
7070 #define LCD_F_PCTL1_S55_OFS                      (23)                            /*!< LCDS55 Bit Offset */
7071 #define LCD_F_PCTL1_S55                          ((uint32_t)0x00800000)          /*!< LCD pin 55 enable */
7072 #define LCD_F_PCTL1_S56_OFS                      (24)                            /*!< LCDS56 Bit Offset */
7073 #define LCD_F_PCTL1_S56                          ((uint32_t)0x01000000)          /*!< LCD pin 56 enable */
7074 #define LCD_F_PCTL1_S57_OFS                      (25)                            /*!< LCDS57 Bit Offset */
7075 #define LCD_F_PCTL1_S57                          ((uint32_t)0x02000000)          /*!< LCD pin 57 enable */
7076 #define LCD_F_PCTL1_S58_OFS                      (26)                            /*!< LCDS58 Bit Offset */
7077 #define LCD_F_PCTL1_S58                          ((uint32_t)0x04000000)          /*!< LCD pin 58 enable */
7078 #define LCD_F_PCTL1_S59_OFS                      (27)                            /*!< LCDS59 Bit Offset */
7079 #define LCD_F_PCTL1_S59                          ((uint32_t)0x08000000)          /*!< LCD pin 59 enable */
7080 #define LCD_F_PCTL1_S60_OFS                      (28)                            /*!< LCDS60 Bit Offset */
7081 #define LCD_F_PCTL1_S60                          ((uint32_t)0x10000000)          /*!< LCD pin 60 enable */
7082 #define LCD_F_PCTL1_S61_OFS                      (29)                            /*!< LCDS61 Bit Offset */
7083 #define LCD_F_PCTL1_S61                          ((uint32_t)0x20000000)          /*!< LCD pin 61 enable */
7084 #define LCD_F_PCTL1_S62_OFS                      (30)                            /*!< LCDS62 Bit Offset */
7085 #define LCD_F_PCTL1_S62                          ((uint32_t)0x40000000)          /*!< LCD pin 62 enable */
7086 #define LCD_F_PCTL1_S63_OFS                      (31)                            /*!< LCDS63 Bit Offset */
7087 #define LCD_F_PCTL1_S63                          ((uint32_t)0x80000000)          /*!< LCD pin 63 enable */
7088 #define LCD_F_CSSEL0_CSS0_OFS                    ( 0)                            /*!< LCDCSS0 Bit Offset */
7089 #define LCD_F_CSSEL0_CSS0                        ((uint32_t)0x00000001)          /*!< L0 Com Seg select */
7090 #define LCD_F_CSSEL0_CSS1_OFS                    ( 1)                            /*!< LCDCSS1 Bit Offset */
7091 #define LCD_F_CSSEL0_CSS1                        ((uint32_t)0x00000002)          /*!< L1 Com Seg select */
7092 #define LCD_F_CSSEL0_CSS2_OFS                    ( 2)                            /*!< LCDCSS2 Bit Offset */
7093 #define LCD_F_CSSEL0_CSS2                        ((uint32_t)0x00000004)          /*!< L2 Com Seg select */
7094 #define LCD_F_CSSEL0_CSS3_OFS                    ( 3)                            /*!< LCDCSS3 Bit Offset */
7095 #define LCD_F_CSSEL0_CSS3                        ((uint32_t)0x00000008)          /*!< L3 Com Seg select */
7096 #define LCD_F_CSSEL0_CSS4_OFS                    ( 4)                            /*!< LCDCSS4 Bit Offset */
7097 #define LCD_F_CSSEL0_CSS4                        ((uint32_t)0x00000010)          /*!< L4 Com Seg select */
7098 #define LCD_F_CSSEL0_CSS5_OFS                    ( 5)                            /*!< LCDCSS5 Bit Offset */
7099 #define LCD_F_CSSEL0_CSS5                        ((uint32_t)0x00000020)          /*!< L5 Com Seg select */
7100 #define LCD_F_CSSEL0_CSS6_OFS                    ( 6)                            /*!< LCDCSS6 Bit Offset */
7101 #define LCD_F_CSSEL0_CSS6                        ((uint32_t)0x00000040)          /*!< L6 Com Seg select */
7102 #define LCD_F_CSSEL0_CSS7_OFS                    ( 7)                            /*!< LCDCSS7 Bit Offset */
7103 #define LCD_F_CSSEL0_CSS7                        ((uint32_t)0x00000080)          /*!< L7 Com Seg select */
7104 #define LCD_F_CSSEL0_CSS8_OFS                    ( 8)                            /*!< LCDCSS8 Bit Offset */
7105 #define LCD_F_CSSEL0_CSS8                        ((uint32_t)0x00000100)          /*!< L8 Com Seg select */
7106 #define LCD_F_CSSEL0_CSS9_OFS                    ( 9)                            /*!< LCDCSS9 Bit Offset */
7107 #define LCD_F_CSSEL0_CSS9                        ((uint32_t)0x00000200)          /*!< L9 Com Seg select */
7108 #define LCD_F_CSSEL0_CSS10_OFS                   (10)                            /*!< LCDCSS10 Bit Offset */
7109 #define LCD_F_CSSEL0_CSS10                       ((uint32_t)0x00000400)          /*!< L10 Com Seg select */
7110 #define LCD_F_CSSEL0_CSS11_OFS                   (11)                            /*!< LCDCSS11 Bit Offset */
7111 #define LCD_F_CSSEL0_CSS11                       ((uint32_t)0x00000800)          /*!< L11 Com Seg select */
7112 #define LCD_F_CSSEL0_CSS12_OFS                   (12)                            /*!< LCDCSS12 Bit Offset */
7113 #define LCD_F_CSSEL0_CSS12                       ((uint32_t)0x00001000)          /*!< L12 Com Seg select */
7114 #define LCD_F_CSSEL0_CSS13_OFS                   (13)                            /*!< LCDCSS13 Bit Offset */
7115 #define LCD_F_CSSEL0_CSS13                       ((uint32_t)0x00002000)          /*!< L13 Com Seg select */
7116 #define LCD_F_CSSEL0_CSS14_OFS                   (14)                            /*!< LCDCSS14 Bit Offset */
7117 #define LCD_F_CSSEL0_CSS14                       ((uint32_t)0x00004000)          /*!< L14 Com Seg select */
7118 #define LCD_F_CSSEL0_CSS15_OFS                   (15)                            /*!< LCDCSS15 Bit Offset */
7119 #define LCD_F_CSSEL0_CSS15                       ((uint32_t)0x00008000)          /*!< L15 Com Seg select */
7120 #define LCD_F_CSSEL0_CSS16_OFS                   (16)                            /*!< LCDCSS16 Bit Offset */
7121 #define LCD_F_CSSEL0_CSS16                       ((uint32_t)0x00010000)          /*!< L16 Com Seg select */
7122 #define LCD_F_CSSEL0_CSS17_OFS                   (17)                            /*!< LCDCSS17 Bit Offset */
7123 #define LCD_F_CSSEL0_CSS17                       ((uint32_t)0x00020000)          /*!< L17 Com Seg select */
7124 #define LCD_F_CSSEL0_CSS18_OFS                   (18)                            /*!< LCDCSS18 Bit Offset */
7125 #define LCD_F_CSSEL0_CSS18                       ((uint32_t)0x00040000)          /*!< L18 Com Seg select */
7126 #define LCD_F_CSSEL0_CSS19_OFS                   (19)                            /*!< LCDCSS19 Bit Offset */
7127 #define LCD_F_CSSEL0_CSS19                       ((uint32_t)0x00080000)          /*!< L19 Com Seg select */
7128 #define LCD_F_CSSEL0_CSS20_OFS                   (20)                            /*!< LCDCSS20 Bit Offset */
7129 #define LCD_F_CSSEL0_CSS20                       ((uint32_t)0x00100000)          /*!< L20 Com Seg select */
7130 #define LCD_F_CSSEL0_CSS21_OFS                   (21)                            /*!< LCDCSS21 Bit Offset */
7131 #define LCD_F_CSSEL0_CSS21                       ((uint32_t)0x00200000)          /*!< L21 Com Seg select */
7132 #define LCD_F_CSSEL0_CSS22_OFS                   (22)                            /*!< LCDCSS22 Bit Offset */
7133 #define LCD_F_CSSEL0_CSS22                       ((uint32_t)0x00400000)          /*!< L22 Com Seg select */
7134 #define LCD_F_CSSEL0_CSS23_OFS                   (23)                            /*!< LCDCSS23 Bit Offset */
7135 #define LCD_F_CSSEL0_CSS23                       ((uint32_t)0x00800000)          /*!< L23 Com Seg select */
7136 #define LCD_F_CSSEL0_CSS24_OFS                   (24)                            /*!< LCDCSS24 Bit Offset */
7137 #define LCD_F_CSSEL0_CSS24                       ((uint32_t)0x01000000)          /*!< L24 Com Seg select */
7138 #define LCD_F_CSSEL0_CSS25_OFS                   (25)                            /*!< LCDCSS25 Bit Offset */
7139 #define LCD_F_CSSEL0_CSS25                       ((uint32_t)0x02000000)          /*!< L25 Com Seg select */
7140 #define LCD_F_CSSEL0_CSS26_OFS                   (26)                            /*!< LCDCSS26 Bit Offset */
7141 #define LCD_F_CSSEL0_CSS26                       ((uint32_t)0x04000000)          /*!< L26 Com Seg select */
7142 #define LCD_F_CSSEL0_CSS27_OFS                   (27)                            /*!< LCDCSS27 Bit Offset */
7143 #define LCD_F_CSSEL0_CSS27                       ((uint32_t)0x08000000)          /*!< L27 Com Seg select */
7144 #define LCD_F_CSSEL0_CSS28_OFS                   (28)                            /*!< LCDCSS28 Bit Offset */
7145 #define LCD_F_CSSEL0_CSS28                       ((uint32_t)0x10000000)          /*!< L28 Com Seg select */
7146 #define LCD_F_CSSEL0_CSS29_OFS                   (29)                            /*!< LCDCSS29 Bit Offset */
7147 #define LCD_F_CSSEL0_CSS29                       ((uint32_t)0x20000000)          /*!< L29 Com Seg select */
7148 #define LCD_F_CSSEL0_CSS30_OFS                   (30)                            /*!< LCDCSS30 Bit Offset */
7149 #define LCD_F_CSSEL0_CSS30                       ((uint32_t)0x40000000)          /*!< L30 Com Seg select */
7150 #define LCD_F_CSSEL0_CSS31_OFS                   (31)                            /*!< LCDCSS31 Bit Offset */
7151 #define LCD_F_CSSEL0_CSS31                       ((uint32_t)0x80000000)          /*!< L31 Com Seg select */
7152 #define LCD_F_CSSEL1_CSS32_OFS                   ( 0)                            /*!< LCDCSS32 Bit Offset */
7153 #define LCD_F_CSSEL1_CSS32                       ((uint32_t)0x00000001)          /*!< L32 Com Seg select */
7154 #define LCD_F_CSSEL1_CSS33_OFS                   ( 1)                            /*!< LCDCSS33 Bit Offset */
7155 #define LCD_F_CSSEL1_CSS33                       ((uint32_t)0x00000002)          /*!< L33 Com Seg select */
7156 #define LCD_F_CSSEL1_CSS34_OFS                   ( 2)                            /*!< LCDCSS34 Bit Offset */
7157 #define LCD_F_CSSEL1_CSS34                       ((uint32_t)0x00000004)          /*!< L34 Com Seg select */
7158 #define LCD_F_CSSEL1_CSS35_OFS                   ( 3)                            /*!< LCDCSS35 Bit Offset */
7159 #define LCD_F_CSSEL1_CSS35                       ((uint32_t)0x00000008)          /*!< L35 Com Seg select */
7160 #define LCD_F_CSSEL1_CSS36_OFS                   ( 4)                            /*!< LCDCSS36 Bit Offset */
7161 #define LCD_F_CSSEL1_CSS36                       ((uint32_t)0x00000010)          /*!< L36 Com Seg select */
7162 #define LCD_F_CSSEL1_CSS37_OFS                   ( 5)                            /*!< LCDCSS37 Bit Offset */
7163 #define LCD_F_CSSEL1_CSS37                       ((uint32_t)0x00000020)          /*!< L37 Com Seg select */
7164 #define LCD_F_CSSEL1_CSS38_OFS                   ( 6)                            /*!< LCDCSS38 Bit Offset */
7165 #define LCD_F_CSSEL1_CSS38                       ((uint32_t)0x00000040)          /*!< L38 Com Seg select */
7166 #define LCD_F_CSSEL1_CSS39_OFS                   ( 7)                            /*!< LCDCSS39 Bit Offset */
7167 #define LCD_F_CSSEL1_CSS39                       ((uint32_t)0x00000080)          /*!< L39 Com Seg select */
7168 #define LCD_F_CSSEL1_CSS40_OFS                   ( 8)                            /*!< LCDCSS40 Bit Offset */
7169 #define LCD_F_CSSEL1_CSS40                       ((uint32_t)0x00000100)          /*!< L40 Com Seg select */
7170 #define LCD_F_CSSEL1_CSS41_OFS                   ( 9)                            /*!< LCDCSS41 Bit Offset */
7171 #define LCD_F_CSSEL1_CSS41                       ((uint32_t)0x00000200)          /*!< L41 Com Seg select */
7172 #define LCD_F_CSSEL1_CSS42_OFS                   (10)                            /*!< LCDCSS42 Bit Offset */
7173 #define LCD_F_CSSEL1_CSS42                       ((uint32_t)0x00000400)          /*!< L42 Com Seg select */
7174 #define LCD_F_CSSEL1_CSS43_OFS                   (11)                            /*!< LCDCSS43 Bit Offset */
7175 #define LCD_F_CSSEL1_CSS43                       ((uint32_t)0x00000800)          /*!< L43 Com Seg select */
7176 #define LCD_F_CSSEL1_CSS44_OFS                   (12)                            /*!< LCDCSS44 Bit Offset */
7177 #define LCD_F_CSSEL1_CSS44                       ((uint32_t)0x00001000)          /*!< L44 Com Seg select */
7178 #define LCD_F_CSSEL1_CSS45_OFS                   (13)                            /*!< LCDCSS45 Bit Offset */
7179 #define LCD_F_CSSEL1_CSS45                       ((uint32_t)0x00002000)          /*!< L45 Com Seg select */
7180 #define LCD_F_CSSEL1_CSS46_OFS                   (14)                            /*!< LCDCSS46 Bit Offset */
7181 #define LCD_F_CSSEL1_CSS46                       ((uint32_t)0x00004000)          /*!< L46 Com Seg select */
7182 #define LCD_F_CSSEL1_CSS47_OFS                   (15)                            /*!< LCDCSS47 Bit Offset */
7183 #define LCD_F_CSSEL1_CSS47                       ((uint32_t)0x00008000)          /*!< L47 Com Seg select */
7184 #define LCD_F_CSSEL1_CSS48_OFS                   (16)                            /*!< LCDCSS48 Bit Offset */
7185 #define LCD_F_CSSEL1_CSS48                       ((uint32_t)0x00010000)          /*!< L48 Com Seg select */
7186 #define LCD_F_CSSEL1_CSS49_OFS                   (17)                            /*!< LCDCSS49 Bit Offset */
7187 #define LCD_F_CSSEL1_CSS49                       ((uint32_t)0x00020000)          /*!< L49 Com Seg select */
7188 #define LCD_F_CSSEL1_CSS50_OFS                   (18)                            /*!< LCDCSS50 Bit Offset */
7189 #define LCD_F_CSSEL1_CSS50                       ((uint32_t)0x00040000)          /*!< L50 Com Seg select */
7190 #define LCD_F_CSSEL1_CSS51_OFS                   (19)                            /*!< LCDCSS51 Bit Offset */
7191 #define LCD_F_CSSEL1_CSS51                       ((uint32_t)0x00080000)          /*!< L51 Com Seg select */
7192 #define LCD_F_CSSEL1_CSS52_OFS                   (20)                            /*!< LCDCSS52 Bit Offset */
7193 #define LCD_F_CSSEL1_CSS52                       ((uint32_t)0x00100000)          /*!< L52 Com Seg select */
7194 #define LCD_F_CSSEL1_CSS53_OFS                   (21)                            /*!< LCDCSS53 Bit Offset */
7195 #define LCD_F_CSSEL1_CSS53                       ((uint32_t)0x00200000)          /*!< L53 Com Seg select */
7196 #define LCD_F_CSSEL1_CSS54_OFS                   (22)                            /*!< LCDCSS54 Bit Offset */
7197 #define LCD_F_CSSEL1_CSS54                       ((uint32_t)0x00400000)          /*!< L54 Com Seg select */
7198 #define LCD_F_CSSEL1_CSS55_OFS                   (23)                            /*!< LCDCSS55 Bit Offset */
7199 #define LCD_F_CSSEL1_CSS55                       ((uint32_t)0x00800000)          /*!< L55 Com Seg select */
7200 #define LCD_F_CSSEL1_CSS56_OFS                   (24)                            /*!< LCDCSS56 Bit Offset */
7201 #define LCD_F_CSSEL1_CSS56                       ((uint32_t)0x01000000)          /*!< L56 Com Seg select */
7202 #define LCD_F_CSSEL1_CSS57_OFS                   (25)                            /*!< LCDCSS57 Bit Offset */
7203 #define LCD_F_CSSEL1_CSS57                       ((uint32_t)0x02000000)          /*!< L57 Com Seg select */
7204 #define LCD_F_CSSEL1_CSS58_OFS                   (26)                            /*!< LCDCSS58 Bit Offset */
7205 #define LCD_F_CSSEL1_CSS58                       ((uint32_t)0x04000000)          /*!< L58 Com Seg select */
7206 #define LCD_F_CSSEL1_CSS59_OFS                   (27)                            /*!< LCDCSS59 Bit Offset */
7207 #define LCD_F_CSSEL1_CSS59                       ((uint32_t)0x08000000)          /*!< L59 Com Seg select */
7208 #define LCD_F_CSSEL1_CSS60_OFS                   (28)                            /*!< LCDCSS60 Bit Offset */
7209 #define LCD_F_CSSEL1_CSS60                       ((uint32_t)0x10000000)          /*!< L60 Com Seg select */
7210 #define LCD_F_CSSEL1_CSS61_OFS                   (29)                            /*!< LCDCSS61 Bit Offset */
7211 #define LCD_F_CSSEL1_CSS61                       ((uint32_t)0x20000000)          /*!< L61 Com Seg select */
7212 #define LCD_F_CSSEL1_CSS62_OFS                   (30)                            /*!< LCDCSS62 Bit Offset */
7213 #define LCD_F_CSSEL1_CSS62                       ((uint32_t)0x40000000)          /*!< L62 Com Seg select */
7214 #define LCD_F_CSSEL1_CSS63_OFS                   (31)                            /*!< LCDCSS63 Bit Offset */
7215 #define LCD_F_CSSEL1_CSS63                       ((uint32_t)0x80000000)          /*!< L63 Com Seg select */
7216 #define LCD_F_ANMCTL_ANMEN_OFS                   ( 0)                            /*!< LCDANMEN Bit Offset */
7217 #define LCD_F_ANMCTL_ANMEN                       ((uint32_t)0x00000001)          /*!< Enable Animation */
7218 #define LCD_F_ANMCTL_ANMSTP_OFS                  ( 1)                            /*!< LCDANMSTP Bit Offset */
7219 #define LCD_F_ANMCTL_ANMSTP_MASK                 ((uint32_t)0x0000000E)          /*!< LCDANMSTP Bit Mask */
7220 #define LCD_F_ANMCTL_ANMSTP0                     ((uint32_t)0x00000002)          /*!< ANMSTP Bit 0 */
7221 #define LCD_F_ANMCTL_ANMSTP1                     ((uint32_t)0x00000004)          /*!< ANMSTP Bit 1 */
7222 #define LCD_F_ANMCTL_ANMSTP2                     ((uint32_t)0x00000008)          /*!< ANMSTP Bit 2 */
7223 #define LCD_F_ANMCTL_ANMSTP_0                    ((uint32_t)0x00000000)          /*!< T0 */
7224 #define LCD_F_ANMCTL_ANMSTP_1                    ((uint32_t)0x00000002)          /*!< T0 to T1 */
7225 #define LCD_F_ANMCTL_ANMSTP_2                    ((uint32_t)0x00000004)          /*!< T0 to T2 */
7226 #define LCD_F_ANMCTL_ANMSTP_3                    ((uint32_t)0x00000006)          /*!< T0 to T3 */
7227 #define LCD_F_ANMCTL_ANMSTP_4                    ((uint32_t)0x00000008)          /*!< T0 to T4 */
7228 #define LCD_F_ANMCTL_ANMSTP_5                    ((uint32_t)0x0000000A)          /*!< T0 to T5 */
7229 #define LCD_F_ANMCTL_ANMSTP_6                    ((uint32_t)0x0000000C)          /*!< T0 to T6 */
7230 #define LCD_F_ANMCTL_ANMSTP_7                    ((uint32_t)0x0000000E)          /*!< T0 to T7 */
7231 #define LCD_F_ANMCTL_ANMCLR_OFS                  ( 7)                            /*!< LCDANMCLR Bit Offset */
7232 #define LCD_F_ANMCTL_ANMCLR                      ((uint32_t)0x00000080)          /*!< Clear Animation Memory */
7233 #define LCD_F_ANMCTL_ANMPRE_OFS                  (16)                            /*!< LCDANMPREx Bit Offset */
7234 #define LCD_F_ANMCTL_ANMPRE_MASK                 ((uint32_t)0x00070000)          /*!< LCDANMPREx Bit Mask */
7235 #define LCD_F_ANMCTL_ANMPRE0                     ((uint32_t)0x00010000)          /*!< ANMPRE Bit 0 */
7236 #define LCD_F_ANMCTL_ANMPRE1                     ((uint32_t)0x00020000)          /*!< ANMPRE Bit 1 */
7237 #define LCD_F_ANMCTL_ANMPRE2                     ((uint32_t)0x00040000)          /*!< ANMPRE Bit 2 */
7238 #define LCD_F_ANMCTL_ANMPRE_0                    ((uint32_t)0x00000000)          /*!< Divide by 512 */
7239 #define LCD_F_ANMCTL_ANMPRE_1                    ((uint32_t)0x00010000)          /*!< Divide by 1024 */
7240 #define LCD_F_ANMCTL_ANMPRE_2                    ((uint32_t)0x00020000)          /*!< Divide by 2048 */
7241 #define LCD_F_ANMCTL_ANMPRE_3                    ((uint32_t)0x00030000)          /*!< Divide by 4096 */
7242 #define LCD_F_ANMCTL_ANMPRE_4                    ((uint32_t)0x00040000)          /*!< Divide by 8162 */
7243 #define LCD_F_ANMCTL_ANMPRE_5                    ((uint32_t)0x00050000)          /*!< Divide by 16384 */
7244 #define LCD_F_ANMCTL_ANMPRE_6                    ((uint32_t)0x00060000)          /*!< Divide by 32768 */
7245 #define LCD_F_ANMCTL_ANMPRE_7                    ((uint32_t)0x00070000)          /*!< Divide by 65536 */
7246 #define LCD_F_ANMCTL_ANMDIV_OFS                  (19)                            /*!< LCDANMDIVx Bit Offset */
7247 #define LCD_F_ANMCTL_ANMDIV_MASK                 ((uint32_t)0x00380000)          /*!< LCDANMDIVx Bit Mask */
7248 #define LCD_F_ANMCTL_ANMDIV0                     ((uint32_t)0x00080000)          /*!< ANMDIV Bit 0 */
7249 #define LCD_F_ANMCTL_ANMDIV1                     ((uint32_t)0x00100000)          /*!< ANMDIV Bit 1 */
7250 #define LCD_F_ANMCTL_ANMDIV2                     ((uint32_t)0x00200000)          /*!< ANMDIV Bit 2 */
7251 #define LCD_F_ANMCTL_ANMDIV_0                    ((uint32_t)0x00000000)          /*!< Divide by 1 */
7252 #define LCD_F_ANMCTL_ANMDIV_1                    ((uint32_t)0x00080000)          /*!< Divide by 2 */
7253 #define LCD_F_ANMCTL_ANMDIV_2                    ((uint32_t)0x00100000)          /*!< Divide by 3 */
7254 #define LCD_F_ANMCTL_ANMDIV_3                    ((uint32_t)0x00180000)          /*!< Divide by 4 */
7255 #define LCD_F_ANMCTL_ANMDIV_4                    ((uint32_t)0x00200000)          /*!< Divide by 5 */
7256 #define LCD_F_ANMCTL_ANMDIV_5                    ((uint32_t)0x00280000)          /*!< Divide by 6 */
7257 #define LCD_F_ANMCTL_ANMDIV_6                    ((uint32_t)0x00300000)          /*!< Divide by 7 */
7258 #define LCD_F_ANMCTL_ANMDIV_7                    ((uint32_t)0x00380000)          /*!< Divide by 8 */
7259 #define LCD_F_IE_BLKOFFIE_OFS                    ( 1)                            /*!< LCDBLKOFFIE Bit Offset */
7260 #define LCD_F_IE_BLKOFFIE                        ((uint32_t)0x00000002)          /*!< LCD Blink, segments off interrupt enable */
7261 #define LCD_F_IE_BLKONIE_OFS                     ( 2)                            /*!< LCDBLKONIE Bit Offset */
7262 #define LCD_F_IE_BLKONIE                         ((uint32_t)0x00000004)          /*!< LCD Blink, segments on interrupt enable */
7263 #define LCD_F_IE_FRMIE_OFS                       ( 3)                            /*!< LCDFRMIE Bit Offset */
7264 #define LCD_F_IE_FRMIE                           ((uint32_t)0x00000008)          /*!< LCD Frame interrupt enable */
7265 #define LCD_F_IE_ANMSTPIE_OFS                    ( 8)                            /*!< LCDANMSTPIE Bit Offset */
7266 #define LCD_F_IE_ANMSTPIE                        ((uint32_t)0x00000100)          /*!< LCD Animation step interrupt enable */
7267 #define LCD_F_IE_ANMLOOPIE_OFS                   ( 9)                            /*!< LCDANMLOOPIE Bit Offset */
7268 #define LCD_F_IE_ANMLOOPIE                       ((uint32_t)0x00000200)          /*!< LCD Animation loop interrupt enable */
7269 #define LCD_F_IFG_BLKOFFIFG_OFS                  ( 1)                            /*!< LCDBLKOFFIFG Bit Offset */
7270 #define LCD_F_IFG_BLKOFFIFG                      ((uint32_t)0x00000002)          /*!< LCD Blink, segments off interrupt flag */
7271 #define LCD_F_IFG_BLKONIFG_OFS                   ( 2)                            /*!< LCDBLKONIFG Bit Offset */
7272 #define LCD_F_IFG_BLKONIFG                       ((uint32_t)0x00000004)          /*!< LCD Blink, segments on interrupt flag */
7273 #define LCD_F_IFG_FRMIFG_OFS                     ( 3)                            /*!< LCDFRMIFG Bit Offset */
7274 #define LCD_F_IFG_FRMIFG                         ((uint32_t)0x00000008)          /*!< LCD Frame interrupt flag */
7275 #define LCD_F_IFG_ANMSTPIFG_OFS                  ( 8)                            /*!< LCDANMSTPIFG Bit Offset */
7276 #define LCD_F_IFG_ANMSTPIFG                      ((uint32_t)0x00000100)          /*!< LCD Animation step interrupt flag */
7277 #define LCD_F_IFG_ANMLOOPIFG_OFS                 ( 9)                            /*!< LCDANMLOOPIFG Bit Offset */
7278 #define LCD_F_IFG_ANMLOOPIFG                     ((uint32_t)0x00000200)          /*!< LCD Animation loop interrupt flag */
7279 #define LCD_F_SETIFG_SETLCDBLKOFFIFG_OFS         ( 1)                            /*!< SETLCDBLKOFFIFG Bit Offset */
7280 #define LCD_F_SETIFG_SETLCDBLKOFFIFG             ((uint32_t)0x00000002)          /*!< Sets LCDBLKOFFIFG */
7281 #define LCD_F_SETIFG_SETLCDBLKONIFG_OFS          ( 2)                            /*!< SETLCDBLKONIFG Bit Offset */
7282 #define LCD_F_SETIFG_SETLCDBLKONIFG              ((uint32_t)0x00000004)          /*!< Sets LCDBLKONIFG */
7283 #define LCD_F_SETIFG_SETLCDFRMIFG_OFS            ( 3)                            /*!< SETLCDFRMIFG Bit Offset */
7284 #define LCD_F_SETIFG_SETLCDFRMIFG                ((uint32_t)0x00000008)          /*!< Sets LCDFRMIFG */
7285 #define LCD_F_SETIFG_SETLCDANMSTPIFG_OFS         ( 8)                            /*!< SETLCDANMSTPIFG Bit Offset */
7286 #define LCD_F_SETIFG_SETLCDANMSTPIFG             ((uint32_t)0x00000100)          /*!< Sets LCDANMSTPIFG */
7287 #define LCD_F_SETIFG_SETLCDANMLOOPIFG_OFS        ( 9)                            /*!< SETLCDANMLOOPIFG Bit Offset */
7288 #define LCD_F_SETIFG_SETLCDANMLOOPIFG            ((uint32_t)0x00000200)          /*!< Sets LCDANMLOOPIFG */
7289 #define LCD_F_CLRIFG_CLRLCDBLKOFFIFG_OFS         ( 1)                            /*!< CLRLCDBLKOFFIFG Bit Offset */
7290 #define LCD_F_CLRIFG_CLRLCDBLKOFFIFG             ((uint32_t)0x00000002)          /*!< Clears LCDBLKOFFIFG */
7291 #define LCD_F_CLRIFG_CLRLCDBLKONIFG_OFS          ( 2)                            /*!< CLRLCDBLKONIFG Bit Offset */
7292 #define LCD_F_CLRIFG_CLRLCDBLKONIFG              ((uint32_t)0x00000004)          /*!< Clears LCDBLKONIFG */
7293 #define LCD_F_CLRIFG_CLRLCDFRMIFG_OFS            ( 3)                            /*!< CLRLCDFRMIFG Bit Offset */
7294 #define LCD_F_CLRIFG_CLRLCDFRMIFG                ((uint32_t)0x00000008)          /*!< Clears LCDFRMIFG */
7295 #define LCD_F_CLRIFG_CLRLCDANMSTPIFG_OFS         ( 8)                            /*!< CLRLCDANMSTPIFG Bit Offset */
7296 #define LCD_F_CLRIFG_CLRLCDANMSTPIFG             ((uint32_t)0x00000100)          /*!< Clears LCDANMSTPIFG */
7297 #define LCD_F_CLRIFG_CLRLCDANMLOOPIFG_OFS        ( 9)                            /*!< CLRLCDANMLOOPIFG Bit Offset */
7298 #define LCD_F_CLRIFG_CLRLCDANMLOOPIFG            ((uint32_t)0x00000200)          /*!< Clears LCDANMLOOPIFG */
7299 #define SYSCTL_A_REBOOT_CTL_REBOOT_OFS           ( 0)                            /*!< REBOOT Bit Offset */
7300 #define SYSCTL_A_REBOOT_CTL_REBOOT               ((uint32_t)0x00000001)          /*!< Write 1 initiates a Reboot of the device */
7301 #define SYSCTL_A_REBOOT_CTL_WKEY_OFS             ( 8)                            /*!< WKEY Bit Offset */
7302 #define SYSCTL_A_REBOOT_CTL_WKEY_MASK            ((uint32_t)0x0000FF00)          /*!< WKEY Bit Mask */
7303 #define SYSCTL_A_NMI_CTLSTAT_CS_SRC_OFS          ( 0)                            /*!< CS_SRC Bit Offset */
7304 #define SYSCTL_A_NMI_CTLSTAT_CS_SRC              ((uint32_t)0x00000001)          /*!< CS interrupt as a source of NMI */
7305 #define SYSCTL_A_NMI_CTLSTAT_PSS_SRC_OFS         ( 1)                            /*!< PSS_SRC Bit Offset */
7306 #define SYSCTL_A_NMI_CTLSTAT_PSS_SRC             ((uint32_t)0x00000002)          /*!< PSS interrupt as a source of NMI */
7307 #define SYSCTL_A_NMI_CTLSTAT_PCM_SRC_OFS         ( 2)                            /*!< PCM_SRC Bit Offset */
7308 #define SYSCTL_A_NMI_CTLSTAT_PCM_SRC             ((uint32_t)0x00000004)          /*!< PCM interrupt as a source of NMI */
7309 #define SYSCTL_A_NMI_CTLSTAT_PIN_SRC_OFS         ( 3)                            /*!< PIN_SRC Bit Offset */
7310 #define SYSCTL_A_NMI_CTLSTAT_PIN_SRC             ((uint32_t)0x00000008)
7311 #define SYSCTL_A_NMI_CTLSTAT_CS_FLG_OFS          (16)                            /*!< CS_FLG Bit Offset */
7312 #define SYSCTL_A_NMI_CTLSTAT_CS_FLG              ((uint32_t)0x00010000)          /*!< CS interrupt was the source of NMI */
7313 #define SYSCTL_A_NMI_CTLSTAT_PSS_FLG_OFS         (17)                            /*!< PSS_FLG Bit Offset */
7314 #define SYSCTL_A_NMI_CTLSTAT_PSS_FLG             ((uint32_t)0x00020000)          /*!< PSS interrupt was the source of NMI */
7315 #define SYSCTL_A_NMI_CTLSTAT_PCM_FLG_OFS         (18)                            /*!< PCM_FLG Bit Offset */
7316 #define SYSCTL_A_NMI_CTLSTAT_PCM_FLG             ((uint32_t)0x00040000)          /*!< PCM interrupt was the source of NMI */
7317 #define SYSCTL_A_NMI_CTLSTAT_PIN_FLG_OFS         (19)                            /*!< PIN_FLG Bit Offset */
7318 #define SYSCTL_A_NMI_CTLSTAT_PIN_FLG             ((uint32_t)0x00080000)          /*!< RSTn/NMI pin was the source of NMI */
7319 #define SYSCTL_A_WDTRESET_CTL_TIMEOUT_OFS        ( 0)                            /*!< TIMEOUT Bit Offset */
7320 #define SYSCTL_A_WDTRESET_CTL_TIMEOUT            ((uint32_t)0x00000001)          /*!< WDT timeout reset type */
7321 #define SYSCTL_A_WDTRESET_CTL_VIOLATION_OFS      ( 1)                            /*!< VIOLATION Bit Offset */
7322 #define SYSCTL_A_WDTRESET_CTL_VIOLATION          ((uint32_t)0x00000002)          /*!< WDT password violation reset type */
7323 #define SYSCTL_A_PERIHALT_CTL_HALT_T16_0_OFS     ( 0)                            /*!< HALT_T16_0 Bit Offset */
7324 #define SYSCTL_A_PERIHALT_CTL_HALT_T16_0         ((uint32_t)0x00000001)          /*!< Freezes IP operation when CPU is halted */
7325 #define SYSCTL_A_PERIHALT_CTL_HALT_T16_1_OFS     ( 1)                            /*!< HALT_T16_1 Bit Offset */
7326 #define SYSCTL_A_PERIHALT_CTL_HALT_T16_1         ((uint32_t)0x00000002)          /*!< Freezes IP operation when CPU is halted */
7327 #define SYSCTL_A_PERIHALT_CTL_HALT_T16_2_OFS     ( 2)                            /*!< HALT_T16_2 Bit Offset */
7328 #define SYSCTL_A_PERIHALT_CTL_HALT_T16_2         ((uint32_t)0x00000004)          /*!< Freezes IP operation when CPU is halted */
7329 #define SYSCTL_A_PERIHALT_CTL_HALT_T16_3_OFS     ( 3)                            /*!< HALT_T16_3 Bit Offset */
7330 #define SYSCTL_A_PERIHALT_CTL_HALT_T16_3         ((uint32_t)0x00000008)          /*!< Freezes IP operation when CPU is halted */
7331 #define SYSCTL_A_PERIHALT_CTL_HALT_T32_0_OFS     ( 4)                            /*!< HALT_T32_0 Bit Offset */
7332 #define SYSCTL_A_PERIHALT_CTL_HALT_T32_0         ((uint32_t)0x00000010)          /*!< Freezes IP operation when CPU is halted */
7333 #define SYSCTL_A_PERIHALT_CTL_HALT_EUA0_OFS      ( 5)                            /*!< HALT_eUA0 Bit Offset */
7334 #define SYSCTL_A_PERIHALT_CTL_HALT_EUA0          ((uint32_t)0x00000020)          /*!< Freezes IP operation when CPU is halted */
7335 #define SYSCTL_A_PERIHALT_CTL_HALT_EUA1_OFS      ( 6)                            /*!< HALT_eUA1 Bit Offset */
7336 #define SYSCTL_A_PERIHALT_CTL_HALT_EUA1          ((uint32_t)0x00000040)          /*!< Freezes IP operation when CPU is halted */
7337 #define SYSCTL_A_PERIHALT_CTL_HALT_EUA2_OFS      ( 7)                            /*!< HALT_eUA2 Bit Offset */
7338 #define SYSCTL_A_PERIHALT_CTL_HALT_EUA2          ((uint32_t)0x00000080)          /*!< Freezes IP operation when CPU is halted */
7339 #define SYSCTL_A_PERIHALT_CTL_HALT_EUA3_OFS      ( 8)                            /*!< HALT_eUA3 Bit Offset */
7340 #define SYSCTL_A_PERIHALT_CTL_HALT_EUA3          ((uint32_t)0x00000100)          /*!< Freezes IP operation when CPU is halted */
7341 #define SYSCTL_A_PERIHALT_CTL_HALT_EUB0_OFS      ( 9)                            /*!< HALT_eUB0 Bit Offset */
7342 #define SYSCTL_A_PERIHALT_CTL_HALT_EUB0          ((uint32_t)0x00000200)          /*!< Freezes IP operation when CPU is halted */
7343 #define SYSCTL_A_PERIHALT_CTL_HALT_EUB1_OFS      (10)                            /*!< HALT_eUB1 Bit Offset */
7344 #define SYSCTL_A_PERIHALT_CTL_HALT_EUB1          ((uint32_t)0x00000400)          /*!< Freezes IP operation when CPU is halted */
7345 #define SYSCTL_A_PERIHALT_CTL_HALT_EUB2_OFS      (11)                            /*!< HALT_eUB2 Bit Offset */
7346 #define SYSCTL_A_PERIHALT_CTL_HALT_EUB2          ((uint32_t)0x00000800)          /*!< Freezes IP operation when CPU is halted */
7347 #define SYSCTL_A_PERIHALT_CTL_HALT_EUB3_OFS      (12)                            /*!< HALT_eUB3 Bit Offset */
7348 #define SYSCTL_A_PERIHALT_CTL_HALT_EUB3          ((uint32_t)0x00001000)          /*!< Freezes IP operation when CPU is halted */
7349 #define SYSCTL_A_PERIHALT_CTL_HALT_ADC_OFS       (13)                            /*!< HALT_ADC Bit Offset */
7350 #define SYSCTL_A_PERIHALT_CTL_HALT_ADC           ((uint32_t)0x00002000)          /*!< Freezes IP operation when CPU is halted */
7351 #define SYSCTL_A_PERIHALT_CTL_HALT_WDT_OFS       (14)                            /*!< HALT_WDT Bit Offset */
7352 #define SYSCTL_A_PERIHALT_CTL_HALT_WDT           ((uint32_t)0x00004000)          /*!< Freezes IP operation when CPU is halted */
7353 #define SYSCTL_A_PERIHALT_CTL_HALT_DMA_OFS       (15)                            /*!< HALT_DMA Bit Offset */
7354 #define SYSCTL_A_PERIHALT_CTL_HALT_DMA           ((uint32_t)0x00008000)          /*!< Freezes IP operation when CPU is halted */
7355 #define SYSCTL_A_PERIHALT_CTL_HALT_LCD_OFS       (16)                            /*!< HALT_LCD Bit Offset */
7356 #define SYSCTL_A_PERIHALT_CTL_HALT_LCD           ((uint32_t)0x00010000)          /*!< Freezes IP operation when CPU is halted */
7357 #define SYSCTL_A_DIO_GLTFLT_CTL_GLTCH_EN_OFS     ( 0)                            /*!< GLTCH_EN Bit Offset */
7358 #define SYSCTL_A_DIO_GLTFLT_CTL_GLTCH_EN         ((uint32_t)0x00000001)          /*!< Glitch filter enable */
7359 #define SYSCTL_A_SECDATA_UNLOCK_UNLKEY_OFS       ( 0)                            /*!< UNLKEY Bit Offset */
7360 #define SYSCTL_A_SECDATA_UNLOCK_UNLKEY_MASK      ((uint32_t)0x0000FFFF)          /*!< UNLKEY Bit Mask */
7361 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK0_EN_OFS    ( 0)                            /*!< BNK0_EN Bit Offset */
7362 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK0_EN        ((uint32_t)0x00000001)          /*!< When 1, enables Bank0 of the SRAM */
7363 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK1_EN_OFS    ( 1)                            /*!< BNK1_EN Bit Offset */
7364 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK1_EN        ((uint32_t)0x00000002)          /*!< When 1, enables Bank1 of the SRAM */
7365 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK2_EN_OFS    ( 2)                            /*!< BNK2_EN Bit Offset */
7366 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK2_EN        ((uint32_t)0x00000004)          /*!< When 1, enables Bank2 of the SRAM */
7367 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK3_EN_OFS    ( 3)                            /*!< BNK3_EN Bit Offset */
7368 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK3_EN        ((uint32_t)0x00000008)          /*!< When 1, enables Bank3 of the SRAM */
7369 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK4_EN_OFS    ( 4)                            /*!< BNK4_EN Bit Offset */
7370 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK4_EN        ((uint32_t)0x00000010)          /*!< When 1, enables Bank4 of the SRAM */
7371 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK5_EN_OFS    ( 5)                            /*!< BNK5_EN Bit Offset */
7372 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK5_EN        ((uint32_t)0x00000020)          /*!< When 1, enables Bank5 of the SRAM */
7373 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK6_EN_OFS    ( 6)                            /*!< BNK6_EN Bit Offset */
7374 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK6_EN        ((uint32_t)0x00000040)          /*!< When 1, enables Bank6 of the SRAM */
7375 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK7_EN_OFS    ( 7)                            /*!< BNK7_EN Bit Offset */
7376 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK7_EN        ((uint32_t)0x00000080)          /*!< When 1, enables Bank7 of the SRAM */
7377 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK8_EN_OFS    ( 8)                            /*!< BNK8_EN Bit Offset */
7378 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK8_EN        ((uint32_t)0x00000100)          /*!< When 1, enables Bank8 of the SRAM */
7379 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK9_EN_OFS    ( 9)                            /*!< BNK9_EN Bit Offset */
7380 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK9_EN        ((uint32_t)0x00000200)          /*!< When 1, enables Bank9 of the SRAM */
7381 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK10_EN_OFS   (10)                            /*!< BNK10_EN Bit Offset */
7382 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK10_EN       ((uint32_t)0x00000400)          /*!< When 1, enables Bank10 of the SRAM */
7383 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK11_EN_OFS   (11)                            /*!< BNK11_EN Bit Offset */
7384 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK11_EN       ((uint32_t)0x00000800)          /*!< When 1, enables Bank11 of the SRAM */
7385 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK12_EN_OFS   (12)                            /*!< BNK12_EN Bit Offset */
7386 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK12_EN       ((uint32_t)0x00001000)          /*!< When 1, enables Bank12 of the SRAM */
7387 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK13_EN_OFS   (13)                            /*!< BNK13_EN Bit Offset */
7388 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK13_EN       ((uint32_t)0x00002000)          /*!< When 1, enables Bank13 of the SRAM */
7389 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK14_EN_OFS   (14)                            /*!< BNK14_EN Bit Offset */
7390 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK14_EN       ((uint32_t)0x00004000)          /*!< When 1, enables Bank14 of the SRAM */
7391 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK15_EN_OFS   (15)                            /*!< BNK15_EN Bit Offset */
7392 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK15_EN       ((uint32_t)0x00008000)          /*!< When 1, enables Bank15 of the SRAM */
7393 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK16_EN_OFS   (16)                            /*!< BNK16_EN Bit Offset */
7394 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK16_EN       ((uint32_t)0x00010000)          /*!< When 1, enables Bank16 of the SRAM */
7395 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK17_EN_OFS   (17)                            /*!< BNK17_EN Bit Offset */
7396 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK17_EN       ((uint32_t)0x00020000)          /*!< When 1, enables Bank17 of the SRAM */
7397 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK18_EN_OFS   (18)                            /*!< BNK18_EN Bit Offset */
7398 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK18_EN       ((uint32_t)0x00040000)          /*!< When 1, enables Bank18 of the SRAM */
7399 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK19_EN_OFS   (19)                            /*!< BNK19_EN Bit Offset */
7400 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK19_EN       ((uint32_t)0x00080000)          /*!< When 1, enables Bank19 of the SRAM */
7401 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK20_EN_OFS   (20)                            /*!< BNK20_EN Bit Offset */
7402 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK20_EN       ((uint32_t)0x00100000)          /*!< When 1, enables Bank20 of the SRAM */
7403 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK21_EN_OFS   (21)                            /*!< BNK21_EN Bit Offset */
7404 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK21_EN       ((uint32_t)0x00200000)          /*!< When 1, enables Bank21 of the SRAM */
7405 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK22_EN_OFS   (22)                            /*!< BNK22_EN Bit Offset */
7406 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK22_EN       ((uint32_t)0x00400000)          /*!< When 1, enables Bank22 of the SRAM */
7407 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK23_EN_OFS   (23)                            /*!< BNK23_EN Bit Offset */
7408 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK23_EN       ((uint32_t)0x00800000)          /*!< When 1, enables Bank23 of the SRAM */
7409 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK24_EN_OFS   (24)                            /*!< BNK24_EN Bit Offset */
7410 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK24_EN       ((uint32_t)0x01000000)          /*!< When 1, enables Bank24 of the SRAM */
7411 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK25_EN_OFS   (25)                            /*!< BNK25_EN Bit Offset */
7412 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK25_EN       ((uint32_t)0x02000000)          /*!< When 1, enables Bank25 of the SRAM */
7413 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK26_EN_OFS   (26)                            /*!< BNK26_EN Bit Offset */
7414 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK26_EN       ((uint32_t)0x04000000)          /*!< When 1, enables Bank26 of the SRAM */
7415 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK27_EN_OFS   (27)                            /*!< BNK27_EN Bit Offset */
7416 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK27_EN       ((uint32_t)0x08000000)          /*!< When 1, enables Bank27 of the SRAM */
7417 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK28_EN_OFS   (28)                            /*!< BNK28_EN Bit Offset */
7418 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK28_EN       ((uint32_t)0x10000000)          /*!< When 1, enables Bank28 of the SRAM */
7419 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK29_EN_OFS   (29)                            /*!< BNK29_EN Bit Offset */
7420 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK29_EN       ((uint32_t)0x20000000)          /*!< When 1, enables Bank29 of the SRAM */
7421 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK30_EN_OFS   (30)                            /*!< BNK30_EN Bit Offset */
7422 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK30_EN       ((uint32_t)0x40000000)          /*!< When 1, enables Bank30 of the SRAM */
7423 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK31_EN_OFS   (31)                            /*!< BNK31_EN Bit Offset */
7424 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK31_EN       ((uint32_t)0x80000000)          /*!< When 1, enables Bank31 of the SRAM */
7425 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK32_EN_OFS   ( 0)                            /*!< BNK32_EN Bit Offset */
7426 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK32_EN       ((uint32_t)0x00000001)          /*!< When 1, enables Bank32 of the SRAM */
7427 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK33_EN_OFS   ( 1)                            /*!< BNK33_EN Bit Offset */
7428 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK33_EN       ((uint32_t)0x00000002)          /*!< When 1, enables Bank33 of the SRAM */
7429 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK34_EN_OFS   ( 2)                            /*!< BNK34_EN Bit Offset */
7430 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK34_EN       ((uint32_t)0x00000004)          /*!< When 1, enables Bank34 of the SRAM */
7431 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK35_EN_OFS   ( 3)                            /*!< BNK35_EN Bit Offset */
7432 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK35_EN       ((uint32_t)0x00000008)          /*!< When 1, enables Bank35 of the SRAM */
7433 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK36_EN_OFS   ( 4)                            /*!< BNK36_EN Bit Offset */
7434 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK36_EN       ((uint32_t)0x00000010)          /*!< When 1, enables Bank36 of the SRAM */
7435 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK37_EN_OFS   ( 5)                            /*!< BNK37_EN Bit Offset */
7436 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK37_EN       ((uint32_t)0x00000020)          /*!< When 1, enables Bank37 of the SRAM */
7437 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK38_EN_OFS   ( 6)                            /*!< BNK38_EN Bit Offset */
7438 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK38_EN       ((uint32_t)0x00000040)          /*!< When 1, enables Bank38 of the SRAM */
7439 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK39_EN_OFS   ( 7)                            /*!< BNK39_EN Bit Offset */
7440 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK39_EN       ((uint32_t)0x00000080)          /*!< When 1, enables Bank39 of the SRAM */
7441 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK40_EN_OFS   ( 8)                            /*!< BNK40_EN Bit Offset */
7442 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK40_EN       ((uint32_t)0x00000100)          /*!< When 1, enables Bank40 of the SRAM */
7443 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK41_EN_OFS   ( 9)                            /*!< BNK41_EN Bit Offset */
7444 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK41_EN       ((uint32_t)0x00000200)          /*!< When 1, enables Bank41 of the SRAM */
7445 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK42_EN_OFS   (10)                            /*!< BNK42_EN Bit Offset */
7446 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK42_EN       ((uint32_t)0x00000400)          /*!< When 1, enables Bank42 of the SRAM */
7447 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK43_EN_OFS   (11)                            /*!< BNK43_EN Bit Offset */
7448 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK43_EN       ((uint32_t)0x00000800)          /*!< When 1, enables Bank43 of the SRAM */
7449 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK44_EN_OFS   (12)                            /*!< BNK44_EN Bit Offset */
7450 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK44_EN       ((uint32_t)0x00001000)          /*!< When 1, enables Bank44 of the SRAM */
7451 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK45_EN_OFS   (13)                            /*!< BNK45_EN Bit Offset */
7452 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK45_EN       ((uint32_t)0x00002000)          /*!< When 1, enables Bank45 of the SRAM */
7453 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK46_EN_OFS   (14)                            /*!< BNK46_EN Bit Offset */
7454 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK46_EN       ((uint32_t)0x00004000)          /*!< When 1, enables Bank46 of the SRAM */
7455 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK47_EN_OFS   (15)                            /*!< BNK47_EN Bit Offset */
7456 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK47_EN       ((uint32_t)0x00008000)          /*!< When 1, enables Bank47 of the SRAM */
7457 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK48_EN_OFS   (16)                            /*!< BNK48_EN Bit Offset */
7458 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK48_EN       ((uint32_t)0x00010000)          /*!< When 1, enables Bank48 of the SRAM */
7459 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK49_EN_OFS   (17)                            /*!< BNK49_EN Bit Offset */
7460 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK49_EN       ((uint32_t)0x00020000)          /*!< When 1, enables Bank49 of the SRAM */
7461 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK50_EN_OFS   (18)                            /*!< BNK50_EN Bit Offset */
7462 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK50_EN       ((uint32_t)0x00040000)          /*!< When 1, enables Bank50 of the SRAM */
7463 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK51_EN_OFS   (19)                            /*!< BNK51_EN Bit Offset */
7464 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK51_EN       ((uint32_t)0x00080000)          /*!< When 1, enables Bank51 of the SRAM */
7465 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK52_EN_OFS   (20)                            /*!< BNK52_EN Bit Offset */
7466 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK52_EN       ((uint32_t)0x00100000)          /*!< When 1, enables Bank52 of the SRAM */
7467 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK53_EN_OFS   (21)                            /*!< BNK53_EN Bit Offset */
7468 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK53_EN       ((uint32_t)0x00200000)          /*!< When 1, enables Bank53 of the SRAM */
7469 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK54_EN_OFS   (22)                            /*!< BNK54_EN Bit Offset */
7470 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK54_EN       ((uint32_t)0x00400000)          /*!< When 1, enables Bank54 of the SRAM */
7471 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK55_EN_OFS   (23)                            /*!< BNK55_EN Bit Offset */
7472 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK55_EN       ((uint32_t)0x00800000)          /*!< When 1, enables Bank55 of the SRAM */
7473 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK56_EN_OFS   (24)                            /*!< BNK56_EN Bit Offset */
7474 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK56_EN       ((uint32_t)0x01000000)          /*!< When 1, enables Bank56 of the SRAM */
7475 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK57_EN_OFS   (25)                            /*!< BNK57_EN Bit Offset */
7476 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK57_EN       ((uint32_t)0x02000000)          /*!< When 1, enables Bank57 of the SRAM */
7477 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK58_EN_OFS   (26)                            /*!< BNK58_EN Bit Offset */
7478 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK58_EN       ((uint32_t)0x04000000)          /*!< When 1, enables Bank58 of the SRAM */
7479 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK59_EN_OFS   (27)                            /*!< BNK59_EN Bit Offset */
7480 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK59_EN       ((uint32_t)0x08000000)          /*!< When 1, enables Bank59 of the SRAM */
7481 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK60_EN_OFS   (28)                            /*!< BNK60_EN Bit Offset */
7482 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK60_EN       ((uint32_t)0x10000000)          /*!< When 1, enables Bank60 of the SRAM */
7483 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK61_EN_OFS   (29)                            /*!< BNK61_EN Bit Offset */
7484 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK61_EN       ((uint32_t)0x20000000)          /*!< When 1, enables Bank61 of the SRAM */
7485 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK62_EN_OFS   (30)                            /*!< BNK62_EN Bit Offset */
7486 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK62_EN       ((uint32_t)0x40000000)          /*!< When 1, enables Bank62 of the SRAM */
7487 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK63_EN_OFS   (31)                            /*!< BNK63_EN Bit Offset */
7488 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK63_EN       ((uint32_t)0x80000000)          /*!< When 1, enables Bank63 of the SRAM */
7489 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK64_EN_OFS   ( 0)                            /*!< BNK64_EN Bit Offset */
7490 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK64_EN       ((uint32_t)0x00000001)          /*!< When 1, enables Bank64 of the SRAM */
7491 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK65_EN_OFS   ( 1)                            /*!< BNK65_EN Bit Offset */
7492 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK65_EN       ((uint32_t)0x00000002)          /*!< When 1, enables Bank65 of the SRAM */
7493 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK66_EN_OFS   ( 2)                            /*!< BNK66_EN Bit Offset */
7494 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK66_EN       ((uint32_t)0x00000004)          /*!< When 1, enables Bank66 of the SRAM */
7495 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK67_EN_OFS   ( 3)                            /*!< BNK67_EN Bit Offset */
7496 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK67_EN       ((uint32_t)0x00000008)          /*!< When 1, enables Bank67 of the SRAM */
7497 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK68_EN_OFS   ( 4)                            /*!< BNK68_EN Bit Offset */
7498 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK68_EN       ((uint32_t)0x00000010)          /*!< When 1, enables Bank68 of the SRAM */
7499 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK69_EN_OFS   ( 5)                            /*!< BNK69_EN Bit Offset */
7500 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK69_EN       ((uint32_t)0x00000020)          /*!< When 1, enables Bank69 of the SRAM */
7501 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK70_EN_OFS   ( 6)                            /*!< BNK70_EN Bit Offset */
7502 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK70_EN       ((uint32_t)0x00000040)          /*!< When 1, enables Bank70 of the SRAM */
7503 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK71_EN_OFS   ( 7)                            /*!< BNK71_EN Bit Offset */
7504 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK71_EN       ((uint32_t)0x00000080)          /*!< When 1, enables Bank71 of the SRAM */
7505 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK72_EN_OFS   ( 8)                            /*!< BNK72_EN Bit Offset */
7506 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK72_EN       ((uint32_t)0x00000100)          /*!< When 1, enables Bank72 of the SRAM */
7507 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK73_EN_OFS   ( 9)                            /*!< BNK73_EN Bit Offset */
7508 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK73_EN       ((uint32_t)0x00000200)          /*!< When 1, enables Bank73 of the SRAM */
7509 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK74_EN_OFS   (10)                            /*!< BNK74_EN Bit Offset */
7510 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK74_EN       ((uint32_t)0x00000400)          /*!< When 1, enables Bank74 of the SRAM */
7511 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK75_EN_OFS   (11)                            /*!< BNK75_EN Bit Offset */
7512 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK75_EN       ((uint32_t)0x00000800)          /*!< When 1, enables Bank75 of the SRAM */
7513 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK76_EN_OFS   (12)                            /*!< BNK76_EN Bit Offset */
7514 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK76_EN       ((uint32_t)0x00001000)          /*!< When 1, enables Bank76 of the SRAM */
7515 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK77_EN_OFS   (13)                            /*!< BNK77_EN Bit Offset */
7516 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK77_EN       ((uint32_t)0x00002000)          /*!< When 1, enables Bank77 of the SRAM */
7517 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK78_EN_OFS   (14)                            /*!< BNK78_EN Bit Offset */
7518 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK78_EN       ((uint32_t)0x00004000)          /*!< When 1, enables Bank78 of the SRAM */
7519 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK79_EN_OFS   (15)                            /*!< BNK79_EN Bit Offset */
7520 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK79_EN       ((uint32_t)0x00008000)          /*!< When 1, enables Bank79 of the SRAM */
7521 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK80_EN_OFS   (16)                            /*!< BNK80_EN Bit Offset */
7522 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK80_EN       ((uint32_t)0x00010000)          /*!< When 1, enables Bank80 of the SRAM */
7523 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK81_EN_OFS   (17)                            /*!< BNK81_EN Bit Offset */
7524 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK81_EN       ((uint32_t)0x00020000)          /*!< When 1, enables Bank81 of the SRAM */
7525 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK82_EN_OFS   (18)                            /*!< BNK82_EN Bit Offset */
7526 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK82_EN       ((uint32_t)0x00040000)          /*!< When 1, enables Bank82 of the SRAM */
7527 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK83_EN_OFS   (19)                            /*!< BNK83_EN Bit Offset */
7528 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK83_EN       ((uint32_t)0x00080000)          /*!< When 1, enables Bank83 of the SRAM */
7529 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK84_EN_OFS   (20)                            /*!< BNK84_EN Bit Offset */
7530 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK84_EN       ((uint32_t)0x00100000)          /*!< When 1, enables Bank84 of the SRAM */
7531 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK85_EN_OFS   (21)                            /*!< BNK85_EN Bit Offset */
7532 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK85_EN       ((uint32_t)0x00200000)          /*!< When 1, enables Bank85 of the SRAM */
7533 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK86_EN_OFS   (22)                            /*!< BNK86_EN Bit Offset */
7534 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK86_EN       ((uint32_t)0x00400000)          /*!< When 1, enables Bank86 of the SRAM */
7535 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK87_EN_OFS   (23)                            /*!< BNK87_EN Bit Offset */
7536 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK87_EN       ((uint32_t)0x00800000)          /*!< When 1, enables Bank87 of the SRAM */
7537 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK88_EN_OFS   (24)                            /*!< BNK88_EN Bit Offset */
7538 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK88_EN       ((uint32_t)0x01000000)          /*!< When 1, enables Bank88 of the SRAM */
7539 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK89_EN_OFS   (25)                            /*!< BNK89_EN Bit Offset */
7540 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK89_EN       ((uint32_t)0x02000000)          /*!< When 1, enables Bank89 of the SRAM */
7541 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK90_EN_OFS   (26)                            /*!< BNK90_EN Bit Offset */
7542 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK90_EN       ((uint32_t)0x04000000)          /*!< When 1, enables Bank90 of the SRAM */
7543 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK91_EN_OFS   (27)                            /*!< BNK91_EN Bit Offset */
7544 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK91_EN       ((uint32_t)0x08000000)          /*!< When 1, enables Bank91 of the SRAM */
7545 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK92_EN_OFS   (28)                            /*!< BNK92_EN Bit Offset */
7546 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK92_EN       ((uint32_t)0x10000000)          /*!< When 1, enables Bank92 of the SRAM */
7547 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK93_EN_OFS   (29)                            /*!< BNK93_EN Bit Offset */
7548 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK93_EN       ((uint32_t)0x20000000)          /*!< When 1, enables Bank93 of the SRAM */
7549 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK94_EN_OFS   (30)                            /*!< BNK94_EN Bit Offset */
7550 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK94_EN       ((uint32_t)0x40000000)          /*!< When 1, enables Bank94 of the SRAM */
7551 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK95_EN_OFS   (31)                            /*!< BNK95_EN Bit Offset */
7552 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK95_EN       ((uint32_t)0x80000000)          /*!< When 1, enables Bank95 of the SRAM */
7553 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK96_EN_OFS   ( 0)                            /*!< BNK96_EN Bit Offset */
7554 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK96_EN       ((uint32_t)0x00000001)          /*!< When 1, enables Bank96 of the SRAM */
7555 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK97_EN_OFS   ( 1)                            /*!< BNK97_EN Bit Offset */
7556 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK97_EN       ((uint32_t)0x00000002)          /*!< When 1, enables Bank97 of the SRAM */
7557 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK98_EN_OFS   ( 2)                            /*!< BNK98_EN Bit Offset */
7558 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK98_EN       ((uint32_t)0x00000004)          /*!< When 1, enables Bank98 of the SRAM */
7559 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK99_EN_OFS   ( 3)                            /*!< BNK99_EN Bit Offset */
7560 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK99_EN       ((uint32_t)0x00000008)          /*!< When 1, enables Bank99 of the SRAM */
7561 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK100_EN_OFS  ( 4)                            /*!< BNK100_EN Bit Offset */
7562 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK100_EN      ((uint32_t)0x00000010)          /*!< When 1, enables Bank100 of the SRAM */
7563 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK101_EN_OFS  ( 5)                            /*!< BNK101_EN Bit Offset */
7564 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK101_EN      ((uint32_t)0x00000020)          /*!< When 1, enables Bank101 of the SRAM */
7565 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK102_EN_OFS  ( 6)                            /*!< BNK102_EN Bit Offset */
7566 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK102_EN      ((uint32_t)0x00000040)          /*!< When 1, enables Bank102 of the SRAM */
7567 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK103_EN_OFS  ( 7)                            /*!< BNK103_EN Bit Offset */
7568 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK103_EN      ((uint32_t)0x00000080)          /*!< When 1, enables Bank103 of the SRAM */
7569 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK104_EN_OFS  ( 8)                            /*!< BNK104_EN Bit Offset */
7570 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK104_EN      ((uint32_t)0x00000100)          /*!< When 1, enables Bank104 of the SRAM */
7571 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK105_EN_OFS  ( 9)                            /*!< BNK105_EN Bit Offset */
7572 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK105_EN      ((uint32_t)0x00000200)          /*!< When 1, enables Bank105 of the SRAM */
7573 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK106_EN_OFS  (10)                            /*!< BNK106_EN Bit Offset */
7574 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK106_EN      ((uint32_t)0x00000400)          /*!< When 1, enables Bank106 of the SRAM */
7575 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK107_EN_OFS  (11)                            /*!< BNK107_EN Bit Offset */
7576 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK107_EN      ((uint32_t)0x00000800)          /*!< When 1, enables Bank107 of the SRAM */
7577 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK108_EN_OFS  (12)                            /*!< BNK108_EN Bit Offset */
7578 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK108_EN      ((uint32_t)0x00001000)          /*!< When 1, enables Bank108 of the SRAM */
7579 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK109_EN_OFS  (13)                            /*!< BNK109_EN Bit Offset */
7580 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK109_EN      ((uint32_t)0x00002000)          /*!< When 1, enables Bank109 of the SRAM */
7581 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK110_EN_OFS  (14)                            /*!< BNK110_EN Bit Offset */
7582 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK110_EN      ((uint32_t)0x00004000)          /*!< When 1, enables Bank110 of the SRAM */
7583 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK111_EN_OFS  (15)                            /*!< BNK111_EN Bit Offset */
7584 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK111_EN      ((uint32_t)0x00008000)          /*!< When 1, enables Bank111 of the SRAM */
7585 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK112_EN_OFS  (16)                            /*!< BNK112_EN Bit Offset */
7586 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK112_EN      ((uint32_t)0x00010000)          /*!< When 1, enables Bank112 of the SRAM */
7587 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK113_EN_OFS  (17)                            /*!< BNK113_EN Bit Offset */
7588 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK113_EN      ((uint32_t)0x00020000)          /*!< When 1, enables Bank113 of the SRAM */
7589 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK114_EN_OFS  (18)                            /*!< BNK114_EN Bit Offset */
7590 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK114_EN      ((uint32_t)0x00040000)          /*!< When 1, enables Bank114 of the SRAM */
7591 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK115_EN_OFS  (19)                            /*!< BNK115_EN Bit Offset */
7592 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK115_EN      ((uint32_t)0x00080000)          /*!< When 1, enables Bank115 of the SRAM */
7593 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK116_EN_OFS  (20)                            /*!< BNK116_EN Bit Offset */
7594 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK116_EN      ((uint32_t)0x00100000)          /*!< When 1, enables Bank116 of the SRAM */
7595 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK117_EN_OFS  (21)                            /*!< BNK117_EN Bit Offset */
7596 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK117_EN      ((uint32_t)0x00200000)          /*!< When 1, enables Bank117 of the SRAM */
7597 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK118_EN_OFS  (22)                            /*!< BNK118_EN Bit Offset */
7598 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK118_EN      ((uint32_t)0x00400000)          /*!< When 1, enables Bank118 of the SRAM */
7599 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK119_EN_OFS  (23)                            /*!< BNK119_EN Bit Offset */
7600 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK119_EN      ((uint32_t)0x00800000)          /*!< When 1, enables Bank119 of the SRAM */
7601 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK120_EN_OFS  (24)                            /*!< BNK120_EN Bit Offset */
7602 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK120_EN      ((uint32_t)0x01000000)          /*!< When 1, enables Bank120 of the SRAM */
7603 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK121_EN_OFS  (25)                            /*!< BNK121_EN Bit Offset */
7604 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK121_EN      ((uint32_t)0x02000000)          /*!< When 1, enables Bank121 of the SRAM */
7605 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK122_EN_OFS  (26)                            /*!< BNK122_EN Bit Offset */
7606 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK122_EN      ((uint32_t)0x04000000)          /*!< When 1, enables Bank122 of the SRAM */
7607 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK123_EN_OFS  (27)                            /*!< BNK123_EN Bit Offset */
7608 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK123_EN      ((uint32_t)0x08000000)          /*!< When 1, enables Bank123 of the SRAM */
7609 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK124_EN_OFS  (28)                            /*!< BNK124_EN Bit Offset */
7610 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK124_EN      ((uint32_t)0x10000000)          /*!< When 1, enables Bank124 of the SRAM */
7611 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK125_EN_OFS  (29)                            /*!< BNK125_EN Bit Offset */
7612 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK125_EN      ((uint32_t)0x20000000)          /*!< When 1, enables Bank125 of the SRAM */
7613 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK126_EN_OFS  (30)                            /*!< BNK126_EN Bit Offset */
7614 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK126_EN      ((uint32_t)0x40000000)          /*!< When 1, enables Bank126 of the SRAM */
7615 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK127_EN_OFS  (31)                            /*!< BNK127_EN Bit Offset */
7616 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK127_EN      ((uint32_t)0x80000000)          /*!< When 1, enables Bank127 of the SRAM */
7617 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK0_EN_OFS    ( 0)                            /*!< BLK0_EN Bit Offset */
7618 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK0_EN        ((uint32_t)0x00000001)          /*!< Block0 is always retained in LPM3, LPM4 and LPM3.5 modes of operation */
7619 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK1_EN_OFS    ( 1)                            /*!< BLK1_EN Bit Offset */
7620 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK1_EN        ((uint32_t)0x00000002)          /*!< When 1, Block1 of the SRAM is retained in LPM3 and LPM4 */
7621 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK2_EN_OFS    ( 2)                            /*!< BLK2_EN Bit Offset */
7622 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK2_EN        ((uint32_t)0x00000004)          /*!< When 1, Block2 of the SRAM is retained in LPM3 and LPM4 */
7623 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK3_EN_OFS    ( 3)                            /*!< BLK3_EN Bit Offset */
7624 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK3_EN        ((uint32_t)0x00000008)          /*!< When 1, Block3 of the SRAM is retained in LPM3 and LPM4 */
7625 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK4_EN_OFS    ( 4)                            /*!< BLK4_EN Bit Offset */
7626 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK4_EN        ((uint32_t)0x00000010)          /*!< When 1, Block4 of the SRAM is retained in LPM3 and LPM4 */
7627 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK5_EN_OFS    ( 5)                            /*!< BLK5_EN Bit Offset */
7628 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK5_EN        ((uint32_t)0x00000020)          /*!< When 1, Block5 of the SRAM is retained in LPM3 and LPM4 */
7629 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK6_EN_OFS    ( 6)                            /*!< BLK6_EN Bit Offset */
7630 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK6_EN        ((uint32_t)0x00000040)          /*!< When 1, Block6 of the SRAM is retained in LPM3 and LPM4 */
7631 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK7_EN_OFS    ( 7)                            /*!< BLK7_EN Bit Offset */
7632 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK7_EN        ((uint32_t)0x00000080)          /*!< When 1, Block7 of the SRAM is retained in LPM3 and LPM4 */
7633 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK8_EN_OFS    ( 8)                            /*!< BLK8_EN Bit Offset */
7634 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK8_EN        ((uint32_t)0x00000100)          /*!< When 1, Block8 of the SRAM is retained in LPM3 and LPM4 */
7635 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK9_EN_OFS    ( 9)                            /*!< BLK9_EN Bit Offset */
7636 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK9_EN        ((uint32_t)0x00000200)          /*!< When 1, Block9 of the SRAM is retained in LPM3 and LPM4 */
7637 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK10_EN_OFS   (10)                            /*!< BLK10_EN Bit Offset */
7638 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK10_EN       ((uint32_t)0x00000400)          /*!< When 1, Block10 of the SRAM is retained in LPM3 and LPM4 */
7639 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK11_EN_OFS   (11)                            /*!< BLK11_EN Bit Offset */
7640 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK11_EN       ((uint32_t)0x00000800)          /*!< When 1, Block11 of the SRAM is retained in LPM3 and LPM4 */
7641 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK12_EN_OFS   (12)                            /*!< BLK12_EN Bit Offset */
7642 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK12_EN       ((uint32_t)0x00001000)          /*!< When 1, Block12 of the SRAM is retained in LPM3 and LPM4 */
7643 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK13_EN_OFS   (13)                            /*!< BLK13_EN Bit Offset */
7644 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK13_EN       ((uint32_t)0x00002000)          /*!< When 1, Block13 of the SRAM is retained in LPM3 and LPM4 */
7645 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK14_EN_OFS   (14)                            /*!< BLK14_EN Bit Offset */
7646 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK14_EN       ((uint32_t)0x00004000)          /*!< When 1, Block14 of the SRAM is retained in LPM3 and LPM4 */
7647 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK15_EN_OFS   (15)                            /*!< BLK15_EN Bit Offset */
7648 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK15_EN       ((uint32_t)0x00008000)          /*!< When 1, Block15 of the SRAM is retained in LPM3 and LPM4 */
7649 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK16_EN_OFS   (16)                            /*!< BLK16_EN Bit Offset */
7650 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK16_EN       ((uint32_t)0x00010000)          /*!< When 1, Block16 of the SRAM is retained in LPM3 and LPM4 */
7651 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK17_EN_OFS   (17)                            /*!< BLK17_EN Bit Offset */
7652 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK17_EN       ((uint32_t)0x00020000)          /*!< When 1, Block17 of the SRAM is retained in LPM3 and LPM4 */
7653 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK18_EN_OFS   (18)                            /*!< BLK18_EN Bit Offset */
7654 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK18_EN       ((uint32_t)0x00040000)          /*!< When 1, Block18 of the SRAM is retained in LPM3 and LPM4 */
7655 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK19_EN_OFS   (19)                            /*!< BLK19_EN Bit Offset */
7656 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK19_EN       ((uint32_t)0x00080000)          /*!< When 1, Block19 of the SRAM is retained in LPM3 and LPM4 */
7657 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK20_EN_OFS   (20)                            /*!< BLK20_EN Bit Offset */
7658 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK20_EN       ((uint32_t)0x00100000)          /*!< When 1, Block20 of the SRAM is retained in LPM3 and LPM4 */
7659 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK21_EN_OFS   (21)                            /*!< BLK21_EN Bit Offset */
7660 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK21_EN       ((uint32_t)0x00200000)          /*!< When 1, Block21 of the SRAM is retained in LPM3 and LPM4 */
7661 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK22_EN_OFS   (22)                            /*!< BLK22_EN Bit Offset */
7662 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK22_EN       ((uint32_t)0x00400000)          /*!< When 1, Block22 of the SRAM is retained in LPM3 and LPM4 */
7663 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK23_EN_OFS   (23)                            /*!< BLK23_EN Bit Offset */
7664 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK23_EN       ((uint32_t)0x00800000)          /*!< When 1, Block23 of the SRAM is retained in LPM3 and LPM4 */
7665 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK24_EN_OFS   (24)                            /*!< BLK24_EN Bit Offset */
7666 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK24_EN       ((uint32_t)0x01000000)          /*!< When 1, Block24 of the SRAM is retained in LPM3 and LPM4 */
7667 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK25_EN_OFS   (25)                            /*!< BLK25_EN Bit Offset */
7668 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK25_EN       ((uint32_t)0x02000000)          /*!< When 1, Block25 of the SRAM is retained in LPM3 and LPM4 */
7669 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK26_EN_OFS   (26)                            /*!< BLK26_EN Bit Offset */
7670 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK26_EN       ((uint32_t)0x04000000)          /*!< When 1, Block26 of the SRAM is retained in LPM3 and LPM4 */
7671 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK27_EN_OFS   (27)                            /*!< BLK27_EN Bit Offset */
7672 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK27_EN       ((uint32_t)0x08000000)          /*!< When 1, Block27 of the SRAM is retained in LPM3 and LPM4 */
7673 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK28_EN_OFS   (28)                            /*!< BLK28_EN Bit Offset */
7674 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK28_EN       ((uint32_t)0x10000000)          /*!< When 1, Block28 of the SRAM is retained in LPM3 and LPM4 */
7675 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK29_EN_OFS   (29)                            /*!< BLK29_EN Bit Offset */
7676 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK29_EN       ((uint32_t)0x20000000)          /*!< When 1, Block29 of the SRAM is retained in LPM3 and LPM4 */
7677 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK30_EN_OFS   (30)                            /*!< BLK30_EN Bit Offset */
7678 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK30_EN       ((uint32_t)0x40000000)          /*!< When 1, Block30 of the SRAM is retained in LPM3 and LPM4 */
7679 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK31_EN_OFS   (31)                            /*!< BLK31_EN Bit Offset */
7680 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK31_EN       ((uint32_t)0x80000000)          /*!< When 1, Block31 of the SRAM is retained in LPM3 and LPM4 */
7681 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK32_EN_OFS   ( 0)                            /*!< BLK32_EN Bit Offset */
7682 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK32_EN       ((uint32_t)0x00000001)          /*!< When 1, Block32 of the SRAM is retained in LPM3 and LPM4 */
7683 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK33_EN_OFS   ( 1)                            /*!< BLK33_EN Bit Offset */
7684 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK33_EN       ((uint32_t)0x00000002)          /*!< When 1, Block33 of the SRAM is retained in LPM3 and LPM4 */
7685 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK34_EN_OFS   ( 2)                            /*!< BLK34_EN Bit Offset */
7686 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK34_EN       ((uint32_t)0x00000004)          /*!< When 1, Block34 of the SRAM is retained in LPM3 and LPM4 */
7687 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK35_EN_OFS   ( 3)                            /*!< BLK35_EN Bit Offset */
7688 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK35_EN       ((uint32_t)0x00000008)          /*!< When 1, Block35 of the SRAM is retained in LPM3 and LPM4 */
7689 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK36_EN_OFS   ( 4)                            /*!< BLK36_EN Bit Offset */
7690 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK36_EN       ((uint32_t)0x00000010)          /*!< When 1, Block36 of the SRAM is retained in LPM3 and LPM4 */
7691 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK37_EN_OFS   ( 5)                            /*!< BLK37_EN Bit Offset */
7692 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK37_EN       ((uint32_t)0x00000020)          /*!< When 1, Block37 of the SRAM is retained in LPM3 and LPM4 */
7693 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK38_EN_OFS   ( 6)                            /*!< BLK38_EN Bit Offset */
7694 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK38_EN       ((uint32_t)0x00000040)          /*!< When 1, Block38 of the SRAM is retained in LPM3 and LPM4 */
7695 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK39_EN_OFS   ( 7)                            /*!< BLK39_EN Bit Offset */
7696 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK39_EN       ((uint32_t)0x00000080)          /*!< When 1, Block39 of the SRAM is retained in LPM3 and LPM4 */
7697 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK40_EN_OFS   ( 8)                            /*!< BLK40_EN Bit Offset */
7698 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK40_EN       ((uint32_t)0x00000100)          /*!< When 1, Block40 of the SRAM is retained in LPM3 and LPM4 */
7699 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK41_EN_OFS   ( 9)                            /*!< BLK41_EN Bit Offset */
7700 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK41_EN       ((uint32_t)0x00000200)          /*!< When 1, Block41 of the SRAM is retained in LPM3 and LPM4 */
7701 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK42_EN_OFS   (10)                            /*!< BLK42_EN Bit Offset */
7702 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK42_EN       ((uint32_t)0x00000400)          /*!< When 1, Block42 of the SRAM is retained in LPM3 and LPM4 */
7703 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK43_EN_OFS   (11)                            /*!< BLK43_EN Bit Offset */
7704 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK43_EN       ((uint32_t)0x00000800)          /*!< When 1, Block43 of the SRAM is retained in LPM3 and LPM4 */
7705 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK44_EN_OFS   (12)                            /*!< BLK44_EN Bit Offset */
7706 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK44_EN       ((uint32_t)0x00001000)          /*!< When 1, Block44 of the SRAM is retained in LPM3 and LPM4 */
7707 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK45_EN_OFS   (13)                            /*!< BLK45_EN Bit Offset */
7708 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK45_EN       ((uint32_t)0x00002000)          /*!< When 1, Block45 of the SRAM is retained in LPM3 and LPM4 */
7709 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK46_EN_OFS   (14)                            /*!< BLK46_EN Bit Offset */
7710 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK46_EN       ((uint32_t)0x00004000)          /*!< When 1, Block46 of the SRAM is retained in LPM3 and LPM4 */
7711 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK47_EN_OFS   (15)                            /*!< BLK47_EN Bit Offset */
7712 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK47_EN       ((uint32_t)0x00008000)          /*!< When 1, Block47 of the SRAM is retained in LPM3 and LPM4 */
7713 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK48_EN_OFS   (16)                            /*!< BLK48_EN Bit Offset */
7714 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK48_EN       ((uint32_t)0x00010000)          /*!< When 1, Block48 of the SRAM is retained in LPM3 and LPM4 */
7715 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK49_EN_OFS   (17)                            /*!< BLK49_EN Bit Offset */
7716 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK49_EN       ((uint32_t)0x00020000)          /*!< When 1, Block49 of the SRAM is retained in LPM3 and LPM4 */
7717 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK50_EN_OFS   (18)                            /*!< BLK50_EN Bit Offset */
7718 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK50_EN       ((uint32_t)0x00040000)          /*!< When 1, Block50 of the SRAM is retained in LPM3 and LPM4 */
7719 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK51_EN_OFS   (19)                            /*!< BLK51_EN Bit Offset */
7720 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK51_EN       ((uint32_t)0x00080000)          /*!< When 1, Block51 of the SRAM is retained in LPM3 and LPM4 */
7721 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK52_EN_OFS   (20)                            /*!< BLK52_EN Bit Offset */
7722 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK52_EN       ((uint32_t)0x00100000)          /*!< When 1, Block52 of the SRAM is retained in LPM3 and LPM4 */
7723 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK53_EN_OFS   (21)                            /*!< BLK53_EN Bit Offset */
7724 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK53_EN       ((uint32_t)0x00200000)          /*!< When 1, Block53 of the SRAM is retained in LPM3 and LPM4 */
7725 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK54_EN_OFS   (22)                            /*!< BLK54_EN Bit Offset */
7726 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK54_EN       ((uint32_t)0x00400000)          /*!< When 1, Block54 of the SRAM is retained in LPM3 and LPM4 */
7727 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK55_EN_OFS   (23)                            /*!< BLK55_EN Bit Offset */
7728 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK55_EN       ((uint32_t)0x00800000)          /*!< When 1, Block55 of the SRAM is retained in LPM3 and LPM4 */
7729 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK56_EN_OFS   (24)                            /*!< BLK56_EN Bit Offset */
7730 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK56_EN       ((uint32_t)0x01000000)          /*!< When 1, Block56 of the SRAM is retained in LPM3 and LPM4 */
7731 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK57_EN_OFS   (25)                            /*!< BLK57_EN Bit Offset */
7732 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK57_EN       ((uint32_t)0x02000000)          /*!< When 1, Block57 of the SRAM is retained in LPM3 and LPM4 */
7733 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK58_EN_OFS   (26)                            /*!< BLK58_EN Bit Offset */
7734 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK58_EN       ((uint32_t)0x04000000)          /*!< When 1, Block58 of the SRAM is retained in LPM3 and LPM4 */
7735 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK59_EN_OFS   (27)                            /*!< BLK59_EN Bit Offset */
7736 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK59_EN       ((uint32_t)0x08000000)          /*!< When 1, Block59 of the SRAM is retained in LPM3 and LPM4 */
7737 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK60_EN_OFS   (28)                            /*!< BLK60_EN Bit Offset */
7738 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK60_EN       ((uint32_t)0x10000000)          /*!< When 1, Block60 of the SRAM is retained in LPM3 and LPM4 */
7739 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK61_EN_OFS   (29)                            /*!< BLK61_EN Bit Offset */
7740 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK61_EN       ((uint32_t)0x20000000)          /*!< When 1, Block61 of the SRAM is retained in LPM3 and LPM4 */
7741 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK62_EN_OFS   (30)                            /*!< BLK62_EN Bit Offset */
7742 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK62_EN       ((uint32_t)0x40000000)          /*!< When 1, Block62 of the SRAM is retained in LPM3 and LPM4 */
7743 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK63_EN_OFS   (31)                            /*!< BLK63_EN Bit Offset */
7744 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK63_EN       ((uint32_t)0x80000000)          /*!< When 1, Block63 of the SRAM is retained in LPM3 and LPM4 */
7745 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK64_EN_OFS   ( 0)                            /*!< BLK64_EN Bit Offset */
7746 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK64_EN       ((uint32_t)0x00000001)          /*!< When 1, Block64 of the SRAM is retained in LPM3 and LPM4 */
7747 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK65_EN_OFS   ( 1)                            /*!< BLK65_EN Bit Offset */
7748 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK65_EN       ((uint32_t)0x00000002)          /*!< When 1, Block65 of the SRAM is retained in LPM3 and LPM4 */
7749 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK66_EN_OFS   ( 2)                            /*!< BLK66_EN Bit Offset */
7750 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK66_EN       ((uint32_t)0x00000004)          /*!< When 1, Block66 of the SRAM is retained in LPM3 and LPM4 */
7751 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK67_EN_OFS   ( 3)                            /*!< BLK67_EN Bit Offset */
7752 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK67_EN       ((uint32_t)0x00000008)          /*!< When 1, Block67 of the SRAM is retained in LPM3 and LPM4 */
7753 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK68_EN_OFS   ( 4)                            /*!< BLK68_EN Bit Offset */
7754 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK68_EN       ((uint32_t)0x00000010)          /*!< When 1, Block68 of the SRAM is retained in LPM3 and LPM4 */
7755 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK69_EN_OFS   ( 5)                            /*!< BLK69_EN Bit Offset */
7756 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK69_EN       ((uint32_t)0x00000020)          /*!< When 1, Block69 of the SRAM is retained in LPM3 and LPM4 */
7757 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK70_EN_OFS   ( 6)                            /*!< BLK70_EN Bit Offset */
7758 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK70_EN       ((uint32_t)0x00000040)          /*!< When 1, Block70 of the SRAM is retained in LPM3 and LPM4 */
7759 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK71_EN_OFS   ( 7)                            /*!< BLK71_EN Bit Offset */
7760 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK71_EN       ((uint32_t)0x00000080)          /*!< When 1, Block71 of the SRAM is retained in LPM3 and LPM4 */
7761 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK72_EN_OFS   ( 8)                            /*!< BLK72_EN Bit Offset */
7762 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK72_EN       ((uint32_t)0x00000100)          /*!< When 1, Block72 of the SRAM is retained in LPM3 and LPM4 */
7763 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK73_EN_OFS   ( 9)                            /*!< BLK73_EN Bit Offset */
7764 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK73_EN       ((uint32_t)0x00000200)          /*!< When 1, Block73 of the SRAM is retained in LPM3 and LPM4 */
7765 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK74_EN_OFS   (10)                            /*!< BLK74_EN Bit Offset */
7766 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK74_EN       ((uint32_t)0x00000400)          /*!< When 1, Block74 of the SRAM is retained in LPM3 and LPM4 */
7767 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK75_EN_OFS   (11)                            /*!< BLK75_EN Bit Offset */
7768 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK75_EN       ((uint32_t)0x00000800)          /*!< When 1, Block75 of the SRAM is retained in LPM3 and LPM4 */
7769 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK76_EN_OFS   (12)                            /*!< BLK76_EN Bit Offset */
7770 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK76_EN       ((uint32_t)0x00001000)          /*!< When 1, Block76 of the SRAM is retained in LPM3 and LPM4 */
7771 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK77_EN_OFS   (13)                            /*!< BLK77_EN Bit Offset */
7772 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK77_EN       ((uint32_t)0x00002000)          /*!< When 1, Block77 of the SRAM is retained in LPM3 and LPM4 */
7773 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK78_EN_OFS   (14)                            /*!< BLK78_EN Bit Offset */
7774 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK78_EN       ((uint32_t)0x00004000)          /*!< When 1, Block78 of the SRAM is retained in LPM3 and LPM4 */
7775 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK79_EN_OFS   (15)                            /*!< BLK79_EN Bit Offset */
7776 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK79_EN       ((uint32_t)0x00008000)          /*!< When 1, Block79 of the SRAM is retained in LPM3 and LPM4 */
7777 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK80_EN_OFS   (16)                            /*!< BLK80_EN Bit Offset */
7778 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK80_EN       ((uint32_t)0x00010000)          /*!< When 1, Block80 of the SRAM is retained in LPM3 and LPM4 */
7779 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK81_EN_OFS   (17)                            /*!< BLK81_EN Bit Offset */
7780 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK81_EN       ((uint32_t)0x00020000)          /*!< When 1, Block81 of the SRAM is retained in LPM3 and LPM4 */
7781 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK82_EN_OFS   (18)                            /*!< BLK82_EN Bit Offset */
7782 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK82_EN       ((uint32_t)0x00040000)          /*!< When 1, Block82 of the SRAM is retained in LPM3 and LPM4 */
7783 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK83_EN_OFS   (19)                            /*!< BLK83_EN Bit Offset */
7784 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK83_EN       ((uint32_t)0x00080000)          /*!< When 1, Block83 of the SRAM is retained in LPM3 and LPM4 */
7785 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK84_EN_OFS   (20)                            /*!< BLK84_EN Bit Offset */
7786 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK84_EN       ((uint32_t)0x00100000)          /*!< When 1, Block84 of the SRAM is retained in LPM3 and LPM4 */
7787 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK85_EN_OFS   (21)                            /*!< BLK85_EN Bit Offset */
7788 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK85_EN       ((uint32_t)0x00200000)          /*!< When 1, Block85 of the SRAM is retained in LPM3 and LPM4 */
7789 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK86_EN_OFS   (22)                            /*!< BLK86_EN Bit Offset */
7790 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK86_EN       ((uint32_t)0x00400000)          /*!< When 1, Block86 of the SRAM is retained in LPM3 and LPM4 */
7791 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK87_EN_OFS   (23)                            /*!< BLK87_EN Bit Offset */
7792 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK87_EN       ((uint32_t)0x00800000)          /*!< When 1, Block87 of the SRAM is retained in LPM3 and LPM4 */
7793 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK88_EN_OFS   (24)                            /*!< BLK88_EN Bit Offset */
7794 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK88_EN       ((uint32_t)0x01000000)          /*!< When 1, Block88 of the SRAM is retained in LPM3 and LPM4 */
7795 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK89_EN_OFS   (25)                            /*!< BLK89_EN Bit Offset */
7796 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK89_EN       ((uint32_t)0x02000000)          /*!< When 1, Block89 of the SRAM is retained in LPM3 and LPM4 */
7797 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK90_EN_OFS   (26)                            /*!< BLK90_EN Bit Offset */
7798 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK90_EN       ((uint32_t)0x04000000)          /*!< When 1, Block90 of the SRAM is retained in LPM3 and LPM4 */
7799 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK91_EN_OFS   (27)                            /*!< BLK91_EN Bit Offset */
7800 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK91_EN       ((uint32_t)0x08000000)          /*!< When 1, Block91 of the SRAM is retained in LPM3 and LPM4 */
7801 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK92_EN_OFS   (28)                            /*!< BLK92_EN Bit Offset */
7802 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK92_EN       ((uint32_t)0x10000000)          /*!< When 1, Block92 of the SRAM is retained in LPM3 and LPM4 */
7803 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK93_EN_OFS   (29)                            /*!< BLK93_EN Bit Offset */
7804 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK93_EN       ((uint32_t)0x20000000)          /*!< When 1, Block93 of the SRAM is retained in LPM3 and LPM4 */
7805 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK94_EN_OFS   (30)                            /*!< BLK94_EN Bit Offset */
7806 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK94_EN       ((uint32_t)0x40000000)          /*!< When 1, Block94 of the SRAM is retained in LPM3 and LPM4 */
7807 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK95_EN_OFS   (31)                            /*!< BLK95_EN Bit Offset */
7808 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK95_EN       ((uint32_t)0x80000000)          /*!< When 1, Block95 of the SRAM is retained in LPM3 and LPM4 */
7809 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK96_EN_OFS   ( 0)                            /*!< BLK96_EN Bit Offset */
7810 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK96_EN       ((uint32_t)0x00000001)          /*!< When 1, Block96 of the SRAM is retained in LPM3 and LPM4 */
7811 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK97_EN_OFS   ( 1)                            /*!< BLK97_EN Bit Offset */
7812 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK97_EN       ((uint32_t)0x00000002)          /*!< When 1, Block97 of the SRAM is retained in LPM3 and LPM4 */
7813 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK98_EN_OFS   ( 2)                            /*!< BLK98_EN Bit Offset */
7814 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK98_EN       ((uint32_t)0x00000004)          /*!< When 1, Block98 of the SRAM is retained in LPM3 and LPM4 */
7815 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK99_EN_OFS   ( 3)                            /*!< BLK99_EN Bit Offset */
7816 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK99_EN       ((uint32_t)0x00000008)          /*!< When 1, Block99 of the SRAM is retained in LPM3 and LPM4 */
7817 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK100_EN_OFS  ( 4)                            /*!< BLK100_EN Bit Offset */
7818 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK100_EN      ((uint32_t)0x00000010)          /*!< When 1, Block100 of the SRAM is retained in LPM3 and LPM4 */
7819 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK101_EN_OFS  ( 5)                            /*!< BLK101_EN Bit Offset */
7820 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK101_EN      ((uint32_t)0x00000020)          /*!< When 1, Block101 of the SRAM is retained in LPM3 and LPM4 */
7821 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK102_EN_OFS  ( 6)                            /*!< BLK102_EN Bit Offset */
7822 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK102_EN      ((uint32_t)0x00000040)          /*!< When 1, Block102 of the SRAM is retained in LPM3 and LPM4 */
7823 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK103_EN_OFS  ( 7)                            /*!< BLK103_EN Bit Offset */
7824 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK103_EN      ((uint32_t)0x00000080)          /*!< When 1, Block103 of the SRAM is retained in LPM3 and LPM4 */
7825 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK104_EN_OFS  ( 8)                            /*!< BLK104_EN Bit Offset */
7826 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK104_EN      ((uint32_t)0x00000100)          /*!< When 1, Block104 of the SRAM is retained in LPM3 and LPM4 */
7827 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK105_EN_OFS  ( 9)                            /*!< BLK105_EN Bit Offset */
7828 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK105_EN      ((uint32_t)0x00000200)          /*!< When 1, Block105 of the SRAM is retained in LPM3 and LPM4 */
7829 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK106_EN_OFS  (10)                            /*!< BLK106_EN Bit Offset */
7830 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK106_EN      ((uint32_t)0x00000400)          /*!< When 1, Block106 of the SRAM is retained in LPM3 and LPM4 */
7831 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK107_EN_OFS  (11)                            /*!< BLK107_EN Bit Offset */
7832 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK107_EN      ((uint32_t)0x00000800)          /*!< When 1, Block107 of the SRAM is retained in LPM3 and LPM4 */
7833 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK108_EN_OFS  (12)                            /*!< BLK108_EN Bit Offset */
7834 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK108_EN      ((uint32_t)0x00001000)          /*!< When 1, Block108 of the SRAM is retained in LPM3 and LPM4 */
7835 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK109_EN_OFS  (13)                            /*!< BLK109_EN Bit Offset */
7836 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK109_EN      ((uint32_t)0x00002000)          /*!< When 1, Block109 of the SRAM is retained in LPM3 and LPM4 */
7837 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK110_EN_OFS  (14)                            /*!< BLK110_EN Bit Offset */
7838 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK110_EN      ((uint32_t)0x00004000)          /*!< When 1, Block110 of the SRAM is retained in LPM3 and LPM4 */
7839 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK111_EN_OFS  (15)                            /*!< BLK111_EN Bit Offset */
7840 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK111_EN      ((uint32_t)0x00008000)          /*!< When 1, Block111 of the SRAM is retained in LPM3 and LPM4 */
7841 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK112_EN_OFS  (16)                            /*!< BLK112_EN Bit Offset */
7842 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK112_EN      ((uint32_t)0x00010000)          /*!< When 1, Block112 of the SRAM is retained in LPM3 and LPM4 */
7843 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK113_EN_OFS  (17)                            /*!< BLK113_EN Bit Offset */
7844 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK113_EN      ((uint32_t)0x00020000)          /*!< When 1, Block113 of the SRAM is retained in LPM3 and LPM4 */
7845 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK114_EN_OFS  (18)                            /*!< BLK114_EN Bit Offset */
7846 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK114_EN      ((uint32_t)0x00040000)          /*!< When 1, Block114 of the SRAM is retained in LPM3 and LPM4 */
7847 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK115_EN_OFS  (19)                            /*!< BLK115_EN Bit Offset */
7848 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK115_EN      ((uint32_t)0x00080000)          /*!< When 1, Block115 of the SRAM is retained in LPM3 and LPM4 */
7849 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK116_EN_OFS  (20)                            /*!< BLK116_EN Bit Offset */
7850 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK116_EN      ((uint32_t)0x00100000)          /*!< When 1, Block116 of the SRAM is retained in LPM3 and LPM4 */
7851 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK117_EN_OFS  (21)                            /*!< BLK117_EN Bit Offset */
7852 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK117_EN      ((uint32_t)0x00200000)          /*!< When 1, Block117 of the SRAM is retained in LPM3 and LPM4 */
7853 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK118_EN_OFS  (22)                            /*!< BLK118_EN Bit Offset */
7854 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK118_EN      ((uint32_t)0x00400000)          /*!< When 1, Block118 of the SRAM is retained in LPM3 and LPM4 */
7855 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK119_EN_OFS  (23)                            /*!< BLK119_EN Bit Offset */
7856 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK119_EN      ((uint32_t)0x00800000)          /*!< When 1, Block119 of the SRAM is retained in LPM3 and LPM4 */
7857 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK120_EN_OFS  (24)                            /*!< BLK120_EN Bit Offset */
7858 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK120_EN      ((uint32_t)0x01000000)          /*!< When 1, Block120 of the SRAM is retained in LPM3 and LPM4 */
7859 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK121_EN_OFS  (25)                            /*!< BLK121_EN Bit Offset */
7860 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK121_EN      ((uint32_t)0x02000000)          /*!< When 1, Block121 of the SRAM is retained in LPM3 and LPM4 */
7861 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK122_EN_OFS  (26)                            /*!< BLK122_EN Bit Offset */
7862 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK122_EN      ((uint32_t)0x04000000)          /*!< When 1, Block122 of the SRAM is retained in LPM3 and LPM4 */
7863 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK123_EN_OFS  (27)                            /*!< BLK123_EN Bit Offset */
7864 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK123_EN      ((uint32_t)0x08000000)          /*!< When 1, Block123 of the SRAM is retained in LPM3 and LPM4 */
7865 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK124_EN_OFS  (28)                            /*!< BLK124_EN Bit Offset */
7866 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK124_EN      ((uint32_t)0x10000000)          /*!< When 1, Block124 of the SRAM is retained in LPM3 and LPM4 */
7867 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK125_EN_OFS  (29)                            /*!< BLK125_EN Bit Offset */
7868 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK125_EN      ((uint32_t)0x20000000)          /*!< When 1, Block125 of the SRAM is retained in LPM3 and LPM4 */
7869 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK126_EN_OFS  (30)                            /*!< BLK126_EN Bit Offset */
7870 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK126_EN      ((uint32_t)0x40000000)          /*!< When 1, Block126 of the SRAM is retained in LPM3 and LPM4 */
7871 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK127_EN_OFS  (31)                            /*!< BLK127_EN Bit Offset */
7872 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK127_EN      ((uint32_t)0x80000000)          /*!< When 1, Block127 of the SRAM is retained in LPM3 and LPM4 */
7873 #define SYSCTL_A_SRAM_STAT_BNKEN_RDY_OFS         ( 0)                            /*!< BNKEN_RDY Bit Offset */
7874 #define SYSCTL_A_SRAM_STAT_BNKEN_RDY             ((uint32_t)0x00000001)          /*!< When 1, indicates SRAM is ready for access and banks can be  */
7875 #define SYSCTL_A_SRAM_STAT_BLKRET_RDY_OFS        ( 1)                            /*!< BLKRET_RDY Bit Offset */
7876 #define SYSCTL_A_SRAM_STAT_BLKRET_RDY            ((uint32_t)0x00000002)          /*!< When 1, indicates SRAM is ready for access and blocks can be  */
7877 #define SYSCTL_A_MASTER_UNLOCK_UNLKEY_OFS        ( 0)                            /*!< UNLKEY Bit Offset */
7878 #define SYSCTL_A_MASTER_UNLOCK_UNLKEY_MASK       ((uint32_t)0x0000FFFF)          /*!< UNLKEY Bit Mask */
7879 #define SYSCTL_A_RESET_REQ_POR_OFS               ( 0)                            /*!< POR Bit Offset */
7880 #define SYSCTL_A_RESET_REQ_POR                   ((uint32_t)0x00000001)          /*!< Generate POR */
7881 #define SYSCTL_A_RESET_REQ_REBOOT_OFS            ( 1)                            /*!< REBOOT Bit Offset */
7882 #define SYSCTL_A_RESET_REQ_REBOOT                ((uint32_t)0x00000002)          /*!< Generate Reboot_Reset */
7883 #define SYSCTL_A_RESET_REQ_WKEY_OFS              ( 8)                            /*!< WKEY Bit Offset */
7884 #define SYSCTL_A_RESET_REQ_WKEY_MASK             ((uint32_t)0x0000FF00)          /*!< WKEY Bit Mask */
7885 #define SYSCTL_A_RESET_STATOVER_SOFT_OFS         ( 0)                            /*!< SOFT Bit Offset */
7886 #define SYSCTL_A_RESET_STATOVER_SOFT             ((uint32_t)0x00000001)          /*!< Indicates if SOFT Reset is active */
7887 #define SYSCTL_A_RESET_STATOVER_HARD_OFS         ( 1)                            /*!< HARD Bit Offset */
7888 #define SYSCTL_A_RESET_STATOVER_HARD             ((uint32_t)0x00000002)          /*!< Indicates if HARD Reset is active */
7889 #define SYSCTL_A_RESET_STATOVER_REBOOT_OFS       ( 2)                            /*!< REBOOT Bit Offset */
7890 #define SYSCTL_A_RESET_STATOVER_REBOOT           ((uint32_t)0x00000004)          /*!< Indicates if Reboot Reset is active */
7891 #define SYSCTL_A_RESET_STATOVER_SOFT_OVER_OFS    ( 8)                            /*!< SOFT_OVER Bit Offset */
7892 #define SYSCTL_A_RESET_STATOVER_SOFT_OVER        ((uint32_t)0x00000100)          /*!< SOFT_Reset overwrite request */
7893 #define SYSCTL_A_RESET_STATOVER_HARD_OVER_OFS    ( 9)                            /*!< HARD_OVER Bit Offset */
7894 #define SYSCTL_A_RESET_STATOVER_HARD_OVER        ((uint32_t)0x00000200)          /*!< HARD_Reset overwrite request */
7895 #define SYSCTL_A_RESET_STATOVER_RBT_OVER_OFS     (10)                            /*!< RBT_OVER Bit Offset */
7896 #define SYSCTL_A_RESET_STATOVER_RBT_OVER         ((uint32_t)0x00000400)          /*!< Reboot Reset overwrite request */
7897 #define SYSCTL_A_CSYS_MASTER_UNLOCK_UNLKEY_VAL  ((uint32_t)0x0000695A)          /*!< Unlock key value which when written, determines if accesses to other CPU_SYS register */
7898 #define SYSCTL_A_REBOOT_CTL_WKEY_VAL            ((uint32_t)0x00006900)          /*!< Key value to validate write to bit 0 */
7899 #define SYSCTL_A_BOOT_CTL_WKEY_VAL              ((uint32_t)0x00006900)          /*!< Key value to validate write to bit 0 */
7900 #define SYSCTL_A_ETW_CTL_WKEY_VAL               ((uint32_t)0x00006900)          /*!< Key value to validate write to bit 0 */
7901 #define SYSCTL_A_SECDATA_UNLOCK_KEY_VAL         ((uint32_t)0x0000695A)          /*!< Unlock Key value, which requests for secure data region to be unlocked for data access */
7902 
7903 
7904 /******************************************************************************
7905 * BSL                                                                         *
7906 ******************************************************************************/
7907 #define BSL_DEFAULT_PARAM                        ((uint32_t)0xFC48FFFF)          /*!< I2C slave address = 0x48, Interface selection = Auto */
7908 #define BSL_API_TABLE_ADDR                       ((uint32_t)0x00202000)          /*!< Address of BSL API table */
7909 #define BSL_ENTRY_FUNCTION                       (*((uint32_t *)BSL_API_TABLE_ADDR))
7910 
7911 #define BSL_AUTO_INTERFACE                       ((uint32_t)0x0000E0000)         /*!< Auto detect interface */
7912 #define BSL_UART_INTERFACE                       ((uint32_t)0x0000C0000)         /*!< UART interface */
7913 #define BSL_SPI_INTERFACE                        ((uint32_t)0x0000A0000)         /*!< SPI interface */
7914 #define BSL_I2C_INTERFACE                        ((uint32_t)0x000080000)         /*!< I2C interface */
7915 
7916 #define BSL_INVOKE(x)                            ((void (*)())BSL_ENTRY_FUNCTION)((uint32_t) x) /*!< Invoke the BSL with parameters */
7917 
7918 
7919 /******************************************************************************
7920 * Mailbox struct legacy definition                                            *
7921 ******************************************************************************/
7922 #define FLASH_MAILBOX_Type                    FL_BOOTOVER_MAILBOX_Type
7923 
7924 /******************************************************************************
7925 * Device Unlock Support                                                       *
7926 ******************************************************************************/
7927 /* unlock the device by:
7928  *   Load SYSCTL_SECDATA_UNLOCK register address into R0
7929  *   Load SYSCTL_SECDATA_UNLOCK unlock key into R1
7930  *   Write the unlock key to the SYSCTL_SECDATA_UNLOCK register
7931  */
7932 #define UNLOCK_DEVICE\
7933     __asm("  MOVW.W          R0, #0x3040");\
7934     __asm("  MOVT.W          R0, #0xE004");\
7935     __asm("  MOVW.W          R1, #0x695A");\
7936     __asm("  MOVT.W          R1, #0x0000");\
7937     __asm("  STR             R1, [R0]");
7938 
7939 /******************************************************************************
7940 *
7941 * The following are values that can be used to choose the command that will be
7942 * run by the boot code. Perform a logical OR of these settings to create your
7943 * general parameter command.
7944 *
7945 ******************************************************************************/
7946 #define COMMAND_FACTORY_RESET                    ((uint32_t)0x00010000)
7947 #define COMMAND_BSL_CONFIG                       ((uint32_t)0x00020000)
7948 #define COMMAND_JTAG_SWD_LOCK_SECEN              ((uint32_t)0x00080000)
7949 #define COMMAND_SEC_ZONE0_EN                     ((uint32_t)0x00100000)
7950 #define COMMAND_SEC_ZONE1_EN                     ((uint32_t)0x00200000)
7951 #define COMMAND_SEC_ZONE2_EN                     ((uint32_t)0x00400000)
7952 #define COMMAND_SEC_ZONE3_EN                     ((uint32_t)0x00800000)
7953 #define COMMAND_SEC_ZONE0_UPDATE                 ((uint32_t)0x01000000)
7954 #define COMMAND_SEC_ZONE1_UPDATE                 ((uint32_t)0x02000000)
7955 #define COMMAND_SEC_ZONE2_UPDATE                 ((uint32_t)0x04000000)
7956 #define COMMAND_SEC_ZONE3_UPDATE                 ((uint32_t)0x08000000)
7957 #define COMMAND_JTAG_SWD_LOCK_ENC_UPDATE         ((uint32_t)0x10000000)
7958 #define COMMAND_NONE                             ((uint32_t)0xFFFFFFFF)
7959 
7960 /******************************************************************************
7961 *
7962 * The following are values that can be used to configure the BSL. Perform a
7963 * logical OR of these settings to create your BSL parameter.
7964 *
7965 ******************************************************************************/
7966 #define BSL_CONFIG_HW_INVOKE                     ((uint32_t)0x70000000)
7967 
7968 #define BSL_CONFIG_HW_INVOKE_PORT1               ((uint32_t)0x00000000)
7969 #define BSL_CONFIG_HW_INVOKE_PORT2               ((uint32_t)0x00000001)
7970 #define BSL_CONFIG_HW_INVOKE_PORT3               ((uint32_t)0x00000002)
7971 
7972 #define BSL_CONFIG_HW_INVOKE_PIN0                ((uint32_t)0x00000000)
7973 #define BSL_CONFIG_HW_INVOKE_PIN1                ((uint32_t)0x00000010)
7974 #define BSL_CONFIG_HW_INVOKE_PIN2                ((uint32_t)0x00000020)
7975 #define BSL_CONFIG_HW_INVOKE_PIN3                ((uint32_t)0x00000030)
7976 #define BSL_CONFIG_HW_INVOKE_PIN4                ((uint32_t)0x00000040)
7977 #define BSL_CONFIG_HW_INVOKE_PIN5                ((uint32_t)0x00000050)
7978 #define BSL_CONFIG_HW_INVOKE_PIN6                ((uint32_t)0x00000060)
7979 #define BSL_CONFIG_HW_INVOKE_PIN7                ((uint32_t)0x00000070)
7980 
7981 #define BSL_CONFIG_HW_INVOKE_PIN_LOW             ((uint32_t)0x00000000)
7982 #define BSL_CONFIG_HW_INVOKE_PIN_HIGH            ((uint32_t)0x00001000)
7983 
7984 #define BSL_CONFIG_INTERFACE_I2C                 ((uint32_t)0x00008000)
7985 #define BSL_CONFIG_INTERFACE_SPI                 ((uint32_t)0x0000A000)
7986 #define BSL_CONFIG_INTERFACE_UART                ((uint32_t)0x0000C000)
7987 #define BSL_CONFIG_INTERFACE_AUTO                ((uint32_t)0x0000E000)
7988 
7989 #define BSL_CONFIG_I2C_ADD_OFFSET                (16)
7990 
7991 
7992 /******************************************************************************
7993 * ULP Advisor                                                                 *
7994 ******************************************************************************/
7995 #ifdef __TI_ARM__
7996 #pragma ULP_PORT_CONFIG(1,DIR={0x40004C04,8},OUT={0x40004C02,8},SEL1={0x40004C0A,8},SEL2={0x40004C0C,8})
7997 #pragma ULP_PORT_CONFIG(2,DIR={0x40004C05,8},OUT={0x40004C03,8},SEL1={0x40004C0B,8},SEL2={0x40004C0D,8})
7998 #pragma ULP_PORT_CONFIG(3,DIR={0x40004C24,8},OUT={0x40004C22,8},SEL1={0x40004C2A,8},SEL2={0x40004C2C,8})
7999 #pragma ULP_PORT_CONFIG(4,DIR={0x40004C25,8},OUT={0x40004C23,8},SEL1={0x40004C2B,8},SEL2={0x40004C2D,8})
8000 #pragma ULP_PORT_CONFIG(5,DIR={0x40004C44,8},OUT={0x40004C42,8},SEL1={0x40004C4A,8},SEL2={0x40004C4C,8})
8001 #pragma ULP_PORT_CONFIG(6,DIR={0x40004C45,8},OUT={0x40004C43,8},SEL1={0x40004C4B,8},SEL2={0x40004C4D,8})
8002 #pragma ULP_PORT_CONFIG(7,DIR={0x40004C64,8},OUT={0x40004C62,8},SEL1={0x40004C6A,8},SEL2={0x40004C6C,8})
8003 #pragma ULP_PORT_CONFIG(8,DIR={0x40004C65,8},OUT={0x40004C63,8},SEL1={0x40004C6B,8},SEL2={0x40004C6D,8})
8004 #pragma ULP_PORT_CONFIG(9,DIR={0x40004C84,8},OUT={0x40004C82,8},SEL1={0x40004C8A,8},SEL2={0x40004C8C,8})
8005 #pragma ULP_PORT_CONFIG(10,DIR={0x40004C85,8},OUT={0x40004C83,8},SEL1={0x40004C8B,8},SEL2={0x40004C8D,8})
8006 #endif
8007 
8008 
8009 #ifdef __cplusplus
8010 }
8011 #endif
8012 
8013 #endif /* __MSP432P4XX_H__ */
8014 
8015