1 /* --COPYRIGHT--,BSD 2 * Copyright (c) 2017, Texas Instruments Incorporated 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * * Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 12 * * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * * Neither the name of Texas Instruments Incorporated nor the names of 17 * its contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * --/COPYRIGHT--*/ 32 /* Standard Includes */ 33 #include <stdint.h> 34 #include <stdbool.h> 35 36 /* DriverLib Includes */ 37 #include <ti/devices/msp432p4xx/driverlib/sysctl_a.h> 38 #include <ti/devices/msp432p4xx/driverlib/debug.h> 39 40 /* Define to ensure that our current MSP432 has the SYSCTL_A module. This 41 definition is included in the device specific header file */ 42 #ifdef __MCU_HAS_SYSCTL_A__ 43 44 void SysCtl_A_getTLVInfo(uint_fast8_t tag, uint_fast8_t instance, 45 uint_fast8_t *length, uint32_t **data_address) 46 { 47 /* TLV Structure Start Address */ 48 uint32_t *TLV_address = (uint32_t *) TLV_START; 49 50 if(*TLV_address == 0xFFFFFFFF) 51 { 52 *length = 0; 53 // Return 0 for TAG not found 54 *data_address = 0; 55 return; 56 } 57 58 while (((*TLV_address != tag)) // check for tag and instance 59 && (*TLV_address != TLV_TAGEND)) // do range check first 60 { 61 if (*TLV_address == tag) 62 { 63 if (instance == 0) 64 { 65 break; 66 } 67 68 /* Repeat until requested instance is reached */ 69 instance--; 70 } 71 72 TLV_address += (*(TLV_address + 1)) + 2; 73 } 74 75 /* Check if Tag match happened... */ 76 if (*TLV_address == tag) 77 { 78 /* Return length = Address + 1 */ 79 *length = (*(TLV_address + 1)) * 4; 80 /* Return address of first data/value info = Address + 2 */ 81 *data_address = (uint32_t *) (TLV_address + 2); 82 } 83 // If there was no tag match and the end of TLV structure was reached.. 84 else 85 { 86 // Return 0 for TAG not found 87 *length = 0; 88 // Return 0 for TAG not found 89 *data_address = 0; 90 } 91 } 92 93 uint_least32_t SysCtl_A_getSRAMSize(void) 94 { 95 return SYSCTL_A->SRAM_SIZE; 96 } 97 98 uint_least32_t SysCtl_A_getFlashSize(void) 99 { 100 return SYSCTL_A->MAINFLASH_SIZE; 101 } 102 103 uint_least32_t SysCtl_A_getInfoFlashSize(void) 104 { 105 return SYSCTL_A->INFOFLASH_SIZE; 106 } 107 108 void SysCtl_A_disableNMISource(uint_fast8_t flags) 109 { 110 SYSCTL_A->NMI_CTLSTAT &= ~(flags); 111 } 112 113 void SysCtl_A_enableNMISource(uint_fast8_t flags) 114 { 115 SYSCTL_A->NMI_CTLSTAT |= flags; 116 } 117 118 uint_fast8_t SysCtl_A_getNMISourceStatus(void) 119 { 120 return SYSCTL_A->NMI_CTLSTAT & (SYSCTL_A_NMI_CTLSTAT_CS_FLG | 121 SYSCTL_A_NMI_CTLSTAT_PSS_FLG | 122 SYSCTL_A_NMI_CTLSTAT_PCM_FLG | 123 SYSCTL_A_NMI_CTLSTAT_PIN_FLG); 124 } 125 126 void SysCtl_A_rebootDevice(void) 127 { 128 SYSCTL_A->REBOOT_CTL = (SYSCTL_A_REBOOT_CTL_REBOOT | SYSCTL_A_REBOOT_KEY); 129 } 130 131 void SysCtl_A_enablePeripheralAtCPUHalt(uint_fast16_t devices) 132 { 133 SYSCTL_A->PERIHALT_CTL &= ~devices; 134 } 135 136 void SysCtl_A_disablePeripheralAtCPUHalt(uint_fast16_t devices) 137 { 138 SYSCTL_A->PERIHALT_CTL |= devices; 139 } 140 141 void SysCtl_A_setWDTTimeoutResetType(uint_fast8_t resetType) 142 { 143 if (resetType) 144 SYSCTL_A->WDTRESET_CTL |= SYSCTL_A_WDTRESET_CTL_TIMEOUT; 145 else 146 SYSCTL_A->WDTRESET_CTL &= ~SYSCTL_A_WDTRESET_CTL_TIMEOUT; 147 } 148 149 void SysCtl_A_setWDTPasswordViolationResetType(uint_fast8_t resetType) 150 { 151 if (resetType) 152 SYSCTL_A->WDTRESET_CTL |= SYSCTL_A_WDTRESET_CTL_VIOLATION; 153 else 154 SYSCTL_A->WDTRESET_CTL &= ~SYSCTL_A_WDTRESET_CTL_VIOLATION; 155 } 156 157 void SysCtl_A_enableGlitchFilter(void) 158 { 159 SYSCTL_A->DIO_GLTFLT_CTL |= SYSCTL_A_DIO_GLTFLT_CTL_GLTCH_EN; 160 } 161 162 void SysCtl_A_disableGlitchFilter(void) 163 { 164 SYSCTL_A->DIO_GLTFLT_CTL &= ~SYSCTL_A_DIO_GLTFLT_CTL_GLTCH_EN; 165 } 166 167 uint_fast16_t SysCtl_A_getTempCalibrationConstant(uint32_t refVoltage, 168 uint32_t temperature) 169 { 170 return HWREG16(TLV_BASE + refVoltage + temperature); 171 } 172 173 bool SysCtl_A_enableSRAM(uint32_t addr) 174 { 175 uint32_t bankSize, bankBit; 176 177 /* If SRAM is busy, return false */ 178 if(!(SYSCTL_A->SRAM_STAT & SYSCTL_A_SRAM_STAT_BNKEN_RDY)) 179 return false; 180 181 /* Grabbing the bank size */ 182 bankSize = SysCtl_A_getSRAMSize() / SYSCTL_A->SRAM_NUMBANKS; 183 bankBit = (addr - SRAM_BASE) / bankSize; 184 185 if (bankBit < 32) 186 { 187 SYSCTL_A->SRAM_BANKEN_CTL0 |= (1 << bankBit); 188 } else if (bankBit < 64) 189 { 190 SYSCTL_A->SRAM_BANKEN_CTL1 |= (1 << (bankBit - 32)); 191 } else if (bankBit < 96) 192 { 193 SYSCTL_A->SRAM_BANKEN_CTL2 |= (1 << (bankBit - 64)); 194 } else 195 { 196 SYSCTL_A->SRAM_BANKEN_CTL3 |= (1 << (bankBit - 96)); 197 } 198 199 200 return true; 201 } 202 203 bool SysCtl_A_disableSRAM(uint32_t addr) 204 { 205 uint32_t bankSize, bankBit; 206 207 /* If SRAM is busy, return false */ 208 if(!(SYSCTL_A->SRAM_STAT & SYSCTL_A_SRAM_STAT_BNKEN_RDY)) 209 return false; 210 211 /* Grabbing the bank size */ 212 bankSize = SysCtl_A_getSRAMSize() / SYSCTL_A->SRAM_NUMBANKS; 213 bankBit = (addr - SRAM_BASE) / bankSize; 214 215 if (bankBit < 32) 216 { 217 SYSCTL_A->SRAM_BANKEN_CTL0 &= ~(0xFFFFFFFF << bankBit); 218 } else if (bankBit < 64) 219 { 220 SYSCTL_A->SRAM_BANKEN_CTL1 &= ~(0xFFFFFFFF << (bankBit - 32)); 221 } else if (bankBit < 96) 222 { 223 SYSCTL_A->SRAM_BANKEN_CTL2 &= ~(0xFFFFFFFF << (bankBit - 64)); 224 } else 225 { 226 SYSCTL_A->SRAM_BANKEN_CTL3 &= ~(0xFFFFFFFF << (bankBit - 96)); 227 } 228 229 230 return true; 231 } 232 233 bool SysCtl_A_enableSRAMRetention(uint32_t startAddr, 234 uint32_t endAddr) 235 { 236 uint32_t blockSize, blockBitStart, blockBitEnd; 237 238 if (startAddr > endAddr) 239 return false; 240 241 /* If SRAM is busy, return false */ 242 if(!(SYSCTL_A->SRAM_STAT & SYSCTL_A_SRAM_STAT_BLKRET_RDY)) 243 return false; 244 245 /* Getting how big each bank is and how many blocks we have per bank */ 246 blockSize = SysCtl_A_getSRAMSize() / SYSCTL_A->SRAM_NUMBLOCKS; 247 blockBitStart = (startAddr - SRAM_BASE) / blockSize; 248 blockBitEnd = (endAddr - SRAM_BASE) / blockSize; 249 250 if (blockBitStart < 32) 251 { 252 if (blockBitEnd < 32) 253 { 254 SYSCTL_A->SRAM_BLKRET_CTL0 |= (0xFFFFFFFF >> (31 - blockBitEnd)) 255 & (0xFFFFFFFF << blockBitStart); 256 return true; 257 } else if (blockBitEnd < 64) 258 { 259 SYSCTL_A->SRAM_BLKRET_CTL0 |= (0xFFFFFFFF << blockBitStart); 260 SYSCTL_A->SRAM_BLKRET_CTL1 |= (0xFFFFFFFF 261 >> (31 - (blockBitEnd - 32))); 262 } else if (blockBitEnd < 96) 263 { 264 SYSCTL_A->SRAM_BLKRET_CTL0 |= (0xFFFFFFFF << blockBitStart); 265 SYSCTL_A->SRAM_BLKRET_CTL1 = 0xFFFFFFFF; 266 SYSCTL_A->SRAM_BLKRET_CTL2 |= (0xFFFFFFFF 267 >> (31 - (blockBitEnd - 64))); 268 } else 269 { 270 SYSCTL_A->SRAM_BLKRET_CTL0 |= (0xFFFFFFFF << blockBitStart); 271 SYSCTL_A->SRAM_BLKRET_CTL1 = 0xFFFFFFFF; 272 SYSCTL_A->SRAM_BLKRET_CTL2 = 0xFFFFFFFF; 273 SYSCTL_A->SRAM_BLKRET_CTL3 |= (0xFFFFFFFF 274 >> (31 - (blockBitEnd - 96))); 275 } 276 } else if (blockBitStart < 64) 277 { 278 if (blockBitEnd < 64) 279 { 280 SYSCTL_A->SRAM_BLKRET_CTL1 |= ((0xFFFFFFFF 281 >> (31 - (blockBitEnd - 32))) 282 & (0xFFFFFFFF << (blockBitStart - 32))); 283 return true; 284 } 285 286 SYSCTL_A->SRAM_BLKRET_CTL1 = (0xFFFFFFFF << (blockBitStart - 32)); 287 288 if (blockBitEnd < 96) 289 { 290 SYSCTL_A->SRAM_BLKRET_CTL2 |= (0xFFFFFFFF 291 >> (31 - (blockBitEnd - 64))); 292 } else 293 { 294 295 SYSCTL_A->SRAM_BLKRET_CTL2 |= 0xFFFFFFFF; 296 SYSCTL_A->SRAM_BLKRET_CTL3 |= (0xFFFFFFFF 297 >> (31 - (blockBitEnd - 96))); 298 } 299 } else if (blockBitStart < 96) 300 { 301 if (blockBitEnd < 96) 302 { 303 SYSCTL_A->SRAM_BLKRET_CTL2 |= (0xFFFFFFFF 304 >> (31 - (blockBitEnd - 64))) 305 & (0xFFFFFFFF << (blockBitStart - 64)); 306 return true; 307 } else 308 { 309 SYSCTL_A->SRAM_BLKRET_CTL2 |= (0xFFFFFFFF << (blockBitStart - 64)); 310 SYSCTL_A->SRAM_BLKRET_CTL3 |= (0xFFFFFFFF 311 >> (31 - (blockBitEnd - 96))); 312 } 313 } else 314 { 315 SYSCTL_A->SRAM_BLKRET_CTL3 |= (0xFFFFFFFF >> (31 - (blockBitEnd - 96))) 316 & (0xFFFFFFFF << (blockBitStart - 96)); 317 } 318 319 return true; 320 321 } 322 323 bool SysCtl_A_disableSRAMRetention(uint32_t startAddr, 324 uint32_t endAddr) 325 { 326 uint32_t blockSize, blockBitStart, blockBitEnd; 327 328 if (startAddr > endAddr) 329 return false; 330 331 /* If SRAM is busy, return false */ 332 if(!(SYSCTL_A->SRAM_STAT & SYSCTL_A_SRAM_STAT_BLKRET_RDY)) 333 return false; 334 335 336 /* Getting how big each bank is and how many blocks we have per bank */ 337 blockSize = SysCtl_A_getSRAMSize() / SYSCTL_A->SRAM_NUMBLOCKS; 338 blockBitStart = (startAddr - SRAM_BASE) / blockSize; 339 blockBitEnd = (endAddr - SRAM_BASE) / blockSize; 340 341 if (blockBitStart < 32) 342 { 343 if (blockBitEnd < 32) 344 { 345 SYSCTL_A->SRAM_BLKRET_CTL0 &= ~((0xFFFFFFFF >> (31 - blockBitEnd)) 346 & (0xFFFFFFFF << blockBitStart)); 347 return true; 348 } 349 350 SYSCTL_A->SRAM_BLKRET_CTL0 &= ~((0xFFFFFFFF << blockBitStart)); 351 352 if (blockBitEnd < 64) 353 { 354 SYSCTL_A->SRAM_BLKRET_CTL1 &= ~((0xFFFFFFFF 355 >> (31 - (blockBitEnd - 32)))); 356 } else if (blockBitEnd < 96) 357 { 358 SYSCTL_A->SRAM_BLKRET_CTL1 = 0; 359 SYSCTL_A->SRAM_BLKRET_CTL2 &= ~(0xFFFFFFFF 360 >> (31 - (blockBitEnd - 64))); 361 } else 362 { 363 SYSCTL_A->SRAM_BLKRET_CTL1 = 0; 364 SYSCTL_A->SRAM_BLKRET_CTL2 = 0; 365 SYSCTL_A->SRAM_BLKRET_CTL3 &= ~(0xFFFFFFFF 366 >> (31 - (blockBitEnd - 96))); 367 } 368 } else if (blockBitStart < 64) 369 { 370 if (blockBitEnd < 64) 371 { 372 SYSCTL_A->SRAM_BLKRET_CTL1 &= ~((0xFFFFFFFF 373 >> (31 - (blockBitEnd - 32))) 374 & (0xFFFFFFFF << (blockBitStart - 32))); 375 return true; 376 } 377 378 SYSCTL_A->SRAM_BLKRET_CTL1 &= ~(0xFFFFFFFF << (blockBitStart - 32)); 379 380 if (blockBitEnd < 96) 381 { 382 SYSCTL_A->SRAM_BLKRET_CTL2 &= ~(0xFFFFFFFF 383 >> (31 - (blockBitEnd - 64))); 384 } else 385 { 386 387 SYSCTL_A->SRAM_BLKRET_CTL2 = 0; 388 SYSCTL_A->SRAM_BLKRET_CTL3 &= ~(0xFFFFFFFF 389 >> (31 - (blockBitEnd - 96))); 390 } 391 } else if (blockBitStart < 96) 392 { 393 if (blockBitEnd < 96) 394 { 395 SYSCTL_A->SRAM_BLKRET_CTL2 &= ~((0xFFFFFFFF 396 >> (31 - (blockBitEnd - 64))) 397 & (0xFFFFFFFF << (blockBitStart - 64))); 398 } else 399 { 400 SYSCTL_A->SRAM_BLKRET_CTL2 &= ~(0xFFFFFFFF << (blockBitStart - 64)); 401 SYSCTL_A->SRAM_BLKRET_CTL3 &= ~(0xFFFFFFFF 402 >> (31 - (blockBitEnd - 96))); 403 } 404 } else 405 { 406 SYSCTL_A->SRAM_BLKRET_CTL3 &= ~((0xFFFFFFFF >> (31 - (blockBitEnd - 96))) 407 & (0xFFFFFFFF << (blockBitStart - 96))); 408 } 409 410 return true; 411 } 412 413 #endif /* __MCU_HAS_SYSCTL_A__ */ 414