1 /* --COPYRIGHT--,BSD 2 * Copyright (c) 2017, Texas Instruments Incorporated 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * * Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 12 * * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * * Neither the name of Texas Instruments Incorporated nor the names of 17 * its contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * --/COPYRIGHT--*/ 32 /* Standard Includes */ 33 #include <stdint.h> 34 #include <stdbool.h> 35 36 /* DriverLib Includes */ 37 #include <ti/devices/msp432p4xx/driverlib/sysctl.h> 38 #include <ti/devices/msp432p4xx/driverlib/debug.h> 39 40 /* Define to ensure that our current MSP432 has the SYSCTL module. This 41 definition is included in the device specific header file */ 42 #ifdef __MCU_HAS_SYSCTL__ 43 44 #ifdef DEBUG 45 46 static bool SysCtlSRAMBankValid(uint8_t sramBank) 47 { 48 return( 49 sramBank == SYSCTL_SRAM_BANK7 || 50 sramBank == SYSCTL_SRAM_BANK6 || 51 sramBank == SYSCTL_SRAM_BANK5 || 52 sramBank == SYSCTL_SRAM_BANK4 || 53 sramBank == SYSCTL_SRAM_BANK3 || 54 sramBank == SYSCTL_SRAM_BANK2 || 55 sramBank == SYSCTL_SRAM_BANK1 56 ); 57 } 58 59 static bool SysCtlSRAMBankValidRet(uint8_t sramBank) 60 { 61 sramBank &= ~(SYSCTL_SRAM_BANK7 & SYSCTL_SRAM_BANK6 & 62 SYSCTL_SRAM_BANK5 & SYSCTL_SRAM_BANK4 & 63 SYSCTL_SRAM_BANK3 & SYSCTL_SRAM_BANK2 & 64 SYSCTL_SRAM_BANK1); 65 66 return (sramBank == 0); 67 } 68 69 static bool SysCtlPeripheralIsValid (uint16_t hwPeripheral) 70 { 71 hwPeripheral &= ~(SYSCTL_PERIPH_DMA & SYSCTL_PERIPH_WDT & 72 SYSCTL_PERIPH_ADC & SYSCTL_PERIPH_EUSCIB3 & 73 SYSCTL_PERIPH_EUSCIB2 & SYSCTL_PERIPH_EUSCIB1 & 74 SYSCTL_PERIPH_EUSCIB0 & SYSCTL_PERIPH_EUSCIA3 & 75 SYSCTL_PERIPH_EUSCIA2 & SYSCTL_PERIPH_EUSCIA1 & 76 SYSCTL_PERIPH_EUSCIA0 & SYSCTL_PERIPH_TIMER32_0_MODULE & 77 SYSCTL_PERIPH_TIMER16_3 & SYSCTL_PERIPH_TIMER16_2 & 78 SYSCTL_PERIPH_TIMER16_2 & SYSCTL_PERIPH_TIMER16_1 & 79 SYSCTL_PERIPH_TIMER16_0); 80 81 return (hwPeripheral == 0); 82 } 83 #endif 84 85 void SysCtl_getTLVInfo(uint_fast8_t tag, uint_fast8_t instance, 86 uint_fast8_t *length, uint32_t **data_address) 87 { 88 /* TLV Structure Start Address */ 89 uint32_t *TLV_address = (uint32_t *) TLV_START; 90 91 while (((*TLV_address != tag)) // check for tag and instance 92 && (*TLV_address != TLV_TAGEND)) // do range check first 93 { 94 if (*TLV_address == tag) 95 { 96 if(instance == 0) 97 { 98 break; 99 } 100 101 /* Repeat until requested instance is reached */ 102 instance--; 103 } 104 105 TLV_address += (*(TLV_address + 1)) + 2; 106 } 107 108 /* Check if Tag match happened... */ 109 if (*TLV_address == tag) 110 { 111 /* Return length = Address + 1 */ 112 *length = (*(TLV_address + 1))*4; 113 /* Return address of first data/value info = Address + 2 */ 114 *data_address = (uint32_t *) (TLV_address + 2); 115 } 116 // If there was no tag match and the end of TLV structure was reached.. 117 else 118 { 119 // Return 0 for TAG not found 120 *length = 0; 121 // Return 0 for TAG not found 122 *data_address = 0; 123 } 124 } 125 126 uint_least32_t SysCtl_getSRAMSize(void) 127 { 128 return SYSCTL->SRAM_SIZE; 129 } 130 131 uint_least32_t SysCtl_getFlashSize(void) 132 { 133 return SYSCTL->FLASH_SIZE; 134 } 135 136 void SysCtl_disableNMISource(uint_fast8_t flags) 137 { 138 SYSCTL->NMI_CTLSTAT &= ~(flags); 139 } 140 141 void SysCtl_enableNMISource(uint_fast8_t flags) 142 { 143 SYSCTL->NMI_CTLSTAT |= flags; 144 } 145 146 uint_fast8_t SysCtl_getNMISourceStatus(void) 147 { 148 return SYSCTL->NMI_CTLSTAT & (SYSCTL_NMI_CTLSTAT_CS_FLG | 149 SYSCTL_NMI_CTLSTAT_PSS_FLG | 150 SYSCTL_NMI_CTLSTAT_PCM_FLG | 151 SYSCTL_NMI_CTLSTAT_PIN_FLG); 152 } 153 154 void SysCtl_enableSRAMBank(uint_fast8_t sramBank) 155 { 156 ASSERT(SysCtlSRAMBankValid(sramBank)); 157 158 /* Waiting for SRAM Ready Bit to be set */ 159 while (!(SYSCTL->SRAM_BANKEN & SYSCTL_SRAM_BANKEN_SRAM_RDY)) 160 ; 161 162 SYSCTL->SRAM_BANKEN = (sramBank | SYSCTL_SRAM_BANKEN_BNK0_EN); 163 } 164 165 void SysCtl_disableSRAMBank(uint_fast8_t sramBank) 166 { 167 ASSERT(SysCtlSRAMBankValid(sramBank)); 168 169 /* Waiting for SRAM Ready Bit to be set */ 170 while (!(SYSCTL->SRAM_BANKEN & SYSCTL_SRAM_BANKEN_SRAM_RDY)) 171 ; 172 173 switch (sramBank) 174 { 175 case SYSCTL_SRAM_BANK7: 176 sramBank = SYSCTL_SRAM_BANK6 + SYSCTL_SRAM_BANK5 + SYSCTL_SRAM_BANK4 177 + SYSCTL_SRAM_BANK3 + SYSCTL_SRAM_BANK2 178 + SYSCTL_SRAM_BANK1; 179 break; 180 case SYSCTL_SRAM_BANK6: 181 sramBank = SYSCTL_SRAM_BANK5 + SYSCTL_SRAM_BANK4 182 + SYSCTL_SRAM_BANK3 + SYSCTL_SRAM_BANK2 183 + SYSCTL_SRAM_BANK1; 184 break; 185 case SYSCTL_SRAM_BANK5: 186 sramBank = SYSCTL_SRAM_BANK4 + SYSCTL_SRAM_BANK3 187 + SYSCTL_SRAM_BANK2 + SYSCTL_SRAM_BANK1; 188 break; 189 case SYSCTL_SRAM_BANK4: 190 sramBank = SYSCTL_SRAM_BANK3 + SYSCTL_SRAM_BANK2 191 + SYSCTL_SRAM_BANK1; 192 break; 193 case SYSCTL_SRAM_BANK3: 194 sramBank = SYSCTL_SRAM_BANK2 + SYSCTL_SRAM_BANK1; 195 break; 196 case SYSCTL_SRAM_BANK2: 197 sramBank = SYSCTL_SRAM_BANK1; 198 break; 199 case SYSCTL_SRAM_BANK1: 200 sramBank = 0; 201 break; 202 default: 203 return; 204 } 205 206 SYSCTL->SRAM_BANKEN = (sramBank | SYSCTL_SRAM_BANKEN_BNK0_EN); 207 } 208 209 void SysCtl_enableSRAMBankRetention(uint_fast8_t sramBank) 210 { 211 ASSERT(SysCtlSRAMBankValidRet(sramBank)); 212 213 /* Waiting for SRAM Ready Bit to be set */ 214 while (!(SYSCTL->SRAM_BANKRET & SYSCTL_SRAM_BANKRET_SRAM_RDY)) 215 ; 216 217 SYSCTL->SRAM_BANKRET |= sramBank; 218 } 219 220 void SysCtl_disableSRAMBankRetention(uint_fast8_t sramBank) 221 { 222 ASSERT(SysCtlSRAMBankValidRet(sramBank)); 223 224 /* Waiting for SRAM Ready Bit to be set */ 225 while (!(SYSCTL->SRAM_BANKRET & SYSCTL_SRAM_BANKRET_SRAM_RDY)) 226 ; 227 228 SYSCTL->SRAM_BANKRET &= ~sramBank; 229 } 230 231 void SysCtl_rebootDevice(void) 232 { 233 SYSCTL->REBOOT_CTL = (SYSCTL_REBOOT_CTL_REBOOT | SYSCTL_REBOOT_KEY); 234 } 235 236 void SysCtl_enablePeripheralAtCPUHalt(uint_fast16_t devices) 237 { 238 ASSERT(SysCtlPeripheralIsValid(devices)); 239 SYSCTL->PERIHALT_CTL &= ~devices; 240 } 241 242 void SysCtl_disablePeripheralAtCPUHalt(uint_fast16_t devices) 243 { 244 ASSERT(SysCtlPeripheralIsValid(devices)); 245 SYSCTL->PERIHALT_CTL |= devices; 246 } 247 248 void SysCtl_setWDTTimeoutResetType(uint_fast8_t resetType) 249 { 250 if (resetType) 251 SYSCTL->WDTRESET_CTL |= 252 SYSCTL_WDTRESET_CTL_TIMEOUT; 253 else 254 SYSCTL->WDTRESET_CTL &= ~SYSCTL_WDTRESET_CTL_TIMEOUT; 255 } 256 257 void SysCtl_setWDTPasswordViolationResetType(uint_fast8_t resetType) 258 { 259 ASSERT(resetType <= SYSCTL_HARD_RESET); 260 261 if (resetType) 262 SYSCTL->WDTRESET_CTL |= 263 SYSCTL_WDTRESET_CTL_VIOLATION; 264 else 265 SYSCTL->WDTRESET_CTL &= ~SYSCTL_WDTRESET_CTL_VIOLATION; 266 } 267 268 void SysCtl_enableGlitchFilter(void) 269 { 270 SYSCTL->DIO_GLTFLT_CTL |= SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN; 271 } 272 273 void SysCtl_disableGlitchFilter(void) 274 { 275 SYSCTL->DIO_GLTFLT_CTL &= ~SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN; 276 } 277 278 uint_fast16_t SysCtl_getTempCalibrationConstant(uint32_t refVoltage, 279 uint32_t temperature) 280 { 281 return HWREG16(TLV_BASE + refVoltage + temperature); 282 } 283 284 #endif /* __MCU_HAS_SYSCTL__ */ 285