1*5fd0122aSMatthias Ringwald /* --COPYRIGHT--,BSD
2*5fd0122aSMatthias Ringwald * Copyright (c) 2017, Texas Instruments Incorporated
3*5fd0122aSMatthias Ringwald * All rights reserved.
4*5fd0122aSMatthias Ringwald *
5*5fd0122aSMatthias Ringwald * Redistribution and use in source and binary forms, with or without
6*5fd0122aSMatthias Ringwald * modification, are permitted provided that the following conditions
7*5fd0122aSMatthias Ringwald * are met:
8*5fd0122aSMatthias Ringwald *
9*5fd0122aSMatthias Ringwald * * Redistributions of source code must retain the above copyright
10*5fd0122aSMatthias Ringwald * notice, this list of conditions and the following disclaimer.
11*5fd0122aSMatthias Ringwald *
12*5fd0122aSMatthias Ringwald * * Redistributions in binary form must reproduce the above copyright
13*5fd0122aSMatthias Ringwald * notice, this list of conditions and the following disclaimer in the
14*5fd0122aSMatthias Ringwald * documentation and/or other materials provided with the distribution.
15*5fd0122aSMatthias Ringwald *
16*5fd0122aSMatthias Ringwald * * Neither the name of Texas Instruments Incorporated nor the names of
17*5fd0122aSMatthias Ringwald * its contributors may be used to endorse or promote products derived
18*5fd0122aSMatthias Ringwald * from this software without specific prior written permission.
19*5fd0122aSMatthias Ringwald *
20*5fd0122aSMatthias Ringwald * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21*5fd0122aSMatthias Ringwald * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22*5fd0122aSMatthias Ringwald * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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31*5fd0122aSMatthias Ringwald * --/COPYRIGHT--*/
32*5fd0122aSMatthias Ringwald #include <ti/devices/msp432p4xx/driverlib/fpu.h>
33*5fd0122aSMatthias Ringwald
FPU_enableModule(void)34*5fd0122aSMatthias Ringwald void FPU_enableModule(void)
35*5fd0122aSMatthias Ringwald {
36*5fd0122aSMatthias Ringwald //
37*5fd0122aSMatthias Ringwald // Enable the coprocessors used by the floating-point unit.
38*5fd0122aSMatthias Ringwald //
39*5fd0122aSMatthias Ringwald SCB->CPACR = ((SCB->CPACR & ~(SCB_CPACR_CP11_MASK | SCB_CPACR_CP10_MASK))
40*5fd0122aSMatthias Ringwald | SCB_CPACR_CP11_MASK | SCB_CPACR_CP10_MASK);
41*5fd0122aSMatthias Ringwald }
42*5fd0122aSMatthias Ringwald
FPU_disableModule(void)43*5fd0122aSMatthias Ringwald void FPU_disableModule(void)
44*5fd0122aSMatthias Ringwald {
45*5fd0122aSMatthias Ringwald //
46*5fd0122aSMatthias Ringwald // Disable the coprocessors used by the floating-point unit.
47*5fd0122aSMatthias Ringwald //
48*5fd0122aSMatthias Ringwald SCB->CPACR = ((SCB->CPACR & ~(SCB_CPACR_CP10_MASK | SCB_CPACR_CP11_MASK)));
49*5fd0122aSMatthias Ringwald }
50*5fd0122aSMatthias Ringwald
FPU_enableStacking(void)51*5fd0122aSMatthias Ringwald void FPU_enableStacking(void)
52*5fd0122aSMatthias Ringwald {
53*5fd0122aSMatthias Ringwald //
54*5fd0122aSMatthias Ringwald // Enable automatic state preservation for the floating-point unit, and
55*5fd0122aSMatthias Ringwald // disable lazy state preservation (meaning that the floating-point state
56*5fd0122aSMatthias Ringwald // is always stacked when floating-point instructions are used).
57*5fd0122aSMatthias Ringwald //
58*5fd0122aSMatthias Ringwald FPU->FPCCR = (FPU->FPCCR & ~FPU_FPCCR_LSPEN_Msk) | FPU_FPCCR_ASPEN_Msk;
59*5fd0122aSMatthias Ringwald }
60*5fd0122aSMatthias Ringwald
FPU_enableLazyStacking(void)61*5fd0122aSMatthias Ringwald void FPU_enableLazyStacking(void)
62*5fd0122aSMatthias Ringwald {
63*5fd0122aSMatthias Ringwald //
64*5fd0122aSMatthias Ringwald // Enable automatic and lazy state preservation for the floating-point
65*5fd0122aSMatthias Ringwald // unit.
66*5fd0122aSMatthias Ringwald //
67*5fd0122aSMatthias Ringwald FPU->FPCCR |= FPU_FPCCR_ASPEN_Msk | FPU_FPCCR_LSPEN_Msk;
68*5fd0122aSMatthias Ringwald }
69*5fd0122aSMatthias Ringwald
FPU_disableStacking(void)70*5fd0122aSMatthias Ringwald void FPU_disableStacking(void)
71*5fd0122aSMatthias Ringwald {
72*5fd0122aSMatthias Ringwald //
73*5fd0122aSMatthias Ringwald // Disable automatic and lazy state preservation for the floating-point
74*5fd0122aSMatthias Ringwald // unit.
75*5fd0122aSMatthias Ringwald //
76*5fd0122aSMatthias Ringwald FPU->FPCCR &= ~(FPU_FPCCR_ASPEN_Msk | FPU_FPCCR_LSPEN_Msk);
77*5fd0122aSMatthias Ringwald }
78*5fd0122aSMatthias Ringwald
FPU_setHalfPrecisionMode(uint32_t mode)79*5fd0122aSMatthias Ringwald void FPU_setHalfPrecisionMode(uint32_t mode)
80*5fd0122aSMatthias Ringwald {
81*5fd0122aSMatthias Ringwald //
82*5fd0122aSMatthias Ringwald // Set the half-precision floating-point format.
83*5fd0122aSMatthias Ringwald //
84*5fd0122aSMatthias Ringwald FPU->FPDSCR = (FPU->FPDSCR & ~(FPU_FPDSCR_AHP_Msk)) | mode;
85*5fd0122aSMatthias Ringwald }
86*5fd0122aSMatthias Ringwald
FPU_setNaNMode(uint32_t mode)87*5fd0122aSMatthias Ringwald void FPU_setNaNMode(uint32_t mode)
88*5fd0122aSMatthias Ringwald {
89*5fd0122aSMatthias Ringwald //
90*5fd0122aSMatthias Ringwald // Set the NaN mode.
91*5fd0122aSMatthias Ringwald //
92*5fd0122aSMatthias Ringwald FPU->FPDSCR = (FPU->FPDSCR & ~(FPU_FPDSCR_DN_Msk)) | mode;
93*5fd0122aSMatthias Ringwald }
94*5fd0122aSMatthias Ringwald
FPU_setFlushToZeroMode(uint32_t mode)95*5fd0122aSMatthias Ringwald void FPU_setFlushToZeroMode(uint32_t mode)
96*5fd0122aSMatthias Ringwald {
97*5fd0122aSMatthias Ringwald //
98*5fd0122aSMatthias Ringwald // Set the flush-to-zero mode.
99*5fd0122aSMatthias Ringwald //
100*5fd0122aSMatthias Ringwald FPU->FPDSCR = (FPU->FPDSCR & ~(FPU_FPDSCR_FZ_Msk)) | mode;
101*5fd0122aSMatthias Ringwald }
102*5fd0122aSMatthias Ringwald
FPU_setRoundingMode(uint32_t mode)103*5fd0122aSMatthias Ringwald void FPU_setRoundingMode(uint32_t mode)
104*5fd0122aSMatthias Ringwald {
105*5fd0122aSMatthias Ringwald //
106*5fd0122aSMatthias Ringwald // Set the rounding mode.
107*5fd0122aSMatthias Ringwald //
108*5fd0122aSMatthias Ringwald FPU->FPDSCR = (FPU->FPDSCR & ~(FPU_FPDSCR_RMode_Msk)) | mode;
109*5fd0122aSMatthias Ringwald }
110*5fd0122aSMatthias Ringwald
111