1 /**************************************************************************//** 2 * @file core_cm4.h 3 * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File 4 * @version V4.20 5 * @date 20. August 2015 6 ******************************************************************************/ 7 /* Copyright (c) 2009 - 2015 ARM LIMITED 8 9 All rights reserved. 10 Redistribution and use in source and binary forms, with or without 11 modification, are permitted provided that the following conditions are met: 12 - Redistributions of source code must retain the above copyright 13 notice, this list of conditions and the following disclaimer. 14 - Redistributions in binary form must reproduce the above copyright 15 notice, this list of conditions and the following disclaimer in the 16 documentation and/or other materials provided with the distribution. 17 - Neither the name of ARM nor the names of its contributors may be used 18 to endorse or promote products derived from this software without 19 specific prior written permission. 20 * 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 ---------------------------------------------------------------------------*/ 33 34 35 #if defined ( __ICCARM__ ) 36 #pragma system_include /* treat file as system include file for MISRA check */ 37 #elif (__ARMCC_VERSION >= 6010050) 38 #pragma clang system_header /* treat file as system include file */ 39 #endif 40 41 #ifndef __CORE_CM4_H_GENERIC 42 #define __CORE_CM4_H_GENERIC 43 44 #include <stdint.h> 45 46 #ifdef __cplusplus 47 extern "C" { 48 #endif 49 50 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 51 CMSIS violates the following MISRA-C:2004 rules: 52 53 \li Required Rule 8.5, object/function definition in header file.<br> 54 Function definitions in header files are used to allow 'inlining'. 55 56 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> 57 Unions are used for effective representation of core registers. 58 59 \li Advisory Rule 19.7, Function-like macro defined.<br> 60 Function-like macros are used to allow more efficient code. 61 */ 62 63 64 /******************************************************************************* 65 * CMSIS definitions 66 ******************************************************************************/ 67 /** \ingroup Cortex_M4 68 @{ 69 */ 70 71 /* CMSIS CM4 definitions */ 72 #define __CM4_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ 73 #define __CM4_CMSIS_VERSION_SUB (0x14U) /*!< [15:0] CMSIS HAL sub version */ 74 #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ 75 __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ 76 77 #define __CORTEX_M (0x04U) /*!< Cortex-M Core */ 78 79 80 #if defined ( __CC_ARM ) 81 #define __ASM __asm /*!< asm keyword for ARM Compiler */ 82 #define __INLINE __inline /*!< inline keyword for ARM Compiler */ 83 #define __STATIC_INLINE static __inline 84 85 #elif defined ( __GNUC__ ) 86 #define __ASM __asm /*!< asm keyword for GNU Compiler */ 87 #define __INLINE inline /*!< inline keyword for GNU Compiler */ 88 #define __STATIC_INLINE static inline 89 90 #elif defined ( __ICCARM__ ) 91 #define __ASM __asm /*!< asm keyword for IAR Compiler */ 92 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ 93 #define __STATIC_INLINE static inline 94 95 #elif defined ( __TMS470__ ) 96 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ 97 #define __STATIC_INLINE static inline 98 99 #elif defined ( __TASKING__ ) 100 #define __ASM __asm /*!< asm keyword for TASKING Compiler */ 101 #define __INLINE inline /*!< inline keyword for TASKING Compiler */ 102 #define __STATIC_INLINE static inline 103 104 #elif defined ( __CSMC__ ) 105 #define __packed 106 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ 107 #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ 108 #define __STATIC_INLINE static inline 109 110 #elif (__ARMCC_VERSION >= 6010050) 111 #define __ASM __asm /*!< asm keyword for ARM Compiler */ 112 #define __INLINE __inline /*!< inline keyword for ARM Compiler */ 113 #define __STATIC_INLINE static __inline 114 115 #else 116 #error Unknown compiler 117 #endif 118 119 /** __FPU_USED indicates whether an FPU is used or not. 120 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. 121 */ 122 #if defined ( __CC_ARM ) 123 #if defined __TARGET_FPU_VFP 124 #if (__FPU_PRESENT == 1U) 125 #define __FPU_USED 1U 126 #else 127 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 128 #define __FPU_USED 0U 129 #endif 130 #else 131 #define __FPU_USED 0U 132 #endif 133 134 #elif defined ( __GNUC__ ) 135 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 136 #if (__FPU_PRESENT == 1U) 137 #define __FPU_USED 1U 138 #else 139 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 140 #define __FPU_USED 0U 141 #endif 142 #else 143 #define __FPU_USED 0U 144 #endif 145 146 #elif defined ( __ICCARM__ ) 147 #if defined __ARMVFP__ 148 #if (__FPU_PRESENT == 1U) 149 #define __FPU_USED 1U 150 #else 151 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 152 #define __FPU_USED 0U 153 #endif 154 #else 155 #define __FPU_USED 0U 156 #endif 157 158 #elif defined ( __TMS470__ ) 159 #if defined __TI_VFP_SUPPORT__ 160 #if (__FPU_PRESENT == 1U) 161 #define __FPU_USED 1U 162 #else 163 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 164 #define __FPU_USED 0U 165 #endif 166 #else 167 #define __FPU_USED 0U 168 #endif 169 170 #elif defined ( __TASKING__ ) 171 #if defined __FPU_VFP__ 172 #if (__FPU_PRESENT == 1U) 173 #define __FPU_USED 1U 174 #else 175 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 176 #define __FPU_USED 0U 177 #endif 178 #else 179 #define __FPU_USED 0U 180 #endif 181 182 #elif defined ( __CSMC__ ) 183 #if ( __CSMC__ & 0x400U) 184 #if (__FPU_PRESENT == 1U) 185 #define __FPU_USED 1U 186 #else 187 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 188 #define __FPU_USED 0U 189 #endif 190 #else 191 #define __FPU_USED 0U 192 #endif 193 194 #elif (__ARMCC_VERSION >= 6010050) 195 #if defined __ARM_PCS_VFP 196 #if (__FPU_PRESENT == 1) 197 #define __FPU_USED 1U 198 #else 199 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 200 #define __FPU_USED 0U 201 #endif 202 #else 203 #define __FPU_USED 0U 204 #endif 205 206 #endif 207 208 #include "core_cmInstr.h" /* Core Instruction Access */ 209 #include "core_cmFunc.h" /* Core Function Access */ 210 #include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ 211 212 #ifdef __cplusplus 213 } 214 #endif 215 216 #endif /* __CORE_CM4_H_GENERIC */ 217 218 #ifndef __CMSIS_GENERIC 219 220 #ifndef __CORE_CM4_H_DEPENDANT 221 #define __CORE_CM4_H_DEPENDANT 222 223 #ifdef __cplusplus 224 extern "C" { 225 #endif 226 227 /* check device defines and use defaults */ 228 #if defined __CHECK_DEVICE_DEFINES 229 #ifndef __CM4_REV 230 #define __CM4_REV 0x0000U 231 #warning "__CM4_REV not defined in device header file; using default!" 232 #endif 233 234 #ifndef __FPU_PRESENT 235 #define __FPU_PRESENT 0U 236 #warning "__FPU_PRESENT not defined in device header file; using default!" 237 #endif 238 239 #ifndef __MPU_PRESENT 240 #define __MPU_PRESENT 0U 241 #warning "__MPU_PRESENT not defined in device header file; using default!" 242 #endif 243 244 #ifndef __NVIC_PRIO_BITS 245 #define __NVIC_PRIO_BITS 4U 246 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 247 #endif 248 249 #ifndef __Vendor_SysTickConfig 250 #define __Vendor_SysTickConfig 0U 251 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 252 #endif 253 #endif 254 255 /* IO definitions (access restrictions to peripheral registers) */ 256 /** 257 \defgroup CMSIS_glob_defs CMSIS Global Defines 258 259 <strong>IO Type Qualifiers</strong> are used 260 \li to specify the access to peripheral variables. 261 \li for automatic generation of peripheral register debug information. 262 */ 263 #ifdef __cplusplus 264 #define __I volatile /*!< Defines 'read only' permissions */ 265 #else 266 #define __I volatile const /*!< Defines 'read only' permissions */ 267 #endif 268 #define __O volatile /*!< Defines 'write only' permissions */ 269 #define __IO volatile /*!< Defines 'read / write' permissions */ 270 271 /* following defines should be used for structure members */ 272 #define __IM volatile const /*! Defines 'read only' structure member permissions */ 273 #define __OM volatile /*! Defines 'write only' structure member permissions */ 274 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ 275 276 /*@} end of group Cortex_M4 */ 277 278 279 280 /******************************************************************************* 281 * Register Abstraction 282 Core Register contain: 283 - Core Register 284 - Core NVIC Register 285 - Core SCB Register 286 - Core SysTick Register 287 - Core Debug Register 288 - Core MPU Register 289 - Core FPU Register 290 ******************************************************************************/ 291 /** \defgroup CMSIS_core_register Defines and Type Definitions 292 \brief Type definitions and defines for Cortex-M processor based devices. 293 */ 294 295 /** \ingroup CMSIS_core_register 296 \defgroup CMSIS_CORE Status and Control Registers 297 \brief Core Register type definitions. 298 @{ 299 */ 300 301 /** \brief Union type to access the Application Program Status Register (APSR). 302 */ 303 typedef union 304 { 305 struct 306 { 307 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ 308 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 309 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ 310 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 311 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 312 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 313 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 314 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 315 } b; /*!< Structure used for bit access */ 316 uint32_t w; /*!< Type used for word access */ 317 } APSR_Type; 318 319 /* APSR Register Definitions */ 320 #define APSR_N_Pos 31U /*!< APSR: N Position */ 321 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ 322 323 #define APSR_Z_Pos 30U /*!< APSR: Z Position */ 324 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ 325 326 #define APSR_C_Pos 29U /*!< APSR: C Position */ 327 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ 328 329 #define APSR_V_Pos 28U /*!< APSR: V Position */ 330 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ 331 332 #define APSR_Q_Pos 27U /*!< APSR: Q Position */ 333 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ 334 335 #define APSR_GE_Pos 16U /*!< APSR: GE Position */ 336 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ 337 338 339 /** \brief Union type to access the Interrupt Program Status Register (IPSR). 340 */ 341 typedef union 342 { 343 struct 344 { 345 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 346 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ 347 } b; /*!< Structure used for bit access */ 348 uint32_t w; /*!< Type used for word access */ 349 } IPSR_Type; 350 351 /* IPSR Register Definitions */ 352 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ 353 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ 354 355 356 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 357 */ 358 typedef union 359 { 360 struct 361 { 362 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 363 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ 364 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 365 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ 366 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ 367 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ 368 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 369 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 370 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 371 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 372 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 373 } b; /*!< Structure used for bit access */ 374 uint32_t w; /*!< Type used for word access */ 375 } xPSR_Type; 376 377 /* xPSR Register Definitions */ 378 #define xPSR_N_Pos 31U /*!< xPSR: N Position */ 379 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ 380 381 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ 382 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ 383 384 #define xPSR_C_Pos 29U /*!< xPSR: C Position */ 385 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ 386 387 #define xPSR_V_Pos 28U /*!< xPSR: V Position */ 388 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ 389 390 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ 391 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ 392 393 #define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ 394 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ 395 396 #define xPSR_T_Pos 24U /*!< xPSR: T Position */ 397 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ 398 399 #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ 400 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ 401 402 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ 403 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ 404 405 406 /** \brief Union type to access the Control Registers (CONTROL). 407 */ 408 typedef union 409 { 410 struct 411 { 412 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ 413 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ 414 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ 415 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ 416 } b; /*!< Structure used for bit access */ 417 uint32_t w; /*!< Type used for word access */ 418 } CONTROL_Type; 419 420 /* CONTROL Register Definitions */ 421 #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ 422 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ 423 424 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ 425 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ 426 427 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ 428 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ 429 430 /*@} end of group CMSIS_CORE */ 431 432 433 /** \ingroup CMSIS_core_register 434 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 435 \brief Type definitions for the NVIC Registers 436 @{ 437 */ 438 439 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 440 */ 441 typedef struct 442 { 443 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 444 uint32_t RESERVED0[24U]; 445 __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ 446 uint32_t RSERVED1[24U]; 447 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ 448 uint32_t RESERVED2[24U]; 449 __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ 450 uint32_t RESERVED3[24U]; 451 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ 452 uint32_t RESERVED4[56U]; 453 __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ 454 uint32_t RESERVED5[644U]; 455 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ 456 } NVIC_Type; 457 458 /* Software Triggered Interrupt Register Definitions */ 459 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ 460 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ 461 462 /*@} end of group CMSIS_NVIC */ 463 464 465 /** \ingroup CMSIS_core_register 466 \defgroup CMSIS_SCB System Control Block (SCB) 467 \brief Type definitions for the System Control Block Registers 468 @{ 469 */ 470 471 /** \brief Structure type to access the System Control Block (SCB). 472 */ 473 typedef struct 474 { 475 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 476 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ 477 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ 478 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ 479 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 480 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ 481 __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ 482 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ 483 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ 484 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ 485 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ 486 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ 487 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ 488 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ 489 __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ 490 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ 491 __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ 492 __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ 493 __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ 494 uint32_t RESERVED0[5U]; 495 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ 496 } SCB_Type; 497 498 /* SCB CPUID Register Definitions */ 499 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ 500 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 501 502 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ 503 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 504 505 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ 506 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ 507 508 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ 509 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 510 511 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ 512 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ 513 514 /* SCB Interrupt Control State Register Definitions */ 515 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ 516 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ 517 518 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ 519 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 520 521 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ 522 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 523 524 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ 525 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 526 527 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ 528 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 529 530 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ 531 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 532 533 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ 534 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 535 536 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ 537 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 538 539 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ 540 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ 541 542 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ 543 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ 544 545 /* SCB Vector Table Offset Register Definitions */ 546 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ 547 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ 548 549 /* SCB Application Interrupt and Reset Control Register Definitions */ 550 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ 551 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 552 553 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ 554 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 555 556 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ 557 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 558 559 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ 560 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ 561 562 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ 563 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 564 565 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ 566 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 567 568 #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ 569 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ 570 571 /* SCB System Control Register Definitions */ 572 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ 573 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 574 575 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ 576 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 577 578 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ 579 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 580 581 /* SCB Configuration Control Register Definitions */ 582 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ 583 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ 584 585 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ 586 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ 587 588 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ 589 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ 590 591 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ 592 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 593 594 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ 595 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ 596 597 #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ 598 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ 599 600 /* SCB System Handler Control and State Register Definitions */ 601 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ 602 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ 603 604 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ 605 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ 606 607 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ 608 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ 609 610 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ 611 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 612 613 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ 614 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ 615 616 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ 617 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ 618 619 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ 620 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ 621 622 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ 623 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ 624 625 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ 626 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ 627 628 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ 629 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ 630 631 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ 632 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ 633 634 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ 635 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ 636 637 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ 638 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ 639 640 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ 641 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ 642 643 /* SCB Configurable Fault Status Registers Definitions */ 644 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ 645 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ 646 647 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ 648 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ 649 650 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ 651 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ 652 653 /* SCB Hard Fault Status Registers Definitions */ 654 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ 655 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ 656 657 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ 658 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ 659 660 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ 661 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ 662 663 /* SCB Debug Fault Status Register Definitions */ 664 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ 665 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ 666 667 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ 668 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ 669 670 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ 671 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ 672 673 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ 674 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ 675 676 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ 677 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ 678 679 /*@} end of group CMSIS_SCB */ 680 681 682 /** \ingroup CMSIS_core_register 683 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) 684 \brief Type definitions for the System Control and ID Register not in the SCB 685 @{ 686 */ 687 688 /** \brief Structure type to access the System Control and ID Register not in the SCB. 689 */ 690 typedef struct 691 { 692 uint32_t RESERVED0[1U]; 693 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ 694 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ 695 } SCnSCB_Type; 696 697 /* Interrupt Controller Type Register Definitions */ 698 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ 699 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ 700 701 /* Auxiliary Control Register Definitions */ 702 #define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ 703 #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ 704 705 #define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ 706 #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ 707 708 #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ 709 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ 710 711 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ 712 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ 713 714 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ 715 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ 716 717 /*@} end of group CMSIS_SCnotSCB */ 718 719 720 /** \ingroup CMSIS_core_register 721 \defgroup CMSIS_SysTick System Tick Timer (SysTick) 722 \brief Type definitions for the System Timer Registers. 723 @{ 724 */ 725 726 /** \brief Structure type to access the System Timer (SysTick). 727 */ 728 typedef struct 729 { 730 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ 731 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 732 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ 733 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 734 } SysTick_Type; 735 736 /* SysTick Control / Status Register Definitions */ 737 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ 738 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 739 740 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ 741 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 742 743 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ 744 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 745 746 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ 747 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ 748 749 /* SysTick Reload Register Definitions */ 750 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ 751 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ 752 753 /* SysTick Current Register Definitions */ 754 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ 755 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ 756 757 /* SysTick Calibration Register Definitions */ 758 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ 759 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 760 761 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ 762 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 763 764 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ 765 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ 766 767 /*@} end of group CMSIS_SysTick */ 768 769 770 /** \ingroup CMSIS_core_register 771 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) 772 \brief Type definitions for the Instrumentation Trace Macrocell (ITM) 773 @{ 774 */ 775 776 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). 777 */ 778 typedef struct 779 { 780 __OM union 781 { 782 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ 783 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ 784 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ 785 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ 786 uint32_t RESERVED0[864U]; 787 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ 788 uint32_t RESERVED1[15U]; 789 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ 790 uint32_t RESERVED2[15U]; 791 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ 792 uint32_t RESERVED3[29U]; 793 __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ 794 __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ 795 __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ 796 uint32_t RESERVED4[43U]; 797 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ 798 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ 799 uint32_t RESERVED5[6U]; 800 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ 801 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ 802 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ 803 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ 804 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ 805 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ 806 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ 807 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ 808 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ 809 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ 810 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ 811 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ 812 } ITM_Type; 813 814 /* ITM Trace Privilege Register Definitions */ 815 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ 816 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ 817 818 /* ITM Trace Control Register Definitions */ 819 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ 820 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ 821 822 #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ 823 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ 824 825 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ 826 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ 827 828 #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ 829 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ 830 831 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ 832 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ 833 834 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ 835 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ 836 837 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ 838 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ 839 840 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ 841 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ 842 843 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ 844 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ 845 846 /* ITM Integration Write Register Definitions */ 847 #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ 848 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ 849 850 /* ITM Integration Read Register Definitions */ 851 #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ 852 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ 853 854 /* ITM Integration Mode Control Register Definitions */ 855 #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ 856 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ 857 858 /* ITM Lock Status Register Definitions */ 859 #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ 860 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ 861 862 #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ 863 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ 864 865 #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ 866 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ 867 868 /*@}*/ /* end of group CMSIS_ITM */ 869 870 871 /** \ingroup CMSIS_core_register 872 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) 873 \brief Type definitions for the Data Watchpoint and Trace (DWT) 874 @{ 875 */ 876 877 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). 878 */ 879 typedef struct 880 { 881 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ 882 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ 883 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ 884 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ 885 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ 886 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ 887 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ 888 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ 889 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ 890 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ 891 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ 892 uint32_t RESERVED0[1U]; 893 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ 894 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ 895 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ 896 uint32_t RESERVED1[1U]; 897 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ 898 __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ 899 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ 900 uint32_t RESERVED2[1U]; 901 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ 902 __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ 903 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ 904 } DWT_Type; 905 906 /* DWT Control Register Definitions */ 907 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ 908 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ 909 910 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ 911 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ 912 913 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ 914 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ 915 916 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ 917 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ 918 919 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ 920 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ 921 922 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ 923 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ 924 925 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ 926 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ 927 928 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ 929 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ 930 931 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ 932 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ 933 934 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ 935 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ 936 937 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ 938 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ 939 940 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ 941 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ 942 943 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ 944 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ 945 946 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ 947 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ 948 949 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ 950 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ 951 952 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ 953 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ 954 955 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ 956 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ 957 958 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ 959 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ 960 961 /* DWT CPI Count Register Definitions */ 962 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ 963 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ 964 965 /* DWT Exception Overhead Count Register Definitions */ 966 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ 967 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ 968 969 /* DWT Sleep Count Register Definitions */ 970 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ 971 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ 972 973 /* DWT LSU Count Register Definitions */ 974 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ 975 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ 976 977 /* DWT Folded-instruction Count Register Definitions */ 978 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ 979 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ 980 981 /* DWT Comparator Mask Register Definitions */ 982 #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ 983 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ 984 985 /* DWT Comparator Function Register Definitions */ 986 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ 987 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ 988 989 #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ 990 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ 991 992 #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ 993 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ 994 995 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ 996 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ 997 998 #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ 999 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ 1000 1001 #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ 1002 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ 1003 1004 #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ 1005 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ 1006 1007 #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ 1008 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ 1009 1010 #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ 1011 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ 1012 1013 /*@}*/ /* end of group CMSIS_DWT */ 1014 1015 1016 /** \ingroup CMSIS_core_register 1017 \defgroup CMSIS_TPI Trace Port Interface (TPI) 1018 \brief Type definitions for the Trace Port Interface (TPI) 1019 @{ 1020 */ 1021 1022 /** \brief Structure type to access the Trace Port Interface Register (TPI). 1023 */ 1024 typedef struct 1025 { 1026 __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ 1027 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ 1028 uint32_t RESERVED0[2U]; 1029 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ 1030 uint32_t RESERVED1[55U]; 1031 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ 1032 uint32_t RESERVED2[131U]; 1033 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ 1034 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ 1035 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ 1036 uint32_t RESERVED3[759U]; 1037 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ 1038 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ 1039 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ 1040 uint32_t RESERVED4[1U]; 1041 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ 1042 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ 1043 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ 1044 uint32_t RESERVED5[39U]; 1045 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ 1046 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ 1047 uint32_t RESERVED7[8U]; 1048 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ 1049 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ 1050 } TPI_Type; 1051 1052 /* TPI Asynchronous Clock Prescaler Register Definitions */ 1053 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ 1054 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ 1055 1056 /* TPI Selected Pin Protocol Register Definitions */ 1057 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ 1058 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ 1059 1060 /* TPI Formatter and Flush Status Register Definitions */ 1061 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ 1062 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ 1063 1064 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ 1065 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ 1066 1067 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ 1068 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ 1069 1070 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ 1071 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ 1072 1073 /* TPI Formatter and Flush Control Register Definitions */ 1074 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ 1075 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ 1076 1077 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ 1078 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ 1079 1080 /* TPI TRIGGER Register Definitions */ 1081 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ 1082 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ 1083 1084 /* TPI Integration ETM Data Register Definitions (FIFO0) */ 1085 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ 1086 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ 1087 1088 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ 1089 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ 1090 1091 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ 1092 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ 1093 1094 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ 1095 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ 1096 1097 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ 1098 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ 1099 1100 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ 1101 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ 1102 1103 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ 1104 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ 1105 1106 /* TPI ITATBCTR2 Register Definitions */ 1107 #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ 1108 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ 1109 1110 /* TPI Integration ITM Data Register Definitions (FIFO1) */ 1111 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ 1112 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ 1113 1114 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ 1115 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ 1116 1117 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ 1118 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ 1119 1120 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ 1121 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ 1122 1123 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ 1124 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ 1125 1126 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ 1127 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ 1128 1129 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ 1130 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ 1131 1132 /* TPI ITATBCTR0 Register Definitions */ 1133 #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ 1134 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ 1135 1136 /* TPI Integration Mode Control Register Definitions */ 1137 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ 1138 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ 1139 1140 /* TPI DEVID Register Definitions */ 1141 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ 1142 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ 1143 1144 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ 1145 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ 1146 1147 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ 1148 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ 1149 1150 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ 1151 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ 1152 1153 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ 1154 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ 1155 1156 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ 1157 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ 1158 1159 /* TPI DEVTYPE Register Definitions */ 1160 #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ 1161 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ 1162 1163 #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ 1164 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ 1165 1166 /*@}*/ /* end of group CMSIS_TPI */ 1167 1168 1169 #if (__MPU_PRESENT == 1U) 1170 /** \ingroup CMSIS_core_register 1171 \defgroup CMSIS_MPU Memory Protection Unit (MPU) 1172 \brief Type definitions for the Memory Protection Unit (MPU) 1173 @{ 1174 */ 1175 1176 /** \brief Structure type to access the Memory Protection Unit (MPU). 1177 */ 1178 typedef struct 1179 { 1180 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ 1181 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ 1182 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ 1183 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ 1184 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ 1185 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ 1186 __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ 1187 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ 1188 __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ 1189 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ 1190 __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ 1191 } MPU_Type; 1192 1193 /* MPU Type Register */ 1194 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ 1195 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ 1196 1197 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ 1198 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ 1199 1200 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ 1201 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ 1202 1203 /* MPU Control Register */ 1204 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ 1205 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ 1206 1207 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ 1208 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ 1209 1210 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ 1211 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ 1212 1213 /* MPU Region Number Register */ 1214 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ 1215 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ 1216 1217 /* MPU Region Base Address Register */ 1218 #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ 1219 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ 1220 1221 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ 1222 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ 1223 1224 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ 1225 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ 1226 1227 /* MPU Region Attribute and Size Register */ 1228 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ 1229 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ 1230 1231 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ 1232 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ 1233 1234 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ 1235 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ 1236 1237 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ 1238 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ 1239 1240 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ 1241 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ 1242 1243 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ 1244 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ 1245 1246 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ 1247 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ 1248 1249 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ 1250 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ 1251 1252 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ 1253 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ 1254 1255 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ 1256 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ 1257 1258 /*@} end of group CMSIS_MPU */ 1259 #endif 1260 1261 1262 #if (__FPU_PRESENT == 1U) 1263 /** \ingroup CMSIS_core_register 1264 \defgroup CMSIS_FPU Floating Point Unit (FPU) 1265 \brief Type definitions for the Floating Point Unit (FPU) 1266 @{ 1267 */ 1268 1269 /** \brief Structure type to access the Floating Point Unit (FPU). 1270 */ 1271 typedef struct 1272 { 1273 uint32_t RESERVED0[1U]; 1274 __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ 1275 __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ 1276 __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ 1277 __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ 1278 __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ 1279 } FPU_Type; 1280 1281 /* Floating-Point Context Control Register */ 1282 #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ 1283 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ 1284 1285 #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ 1286 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ 1287 1288 #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ 1289 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ 1290 1291 #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ 1292 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ 1293 1294 #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ 1295 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ 1296 1297 #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ 1298 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ 1299 1300 #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ 1301 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ 1302 1303 #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ 1304 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ 1305 1306 #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ 1307 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ 1308 1309 /* Floating-Point Context Address Register */ 1310 #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ 1311 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ 1312 1313 /* Floating-Point Default Status Control Register */ 1314 #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ 1315 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ 1316 1317 #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ 1318 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ 1319 1320 #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ 1321 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ 1322 1323 #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ 1324 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ 1325 1326 /* Media and FP Feature Register 0 */ 1327 #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ 1328 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ 1329 1330 #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ 1331 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ 1332 1333 #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ 1334 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ 1335 1336 #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ 1337 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ 1338 1339 #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ 1340 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ 1341 1342 #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ 1343 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ 1344 1345 #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ 1346 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ 1347 1348 #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ 1349 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ 1350 1351 /* Media and FP Feature Register 1 */ 1352 #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ 1353 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ 1354 1355 #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ 1356 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ 1357 1358 #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ 1359 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ 1360 1361 #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ 1362 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ 1363 1364 /*@} end of group CMSIS_FPU */ 1365 #endif 1366 1367 1368 /** \ingroup CMSIS_core_register 1369 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 1370 \brief Type definitions for the Core Debug Registers 1371 @{ 1372 */ 1373 1374 /** \brief Structure type to access the Core Debug Register (CoreDebug). 1375 */ 1376 typedef struct 1377 { 1378 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ 1379 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ 1380 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ 1381 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ 1382 } CoreDebug_Type; 1383 1384 /* Debug Halting Control and Status Register */ 1385 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ 1386 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ 1387 1388 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ 1389 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ 1390 1391 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ 1392 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ 1393 1394 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ 1395 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ 1396 1397 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ 1398 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ 1399 1400 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ 1401 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ 1402 1403 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ 1404 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ 1405 1406 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ 1407 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ 1408 1409 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ 1410 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ 1411 1412 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ 1413 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ 1414 1415 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ 1416 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ 1417 1418 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ 1419 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ 1420 1421 /* Debug Core Register Selector Register */ 1422 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ 1423 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ 1424 1425 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ 1426 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ 1427 1428 /* Debug Exception and Monitor Control Register */ 1429 #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ 1430 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ 1431 1432 #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ 1433 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ 1434 1435 #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ 1436 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ 1437 1438 #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ 1439 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ 1440 1441 #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ 1442 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ 1443 1444 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ 1445 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ 1446 1447 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ 1448 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ 1449 1450 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ 1451 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ 1452 1453 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ 1454 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ 1455 1456 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ 1457 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ 1458 1459 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ 1460 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ 1461 1462 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ 1463 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ 1464 1465 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ 1466 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ 1467 1468 /*@} end of group CMSIS_CoreDebug */ 1469 1470 1471 /** \ingroup CMSIS_core_register 1472 \defgroup CMSIS_core_bitfield Core register bit field macros 1473 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). 1474 @{ 1475 */ 1476 1477 /** 1478 * Mask and shift a bit field value for use in a register bit range. 1479 * 1480 * \param[in] field Name of the register bit field. 1481 * \param[in] value Value of the bit field. 1482 * \return Masked and shifted value. 1483 */ 1484 #define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) 1485 1486 /** 1487 * Mask and shift a register value to extract a bit filed value. 1488 * 1489 * \param[in] field Name of the register bit field. 1490 * \param[in] value Value of register. 1491 * \return Masked and shifted bit field value. 1492 */ 1493 #define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) 1494 1495 /*@} end of group CMSIS_core_bitfield */ 1496 1497 1498 /** \ingroup CMSIS_core_register 1499 \defgroup CMSIS_core_base Core Definitions 1500 \brief Definitions for base addresses, unions, and structures. 1501 @{ 1502 */ 1503 1504 /* Memory mapping of Cortex-M4 Hardware */ 1505 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 1506 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ 1507 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ 1508 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ 1509 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ 1510 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 1511 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 1512 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ 1513 1514 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ 1515 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ 1516 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ 1517 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 1518 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ 1519 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ 1520 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ 1521 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ 1522 1523 #if (__MPU_PRESENT == 1U) 1524 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ 1525 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ 1526 #endif 1527 1528 #if (__FPU_PRESENT == 1U) 1529 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ 1530 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ 1531 #endif 1532 1533 /*@} */ 1534 1535 1536 1537 /******************************************************************************* 1538 * Hardware Abstraction Layer 1539 Core Function Interface contains: 1540 - Core NVIC Functions 1541 - Core SysTick Functions 1542 - Core Debug Functions 1543 - Core Register Access Functions 1544 ******************************************************************************/ 1545 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 1546 */ 1547 1548 1549 1550 /* ########################## NVIC functions #################################### */ 1551 /** \ingroup CMSIS_Core_FunctionInterface 1552 \defgroup CMSIS_Core_NVICFunctions NVIC Functions 1553 \brief Functions that manage interrupts and exceptions via the NVIC. 1554 @{ 1555 */ 1556 1557 /** \brief Set Priority Grouping 1558 1559 The function sets the priority grouping field using the required unlock sequence. 1560 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. 1561 Only values from 0..7 are used. 1562 In case of a conflict between priority grouping and available 1563 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 1564 1565 \param [in] PriorityGroup Priority grouping field. 1566 */ 1567 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) 1568 { 1569 uint32_t reg_value; 1570 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 1571 1572 reg_value = SCB->AIRCR; /* read old register configuration */ 1573 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 1574 reg_value = (reg_value | 1575 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 1576 (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ 1577 SCB->AIRCR = reg_value; 1578 } 1579 1580 1581 /** \brief Get Priority Grouping 1582 1583 The function reads the priority grouping field from the NVIC Interrupt Controller. 1584 1585 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). 1586 */ 1587 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) 1588 { 1589 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 1590 } 1591 1592 1593 /** \brief Enable External Interrupt 1594 1595 The function enables a device-specific interrupt in the NVIC interrupt controller. 1596 1597 \param [in] IRQn External interrupt number. Value cannot be negative. 1598 */ 1599 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) 1600 { 1601 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); 1602 } 1603 1604 1605 /** \brief Disable External Interrupt 1606 1607 The function disables a device-specific interrupt in the NVIC interrupt controller. 1608 1609 \param [in] IRQn External interrupt number. Value cannot be negative. 1610 */ 1611 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) 1612 { 1613 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); 1614 } 1615 1616 1617 /** \brief Get Pending Interrupt 1618 1619 The function reads the pending register in the NVIC and returns the pending bit 1620 for the specified interrupt. 1621 1622 \param [in] IRQn Interrupt number. 1623 1624 \return 0 Interrupt status is not pending. 1625 \return 1 Interrupt status is pending. 1626 */ 1627 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) 1628 { 1629 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 1630 } 1631 1632 1633 /** \brief Set Pending Interrupt 1634 1635 The function sets the pending bit of an external interrupt. 1636 1637 \param [in] IRQn Interrupt number. Value cannot be negative. 1638 */ 1639 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) 1640 { 1641 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); 1642 } 1643 1644 1645 /** \brief Clear Pending Interrupt 1646 1647 The function clears the pending bit of an external interrupt. 1648 1649 \param [in] IRQn External interrupt number. Value cannot be negative. 1650 */ 1651 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) 1652 { 1653 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); 1654 } 1655 1656 1657 /** \brief Get Active Interrupt 1658 1659 The function reads the active register in NVIC and returns the active bit. 1660 1661 \param [in] IRQn Interrupt number. 1662 1663 \return 0 Interrupt status is not active. 1664 \return 1 Interrupt status is active. 1665 */ 1666 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) 1667 { 1668 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 1669 } 1670 1671 1672 /** \brief Set Interrupt Priority 1673 1674 The function sets the priority of an interrupt. 1675 1676 \note The priority cannot be set for every core interrupt. 1677 1678 \param [in] IRQn Interrupt number. 1679 \param [in] priority Priority to set. 1680 */ 1681 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 1682 { 1683 if ((int32_t)(IRQn) < 0) 1684 { 1685 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 1686 } 1687 else 1688 { 1689 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 1690 } 1691 } 1692 1693 1694 /** \brief Get Interrupt Priority 1695 1696 The function reads the priority of an interrupt. The interrupt 1697 number can be positive to specify an external (device specific) 1698 interrupt, or negative to specify an internal (core) interrupt. 1699 1700 1701 \param [in] IRQn Interrupt number. 1702 \return Interrupt Priority. Value is aligned automatically to the implemented 1703 priority bits of the microcontroller. 1704 */ 1705 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) 1706 { 1707 1708 if ((int32_t)(IRQn) < 0) 1709 { 1710 return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); 1711 } 1712 else 1713 { 1714 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); 1715 } 1716 } 1717 1718 1719 /** \brief Encode Priority 1720 1721 The function encodes the priority for an interrupt with the given priority group, 1722 preemptive priority value, and subpriority value. 1723 In case of a conflict between priority grouping and available 1724 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 1725 1726 \param [in] PriorityGroup Used priority group. 1727 \param [in] PreemptPriority Preemptive priority value (starting from 0). 1728 \param [in] SubPriority Subpriority value (starting from 0). 1729 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). 1730 */ 1731 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) 1732 { 1733 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 1734 uint32_t PreemptPriorityBits; 1735 uint32_t SubPriorityBits; 1736 1737 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 1738 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 1739 1740 return ( 1741 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 1742 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 1743 ); 1744 } 1745 1746 1747 /** \brief Decode Priority 1748 1749 The function decodes an interrupt priority value with a given priority group to 1750 preemptive priority value and subpriority value. 1751 In case of a conflict between priority grouping and available 1752 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. 1753 1754 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). 1755 \param [in] PriorityGroup Used priority group. 1756 \param [out] pPreemptPriority Preemptive priority value (starting from 0). 1757 \param [out] pSubPriority Subpriority value (starting from 0). 1758 */ 1759 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) 1760 { 1761 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 1762 uint32_t PreemptPriorityBits; 1763 uint32_t SubPriorityBits; 1764 1765 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 1766 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 1767 1768 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); 1769 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); 1770 } 1771 1772 1773 /** \brief System Reset 1774 1775 The function initiates a system reset request to reset the MCU. 1776 */ 1777 __STATIC_INLINE void NVIC_SystemReset(void) 1778 { 1779 __DSB(); /* Ensure all outstanding memory accesses included 1780 buffered write are completed before reset */ 1781 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 1782 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 1783 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ 1784 __DSB(); /* Ensure completion of memory access */ 1785 1786 for(;;) /* wait until reset */ 1787 { 1788 __NOP(); 1789 } 1790 } 1791 1792 /*@} end of CMSIS_Core_NVICFunctions */ 1793 1794 1795 1796 /* ################################## SysTick function ############################################ */ 1797 /** \ingroup CMSIS_Core_FunctionInterface 1798 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 1799 \brief Functions that configure the System. 1800 @{ 1801 */ 1802 1803 #if (__Vendor_SysTickConfig == 0U) 1804 1805 /** \brief System Tick Configuration 1806 1807 The function initializes the System Timer and its interrupt, and starts the System Tick Timer. 1808 Counter is in free running mode to generate periodic interrupts. 1809 1810 \param [in] ticks Number of ticks between two interrupts. 1811 1812 \return 0 Function succeeded. 1813 \return 1 Function failed. 1814 1815 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 1816 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 1817 must contain a vendor-specific implementation of this function. 1818 1819 */ 1820 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 1821 { 1822 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 1823 { 1824 return (1UL); /* Reload value impossible */ 1825 } 1826 1827 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 1828 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 1829 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 1830 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 1831 SysTick_CTRL_TICKINT_Msk | 1832 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 1833 return (0UL); /* Function successful */ 1834 } 1835 1836 #endif 1837 1838 /*@} end of CMSIS_Core_SysTickFunctions */ 1839 1840 1841 1842 /* ##################################### Debug In/Output function ########################################### */ 1843 /** \ingroup CMSIS_Core_FunctionInterface 1844 \defgroup CMSIS_core_DebugFunctions ITM Functions 1845 \brief Functions that access the ITM debug interface. 1846 @{ 1847 */ 1848 1849 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ 1850 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ 1851 1852 1853 /** \brief ITM Send Character 1854 1855 The function transmits a character via the ITM channel 0, and 1856 \li Just returns when no debugger is connected that has booked the output. 1857 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. 1858 1859 \param [in] ch Character to transmit. 1860 1861 \returns Character to transmit. 1862 */ 1863 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) 1864 { 1865 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ 1866 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ 1867 { 1868 while (ITM->PORT[0U].u32 == 0UL) 1869 { 1870 __NOP(); 1871 } 1872 ITM->PORT[0U].u8 = (uint8_t)ch; 1873 } 1874 return (ch); 1875 } 1876 1877 1878 /** \brief ITM Receive Character 1879 1880 The function inputs a character via the external variable \ref ITM_RxBuffer. 1881 1882 \return Received character. 1883 \return -1 No character pending. 1884 */ 1885 __STATIC_INLINE int32_t ITM_ReceiveChar (void) 1886 { 1887 int32_t ch = -1; /* no character available */ 1888 1889 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) 1890 { 1891 ch = ITM_RxBuffer; 1892 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ 1893 } 1894 1895 return (ch); 1896 } 1897 1898 1899 /** \brief ITM Check Character 1900 1901 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. 1902 1903 \return 0 No character available. 1904 \return 1 Character available. 1905 */ 1906 __STATIC_INLINE int32_t ITM_CheckChar (void) { 1907 1908 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) 1909 { 1910 return (0); /* no character available */ 1911 } 1912 else 1913 { 1914 return (1); /* character available */ 1915 } 1916 } 1917 1918 /*@} end of CMSIS_core_DebugFunctions */ 1919 1920 1921 1922 1923 #ifdef __cplusplus 1924 } 1925 #endif 1926 1927 #endif /* __CORE_CM4_H_DEPENDANT */ 1928 1929 #endif /* __CMSIS_GENERIC */ 1930