xref: /btstack/port/esp32/components/btstack/es8388.h (revision d58a1b5f11ada8ddf896c41fff5a35e7f140c37e)
1 #ifndef ES8388_H
2 
3 #define ES8388_H
4 
5 #include "esp_types.h"
6 #include "driver/i2c.h"
7 
8 /* ES8388 address */
9 #define ES8388_ADDR 0x20  // 0x22:CE=1;0x20:CE=0
10 
11 /* ES8388 register */
12 #define ES8388_CONTROL1         0x00
13 #define ES8388_CONTROL2         0x01
14 
15 #define ES8388_CHIPPOWER        0x02
16 
17 #define ES8388_ADCPOWER         0x03
18 #define ES8388_DACPOWER         0x04
19 
20 #define ES8388_CHIPLOPOW1       0x05
21 #define ES8388_CHIPLOPOW2       0x06
22 
23 #define ES8388_ANAVOLMANAG      0x07
24 
25 #define ES8388_MASTERMODE       0x08
26 /* ADC */
27 #define ES8388_ADCCONTROL1      0x09
28 #define ES8388_ADCCONTROL2      0x0a
29 #define ES8388_ADCCONTROL3      0x0b
30 #define ES8388_ADCCONTROL4      0x0c
31 #define ES8388_ADCCONTROL5      0x0d
32 #define ES8388_ADCCONTROL6      0x0e
33 #define ES8388_ADCCONTROL7      0x0f
34 #define ES8388_ADCCONTROL8      0x10
35 #define ES8388_ADCCONTROL9      0x11
36 #define ES8388_ADCCONTROL10     0x12
37 #define ES8388_ADCCONTROL11     0x13
38 #define ES8388_ADCCONTROL12     0x14
39 #define ES8388_ADCCONTROL13     0x15
40 #define ES8388_ADCCONTROL14     0x16
41 /* DAC */
42 #define ES8388_DACCONTROL1      0x17
43 #define ES8388_DACCONTROL2      0x18
44 #define ES8388_DACCONTROL3      0x19
45 #define ES8388_DACCONTROL4      0x1a
46 #define ES8388_DACCONTROL5      0x1b
47 #define ES8388_DACCONTROL6      0x1c
48 #define ES8388_DACCONTROL7      0x1d
49 #define ES8388_DACCONTROL8      0x1e
50 #define ES8388_DACCONTROL9      0x1f
51 #define ES8388_DACCONTROL10     0x20
52 #define ES8388_DACCONTROL11     0x21
53 #define ES8388_DACCONTROL12     0x22
54 #define ES8388_DACCONTROL13     0x23
55 #define ES8388_DACCONTROL14     0x24
56 #define ES8388_DACCONTROL15     0x25
57 #define ES8388_DACCONTROL16     0x26
58 #define ES8388_DACCONTROL17     0x27
59 #define ES8388_DACCONTROL18     0x28
60 #define ES8388_DACCONTROL19     0x29
61 #define ES8388_DACCONTROL20     0x2a
62 #define ES8388_DACCONTROL21     0x2b
63 #define ES8388_DACCONTROL22     0x2c
64 #define ES8388_DACCONTROL23     0x2d
65 #define ES8388_DACCONTROL24     0x2e
66 #define ES8388_DACCONTROL25     0x2f
67 #define ES8388_DACCONTROL26     0x30
68 #define ES8388_DACCONTROL27     0x31
69 #define ES8388_DACCONTROL28     0x32
70 #define ES8388_DACCONTROL29     0x33
71 #define ES8388_DACCONTROL30     0x34
72 
73 typedef enum {
74     ES_MODULE_MIN = -1,
75     ES_MODULE_ADC = 0x01,
76     ES_MODULE_DAC = 0x02,
77     ES_MODULE_ADC_DAC = 0x03,
78     ES_MODULE_LINE = 0x04,
79     ES_MODULE_MAX
80 } es_codec_module_t;
81 
82 typedef enum {
83     ES_ = -1,
84     ES_I2S_NORMAL = 0,
85     ES_I2S_LEFT = 1,
86     ES_I2S_RIGHT = 2,
87     ES_I2S_DSP = 3,
88     ES_I2S_MAX
89 } es_codec_i2s_fmt_t;
90 
91 typedef enum {
92     MclkDiv_MIN = -1,
93     MclkDiv_1 = 1,
94     MclkDiv_2 = 2,
95     MclkDiv_3 = 3,
96     MclkDiv_4 = 4,
97     MclkDiv_6 = 5,
98     MclkDiv_8 = 6,
99     MclkDiv_9 = 7,
100     MclkDiv_11 = 8,
101     MclkDiv_12 = 9,
102     MclkDiv_16 = 10,
103     MclkDiv_18 = 11,
104     MclkDiv_22 = 12,
105     MclkDiv_24 = 13,
106     MclkDiv_33 = 14,
107     MclkDiv_36 = 15,
108     MclkDiv_44 = 16,
109     MclkDiv_48 = 17,
110     MclkDiv_66 = 18,
111     MclkDiv_72 = 19,
112     MclkDiv_5 = 20,
113     MclkDiv_10 = 21,
114     MclkDiv_15 = 22,
115     MclkDiv_17 = 23,
116     MclkDiv_20 = 24,
117     MclkDiv_25 = 25,
118     MclkDiv_30 = 26,
119     MclkDiv_32 = 27,
120     MclkDiv_34 = 28,
121     MclkDiv_7  = 29,
122     MclkDiv_13 = 30,
123     MclkDiv_14 = 31,
124     MclkDiv_MAX,
125 } sclk_div_t;
126 
127 typedef enum {
128     LclkDiv_MIN = -1,
129     LclkDiv_128 = 0,
130     LclkDiv_192 = 1,
131     LclkDiv_256 = 2,
132     LclkDiv_384 = 3,
133     LclkDiv_512 = 4,
134     LclkDiv_576 = 5,
135     LclkDiv_768 = 6,
136     LclkDiv_1024 = 7,
137     LclkDiv_1152 = 8,
138     LclkDiv_1408 = 9,
139     LclkDiv_1536 = 10,
140     LclkDiv_2112 = 11,
141     LclkDiv_2304 = 12,
142 
143     LclkDiv_125 = 16,
144     LclkDiv_136 = 17,
145     LclkDiv_250 = 18,
146     LclkDiv_272 = 19,
147     LclkDiv_375 = 20,
148     LclkDiv_500 = 21,
149     LclkDiv_544 = 22,
150     LclkDiv_750 = 23,
151     LclkDiv_1000 = 24,
152     LclkDiv_1088 = 25,
153     LclkDiv_1496 = 26,
154     LclkDiv_1500 = 27,
155     LclkDiv_MAX,
156 } lclk_div_t;
157 
158 
159 typedef struct {
160     sclk_div_t sclk_div;
161     lclk_div_t lclk_div;
162 } es_codec_i2s_clock_t;
163 
164 typedef enum {
165     BIT_LENGTH_MIN = -1,
166     BIT_LENGTH_16BITS = 0x03,
167     BIT_LENGTH_18BITS = 0x02,
168     BIT_LENGTH_20BITS = 0x01,
169     BIT_LENGTH_24BITS = 0x00,
170     BIT_LENGTH_32BITS = 0x04,
171     BIT_LENGTH_MAX,
172 } es_codec_bits_len_t;
173 
174 typedef enum {
175     MIC_GAIN_MIN = -1,
176     MIC_GAIN_0DB = 0,
177     MIC_GAIN_3DB = 3,
178     MIC_GAIN_6DB = 6,
179     MIC_GAIN_9DB = 9,
180     MIC_GAIN_12DB = 12,
181     MIC_GAIN_15DB = 15,
182     MIC_GAIN_18DB = 18,
183     MIC_GAIN_21DB = 21,
184     MIC_GAIN_24DB = 24,
185     MIC_GAIN_MAX,
186 } es_codec_mic_gain_t;
187 
188 
189 
190 typedef enum {
191     DAC_OUTPUT_MIN = -1,
192     DAC_OUTPUT_LOUT1 = 0x04,
193     DAC_OUTPUT_LOUT2 = 0x08,
194     DAC_OUTPUT_SPK   = 0x09,
195     DAC_OUTPUT_ROUT1 = 0x10,
196     DAC_OUTPUT_ROUT2 = 0x20,
197     DAC_OUTPUT_ALL = 0x3c,
198     DAC_OUTPUT_MAX,
199 } es_codec_dac_output_t;
200 
201 typedef enum {
202     ADC_INPUT_MIN = -1,
203     ADC_INPUT_LINPUT1_RINPUT1 = 0x00,
204     ADC_INPUT_MIC1	= 0x05,
205     ADC_INPUT_MIC2	= 0x06,
206     ADC_INPUT_LINPUT2_RINPUT2 = 0x50,
207     ADC_INPUT_DIFFERENCE = 0xf0,
208     ADC_INPUT_MAX,
209 } es_codec_adc_input_t;
210 
211 
212 typedef enum {
213     ES_MODE_MIN = -1,
214     ES_MODE_SLAVE = 0x00,
215     ES_MODE_MASTER = 0x01,
216     ES_MODE_MAX,
217 } es_codec_mode_t;
218 
219 typedef struct {
220     es_codec_mode_t es_mode;
221     i2c_port_t i2c_port_num;
222     i2c_config_t i2c_cfg;
223     es_codec_dac_output_t dac_output;
224     es_codec_adc_input_t adc_input;
225 } es8388_config_t;
226 
227 
228 #define AUDIO_CODEC_ES8388_DEFAULT(){ \
229     .es_mode = ES_MODE_SLAVE, \
230     .i2c_port_num = I2C_NUM_0, \
231     .i2c_cfg = { \
232         .mode = I2C_MODE_MASTER, \
233         .sda_io_num = IIC_DATA, \
234         .scl_io_num = IIC_CLK, \
235         .sda_pullup_en = GPIO_PULLUP_ENABLE,\
236         .scl_pullup_en = GPIO_PULLUP_ENABLE,\
237         .master.clk_speed = 100000\
238     }, \
239     .adc_input= ADC_INPUT_LINPUT1_RINPUT1,\
240     .dac_output = DAC_OUTPUT_LOUT1 | DAC_OUTPUT_LOUT2 | DAC_OUTPUT_ROUT1 | DAC_OUTPUT_ROUT2,\
241 };
242 
243 int es8388_init(es8388_config_t *cfg);
244 void es8388_uninit();
245 
246 int es8388_config_fmt(es_codec_module_t mode, es_codec_i2s_fmt_t fmt);
247 
248 int es8388_i2s_config_clock(es_codec_i2s_clock_t cfg);
249 int es8388_set_bits_per_sample(es_codec_module_t mode, es_codec_bits_len_t bits);
250 
251 int es8388_start(es_codec_module_t mode);
252 int es8388_stop(es_codec_module_t mode);
253 
254 int es8388_set_volume(int volume);
255 int es8388_get_volume(int *volume);
256 
257 int es8388_set_mute(int enable);
258 int es8388_get_mute(int *enable);
259 int es8388_set_mic_gain(es_codec_mic_gain_t gain);
260 
261 int es8388_set_adc_input(es_codec_adc_input_t input);
262 int es8388_set_dac_ouput(es_codec_dac_output_t output);
263 void es8388_pa_power(bool enable);
264 
265 
266 #endif
267