1 /* 2 * Copyright (C) 2018 BlueKitchen GmbH 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. Neither the name of the copyright holders nor the names of 14 * contributors may be used to endorse or promote products derived 15 * from this software without specific prior written permission. 16 * 4. Any redistribution, use, or modification is done solely for 17 * personal benefit and not for any commercial purpose or for 18 * monetary gain. 19 * 20 * THIS SOFTWARE IS PROVIDED BY BLUEKITCHEN GMBH AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 23 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL BLUEKITCHEN 24 * GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 26 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 27 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 28 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 29 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 30 * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * Please inquire about commercial licensing options at 34 * [email protected] 35 * 36 */ 37 38 #define BTSTACK_FILE__ "btstack_chipset_intel_firmware.c" 39 40 #include <fcntl.h> 41 #include <unistd.h> 42 #include <stdio.h> 43 44 #include "btstack_chipset_intel_firmware.h" 45 46 #include "bluetooth.h" 47 #include "btstack_debug.h" 48 #include "btstack_event.h" 49 #include "btstack_run_loop.h" 50 #include "btstack_util.h" 51 #include "hci.h" 52 #include "hci_cmd.h" 53 #include "hci_dump.h" 54 55 // assert outgoing and incoming hci packet buffers can hold max hci command resp. event packet 56 #if HCI_OUTGOING_PACKET_BUFFER_SIZE < (HCI_CMD_HEADER_SIZE + 255) 57 #error "HCI_OUTGOING_PACKET_BUFFER_SIZE to small. Outgoing HCI packet buffer to small for largest HCI Command packet. Please set HCI_ACL_PAYLOAD_SIZE to 258 or higher." 58 #endif 59 #if HCI_INCOMING_PACKET_BUFFER_SIZE < (HCI_EVENT_HEADER_SIZE_HEADER_SIZE + 255) 60 #error "HCI_INCOMING_PACKET_BUFFER_SIZE to small. Incoming HCI packet buffer to small for largest HCI Event packet. Please set HCI_ACL_PAYLOAD_SIZE to 257 or higher." 61 #endif 62 63 // Vendor specific structs 64 65 typedef struct { 66 uint8_t status; 67 uint8_t hw_platform; 68 uint8_t hw_variant; 69 uint8_t hw_revision; 70 uint8_t fw_variant; 71 uint8_t fw_revision; 72 uint8_t fw_build_num; 73 uint8_t fw_build_ww; 74 uint8_t fw_build_yy; 75 uint8_t fw_patch_num; 76 } intel_version_t; 77 78 typedef struct { 79 uint8_t status; 80 uint8_t otp_format; 81 uint8_t otp_content; 82 uint8_t otp_patch; 83 uint16_t dev_revid; 84 uint8_t secure_boot; 85 uint8_t key_from_hdr; 86 uint8_t key_type; 87 uint8_t otp_lock; 88 uint8_t api_lock; 89 uint8_t debug_lock; 90 bd_addr_t otp_bdaddr; 91 uint8_t min_fw_build_nn; 92 uint8_t min_fw_build_cw; 93 uint8_t min_fw_build_yy; 94 uint8_t limited_cce; 95 uint8_t unlocked_state; 96 } intel_boot_params_t; 97 98 // Vendor sepcific commands 99 100 static const hci_cmd_t hci_intel_read_version = { 101 0xfc05, "" 102 }; 103 static const hci_cmd_t hci_intel_read_secure_boot_params = { 104 0xfc0d, "" 105 }; 106 107 static const hci_cmd_t hci_intel_reset_param = { 108 0xfc01, "11111111" 109 }; 110 111 static const hci_cmd_t hci_intel_set_event_mask = { 112 0xfc52, "11111111" 113 }; 114 115 static const hci_cmd_t hci_intel_fc9f = { 116 0xfc9f, "1" 117 }; 118 119 // state 120 121 const char * firmware_path = "."; 122 123 const hci_transport_t * transport; 124 125 static int state = 0; 126 127 static uint8_t hci_outgoing[300]; 128 static uint8_t fw_buffer[300]; 129 130 static uint8_t hw_variant; 131 static uint16_t dev_revid; 132 133 static FILE * fw_file; 134 static uint32_t fw_offset; 135 136 static void (*done)(int result); 137 138 // functions 139 140 static int transport_send_packet(uint8_t packet_type, const uint8_t * packet, uint16_t size){ 141 hci_dump_packet(HCI_COMMAND_DATA_PACKET, 0, (uint8_t*) packet, size); 142 return transport->send_packet(packet_type, (uint8_t *) packet, size); 143 } 144 145 static int transport_send_cmd_va_arg(const hci_cmd_t *cmd, va_list argptr){ 146 uint8_t * packet = hci_outgoing; 147 uint16_t size = hci_cmd_create_from_template(packet, cmd, argptr); 148 return transport_send_packet(HCI_COMMAND_DATA_PACKET, packet, size); 149 } 150 151 static int transport_send_cmd(const hci_cmd_t *cmd, ...){ 152 va_list argptr; 153 va_start(argptr, cmd); 154 int res = transport_send_cmd_va_arg(cmd, argptr); 155 va_end(argptr); 156 return res; 157 } 158 159 static int transport_send_intel_secure(uint8_t fragment_type, const uint8_t * data, uint16_t len){ 160 little_endian_store_16(hci_outgoing, 0, 0xfc09); 161 hci_outgoing[2] = 1 + len; 162 hci_outgoing[3] = fragment_type; 163 memcpy(&hci_outgoing[4], data, len); 164 uint16_t size = 3 + 1 + len; 165 return transport_send_packet(HCI_ACL_DATA_PACKET, hci_outgoing, size); 166 } 167 168 static int transport_send_intel_ddc(const uint8_t * data, uint16_t len){ 169 little_endian_store_16(hci_outgoing, 0, 0xfc8b); 170 hci_outgoing[2] = len; 171 memcpy(&hci_outgoing[3], data, len); 172 uint16_t size = 3 + len; 173 return transport_send_packet(HCI_COMMAND_DATA_PACKET, hci_outgoing, size); 174 } 175 176 static void state_machine(uint8_t * packet); 177 178 // read data from fw file and send it via intel_secure + update state 179 static int intel_send_fragment(uint8_t fragment_type, uint16_t len){ 180 int res = fread(fw_buffer, 1, len, fw_file); 181 log_info("offset %6u, read %3u -> res %d", fw_offset, len, res); 182 fw_offset += res; 183 state++; 184 return transport_send_intel_secure(fragment_type, fw_buffer, len); 185 } 186 187 // read data from ddc file and send iva intel ddc command 188 // @returns -1 on eof 189 static int intel_send_ddc(void){ 190 int res; 191 // read len 192 res = fread(fw_buffer, 1, 1, fw_file); 193 log_info("offset %6u, read 1 -> res %d", fw_offset, res); 194 if (res == 0) return -1; 195 uint8_t len = fw_buffer[0]; 196 fw_offset += 1; 197 res = fread(&fw_buffer[1], 1, len, fw_file); 198 log_info("offset %6u, read %u -> res %d", fw_offset, 1, res); 199 return transport_send_intel_ddc(fw_buffer, 1 + len); 200 } 201 202 static void dump_intel_version(intel_version_t * version){ 203 log_info("status 0x%02x", version->status); 204 log_info("hw_platform 0x%02x", version->hw_platform); 205 log_info("hw_variant 0x%02x", version->hw_variant); 206 log_info("hw_revision 0x%02x", version->hw_revision); 207 log_info("fw_variant 0x%02x", version->fw_variant); 208 log_info("fw_revision 0x%02x", version->fw_revision); 209 log_info("fw_build_num 0x%02x", version->fw_build_num); 210 log_info("fw_build_ww 0x%02x", version->fw_build_ww); 211 log_info("fw_build_yy 0x%02x", version->fw_build_yy); 212 log_info("fw_patch_num 0x%02x", version->fw_patch_num); 213 } 214 215 static void dump_intel_boot_params(intel_boot_params_t * boot_params){ 216 bd_addr_t addr; 217 reverse_bd_addr(boot_params->otp_bdaddr, addr); 218 log_info("Device revision: %u", dev_revid); 219 log_info("Secure Boot: %s", boot_params->secure_boot ? "enabled" : "disabled"); 220 log_info("OTP lock: %s", boot_params->otp_lock ? "enabled" : "disabled"); 221 log_info("API lock: %s", boot_params->api_lock ? "enabled" : "disabled"); 222 log_info("Debug lock: %s", boot_params->debug_lock ? "enabled" : "disabled"); 223 log_info("Minimum firmware build %u week %u %u", boot_params->min_fw_build_nn, boot_params->min_fw_build_cw, 2000 + boot_params->min_fw_build_yy); 224 log_info("OTC BD_ADDR: %s", bd_addr_to_str(addr)); 225 } 226 227 static int vendor_firmware_complete_received; 228 static int waiting_for_command_complete; 229 230 static void state_machine(uint8_t * packet){ 231 intel_version_t * version; 232 intel_boot_params_t * boot_params; 233 int res; 234 uint16_t buffer_offset; 235 bd_addr_t addr; 236 char fw_path[300]; 237 238 if (packet){ 239 // firmware upload complete event? 240 if (packet[0] == 0xff && packet[2] == 0x06) { 241 vendor_firmware_complete_received = 1; 242 } 243 244 // command complete 245 if (packet[0] == 0x0e){ 246 waiting_for_command_complete = 0; 247 } 248 } 249 250 switch (state){ 251 case 0: 252 state++; 253 transport_send_cmd(&hci_reset); 254 break; 255 case 1: 256 // check if HCI Reset was supported 257 if (packet[0] == 0x0e && packet[1] == 0x04 && packet[3] == 0x03 && packet[4] == 0x0c && packet[5] == 0x00){ 258 log_info("HCI Reset was successful, no need for firmware upload / or not an Intel chipset"); 259 (*done)(0); 260 break; 261 } 262 263 // Read Intel Version 264 state++; 265 transport_send_cmd(&hci_intel_read_version); 266 break; 267 case 2: 268 version = (intel_version_t*) hci_event_command_complete_get_return_parameters(packet); 269 dump_intel_version(version); 270 271 hw_variant = version->hw_variant; 272 273 // fw_variant = 0x06 bootloader mode / 0x23 operational mode 274 if (version->fw_variant == 0x23) { 275 (*done)(0); 276 break; 277 } 278 279 if (version->fw_variant != 0x06){ 280 log_error("unknown fw_variant 0x%02x", version->fw_variant); 281 break; 282 } 283 284 // Read Intel Secure Boot Params 285 state++; 286 transport_send_cmd(&hci_intel_read_secure_boot_params); 287 break; 288 case 3: 289 boot_params = (intel_boot_params_t *) hci_event_command_complete_get_return_parameters(packet); 290 dump_intel_boot_params(boot_params); 291 292 reverse_bd_addr(boot_params->otp_bdaddr, addr); 293 dev_revid = little_endian_read_16((uint8_t*)&boot_params->dev_revid, 0); 294 295 // assert commmand complete is required 296 if (boot_params->limited_cce != 0) break; 297 298 // firmware file 299 snprintf(fw_path, sizeof(fw_path), "%s/ibt-%u-%u.sfi", firmware_path, hw_variant, dev_revid); 300 log_info("Open firmware %s", fw_path); 301 printf("Firwmare %s\n", fw_path); 302 303 // open firmware file 304 fw_offset = 0; 305 fw_file = fopen(fw_path, "rb"); 306 if (!fw_file){ 307 log_error("can't open file %s", fw_path); 308 (*done)(1); 309 return; 310 } 311 312 vendor_firmware_complete_received = 0; 313 314 // send CCS segment - offset 0 315 intel_send_fragment(0x00, 128); 316 break; 317 case 4: 318 // send public key / part 1 - offset 128 319 intel_send_fragment(0x03, 128); 320 break; 321 case 5: 322 // send public key / part 2 - offset 384 323 intel_send_fragment(0x03, 128); 324 break; 325 case 6: 326 // skip 4 bytes 327 res = fread(fw_buffer, 1, 4, fw_file); 328 log_info("read res %d", res); 329 fw_offset += res; 330 331 // send signature / part 1 - offset 388 332 intel_send_fragment(0x02, 128); 333 break; 334 case 7: 335 // send signature / part 2 - offset 516 336 intel_send_fragment(0x02, 128); 337 break; 338 case 8: 339 // send firmware chunks - offset 644 340 // chunk len must be 4 byte aligned 341 // multiple commands can be combined 342 buffer_offset = 0; 343 do { 344 res = fread(&fw_buffer[buffer_offset], 1, 3, fw_file); 345 log_info("fw_offset %6u, buffer_offset %u, read %3u -> res %d", fw_offset, buffer_offset, 3, res); 346 fw_offset += res; 347 if (res == 0 ){ 348 // EOF 349 log_info("End of file"); 350 fclose(fw_file); 351 fw_file = NULL; 352 state++; 353 break; 354 } 355 int param_len = fw_buffer[buffer_offset + 2]; 356 buffer_offset += 3; 357 if (param_len){ 358 res = fread(&fw_buffer[buffer_offset], 1, param_len, fw_file); 359 fw_offset += res; 360 buffer_offset += res; 361 } 362 } while ((buffer_offset & 3) != 0); 363 364 if (buffer_offset == 0) break; 365 366 waiting_for_command_complete = 1; 367 transport_send_intel_secure(0x01, fw_buffer, buffer_offset); 368 break; 369 370 case 9: 371 // expect Vendor Specific Event 0x06 372 if (!vendor_firmware_complete_received) break; 373 374 printf("Firmware upload complete\n"); 375 log_info("Vendor Event 0x06 - firmware complete"); 376 377 // Reset Params - constants from Windows Intel driver 378 state++; 379 transport_send_cmd(&hci_intel_reset_param, 0x00, 0x00, 0x00, 0x01, 0x00, 0x08, 0x04, 0x00); 380 break; 381 382 case 10: 383 // expect Vendor Specific Event 0x02 384 if (packet[0] != 0xff) break; 385 if (packet[2] != 0x02) break; 386 387 printf("Firmware operational\n"); 388 log_info("Vendor Event 0x02 - firmware operational"); 389 390 // Read Intel Version 391 state++; 392 transport_send_cmd(&hci_intel_read_version); 393 break; 394 395 case 11: 396 version = (intel_version_t*) hci_event_command_complete_get_return_parameters(packet); 397 dump_intel_version(version); 398 399 // ddc config 400 snprintf(fw_path, sizeof(fw_path), "%s/ibt-%u-%u.ddc", firmware_path, hw_variant, dev_revid); 401 log_info("Open DDC %s", fw_path); 402 403 // open ddc file 404 fw_offset = 0; 405 fw_file = fopen(fw_path, "rb"); 406 if (!fw_file){ 407 log_error("can't open file %s", fw_path); 408 409 (*done)(1); 410 return; 411 } 412 413 // load ddc 414 state++; 415 416 /* fall through */ 417 418 case 12: 419 res = intel_send_ddc(); 420 if (res == 0) break; 421 422 // DDC download complete 423 state++; 424 log_info("Load DDC Complete"); 425 426 427 // Set Intel event mask 0xfc52 428 state++; 429 transport_send_cmd(&hci_intel_set_event_mask, 0x87, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); 430 break; 431 432 case 13: 433 // 9F FC 01 00 434 state++; 435 transport_send_cmd(&hci_intel_fc9f, 0x00); 436 break; 437 438 case 14: 439 (*done)(0); 440 break; 441 442 default: 443 break; 444 } 445 } 446 447 static void transport_packet_handler (uint8_t packet_type, uint8_t *packet, uint16_t size){ 448 UNUSED(packet_type); 449 // we also get events with packet_type ACL from the controller 450 hci_dump_packet(HCI_EVENT_PACKET, 1, packet, size); 451 switch (hci_event_packet_get_type(packet)){ 452 case HCI_EVENT_COMMAND_COMPLETE: 453 case HCI_EVENT_VENDOR_SPECIFIC: 454 state_machine(packet); 455 break; 456 default: 457 break; 458 } 459 } 460 461 void btstack_chipset_intel_set_firmware_path(const char * path){ 462 firmware_path = path; 463 } 464 465 void btstack_chipset_intel_download_firmware(const hci_transport_t * hci_transport, void (*callback)(int result)){ 466 467 done = callback; 468 469 transport = hci_transport;; 470 // transport->init(NULL); 471 transport->register_packet_handler(&transport_packet_handler); 472 transport->open(); 473 474 // get started 475 state = 0; 476 state_machine(NULL); 477 } 478