xref: /aosp_15_r20/external/vixl/test/aarch32/traces/assembler-cond-rdlow-rnlow-operand-immediate-zero-rsbs-t32.h (revision f5c631da2f1efdd72b5fd1e20510e4042af13d77)

// Copyright 2015, VIXL authors
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
//   * Redistributions of source code must retain the above copyright notice,
//     this list of conditions and the following disclaimer.
//   * Redistributions in binary form must reproduce the above copyright notice,
//     this list of conditions and the following disclaimer in the documentation
//     and/or other materials provided with the distribution.
//   * Neither the name of ARM Limited nor the names of its contributors may be
//     used to endorse or promote products derived from this software without
//     specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.


// ---------------------------------------------------------------------
// This file is auto generated using tools/generate_simulator_traces.py.
//
// PLEASE DO NOT EDIT.
// ---------------------------------------------------------------------

#ifndef VIXL_ASSEMBLER_COND_RDLOW_RNLOW_OPERAND_IMMEDIATE_ZERO_RSBS_T32_H_
#define VIXL_ASSEMBLER_COND_RDLOW_RNLOW_OPERAND_IMMEDIATE_ZERO_RSBS_T32_H_

const byte kInstruction_rsbs_al_r0_r0_0[] = {
  0x40, 0x42 // rsbs al r0 r0 0
};
const byte kInstruction_rsbs_al_r0_r1_0[] = {
  0x48, 0x42 // rsbs al r0 r1 0
};
const byte kInstruction_rsbs_al_r0_r2_0[] = {
  0x50, 0x42 // rsbs al r0 r2 0
};
const byte kInstruction_rsbs_al_r0_r3_0[] = {
  0x58, 0x42 // rsbs al r0 r3 0
};
const byte kInstruction_rsbs_al_r0_r4_0[] = {
  0x60, 0x42 // rsbs al r0 r4 0
};
const byte kInstruction_rsbs_al_r0_r5_0[] = {
  0x68, 0x42 // rsbs al r0 r5 0
};
const byte kInstruction_rsbs_al_r0_r6_0[] = {
  0x70, 0x42 // rsbs al r0 r6 0
};
const byte kInstruction_rsbs_al_r0_r7_0[] = {
  0x78, 0x42 // rsbs al r0 r7 0
};
const byte kInstruction_rsbs_al_r1_r0_0[] = {
  0x41, 0x42 // rsbs al r1 r0 0
};
const byte kInstruction_rsbs_al_r1_r1_0[] = {
  0x49, 0x42 // rsbs al r1 r1 0
};
const byte kInstruction_rsbs_al_r1_r2_0[] = {
  0x51, 0x42 // rsbs al r1 r2 0
};
const byte kInstruction_rsbs_al_r1_r3_0[] = {
  0x59, 0x42 // rsbs al r1 r3 0
};
const byte kInstruction_rsbs_al_r1_r4_0[] = {
  0x61, 0x42 // rsbs al r1 r4 0
};
const byte kInstruction_rsbs_al_r1_r5_0[] = {
  0x69, 0x42 // rsbs al r1 r5 0
};
const byte kInstruction_rsbs_al_r1_r6_0[] = {
  0x71, 0x42 // rsbs al r1 r6 0
};
const byte kInstruction_rsbs_al_r1_r7_0[] = {
  0x79, 0x42 // rsbs al r1 r7 0
};
const byte kInstruction_rsbs_al_r2_r0_0[] = {
  0x42, 0x42 // rsbs al r2 r0 0
};
const byte kInstruction_rsbs_al_r2_r1_0[] = {
  0x4a, 0x42 // rsbs al r2 r1 0
};
const byte kInstruction_rsbs_al_r2_r2_0[] = {
  0x52, 0x42 // rsbs al r2 r2 0
};
const byte kInstruction_rsbs_al_r2_r3_0[] = {
  0x5a, 0x42 // rsbs al r2 r3 0
};
const byte kInstruction_rsbs_al_r2_r4_0[] = {
  0x62, 0x42 // rsbs al r2 r4 0
};
const byte kInstruction_rsbs_al_r2_r5_0[] = {
  0x6a, 0x42 // rsbs al r2 r5 0
};
const byte kInstruction_rsbs_al_r2_r6_0[] = {
  0x72, 0x42 // rsbs al r2 r6 0
};
const byte kInstruction_rsbs_al_r2_r7_0[] = {
  0x7a, 0x42 // rsbs al r2 r7 0
};
const byte kInstruction_rsbs_al_r3_r0_0[] = {
  0x43, 0x42 // rsbs al r3 r0 0
};
const byte kInstruction_rsbs_al_r3_r1_0[] = {
  0x4b, 0x42 // rsbs al r3 r1 0
};
const byte kInstruction_rsbs_al_r3_r2_0[] = {
  0x53, 0x42 // rsbs al r3 r2 0
};
const byte kInstruction_rsbs_al_r3_r3_0[] = {
  0x5b, 0x42 // rsbs al r3 r3 0
};
const byte kInstruction_rsbs_al_r3_r4_0[] = {
  0x63, 0x42 // rsbs al r3 r4 0
};
const byte kInstruction_rsbs_al_r3_r5_0[] = {
  0x6b, 0x42 // rsbs al r3 r5 0
};
const byte kInstruction_rsbs_al_r3_r6_0[] = {
  0x73, 0x42 // rsbs al r3 r6 0
};
const byte kInstruction_rsbs_al_r3_r7_0[] = {
  0x7b, 0x42 // rsbs al r3 r7 0
};
const byte kInstruction_rsbs_al_r4_r0_0[] = {
  0x44, 0x42 // rsbs al r4 r0 0
};
const byte kInstruction_rsbs_al_r4_r1_0[] = {
  0x4c, 0x42 // rsbs al r4 r1 0
};
const byte kInstruction_rsbs_al_r4_r2_0[] = {
  0x54, 0x42 // rsbs al r4 r2 0
};
const byte kInstruction_rsbs_al_r4_r3_0[] = {
  0x5c, 0x42 // rsbs al r4 r3 0
};
const byte kInstruction_rsbs_al_r4_r4_0[] = {
  0x64, 0x42 // rsbs al r4 r4 0
};
const byte kInstruction_rsbs_al_r4_r5_0[] = {
  0x6c, 0x42 // rsbs al r4 r5 0
};
const byte kInstruction_rsbs_al_r4_r6_0[] = {
  0x74, 0x42 // rsbs al r4 r6 0
};
const byte kInstruction_rsbs_al_r4_r7_0[] = {
  0x7c, 0x42 // rsbs al r4 r7 0
};
const byte kInstruction_rsbs_al_r5_r0_0[] = {
  0x45, 0x42 // rsbs al r5 r0 0
};
const byte kInstruction_rsbs_al_r5_r1_0[] = {
  0x4d, 0x42 // rsbs al r5 r1 0
};
const byte kInstruction_rsbs_al_r5_r2_0[] = {
  0x55, 0x42 // rsbs al r5 r2 0
};
const byte kInstruction_rsbs_al_r5_r3_0[] = {
  0x5d, 0x42 // rsbs al r5 r3 0
};
const byte kInstruction_rsbs_al_r5_r4_0[] = {
  0x65, 0x42 // rsbs al r5 r4 0
};
const byte kInstruction_rsbs_al_r5_r5_0[] = {
  0x6d, 0x42 // rsbs al r5 r5 0
};
const byte kInstruction_rsbs_al_r5_r6_0[] = {
  0x75, 0x42 // rsbs al r5 r6 0
};
const byte kInstruction_rsbs_al_r5_r7_0[] = {
  0x7d, 0x42 // rsbs al r5 r7 0
};
const byte kInstruction_rsbs_al_r6_r0_0[] = {
  0x46, 0x42 // rsbs al r6 r0 0
};
const byte kInstruction_rsbs_al_r6_r1_0[] = {
  0x4e, 0x42 // rsbs al r6 r1 0
};
const byte kInstruction_rsbs_al_r6_r2_0[] = {
  0x56, 0x42 // rsbs al r6 r2 0
};
const byte kInstruction_rsbs_al_r6_r3_0[] = {
  0x5e, 0x42 // rsbs al r6 r3 0
};
const byte kInstruction_rsbs_al_r6_r4_0[] = {
  0x66, 0x42 // rsbs al r6 r4 0
};
const byte kInstruction_rsbs_al_r6_r5_0[] = {
  0x6e, 0x42 // rsbs al r6 r5 0
};
const byte kInstruction_rsbs_al_r6_r6_0[] = {
  0x76, 0x42 // rsbs al r6 r6 0
};
const byte kInstruction_rsbs_al_r6_r7_0[] = {
  0x7e, 0x42 // rsbs al r6 r7 0
};
const byte kInstruction_rsbs_al_r7_r0_0[] = {
  0x47, 0x42 // rsbs al r7 r0 0
};
const byte kInstruction_rsbs_al_r7_r1_0[] = {
  0x4f, 0x42 // rsbs al r7 r1 0
};
const byte kInstruction_rsbs_al_r7_r2_0[] = {
  0x57, 0x42 // rsbs al r7 r2 0
};
const byte kInstruction_rsbs_al_r7_r3_0[] = {
  0x5f, 0x42 // rsbs al r7 r3 0
};
const byte kInstruction_rsbs_al_r7_r4_0[] = {
  0x67, 0x42 // rsbs al r7 r4 0
};
const byte kInstruction_rsbs_al_r7_r5_0[] = {
  0x6f, 0x42 // rsbs al r7 r5 0
};
const byte kInstruction_rsbs_al_r7_r6_0[] = {
  0x77, 0x42 // rsbs al r7 r6 0
};
const byte kInstruction_rsbs_al_r7_r7_0[] = {
  0x7f, 0x42 // rsbs al r7 r7 0
};
const TestResult kReferencersbs[] = {
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r0_r0_0),
    kInstruction_rsbs_al_r0_r0_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r0_r1_0),
    kInstruction_rsbs_al_r0_r1_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r0_r2_0),
    kInstruction_rsbs_al_r0_r2_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r0_r3_0),
    kInstruction_rsbs_al_r0_r3_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r0_r4_0),
    kInstruction_rsbs_al_r0_r4_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r0_r5_0),
    kInstruction_rsbs_al_r0_r5_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r0_r6_0),
    kInstruction_rsbs_al_r0_r6_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r0_r7_0),
    kInstruction_rsbs_al_r0_r7_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r1_r0_0),
    kInstruction_rsbs_al_r1_r0_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r1_r1_0),
    kInstruction_rsbs_al_r1_r1_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r1_r2_0),
    kInstruction_rsbs_al_r1_r2_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r1_r3_0),
    kInstruction_rsbs_al_r1_r3_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r1_r4_0),
    kInstruction_rsbs_al_r1_r4_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r1_r5_0),
    kInstruction_rsbs_al_r1_r5_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r1_r6_0),
    kInstruction_rsbs_al_r1_r6_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r1_r7_0),
    kInstruction_rsbs_al_r1_r7_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r2_r0_0),
    kInstruction_rsbs_al_r2_r0_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r2_r1_0),
    kInstruction_rsbs_al_r2_r1_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r2_r2_0),
    kInstruction_rsbs_al_r2_r2_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r2_r3_0),
    kInstruction_rsbs_al_r2_r3_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r2_r4_0),
    kInstruction_rsbs_al_r2_r4_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r2_r5_0),
    kInstruction_rsbs_al_r2_r5_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r2_r6_0),
    kInstruction_rsbs_al_r2_r6_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r2_r7_0),
    kInstruction_rsbs_al_r2_r7_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r3_r0_0),
    kInstruction_rsbs_al_r3_r0_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r3_r1_0),
    kInstruction_rsbs_al_r3_r1_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r3_r2_0),
    kInstruction_rsbs_al_r3_r2_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r3_r3_0),
    kInstruction_rsbs_al_r3_r3_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r3_r4_0),
    kInstruction_rsbs_al_r3_r4_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r3_r5_0),
    kInstruction_rsbs_al_r3_r5_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r3_r6_0),
    kInstruction_rsbs_al_r3_r6_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r3_r7_0),
    kInstruction_rsbs_al_r3_r7_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r4_r0_0),
    kInstruction_rsbs_al_r4_r0_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r4_r1_0),
    kInstruction_rsbs_al_r4_r1_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r4_r2_0),
    kInstruction_rsbs_al_r4_r2_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r4_r3_0),
    kInstruction_rsbs_al_r4_r3_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r4_r4_0),
    kInstruction_rsbs_al_r4_r4_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r4_r5_0),
    kInstruction_rsbs_al_r4_r5_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r4_r6_0),
    kInstruction_rsbs_al_r4_r6_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r4_r7_0),
    kInstruction_rsbs_al_r4_r7_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r5_r0_0),
    kInstruction_rsbs_al_r5_r0_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r5_r1_0),
    kInstruction_rsbs_al_r5_r1_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r5_r2_0),
    kInstruction_rsbs_al_r5_r2_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r5_r3_0),
    kInstruction_rsbs_al_r5_r3_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r5_r4_0),
    kInstruction_rsbs_al_r5_r4_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r5_r5_0),
    kInstruction_rsbs_al_r5_r5_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r5_r6_0),
    kInstruction_rsbs_al_r5_r6_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r5_r7_0),
    kInstruction_rsbs_al_r5_r7_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r6_r0_0),
    kInstruction_rsbs_al_r6_r0_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r6_r1_0),
    kInstruction_rsbs_al_r6_r1_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r6_r2_0),
    kInstruction_rsbs_al_r6_r2_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r6_r3_0),
    kInstruction_rsbs_al_r6_r3_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r6_r4_0),
    kInstruction_rsbs_al_r6_r4_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r6_r5_0),
    kInstruction_rsbs_al_r6_r5_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r6_r6_0),
    kInstruction_rsbs_al_r6_r6_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r6_r7_0),
    kInstruction_rsbs_al_r6_r7_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r7_r0_0),
    kInstruction_rsbs_al_r7_r0_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r7_r1_0),
    kInstruction_rsbs_al_r7_r1_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r7_r2_0),
    kInstruction_rsbs_al_r7_r2_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r7_r3_0),
    kInstruction_rsbs_al_r7_r3_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r7_r4_0),
    kInstruction_rsbs_al_r7_r4_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r7_r5_0),
    kInstruction_rsbs_al_r7_r5_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r7_r6_0),
    kInstruction_rsbs_al_r7_r6_0,
  },
  {
    ARRAY_SIZE(kInstruction_rsbs_al_r7_r7_0),
    kInstruction_rsbs_al_r7_r7_0,
  },
};

#endif  // VIXL_ASSEMBLER_COND_RDLOW_RNLOW_OPERAND_IMMEDIATE_ZERO_RSBS_T32_H_