1 /*
2 * Copyright 2022 Alyssa Rosenzweig
3 * SPDX-License-Identifier: MIT
4 */
5
6 #include "util/format/u_format.h"
7 #include "agx_tilebuffer.h"
8
9 #include <gtest/gtest.h>
10
11 struct test {
12 const char *name;
13 uint8_t nr_samples;
14 enum pipe_format formats[8];
15 struct agx_tilebuffer_layout layout;
16 uint32_t total_size;
17 };
18
19 /* clang-format off */
20 struct test tests[] = {
21 {
22 "Simple test",
23 1,
24 { PIPE_FORMAT_R8G8B8A8_UNORM },
25 {
26 ._offset_B = { 0 },
27 .sample_size_B = 8,
28 .nr_samples = 1,
29 .tile_size = { 32, 32 },
30 },
31 8192
32 },
33 {
34 "MSAA 2x",
35 2,
36 { PIPE_FORMAT_R8G8B8A8_UNORM },
37 {
38 ._offset_B = { 0 },
39 .sample_size_B = 8,
40 .nr_samples = 2,
41 .tile_size = { 32, 32 },
42 },
43 16384
44 },
45 {
46 "MSAA 4x",
47 4,
48 { PIPE_FORMAT_R8G8B8A8_UNORM },
49 {
50 ._offset_B = { 0 },
51 .sample_size_B = 8,
52 .nr_samples = 4,
53 .tile_size = { 32, 16 },
54 },
55 16384
56 },
57 {
58 "MRT",
59 1,
60 {
61 PIPE_FORMAT_R16_SINT,
62 PIPE_FORMAT_R32G32_FLOAT,
63 PIPE_FORMAT_R8_SINT,
64 PIPE_FORMAT_R32G32_SINT,
65 },
66 {
67 ._offset_B = { 0, 4, 12, 16 },
68 .sample_size_B = 24,
69 .nr_samples = 1,
70 .tile_size = { 32, 32 },
71 },
72 24576
73 },
74 {
75 "MRT with MSAA 2x",
76 2,
77 {
78 PIPE_FORMAT_R16_SINT,
79 PIPE_FORMAT_R32G32_FLOAT,
80 PIPE_FORMAT_R8_SINT,
81 PIPE_FORMAT_R32G32_SINT,
82 },
83 {
84 ._offset_B = { 0, 4, 12, 16 },
85 .sample_size_B = 24,
86 .nr_samples = 2,
87 .tile_size = { 32, 16 },
88 },
89 24576
90 },
91 {
92 "MRT with MSAA 4x",
93 4,
94 {
95 PIPE_FORMAT_R16_SINT,
96 PIPE_FORMAT_R32G32_FLOAT,
97 PIPE_FORMAT_R8_SINT,
98 PIPE_FORMAT_R32G32_SINT,
99 },
100 {
101 ._offset_B = { 0, 4, 12, 16 },
102 .sample_size_B = 24,
103 .nr_samples = 4,
104 .tile_size = { 16, 16 },
105 },
106 24576
107 },
108 {
109 "MRT test requiring 2 alignment on the second RT",
110 1,
111 { PIPE_FORMAT_R8_UNORM, PIPE_FORMAT_R16G16_SNORM },
112 {
113 ._offset_B = { 0, 2 },
114 .sample_size_B = 8,
115 .nr_samples = 1,
116 .tile_size = { 32, 32 },
117 },
118 8192
119 },
120 {
121 "Simple MRT test requiring 4 alignment on the second RT",
122 1,
123 { PIPE_FORMAT_R8_UNORM, PIPE_FORMAT_R10G10B10A2_UNORM },
124 {
125 ._offset_B = { 0, 4 },
126 .sample_size_B = 8,
127 .nr_samples = 1,
128 .tile_size = { 32, 32 },
129 },
130 8192
131 },
132 {
133 "MRT test that requires spilling to consider alignment requirements",
134 4,
135 {
136 PIPE_FORMAT_R32_FLOAT,
137 PIPE_FORMAT_R32_FLOAT,
138 PIPE_FORMAT_R32_FLOAT,
139 PIPE_FORMAT_R32_FLOAT,
140 PIPE_FORMAT_R32_FLOAT,
141 PIPE_FORMAT_R32_FLOAT,
142 PIPE_FORMAT_R32_FLOAT,
143 PIPE_FORMAT_R32_FLOAT,
144 },
145 {
146 .spilled = { false, false, false, false, false, false, true, true },
147 ._offset_B = { 0, 4, 8, 12, 16, 20, 0, 0},
148 .sample_size_B = 24,
149 .nr_samples = 4,
150 .tile_size = { 16, 16 },
151 },
152 24576
153 },
154
155 };
156 /* clang-format on */
157
TEST(Tilebuffer,Layouts)158 TEST(Tilebuffer, Layouts)
159 {
160 for (unsigned i = 0; i < ARRAY_SIZE(tests); ++i) {
161 unsigned nr_cbufs;
162
163 for (nr_cbufs = 0; nr_cbufs < ARRAY_SIZE(tests[i].formats) &&
164 tests[i].formats[nr_cbufs] != PIPE_FORMAT_NONE;
165 ++nr_cbufs)
166 ;
167
168 struct agx_tilebuffer_layout actual = agx_build_tilebuffer_layout(
169 tests[i].formats, nr_cbufs, tests[i].nr_samples, false);
170
171 ASSERT_EQ(tests[i].layout.sample_size_B, actual.sample_size_B)
172 << tests[i].name;
173 ASSERT_EQ(tests[i].layout.nr_samples, actual.nr_samples) << tests[i].name;
174 ASSERT_EQ(tests[i].layout.tile_size.width, actual.tile_size.width)
175 << tests[i].name;
176 ASSERT_EQ(tests[i].layout.tile_size.height, actual.tile_size.height)
177 << tests[i].name;
178 ASSERT_EQ(tests[i].total_size, agx_tilebuffer_total_size(&tests[i].layout))
179 << tests[i].name;
180 }
181 }
182