1*9880d681SAndroid Build Coastguard Worker; RUN: llc < %s -mtriple=x86_64-none-none-gnux32 -mcpu=generic | FileCheck %s 2*9880d681SAndroid Build Coastguard Worker; RUN: llc < %s -mtriple=x86_64-none-none-gnux32 -mcpu=generic -fast-isel | FileCheck %s 3*9880d681SAndroid Build Coastguard Worker; Bug 22859 4*9880d681SAndroid Build Coastguard Worker; 5*9880d681SAndroid Build Coastguard Worker; x32 pointers are 32-bits wide. x86-64 indirect branches use the full 64-bit 6*9880d681SAndroid Build Coastguard Worker; registers. Therefore, x32 CodeGen needs to zero extend indirectbr's target to 7*9880d681SAndroid Build Coastguard Worker; 64-bit. 8*9880d681SAndroid Build Coastguard Worker 9*9880d681SAndroid Build Coastguard Workerdefine i8 @test1() nounwind ssp { 10*9880d681SAndroid Build Coastguard Workerentry: 11*9880d681SAndroid Build Coastguard Worker %0 = select i1 undef, ; <i8*> [#uses=1] 12*9880d681SAndroid Build Coastguard Worker i8* blockaddress(@test1, %bb), 13*9880d681SAndroid Build Coastguard Worker i8* blockaddress(@test1, %bb6) 14*9880d681SAndroid Build Coastguard Worker indirectbr i8* %0, [label %bb, label %bb6] 15*9880d681SAndroid Build Coastguard Workerbb: ; preds = %entry 16*9880d681SAndroid Build Coastguard Worker ret i8 1 17*9880d681SAndroid Build Coastguard Worker 18*9880d681SAndroid Build Coastguard Workerbb6: ; preds = %entry 19*9880d681SAndroid Build Coastguard Worker ret i8 2 20*9880d681SAndroid Build Coastguard Worker} 21*9880d681SAndroid Build Coastguard Worker; CHECK-LABEL: @test1 22*9880d681SAndroid Build Coastguard Worker; We are looking for a movl ???, %r32 followed by a 64-bit jmp through the 23*9880d681SAndroid Build Coastguard Worker; same register. 24*9880d681SAndroid Build Coastguard Worker; CHECK: movl {{.*}}, %{{e|r}}[[REG:.[^d]*]]{{d?}} 25*9880d681SAndroid Build Coastguard Worker; CHECK-NEXT: jmpq *%r[[REG]] 26*9880d681SAndroid Build Coastguard Worker 27